CN117174549A - Electronic source chip, preparation method thereof and electronic equipment - Google Patents

Electronic source chip, preparation method thereof and electronic equipment Download PDF

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Publication number
CN117174549A
CN117174549A CN202210582986.2A CN202210582986A CN117174549A CN 117174549 A CN117174549 A CN 117174549A CN 202210582986 A CN202210582986 A CN 202210582986A CN 117174549 A CN117174549 A CN 117174549A
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CN
China
Prior art keywords
electron
source chip
layer
protective layer
electron source
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CN202210582986.2A
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Chinese (zh)
Inventor
肖祥
何正宇
黄志骏
陈品澔
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to CN202210582986.2A priority Critical patent/CN117174549A/en
Priority to PCT/CN2023/095887 priority patent/WO2023226995A1/en
Publication of CN117174549A publication Critical patent/CN117174549A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00—Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02—Main electrodes
    • H01J1/30—Cold cathodes, e.g. field-emissive cathode
    • H01J1/304—Field-emissive cathodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00—Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/88—Mounting, supporting, spacing, or insulating of electrodes or of electrode assemblies
    • H01J1/90—Insulation between electrodes or supports within the vacuum space
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02—Manufacture of electrodes or electrode systems
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Cold Cathode And The Manufacture (AREA)

Abstract

The embodiment of the application provides an electron source chip, a preparation method thereof and electronic equipment. The electron source chip includes: the device comprises a substrate, a first dielectric layer, a first electrode layer, an electron emitter and a first protective layer; the first dielectric layer is stacked on the substrate; the first electrode layer is stacked on one side of the first dielectric layer, which is far away from the substrate, and is provided with a first electron emission chamber which penetrates through the first dielectric layer and the first electrode layer along the stacking direction and reaches the substrate; an electron emitter located in the first electron emission chamber and stacked on the substrate; a first protective layer is formed on the outer wall surface of the electron emitter and on the inner wall surface of the first electron emission chamber. The electron source chip provided by the embodiment of the application improves the stability and reliability of electron emission of the electron source chip, ensures normal electron emission, and prolongs the service life of the electron source chip.

Description

Electronic source chip, preparation method thereof and electronic equipment
Technical Field
The present application relates to the field of field emission device manufacturing, and in particular, to an electron source chip, a method for manufacturing the same, and an electronic apparatus.
Background
The main function of the electron source chip is to generate and emit electrons. The electron source chip has wide application in the fields of vacuum tube devices, scientific instruments, medical instruments, aerospace equipment, material characterization and the like. In the working process of the electron source chip, it is important to ensure the stability of emitted electrons, and the service life of the electron source chip is also ensured. The electron emission technique of the cold field emission electron source chip will be described below by taking the cold field emission electron source chip as an example.
Fig. 1 is a schematic structural diagram of a cold field emission electron source chip in the prior art. As shown in fig. 1, the cold field emission electron source chip includes a substrate 1, a dielectric layer 2 stacked on the substrate 1, and an electrode layer 3 stacked on the dielectric layer 2; wherein the dielectric layer 2 comprises a cavity 21, the electrode layer 3 comprises a through hole 31, and the cavity 21 is communicated with the through hole 31 to form the accommodating cavity 5.
And the needle tip 4 is cone-shaped or pyramid-shaped and stacked in the accommodating chamber 5, and the bottom of the needle tip 4 is formed on the base 1, and the tip of the needle tip 4 is stacked near the through hole 31. When a forward voltage difference (i.e., electrode layer voltage > tip voltage) is applied across the electrode layer 3 and the tip 4, the tip of the tip 4 will form an electric field enhancement effect, electrons in the tip 4 will gather towards the surface of the tip 4, and the field tunneling effect will cause electrons in the tip 4 to tunnel into vacuum, forming electron emission. The needle tip 4 emits electrons in the first sub-region 4a, and the emitted electron tracks are directly emitted to a vacuum environment outside the electron source chip for later use.
However, there is also electron emission in the second sub-region 4b of the needle tip 4, and most of the electrons bombard the dielectric layer 2 and the electrode layer 3 due to the electron emission position and emission angle in the second sub-region 4 b. In particular, at the intersection 6 of the dielectric layer 2, the substrate 1 and the vacuum junction, the emitted electrons easily move along the surface of the dielectric layer toward the electrode layer, and secondary electron emission, i.e., electron multiplication effect, is formed during the movement, resulting in a creepage breakdown along the sidewall of the dielectric, i.e., what is known as breakdown (triple point) in the industry. Therefore, electrons emitted at the position of the second sub-region 4b affect the reliability of electron emission. And, the tip portion of the needle tip 4 is easy to be adsorbed and desorbed, and may be bombarded and deformed, so that instability of the emission current of the needle tip under actual working conditions is caused, and meanwhile, an abnormal discharge phenomenon is possibly emitted, so that the electron source chip is broken down and damaged, and the reliability and the service life of the chip are affected.
Therefore, how to ensure the reliability of electron emission of the electron source chip is a problem to be solved.
Disclosure of Invention
The embodiment of the application provides an electron source chip, a preparation method thereof and electronic equipment, which are used for solving the technical problem of low electron emission reliability of the electron source chip.
The electron source chip provided by the embodiment of the application can be applied to the fields of vacuum tube devices, scientific instruments, medical instruments, aerospace equipment, material characterization and the like.
In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme:
in a first aspect, there is provided an electron source chip including: the device comprises a substrate, a first dielectric layer, a first electrode layer, an electron emitter and a first protective layer; the first dielectric layer is stacked on the substrate; the first electrode layer is stacked on one side of the first dielectric layer, which is far away from the substrate, and is provided with a first electron emission chamber which penetrates through the first dielectric layer and the first electrode layer along the stacking direction and reaches the substrate; an electron emitter located in the first electron emission chamber and stacked on the substrate; a first protective layer is formed on the outer wall surface of the electron emitter and on the inner wall surface of the first electron emission chamber.
Based on the above description of the structure of the electron source chip provided by the present application, it can be seen that the outer wall surface of the electron emitter and the inner wall surface of the first electron emission chamber are covered with the first protective layer, so that not only the electron emitter but also the first dielectric layer and the first electrode layer can be protected. Specifically, the first protective layer is covered on the outer wall surface of the electron emitter, so that the gas in the working environment can be prevented from being adsorbed and desorbed on the outer wall surface of the electron emitter, the surface work function of the electron emitter cannot fluctuate, the field emission of the needle point is stabilized, and the reliability of the electron emission is further ensured; in addition, the first protective layer prevents the electron emitter from the impact of particle bombardment in the working environment, reduces the deformation of the electron emitter, and accordingly stabilizes the electron emission of the electron emitter; also, the first protective layer may cause a portion of the electron emitter for emitting electrons to normally emit electrons, and other portions of the electron emitter than the portion for emitting electrons may reduce emission of electrons. Meanwhile, the first protection layer covered on the inner wall surface of the first electron emission chamber can protect the first dielectric layer and the first electrode layer from particle bombardment in the working environment, weaken the impact of the particles on the bombardment of the first dielectric layer and the first electrode layer, and inhibit creepage breakdown caused by electron discharge. Therefore, the electron source chip provided by the embodiment of the application improves the stability and reliability of electron emission of the electron source chip, ensures normal electron emission, and prolongs the service life of the electron source chip.
In a possible implementation manner of the first aspect, the electron emitter is a needle tip structure.
In a possible implementation of the first aspect, the radial dimension of the needle tip is smaller and smaller in the stacking direction.
In a possible implementation manner of the first aspect, a first protection layer is formed on a surface of the first electrode layer away from the first dielectric layer. The surface of the first electrode layer far away from the first dielectric layer is the upper surface of the first electrode layer, and the first protection layer covered on the upper surface of the first electrode layer can protect the first electrode layer from being bombarded by electrons or particles outside the electron source chip.
In a possible implementation manner of the first aspect, the first protective layer formed on the outer wall surface of the electron emitter, the inner wall surface of the first electron emission chamber, and the upper surface of the first electrode layer is an integral structure. Therefore, the full coverage of the protective layer structure in the electron source chip can be realized, so that other structures except the protective layer in the electron source chip are prevented from being bombarded by electrons in the working environment, and the reliability of electron emission of the electron source chip is ensured.
In a possible implementation manner of the first aspect, the electron emitter includes a first end remote from the substrate, the first end being configured to emit electrons to an outside of the electron source chip; the electron source chip further includes a second protective layer formed on the first protective layer and located on other regions of the first protective layer than the first end. It can be seen that, in the electron source chip provided by the embodiment of the application, only the first protection layer is disposed at the first end of the electron emitter, i.e. a single-layer structure is adopted; arranging a first protective layer and a second protective layer on other positions except the first end of the electron emitter, namely adopting a double-layer structure; thus, not only the normal emission of electrons at the first end is ensured, but also the escape of electrons at other positions except the first end on the electron emitter can be reduced. Meanwhile, the double-layer structure can further weaken impact of particles in the working environment on bombardment of other positions except the first end on the electron emitter.
In a possible implementation manner of the first aspect, the electron emitter includes a first end remote from the substrate, the first end being configured to emit electrons to an outside of the electron source chip; the electron source chip further includes a second protective layer formed between the first protective layer and the electron emitter and located between the remaining region of the first protective layer except the first end and the outer wall surface of the electron emitter.
In a possible implementation manner of the first aspect, the second protection layer is formed on the first protection layer formed on the inner wall surface of the first electron emission chamber. In this way, the inner wall surface of the first electron emission chamber adopts a multi-layer structure, so that the impact of particles on the wall surface is further weakened, the creepage breakdown is restrained, and meanwhile, the electron emission of the first end of the needle point is not influenced by the stacking of the second protective layer.
In a possible implementation manner of the first aspect, a second protective layer is formed between the first protective layer formed on the inner wall surface of the first electron emission chamber and the inner wall surface of the first electron emission chamber.
In a possible implementation manner of the first aspect, the second protection layer is formed on the first protection layer formed on the upper surface of the first electrode layer. In this way, the upper surface of the first electrode layer adopts a multi-layer structure, so that the impact of the particles on the bombardment of the upper surface of the first electrode layer is further weakened, the creepage breakdown is restrained, and meanwhile, the electron emission of the first end of the needle point is not influenced by the stacking of the second protective layer.
In a possible implementation manner of the first aspect, a second protection layer is formed between the first protection layer formed on the upper surface of the first electrode layer and the first electrode layer.
In a possible implementation manner of the first aspect, the first protection layer formed on the outer wall surface of the electron emitter, the inner wall surface of the first electron emission chamber, and the upper surface of the first electrode layer is made of the same material. Thus, when the first protective layer is plated on the electron source chip, the plating layers on the outer wall surface of the electron emitter, the inner wall surface of the first electron emission chamber and the upper surface of the first electrode layer can be completed at one time, thereby saving time and being beneficial to improving production efficiency.
In a possible implementation manner of the first aspect, an inner surface of the first electron emission chamber is a circular arc. Thus, even if electrons bombard the inner surface of the first electron emission chamber, electrons are not easy to break down, so that damage to the first dielectric layer is reduced.
In a possible implementation manner of the first aspect, a material of the second protection layer is different from a material of the first protection layer. The first protection layer is stacked at the first end, so that the material of the first protection layer needs to ensure the normal emission of electrons at the first end; preferably, no electrons escape from the side surface of the tip. Therefore, considering different requirements of the first end and the side surface of the needle point, the first protective layer is made of a material which does not influence electron escape, and the second protective layer is made of a material which can prevent electron escape, so that normal emission of electrons of the electron source chip is ensured.
In a possible implementation manner of the first aspect, the electron source chip further includes: a second dielectric layer and a second electrode layer; the second dielectric layer is stacked on one side of the first electrode layer far away from the first dielectric layer; the second electrode layer is stacked on one side of the second dielectric layer far away from the first electrode layer, and a second electron emission cavity penetrating through the second dielectric layer and the second electrode layer along the stacking direction is formed in the second electrode layer; wherein the first electron emission chamber and the second electron emission chamber are communicated. In this way, the added second electrode layer may modulate the outgoing electrons, including collimation and increasing current density.
In a possible implementation manner of the first aspect, the central axis of the first electron emission chamber and the central axis of the second electron emission chamber coincide.
In a possible implementation manner of the first aspect, the first protection layer is formed on an inner wall of the second electron emission chamber. In this way, the second dielectric layer and the second electrode layer are protected from the impact of the bombardment of particles in the working environment, and the impact of the particles on the second dielectric layer and the second electrode layer is weakened, and the creepage breakdown caused by the electron discharge is suppressed.
In a possible implementation manner of the first aspect, the first protective layer formed on the inner wall of the second electron emission chamber, on the outer wall surface of the electron emitter, and on the inner wall surface of the first electron emission chamber is an integral structure.
In a possible implementation manner of the first aspect, a radial dimension of the first electron emission chamber is smaller than a radial dimension of the second electron emission chamber.
In a possible implementation manner of the first aspect, a first protection layer is formed on a surface of the second electrode layer away from the second dielectric layer.
In a possible implementation manner of the first aspect, the first protection layer is a dielectric material with a hardness greater than or equal to 2.3GPa, and a material work function of the dielectric material is less than 4.9eV. The high hardness represents strong ability of particle bombardment, and the low work function represents the barrier height which the protective layer can overcome when the needle point emits electrons. In this way, the first protective layer can make the portion for emitting electrons in the electron emitter normally emit electrons, and the other portion of the electron emitter except for the portion for emitting electrons reduces the emission of electrons.
In a possible implementation manner of the first aspect, the material of the protection layer is Y 2 O 3 Or Nd 2 O 3 。
In a possible implementation manner of the first aspect, the material of the first protection layer may be AlN or DLC, and although the work function of the material is greater than 4.9eV, a negative electron affinity may be formed on the surface of the needle tip, so as to ensure normal emission of electrons.
In a possible implementation of the first aspect, the protective layer has a thickness in the range of 1-50nm. As the thickness of the protective layer increases, the electron tunneling probability decreases, and electron emission is affected; as the thickness increases, the charge of the protective layer tends to be serious due to particle bombardment, and emergent electrons are affected; because the protective layer material is continually lost during operation, the lifetime is extended as the thickness increases. In summary, the protective layer thickness is preferably not too thin or too thick, preferably 1-50nm.
In a second aspect, the present application also provides a method for manufacturing an electron source chip, the method comprising: stacking a first dielectric layer on a substrate; stacking a first electrode layer on one side of the first dielectric layer away from the substrate; a first electron emission chamber is arranged on the first electrode layer, and penetrates through the first dielectric layer and the first electrode layer to the substrate along the stacking direction; disposing an electron emitter in the first electron emission chamber, and stacking the electron emitter on the substrate; a first protective layer is formed on the outer wall surface of the electron emitter and on the inner wall surface of the first electron emission chamber.
The electron source chip manufactured by the manufacturing method shown in the embodiment is covered with the first protection layer on the outer wall surface of the electron emitter and the inner wall surface of the first electron emission chamber, the first protection layer can play a role in protecting the electron emitter, the first dielectric layer and the first electrode layer, stability and reliability of electron emission of the electron source chip are improved, normal emission of electrons is guaranteed, and meanwhile, the service life of the electron source chip is prolonged.
In a possible implementation manner of the second aspect, when the first protective layer is formed on the outer wall surface of the electron emitter and the inner wall surface of the first electron emission chamber, the preparation method further includes: a first protective layer is formed on a surface of the first electrode layer remote from the first dielectric layer. In this way, the manufactured electron source chip can protect the first electrode layer from electrons or particles outside the electron source chip.
In a possible implementation manner of the second aspect, the electron emitter includes a first end remote from the substrate, the first end being configured to emit electrons to outside the electron source chip; after forming the first protective layer on the outer wall surface of the electron emitter and the inner wall surface of the first electron emission chamber, the manufacturing method further includes: a second protective layer is formed on the first protective layer, and the second protective layer is located on other areas of the first protective layer except the first end. Thus, the electron source chip is provided with only the first protective layer at the first end of the electron emitter, namely, a single-layer structure is adopted; arranging a first protective layer and a second protective layer on other positions except the first end of the electron emitter, namely adopting a double-layer structure; the electron emission device not only ensures the normal emission of electrons on the first end, but also can reduce the escape of electrons on other positions except the first end on the electron emitter.
In a possible implementation manner of the second aspect, the electron emitter includes a first end remote from the substrate, the first end being configured to emit electrons to outside the electron source chip; before the first protective layer is formed on the outer wall surface of the electron emitter and the inner wall surface of the first electron emission chamber, the preparation method further comprises: a second protective layer is formed on the outer wall surface of the electron emitter, and the second protective layer is located on other regions of the electron emitter than the first end.
In a possible implementation manner of the second aspect, after stacking the first electrode layer on a side of the first dielectric layer away from the substrate; before a first electron emission chamber is formed on the first electrode layer; the preparation method also comprises the following steps: stacking a second dielectric layer on one side of the first electrode layer away from the first dielectric layer; stacking a second electrode layer on one side of the second dielectric layer away from the first electrode layer; a second electron emission chamber penetrating through the second dielectric layer and the second electrode layer is arranged on the second electrode layer along the stacking direction; the first electron emission chamber and the second electron emission chamber are perforated.
In a possible implementation manner of the second aspect, after forming the first protective layer on the outer wall surface of the electron emitter and on the inner wall surface of the first electron emission chamber, the preparation method further includes: a first protective layer is formed on an inner wall of the second electron emission chamber.
In a possible implementation manner of the second aspect, after forming the first protective layer on the outer wall surface of the electron emitter and on the inner wall surface of the first electron emission chamber, the preparation method further includes: a first protective layer is formed on a surface of the second electrode layer remote from the second dielectric layer.
In a third aspect, the present application also provides an electronic device, which includes a printed circuit board, the above-mentioned electron source chip, or an electron source chip manufactured by the above-mentioned method for manufacturing an electron source chip; the electron source chip is arranged on the printed circuit board.
The electronic equipment provided by the embodiment of the application can obtain stably emitted electrons by stacking the electron source chips with high electron emission reliability, and the equipment has high reliability when the electronic equipment works by utilizing electrons. In addition, the service life of the electron source chip is long, so that the service life of the electronic equipment is prolonged.
Drawings
FIG. 1 is a schematic diagram of a cold field electron emission source chip in the prior art;
fig. 2 is a schematic structural diagram of an electronic device 100 according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present application;
fig. 4a is a schematic cross-sectional view of an electron source chip 120 according to an embodiment of the present application;
FIG. 4b is an exploded view of the electron source chip 120 of FIG. 4 a;
FIG. 4c is a schematic diagram of a first electron emission chamber of the electron source chip 120 shown in FIG. 4 a;
fig. 5 is a schematic structural view of an electron emitter 40 according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of a first region 11 on a substrate 10 according to an embodiment of the present application;
fig. 7a is a schematic structural diagram of a first protective layer 60 according to an embodiment of the present application;
fig. 7b is a schematic view of the first end 402 of the electron emitter 40 contacting the air outside the electron source chip;
FIG. 7c is a schematic diagram illustrating an electron source chip in contact with air outside the electron source chip according to an embodiment of the present application;
fig. 8a is a schematic structural diagram of a first protection layer 60 according to an embodiment of the present application;
FIG. 8b is a schematic view of electron emission from a second portion of electron emitter 40;
fig. 8c is an electron emission schematic diagram of the electron emitter 40 in the electron source chip according to an embodiment of the present application;
fig. 9a is a schematic structural diagram of a first protective layer 60 according to an embodiment of the present application;
FIG. 9b is a schematic diagram of electron movement at the intersection of a dielectric layer and vacuum and a substrate;
fig. 9c is a schematic diagram illustrating the movement of electrons in the first electron emission chamber 50 of the electron source chip according to an embodiment of the present application;
fig. 10a is a schematic structural diagram of a first protective layer 60 according to an embodiment of the present application;
FIG. 10b is a schematic diagram of an electron movement outside the electron source chip;
FIG. 11a is a schematic diagram of an electron source chip with multiple passivation layers according to an embodiment of the present application;
FIG. 11b is a schematic diagram of another embodiment of an electron source chip with multiple passivation layers;
FIG. 12 is a schematic diagram of another embodiment of an electron source chip with multiple passivation layers;
Fig. 13 is a schematic structural diagram of another electron source chip 120 according to an embodiment of the present application.
FIG. 14 is a process flow diagram of a method for manufacturing an electron source chip according to an embodiment of the present application;
fig. 15a is a process structure diagram of step S100 in a method for manufacturing an electron source chip according to an embodiment of the present application;
fig. 15b is a process structure diagram of step S200 in the method for manufacturing an electron source chip according to the embodiment of the present application;
fig. 15c is a process structure diagram of step S300 in the method for manufacturing an electron source chip according to the embodiment of the present application;
fig. 15d is a process structure diagram of step S400 in the method for manufacturing an electron source chip according to the embodiment of the present application;
fig. 15e is a process structure diagram of step S500 in the method for manufacturing an electron source chip according to the embodiment of the present application;
FIG. 16 is a process flow diagram of another method for manufacturing an electron source chip according to an embodiment of the present application;
FIG. 17 is a process structure diagram of step S600 in a method for manufacturing an electron source chip according to an embodiment of the present application;
FIG. 18 is a process flow diagram of another method for fabricating an electron source chip according to an embodiment of the present application;
fig. 19 is a process structure diagram of step S600 in a method for manufacturing an electron source chip according to an embodiment of the present application;
FIG. 20 is a process flow diagram of a method for fabricating an electron source chip according to an embodiment of the present application;
fig. 21 is a process structure diagram of step S600 in a method for manufacturing an electron source chip according to an embodiment of the present application;
FIG. 22 is a process flow diagram of a method for fabricating an electron source chip according to an embodiment of the present application;
fig. 23a is a process structure diagram of step S310 in a method for manufacturing an electron source chip according to an embodiment of the present application;
fig. 23b is a process structure diagram of step S410 in the method for manufacturing an electron source chip according to the embodiment of the present application;
fig. 23c is a process structure diagram of steps S510 and S610 in a method for manufacturing an electron source chip according to an embodiment of the present application.
Reference numerals:
1-a substrate; 2-dielectric layer, 21-cavity; 3-electrode layer, 31-via; 4-needle tip, 4 a-first sub-region, 4 b-second sub-region; 5-a receiving cavity; 6-intersection position; 100-electronic equipment, 110-controller, 120-electronic source chip, 130-X-ray source, 131-diagnosis and treatment module, 140-vacuum cavity, 141-electronic outlet, 150-PCB board and 160-electric connection structure; 10-a substrate; 20-a first dielectric layer, 201-a first cavity; 30-a first electrode layer, 301-a first via; 40-electron emitter, 401-bottom surface, 402-first end, 403-second portion; 50-a first electron emission chamber; 51-a second electron emission chamber; 60-a first protective layer; 70-a second protective layer; 80-a second dielectric layer, 801-a second cavity; 90-second electrode layer, 901-second via.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. Wherein, in the description of the present application, "/" means that the related objects are in a "or" relationship, unless otherwise specified, for example, a/B may mean a or B; the "and/or" in the present application is merely an association relationship describing the association object, and indicates that three relationships may exist, for example, a and/or B may indicate: there are three cases, a alone, a and B together, and B alone, wherein a, B may be singular or plural. Also, in the description of the present application, unless otherwise indicated, "a plurality" means two or more than two. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural. In addition, in order to facilitate the clear description of the technical solution of the embodiments of the present application, in the embodiments of the present application, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ. Meanwhile, in the embodiments of the present application, words such as "exemplary" or "such as" are used to mean serving as examples, illustrations or explanations. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion that may be readily understood.
In order to facilitate the description of the technical solution of the present application, before the electronic device provided by the embodiment of the present application is described in detail, some concepts related to the present application are first described.
Work function: also known as work function and work function. Typically, work function refers to the work function of a metal. The work function of a metal is expressed as the minimum energy required for electrons having an initial energy equal to the fermi level to escape from the interior of the metal into the vacuum. The magnitude of the work function marks the strength of the electron bound in the metal, and the larger the work function, the less likely the electron will leave the metal. The work function of a metal is on the order of a few electron volts.
Method for measuring the electrical work function of a sample: many techniques based on different physical effects are used to measure the electrical work function of a sample, including absolute and relative measurements. Absolute measurement experimental results were obtained using electron emission of the sample induced by light absorption (light emission); . And obtaining experimental results by using the contact potential difference between the sample and the reference electrode according to the relative measurement method. For example, a diode cathode current may be used. And the experimental result is obtained according to the displacement current by manually changing the capacitance between the sample and the reference object. Instruments that may be used include, but are not limited to, kelvin detection force microscopy.
Negative electron affinity: electron affinity refers to the energy value from the bottom of the conduction band of a semiconductor to the level of vacuum energy, which characterizes how easily electrons escape a material when a photoelectric effect occurs. The smaller the electron affinity, the easier it is to escape. If the electron affinity is zero or negative, it means that electrons are in a state of being able to escape at any time, and the photocathode made of a material having a negative electron affinity can escape as long as electrons excited by photons can diffuse to the surface, so that the sensitivity is extremely high.
The electronic device provided by the embodiment of the application is described in detail below with reference to the accompanying drawings.
The embodiment of the application provides electronic equipment. The electronic equipment comprises an electron source chip and can be applied to the fields of vacuum tube devices, scientific instruments, medical instruments, aerospace equipment, material characterization and the like.
In some embodiments, the electronic device may be a medical device provided with an X-ray source, and may also be a vacuum tube. The embodiment of the application does not limit the specific form of the electronic device.
Fig. 2 is a schematic diagram of a partial circuit structure of an electronic device 100 according to an embodiment of the present application. As shown in fig. 2, in one embodiment, the electronic device 100 includes a controller 110, an electron source chip 120, and an X-ray source 130. The controller 110 is used for controlling the electron source chip 120 such that the electron source chip 120 generates and emits electrons for supporting the operation of the X-ray source 130. The X-ray source 130 may be used to support the operation of the diagnostic module 131.
The arrangement position of the electron source chip 120 in the electronic device will be described below with reference to the drawings.
Fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present application. As shown in fig. 3, in some embodiments, the electronic device includes, in addition to the electron source chip 120, a vacuum chamber 140, and a printed circuit board (printed circuit board, PCB) 150 disposed within the vacuum chamber 140. The electron source chip 120 is electrically connected to the PCB 150 through the electrical connection structure 160, so that the electron source chip 120 can be signal-interconnected with other chips or other electronic modules on the PCB 150.
In some embodiments, the PCB 150 controls the electronic device 100 to power the electron source chip 120, and the electron source chip 120 generates and escapes electrons under the voltage and emits the electrons into the vacuum chamber 140. The vacuum chamber 140 is provided with an electron outlet 141 penetrating through a wall of the vacuum chamber 140, and when the electron outlet 141 is opened, electrons in the vacuum chamber 140 escape the vacuum chamber 140 to be used by an electronic device.
The structure of the electron source chip 120 is described in detail below.
Fig. 4a is a schematic cross-sectional view of an electron source chip 120 according to an embodiment of the application. As shown in fig. 4a, the electron source chip includes a substrate 10, a first dielectric layer 20, a first electrode layer 30, an electron emitter 40, and a first protective layer 60.
The substrate 10 is used to support other structures of the electron source chip 120.
In some embodiments, the substrate 10 may be a transparent substrate or a non-transparent substrate. The material of the substrate 10 may be silicon (Si), silicon carbide (SiC), sapphire (sapphire), quartz (quartz), spinel (spinel), glass (glass), alumina (Alumina), or the like.
And, a first dielectric layer 20 is stacked on the substrate 10.
In some embodiments, the first dielectric layer 20 is made of an insulating material, for example, the first dielectric layer 20 may be silicon oxide (SiO 2), silicon nitride (SiNx), silicon oxynitride (SiON), or the like, or may be a composite layer made of the foregoing materials.
And, the first electrode layer 30 is stacked on a side of the first dielectric layer 20 remote from the substrate 10. The first electrode layer 30 serves as one electrode to which a voltage is applied when the electron source chip 120 emits electrons.
In some embodiments, the first electrode layer 30 is made of conductive metal, such as Mo, W, cr, ni, cu, al, pd, ti, tiN, taN, nd, or a composite layer made of the foregoing materials.
And the first electrode layer 30 is opened with a first electron emission chamber 50 penetrating the first dielectric layer 20 and the first electrode layer 30 in the stacking direction to the substrate 10. The first electron emission chamber 50 may be used to dispose the electron emitters 40.
And, the electron emitter 40 is stacked on the substrate 10. The electron emitter 40 serves as an electron emission source of the electron source chip 120.
When the electron source chip 120 is generating and emitting electrons, the electron emitter 40 serves as another electrode to which a voltage is applied, and the electron emitter 40 and the first electrode layer 30 serve as a pair of electrodes, by being formed on the first electrode layer 30 and the electron emitter 40Applying a positive voltage difference, i.e. a voltage U applied to the first electrode layer 30 1 Greater than the voltage U applied by the electron emitter 40 2 (U 1 ＞U 2 ) So that an electric field is formed in the first electron emission chamber 50. The electron emitter 40 gradually collects a large amount of electrons on the surface of the electron emitter 40 under the action of the electric field, and when the energy of the collected electrons reaches a certain threshold, the electrons escape from the surface of the electron emitter 40.
And a first protective layer 60 is formed on the outer wall surface of the electron emitter 40, on the inner wall surface of the first electron emission chamber 50.
In one embodiment, the material of the first protection layer 60 has a hardness of 2.3GPa or more and a work function of less than 4.9eV. For example, the first protective layer 60 may be Nd 2 O 3 May also be yttria (Y) 2 O 3 ). The higher the hardness of the material of the first protection layer 60, the stronger the bombardment resistance of the material, which not only can play a role in protecting the first end 402, but also can prolong the service life of the first protection layer 60. The lower the work function, the lower the barrier height that the electrons overcome when exiting from the first protective layer 60, facilitating normal emission of electrons.
In another embodiment, the first protective layer 60 may be selected to have a work function greater than 4.9eV and which will form a negative electron affinity (negative electron affinity, NEA) on the surface of the needle tip. For example, the first protective layer 60 may be aluminum nitride (AlN) or may be a diamond-like film (diamond like carbon, DLC). Thus, even if the work function of the material is larger than 4.9eV, the negative electron affinity still ensures the normal emission of electrons.
In some embodiments, the first protective layer 60 has a thickness dimension in the range of 1-50nm.
As the thickness dimension of the first protective layer 60 increases, the following effects may be caused: firstly, the electron tunneling probability is reduced, and the emission of electrons is affected; secondly, the charge of the protective layer tends to be serious due to particle bombardment, and emergent electrons are influenced; finally, particle bombardment can cause the protective layer material to be lost, and an increase in the thickness dimension of the first protective layer 60 can result in an extended lifetime. It can be seen that an excessive thickness can affect the normal emission of electrons and an excessive thickness can affect the lifetime of the protective layer. The thickness provided by the embodiment of the application has the advantages of moderate thickness and requirements of normal emission of electrons and prolonged service life.
In some embodiments, the material of the first protective layer 60 is uniformly coated on the outer wall surface of the electron emitter 40 and the inner wall surface of the first electron emission chamber 50 by using a vacuum coating technique.
It is understood that in the above-described embodiment, the substrate 10, the first dielectric layer 20, the first electrode layer 30, the electron emitter 40, and the first protective layer 60 may be regarded as one electron emission unit.
Fig. 4b is an exploded view of the electron source chip 120 of fig. 4 a. In combination with fig. 4a and 4b, in some embodiments, the electron source chip may include a plurality of electron emission units as shown in the above-described embodiments. Specifically, the first cavities 201 of the array are stacked in the first dielectric layer 20, the first through holes 301 opposite to the first cavities 201 of the array are stacked in the first electrode layer 30, so that the first cavities 201 of the array and the opposite first through holes 301 form a plurality of first electron emission chambers 50 for stacking a plurality of electron emitters 40, and when the electron source chip needs to emit electrons, the plurality of electron emitters 40 emit electrons at the same time to meet the requirement of emitting a large number of electrons.
As shown in fig. 4a, in one implementation, the substrate 10 is Si and has a thickness M in the range of 500-675 μm; the first dielectric layer 20 is made of SiO 2 The thickness N is 100-2000nm; the material of the first electrode layer 30 is Nd, and the thickness P thereof is 100-500nm; the electron emitter 40 is made of Mo, and the height Q thereof is in the range of 500-2000nm; the first protective layer is made of AlN, and the thickness H of the first protective layer is in the range of 1-50nm.
In another implementation, the substrate 10 is Si and has a thickness M in the range of 500-675 μm; the first dielectric layer 20 is made of SiO 2 The thickness N is 100-2000nm; the material of the first electrode layer 30 is W, and the thickness P thereof is 100-500nm; the electron emitter 40 is made of Si, and the height Q thereof is in the range of 500-2000nm; material of first protective layerThe material is AlN, and the thickness H of the AlN is 1-50nm.
In yet another implementation, the substrate 10 is Si and has a thickness M in the range of 500-675 μm; the first dielectric layer 20 is made of SiO 2 The thickness N is 100-2000nm; the material of the first electrode layer 30 is W, and the thickness P thereof is 100-500nm; the electron emitter 40 is made of Si, and the height Q thereof is in the range of 500-2000nm; the first protective layer is made of Y 2 O 3 The thickness H thereof is in the range of 1-50nm.
The structure of the first electron emission chamber 50 will be described in detail with reference to the accompanying drawings.
Referring to fig. 4a and 4b together, in some embodiments, a first cavity 201 is disposed in the first dielectric layer 20, and a first via 301 is disposed in the first electrode layer 30. Wherein the first through-hole 301 is disposed opposite to the first cavity 201 such that the first cavity 201 and the first through-hole 301 form the first electron emission chamber 50 communicating with each other.
In one implementation, the central axis of the first cavity 201 coincides with the central axis of the first through hole 301.
In some embodiments, the inner wall of the first cavity 201 is in a continuous circular arc shape as shown in fig. 4 b.
As shown in fig. 4c, in one implementation, the first radial dimension U of the first cavity 201 is greater than the radial dimension E of the first through hole 301. The radial dimension of the first cavity 201 is larger and larger in the stacking direction, the second radial dimension T of the first cavity 201 is larger than the first radial dimension U, and the second radial dimension T of the first cavity 201 is larger than the radial dimension E of the first through hole 301.
The structure of the electron emitter 40 will be described in detail with reference to the accompanying drawings.
Fig. 5 is a schematic structural diagram of an electron emitter 40 according to an embodiment of the present application. Referring to fig. 4b in combination with fig. 5, in some embodiments, electron emitter 40 may be a needle tip structure. The electron emitter 40 has a bottom surface 401 opposite to the substrate 10, and a radial dimension R of a cross section of the electron emitter 40 is gradually reduced from the bottom surface 401 in a stacking direction so that the electron emitter 40 has a first end 402 for emitting electrons to the outside of the electron source chip.
In other embodiments, electron emitter 40 may be a cylindrical nanotube structure.
When a forward voltage difference is applied across the first electrode layer 30 and the electron emitter 40, the first end 402 of the electron emitter 40 forms an electric field enhancement effect, electrons are gradually concentrated at the first end 402 of the electron emitter 40, and when the electrons accumulate to a certain energy, the field tunneling effect causes electrons in the first end 402 to tunnel, i.e., electrons are emitted into a vacuum environment outside the electron source chip.
The electron emitter 40 may be a metal material, such as a refractory metal as Mo, W, cr, ni, or a semiconductor material. Such as group IV semiconductor Si, ge, siC, group III-V semiconductor GaN, gaAs, etc., group II-VI semiconductor ZnO, cdS, etc., and composite layers of the above materials.
In one implementation, the central axis of the electron emitter 40 coincides with the central axis of the first through hole 301.
In one implementation, the central axis of the electron emitter 40 coincides with the central axis of the first cavity 201.
In one implementation, as shown in fig. 4a, the first end 402 passes through the first cavity 201 and protrudes into the first through hole 301.
In one implementation, the first end 402 extends beyond the first through-hole 301. In some usage scenarios, the requirement for the angle of electron emission may be satisfied by extending the first end 402 out of the first through hole 301.
In one implementation, the shape of the electron emitter 40 may be conical as shown in fig. 5.
As shown in fig. 5, in some embodiments, the length L of the first end 402 of the electron emitter 40, along the direction of the central axis of the electron emitter 40, ranges from 50-100nm.
In some embodiments, when the electron emitter 40 is stacked on the substrate 10, the electron emitter 40 covers a partial region of the bottom surface of the first electron emission chamber 50. Fig. 6 is a schematic structural diagram of a first region 11 on a substrate 10 according to an embodiment of the present application.
As shown in fig. 6, in one implementation, the substrate 10 has a first region 11 on the upper surface, and the first region 11 refers to the other region on the bottom surface of the first electron emission chamber 50 than the region connected to the electron emitter 40.
In some embodiments, the first region 11 may be an annular region as shown in fig. 6.
The technical effects achieved by the first protective layer 60 according to the embodiment of the present application will be described in detail with reference to fig. 7a to 9 c.
The first protection layer 60 provided in the embodiment of the present application is formed on the outer wall surface of the electron emitter 40 and the inner wall surface of the first electron emission chamber 50, and the first protection layer 60 formed at different positions can achieve different technical effects. Therefore, in describing the technical effects achieved by the first protective layer 60, the first protective layer 60 is divided into different sub-areas to be described.
Referring to fig. 7a, 8a and 9a together, the first protective layer 60 may include a first sub protective layer 61, a second sub protective layer 62 and a third sub protective layer 63; as shown in fig. 7a, a first sub-protective layer 61 is formed on a first end 402 of the electron emitter 40; as shown in fig. 8a, the second sub-protective layer 62 is formed on the second portion 403 of the electron emitter 40 (the second portion 403 refers to the other region of the electron emitter 40 than the first end 402); as shown in fig. 9a, a third sub-protective layer 63 is formed on the inner wall surface of the first electron emission chamber 50.
The technical effects of the first sub-protective layer 61 are described below with reference to fig. 7a to 7 c.
As shown in fig. 7a, the first sub-protective layer 61 is formed on the first end 402 of the electron emitter 40.
Fig. 7b is a schematic view of the first end 402 of the electron emitter 40 in contact with the air outside the electron source chip. As shown in fig. 7b, since the external environment of the electron source chip (i.e. the space where electrons emitted from the electron source chip are reserved) cannot be guaranteed to be in absolute vacuum, gas molecules (such as oxygen molecules and carbon dioxide molecules) may exist, when the electron emitter 40 is exposed to the actual working environment of the electron source chip, the gas molecules may directly contact with the gas molecules, and the gas molecules may form a process of adsorption and desorption on the first end 402, so that the work function of the surface of the electron emitter 40 is changed, and the electron flow emitted from the electron emitter 40 is unstable, which affects the performance of the electron source chip.
As shown in fig. 7c, the embodiment of the present application prevents gas molecules (such as oxygen molecules and carbon dioxide molecules) from contacting the first end 402 of the electron emitter 40 by forming the first sub-protective layer 61 on the first end 402, so that the first end 402 of the electron emitter 40 cannot form a process of adsorption and desorption, thereby ensuring the stability of the electron flow emitted from the electron emitter 40.
The technical effects of the second sub-protective layer 62 are described below with reference to fig. 8a to 8 c.
As shown in fig. 8a, the first protective layer 60 includes a second sub-protective layer 62 in addition to the first sub-protective layer 61, the second sub-protective layer 62 being formed on the second portion of the electron emitter 40. The material of the first protective layer 60 has a certain work function, and a certain barrier height needs to be overcome when electrons are emitted. Since the electric field intensity of the first end 402 (i.e., the first portion of the electron emitter 40) is large, electrons of the first end 402 can be normally emitted; the second portion 403 of the electron emitter 40 has a small electric field intensity, and thus, the second sub-protective layer 62 can block electron emission on the second portion 403, thereby ensuring normal electron emission.
In one implementation, the first sub-protective layer 61 and the second sub-protective layer 62 are a unitary structure.
In one implementation, the thickness of the second sub-protective layer 62 is greater than the thickness of the first sub-protective layer 61. Specifically, when the first sub-protective layer 61 and the second sub-protective layer 62 are formed, the material may be coated on the outer wall surface of the electron emitter 40 with the same material and thickness, and then the material of the first sub-protective layer 61 is uniformly removed with a certain thickness, so that the first end 402 can normally emit electrons, and the electron emission on the second portion 403 can be blocked, thereby ensuring the normal emission of electrons.
Fig. 8b is a schematic view of electron emission from a second portion of the electron emitter 40. As shown in fig. 8b, in the actual operating environment of the electron source chip, not only the first end 402 of the electron emitter 40 emits electrons, but also the second portion 403 of the electron emitter 40 emits electrons. When the electron emitter 40 is exposed to the actual working environment of the electron source chip, electrons emitted outward from the second portion 403 are not introduced into the vacuum environment outside the electron source chip, but are emitted to the inner wall of the first electron emission chamber 50. Thus, electrons bombard the inner wall of the first electron emission chamber 50, damaging the first dielectric layer 20 and the first electrode layer 30. And electrons emitted to the inner wall of the first electron emission chamber 50 form secondary emission of electrons. Electrons emitted outward by the second portion 403 may cause bombardment of the first end 402 by electrons, resulting in deformation of the first end 402. Meanwhile, the secondarily emitted electrons may also cause an abnormal discharge phenomenon. These conditions all lead to abnormal electron emission.
Fig. 8c is an electron emission schematic diagram of the electron emitter 40 in the electron source chip according to an embodiment of the application. As shown in fig. 8c, in the embodiment of the present application, the second sub-protective layer 62 is formed on the outer wall surface of the second portion 403 on the electron emitter 40, so as to block the electron emission on the second portion 403, and prevent the electron from bombarding the inner wall of the first electron emission chamber 50, thereby protecting the first dielectric layer 20 and the first electrode layer 30. Electrons on the second portion 403 are not emitted, and secondary emission of electrons does not occur on the inner wall of the first electron emission chamber 50, thereby avoiding creepage breakdown. In addition, the electrons on the second portion 403 are not emitted, so that the first end 402 is not bombarded, thereby avoiding deformation of the first end 402 and further ensuring normal emission of electrons.
The technical effect of the third sub-protective layer 63 is described below with reference to fig. 9a to 9 c.
As shown in fig. 9a, in some embodiments, the first protective layer 60 includes a third sub-protective layer 63 in addition to the first sub-protective layer 61 and the second sub-protective layer 62. The third sub-protective layer 63 is formed on the inner wall surface of the first electron emission chamber 50.
In one implementation, the first sub-protective layer 61, the second sub-protective layer 62, and the third sub-protective layer 63 are a unitary structure.
Fig. 9b is a schematic diagram of electron movement at the intersection of a dielectric layer and vacuum and a substrate. As shown in fig. 9b, at the junction of the substrate 10, the first dielectric layer 20 and the vacuum, the outgoing electrons move toward the first electrode layer 30 along the inner wall of the first cavity 201 of the first dielectric layer 20, and during the movement, secondary electron emission, i.e. electron multiplication effect, is formed, resulting in creepage breakdown of the electrons along the inner wall of the first cavity 201 of the first dielectric layer 20.
Fig. 9c is a schematic diagram illustrating electron movement in the first electron emission chamber 50 of the electron source chip according to an embodiment of the present application. As shown in fig. 9c, in the embodiment of the present application, by forming the third sub-protective layer 63 on the inner wall surface of the first electron emission chamber 50, electrons in the first electron emission chamber 50 move on the third sub-protective layer 63, and the electrons do not directly contact the first dielectric layer 20 and the first electrode layer 30, so that the electron is prevented from creepage breakdown.
Therefore, the first protection layer 60 is covered on the outer wall surface of the electron emitter 10 and the inner wall surface of the first electron emission chamber 50 in the electron source chip provided by the embodiment of the application, and the first protection layer 60 can play a role in protecting the electron emitter 10, the first dielectric layer 20 and the first electrode layer 30, so that the stability and reliability of electron emission of the electron source chip are improved, normal emission of electrons is ensured, and meanwhile, the service life of the electron source chip is prolonged.
Fig. 10a is a schematic structural diagram of a first protection layer 60 according to an embodiment of the application. As shown in fig. 10a, the first protection layer 60 further includes a fourth sub-protection layer 64, where the fourth sub-protection layer 64 is formed on the upper surface 302 of the first electrode layer 30, and the upper surface 302 of the first electrode layer 30 is a surface of the first electrode layer 30 away from the first dielectric layer 20. Since the first electrode layer 30 includes at least one first via 301, the fourth sub-protective layer 64 is formed in a region other than the first via 301.
In one implementation, the third sub-protective layer 63 and the fourth sub-protective layer 64 are integrally formed, so that the area of the first electrode layer 30 and the first dielectric layer 20 exposed to vacuum is completely covered by the first protective layer 60, and a better protective effect can be obtained for the first electrode layer 30 and the first dielectric layer 20.
Fig. 10b is a schematic diagram of an electron movement outside the electron source chip. As shown in fig. 10b, when the first electrode layer 30 is exposed to the actual operating environment of the electron source chip, electrons emitted to the outside of the electron source chip through the electron emitters 40 may bombard the first electrode layer 30 due to charged particles existing in the environment.
As shown in fig. 10a, in the electron source chip provided in the embodiment of the present application, the fourth sub-protective layer 64 is formed on the upper surface 302 of the first electrode layer 30, so that the electron source chip is protected from the particle bombardment in the working environment on the basis of protecting the needle tip 10, the first dielectric layer 20 and the first electrode layer 30, the deformation of the needle tip is reduced, the field emission of the needle tip is stabilized, the stability and the reliability of the field emission electron source chip are further improved, the normal emission of electrons is ensured, and the service life of the electron source chip is prolonged.
In the above embodiment, each part of the electron source chip is covered with a protective layer, so that the product cost can be reduced while the electron source chip is protected.
However, for some electron source chips for emitting electrons, which have high requirements, in order to ensure reliability of electron emission, a multi-layered protective layer is formed on a portion of the electron source chip in addition to the first protective film formed on the electron source chip, thereby achieving the purpose of avoiding emission of electrons from other portions of the needle tip as much as possible without affecting emission of electrons from the first end of the needle tip. Thus, not only the first end of the needle tip can normally emit electrons.
An electron source chip provided with a plurality of protective layers is described below with reference to the drawings.
Fig. 11a is a schematic structural diagram of an electron source chip with multiple passivation layers according to an embodiment of the present application. As shown in fig. 11a, in some embodiments, the electron source chip further includes a second protective layer 70, the second protective layer 70 being formed on the second sub-protective layer 62. The second protective layer 70 is disposed so as not to affect the emission of electrons from the first end 402 of the electron emitter 40, but to reduce the escape of electrons from the sidewall surface of the second portion 403 of the electron emitter 40.
In another implementation, the first protective layer 60 and the second protective sub-layer 70 are integrally formed as a single piece by vacuum coating.
In one implementation, the substrate 10 is Si and has a thickness M in the range of 500-675 μm; the first dielectric layer 20 is made of SiO 2 The thickness of N ranges from 100nm to 2000nm; the first electrode layer 30 is made of Cr, and the thickness P thereof is 100-500nm; the electron emitter 40 is made of Si, and the height Q thereof is in the range of 500-2000nm; the first protective layer is made of AlN, and the thickness H of the first protective layer is 1-50nm; the second passivation layer 70 is made of SiN, and has a thickness G ranging from 10 nm to 100nm.
Fig. 11b is a schematic structural diagram of another electron source chip with multiple protection layers according to an embodiment of the present application. In other embodiments, as shown in fig. 11b, a second protective layer 70 is positioned between the second sub-protective layer 62 and the electron emitter 40. It should be noted that, for clearly showing the second protection layer 70, the first protection layer 60 in fig. 11b only shows part of the structures, i.e. the first sub protection layer 61 and the second sub protection layer 62, and other parts of the first protection layer 60 can be referred to the foregoing embodiments, which are not repeated herein.
Fig. 12 is a schematic structural diagram of another electron source chip with multiple protection layers according to an embodiment of the present application. As shown in fig. 12, in some embodiments, the second protective layer 70 is formed on the first protective layer 60 and is located on other portions of the first protective layer 60 than the first end 402.
Fig. 13 is a schematic structural diagram of another electron source chip 120 according to an embodiment of the present application. As shown in fig. 13, the electron source chip further includes a second dielectric layer 80 and a second electrode layer 90; the second dielectric layer 80 is stacked on the upper surface 302 of the first electrode layer and is located in a partial region of the upper surface 302. Specifically, the second dielectric layer 80 should be formed at a position avoiding the first through hole 301 on the first electrode layer 30, so that electrons emitted from the electron emitter 40 can be emitted through the first through hole 301.
The second dielectric layer 80 has a second cavity 801 formed therein, and the second cavity 801 is communicated with the first electron emission chamber 50 so that electrons emitted through the first through hole 301 continue to be emitted to the outside of the electron source chip through the second cavity 801.
And a second electrode layer 90 is stacked on a side of the second dielectric layer 80 away from the first electrode layer 30, and a second through hole 901 is disposed in the second electrode layer 90, and the second through hole 901 is communicated with the second cavity 801 to form a second electron emission chamber 51.
Thus, the first electron emission chamber 50, the second cavity 801, and the second through hole 901 are penetrated to each other, and electrons emitted from the electron emitter 40 can be emitted to the outside of the electron source chip through the first electron emission chamber 50, the second cavity 801, and the second through hole 901 in this order.
In some embodiments, the first protective layer 60 is also stacked on the inner wall of the second electron emission chamber 51.
In some embodiments, the first protective layer 60 is also stacked on the upper surface of the second electrode layer 90.
In one implementation, the substrate 10 is Si and has a thickness M in the range of 500-675 μm; the first dielectric layer 20 is made of SiO 2 The thickness N is 100-2000nm; the material of the first electrode layer 30 is Nd, and the thickness P thereof is 100-500nm; the electron emitter 40 is made of Mo, and the height Q thereof is in the range of 500-2000nm; the first protective layer is made of AlN, and the thickness H of the first protective layer is 1-50nm; the second dielectric layer 20 is made of SiO 2 The thickness I is 100-2000nm; the second electrode layer 90 is made of Nd, and the thickness J thereof ranges from 100 nm to 500nm.
In some embodiments, the electron source chip may further include a plurality of electrode layers and dielectric layers in addition to the first dielectric layer 20, the first electrode layer 30, the second dielectric layer 80 and the second electrode layer 90, and the present application is not particularly limited with respect to the number of electrode layers and dielectric layers.
The embodiment of the present application further provides a method for manufacturing the electron source chip 120, and in detail, a method for manufacturing the electron source chip 120 is described below with reference to the process flow chart shown in fig. 14 and the process structure diagrams shown in fig. 15a to 15 e. As shown in fig. 14, the process flow diagram includes steps S100-S500;
in step S100, as shown in fig. 15a, a first dielectric layer 20 is stacked on a substrate 10.
In step S200, as shown in fig. 15b, the first electrode layer 30 is stacked on the side of the first dielectric layer 20 away from the substrate 10.
In step S300, as shown in fig. 15c, a first electron emission chamber 50 is opened on the first electrode layer 30, and the first electron emission chamber 50 penetrates the first dielectric layer 20 and the first electrode layer 30 to the substrate 10 along the stacking direction.
In step S400, as shown in fig. 15d, electron emitters 40 are disposed in the first electron emission chamber 50, and the electron emitters 40 are stacked on the substrate 10.
In step S500, as shown in fig. 15e, the first protective layer 60 is formed on both the outer wall surface of the electron emitter 40 and the inner wall surface of the first electron emission chamber 50.
The electron source chip manufactured by the manufacturing method is characterized in that the outer wall surface of the electron emitter 40 and the inner wall surface of the first electron emission chamber 50 are covered with the first protection layer 60, the first protection layer 60 can play a role in protecting the electron emitter 40, the first dielectric layer 20 and the first electrode layer 30, the stability and reliability of electron emission of the electron source chip are improved, normal electron emission is guaranteed, and meanwhile, the service life of the electron source chip is prolonged.
Fig. 16 is a process flow diagram of another method for manufacturing an electron source chip according to an embodiment of the present application. As shown in fig. 16, in some embodiments, when step S500 is performed, that is, when the first protective layer 60 is formed on both the outer wall surface of the electron emitter 40 and the inner wall surface of the first electron emission chamber 50, the manufacturing method further includes step S601;
in step S601, as shown in fig. 17, a first protective layer 60 is formed on a surface of the first electrode layer 30 remote from the first dielectric layer 20.
In this way, the manufactured electron source chip can protect the first electrode layer 30 from electrons or particles outside the electron source chip.
Fig. 18 is a process flow diagram of another method for manufacturing an electron source chip according to an embodiment of the present application. As shown in fig. 18, when step S400 is performed, that is, when the electron emitter 40 is disposed in the first electron emission chamber 50, the electron emitter 40 includes a first end remote from the substrate 10 for emitting electrons to the outside of the electron source chip; after performing step S500, that is, after forming the first protective layer 60 on the outer wall surface of the electron emitter 40 and the inner wall surface of the first electron emission chamber 50, the manufacturing method further includes step S602;
s602, as shown in fig. 19, the second protective layer 70 is formed on the first protective layer 60, and the second protective layer 70 is located on the other region of the first protective layer 60 than the first end. The electron emitter 40 has a first protective layer 60 and a second protective layer 70.
Thus, the electron source chip is manufactured to have only the first protective layer 60 at the first end of the electron emitter 40, i.e., to have a single-layer structure; the first protective layer 60 and the second protective layer 70 are disposed on the electron emitter 40 at other positions than the first end, i.e., in a double-layer structure; the electron emission at the first end is ensured and the electron emission at other positions than the first end of the electron emitter 40 is reduced.
Fig. 20 is a process flow diagram of a method for manufacturing an electron source chip according to another embodiment of the present application. As shown in fig. 20, when step S400 is performed, that is, when the electron emitter 40 is disposed in the first electron emission chamber 50, the electron emitter 40 includes a first end remote from the substrate 10 for emitting electrons to the outside of the electron source chip; before performing step S500, that is, before forming the first protective layer 60 on the outer wall surface of the electron emitter 40 and the inner wall surface of the first electron emission chamber 50, the manufacturing method further includes step S603;
s603, as shown in fig. 21, a second protective layer 70 is formed on the outer wall surface of the electron emitter 40, and the second protective layer 70 is located on the other region of the electron emitter 40 than the first end. Fig. 22 is a process flow diagram of a method for manufacturing an electron source chip according to another embodiment of the present application. As shown in fig. 22, after performing the above step S200 and before performing the above step S300, the preparation method further includes steps S310 to S510;
s310, as shown in fig. 23a, the second dielectric layer 80 is stacked on the side of the first electrode layer 30 away from the first dielectric layer 20.
S410, as shown in fig. 23b, the second electrode layer 90 is stacked on the side of the second dielectric layer 80 away from the first electrode layer 30.
S510, as shown in fig. 23c, a second electron emission chamber 51 penetrating through the second dielectric layer 80 and the second electrode layer 90 is opened on the second electrode layer 90 in the stacking direction.
S610, as shown in fig. 23c, the first electron emission chamber 50 and the second electron emission chamber 51 are penetrated.
In some embodiments, after forming the first protective layer 60 on the outer wall surface of the electron emitter 40 and the inner wall surface of the first electron emission chamber 50, the manufacturing method further includes: a first protective layer 60 is formed on the inner wall of the second electron emission chamber 51.
In some embodiments, after forming the first protective layer 60 on the outer wall surface of the electron emitter 40 and the inner wall surface of the first electron emission chamber 50, the manufacturing method further includes: a first protective layer 60 is formed on the surface of the second electrode layer 90 remote from the second dielectric layer 80.
In some embodiments, the electron emitter 40 may be formed on the substrate 10, then the first dielectric layer 20 and the first electrode layer 30 are formed, and finally the electron emission chamber 50 is formed. In addition, the protection layer process is the same as above, and will not be repeated.
The electron source chip prepared by the preparation method provided by the embodiment can improve the stability and reliability of emitted electrons and prolong the service life.
In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (18)

1. An electron source chip, comprising:
a substrate;
a first dielectric layer stacked on the substrate;
the first electrode layer is stacked on one side, far away from the substrate, of the first dielectric layer, and a first electron emission cavity penetrating through the first dielectric layer and the first electrode layer along the stacking direction and reaching the substrate is formed in the first electrode layer;
an electron emitter located within the first electron emission chamber and stacked on the substrate;
the first protection layer is formed on the outer wall surface of the electron emitter and the inner wall surface of the first electron emission chamber.
2. The electron source chip according to claim 1, wherein the first protective layer is formed on a surface of the first electrode layer remote from the first dielectric layer.
3. The electron source chip according to claim 1 or 2, wherein the electron emitter comprises a first end remote from the substrate, the first end being for emitting electrons to the outside of the electron source chip;
the electron source chip further includes:
and a second protective layer formed on the first protective layer and located on other regions of the first protective layer than the first end.
4. The electron source chip according to claim 1 or 2, wherein the electron emitter comprises a first end remote from the substrate, the first end being for emitting electrons to the outside of the electron source chip; the electron source chip further includes:
and a second protective layer formed between the first protective layer and the electron emitter and located between the remaining region of the first protective layer excluding the first end and an outer wall surface of the electron emitter.
5. The electron source chip according to any one of claims 1 to 4, further comprising:
The second dielectric layer is stacked on one side of the first electrode layer away from the first dielectric layer;
the second electrode layer is stacked on one side, far away from the first electrode layer, of the second dielectric layer, and a second electron emission cavity penetrating through the second dielectric layer and the second electrode layer along the stacking direction is formed in the second electrode layer;
wherein the first electron emission chamber and the second electron emission chamber are penetrated.
6. The electron source chip according to claim 5, wherein the first protective layer is formed on an inner wall of the second electron emission chamber.
7. The electron source chip according to claim 6, wherein the first protective layer formed on the inner wall of the second electron emission chamber, the outer wall surface of the electron emitter, and the inner wall surface of the first electron emission chamber is an integral structure.
8. The electron source chip according to any one of claims 5 to 7, wherein the first protective layer is formed on a surface of the second electrode layer remote from the second dielectric layer.
9. The electron source chip according to claim 5, wherein a radial dimension of the first electron emission chamber is smaller than a radial dimension of the second electron emission chamber.
10. The electron source chip according to any one of claims 1 to 9, wherein the first protective layer is a dielectric material having a hardness of 2.3GPa or more, and a material work function of the dielectric material is less than 4.9eV.
11. A method of manufacturing an electron source chip, comprising:
stacking a first dielectric layer on a substrate;
stacking a first electrode layer on one side of the first dielectric layer away from the substrate;
a first electron emission chamber is arranged on the first electrode layer, and penetrates through the first dielectric layer and the first electrode layer to the substrate along the stacking direction;
disposing an electron emitter in the first electron emission chamber, and stacking the electron emitter on the substrate;
a first protective layer is formed on the outer wall surface of the electron emitter and on the inner wall surface of the first electron emission chamber.
12. The method of manufacturing an electron source chip according to claim 11, wherein when the first protective layer is formed on the outer wall surface of the electron emitter and the inner wall surface of the first electron emission chamber, the method further comprises:
and forming the first protection layer on the surface of the first electrode layer away from the first dielectric layer.
13. The method of manufacturing an electron source chip according to claim 11 or 12, wherein the electron emitter includes a first end remote from the substrate, the first end being for emitting electrons to the outside of the electron source chip;
after the first protective layer is formed on the outer wall surface of the electron emitter and the inner wall surface of the first electron emission chamber, the manufacturing method further includes:
a second protective layer is formed on the first protective layer, and the second protective layer is located on other areas of the first protective layer than the first end.
14. The method of manufacturing an electron source chip according to claim 11 or 12, wherein the electron emitter includes a first end remote from the substrate, the first end being for emitting electrons to the outside of the electron source chip;
before the first protective layer is formed on the outer wall surface of the electron emitter and the inner wall surface of the first electron emission chamber, the manufacturing method further includes:
a second protective layer is formed on an outer wall surface of the electron emitter, and the second protective layer is located on other regions of the electron emitter than the first end.
15. The method of any one of claims 11 to 14, wherein after stacking a first electrode layer on a side of the first dielectric layer remote from the substrate; before a first electron emission chamber is formed on the first electrode layer; the preparation method further comprises the following steps:
stacking a second dielectric layer on one side of the first electrode layer away from the first dielectric layer;
stacking a second electrode layer on one side of the second dielectric layer away from the first electrode layer;
a second electron emission chamber penetrating through the second dielectric layer and the second electrode layer is formed on the second electrode layer along the stacking direction;
and penetrating the first electron emission chamber and the second electron emission chamber.
16. The method of manufacturing an electron source chip according to claim 15, wherein after the first protective layer is formed on the outer wall surface of the electron emitter and the inner wall surface of the first electron emission chamber, the method further comprises:
the first protective layer is formed on an inner wall of the second electron emission chamber.
17. The method of manufacturing an electron source chip according to claim 15 or 16, wherein after the first protective layer is formed on the outer wall surface of the electron emitter and on the inner wall surface of the first electron emission chamber, the method further comprises:
And forming the first protection layer on the surface of the second electrode layer away from the second dielectric layer.
18. An electronic device, comprising:
a printed circuit board;
an electron source chip according to any one of claims 1 to 10, or an electron source chip produced by the production method of an electron source chip according to any one of claims 11 to 17; the electron source chip is arranged on the printed circuit board.
CN202210582986.2A 2022-05-26 2022-05-26 Electronic source chip, preparation method thereof and electronic equipment Pending CN117174549A (en)

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JP3705803B2 (en) * 2002-07-01 2005-10-12 松下電器産業株式会社 Phosphor light emitting element, method for manufacturing the same, and image drawing apparatus
TW200713377A (en) * 2005-09-13 2007-04-01 Teco Elec & Machinery Co Ltd Method of gaining life-span and adhesion for the electrophoresis-deposition electron emitter
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