CN117174030A - Pixel driving circuit and display panel - Google Patents

Abstract

The invention relates to the field of circuits of display panels, and provides a pixel driving circuit and a display panel, wherein the pixel driving circuit comprises: the first transistor to the seventh transistor, the first capacitor to the second capacitor, 1 data signal line, 1 light emission control signal line, 4 scan signal lines. According to the pixel driving circuit and the display panel, the main components of the emission charge recycling structure and the high-frequency anode resetting structure are formed through the high-frequency third scanning signal, the high-frequency fourth scanning signal, the third transistor and the seventh transistor, so that brightness fluctuation of the display panel caused by defect charge emission is reduced, and picture quality is improved; meanwhile, the influence of the voltage drop of the power supply voltage on the brightness is reduced by storing the potential difference of the gate source and the constant potential as a reference point through a capacitor; in addition, by separating threshold voltage sampling and data storage, full compensation at high refresh rates is realized, and image quality is improved.

Description

Pixel driving circuit and display panel

Technical Field

The present invention relates to the field of circuits of display panels, and in particular, to a pixel driving circuit and a display panel.

Background

Compared with the liquid crystal display panel in the prior art, the OLED (Organic Light Emitting Diode ) display panel has the characteristics of higher reaction speed, better color purity and brightness, higher contrast, wider visual angle and the like, and therefore, the display technology developer is gradually getting attention of increasing wide. The OLED display panel comprises a pixel array and a pixel driving circuit for controlling the pixel array, and luminescent pixels in the pixel array emit light under the combined action of the pixel driving circuit, the scanning driving circuit and the luminescent driving circuit.

In the static picture scene of the OLED display panel, the power consumption can be remarkably reduced by reducing the refresh rate. At a low refresh rate, in the pixel Driving circuit, brightness fluctuation of the display panel caused by drift of a threshold voltage Vth of a Driving transistor (Driving TFT) within one frame, charge delay of an OLED device, defective charge emission of a switching transistor (switching TFT) after switching, and the like affects the use experience and picture quality.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the invention and thus may include information that does not form the prior art that is already known to those of ordinary skill in the art.

Disclosure of Invention

In view of the above, the present invention provides a pixel driving circuit and a display panel to solve at least the above problems.

One aspect of the present invention provides a pixel driving circuit including:

a first transistor having a first electrode connected to the data signal, a second electrode connected to the third node, and a gate connected to the second scan signal;

a second transistor having a first electrode connected to the first node, a second electrode connected to the fourth node, and a gate connected to the second node;

a third transistor having a first electrode connected to the third node, a second electrode connected to the second node, and a gate connected to a third scan signal;

a fourth transistor having a first electrode connected to a first power supply voltage, a second electrode connected to the first node, and a gate connected to a light emission control signal;

a fifth transistor having a first electrode connected to the fourth node, a second electrode connected to the first electrode of the light emitting diode, and a gate connected to the light emission control signal;

a sixth transistor having a first electrode connected to the third node, a second electrode connected to a first reference voltage, and a gate connected to a first scan signal;

a seventh transistor, a second pole of which is connected to the fourth node, and a gate of which is connected to a fourth scan signal;

a first capacitor, a first pole of which is connected to the second node, and a second pole of which is connected to the first node;

and the first electrode of the second capacitor is connected with the first node, and the second electrode of the second capacitor is connected with the light-emitting control signal.

In some embodiments, a second pole of the light emitting diode is connected to a second supply voltage.

In some embodiments, the first pole of the seventh transistor is connected to a second supply voltage.

In some embodiments, the first pole of the seventh transistor is connected to a second reference voltage.

In some embodiments, the first transistor to the seventh transistor are P-type MOS transistors.

In some embodiments, the first transistor to the second transistor, the fourth transistor to the seventh transistor are P-type MOS transistors, and the third transistor is an N-type MOS transistor.

In some embodiments, the frequencies of the light emission control signal, the third scan signal and the fourth scan signal are the same, the frequencies of the first scan signal and the second scan signal are the same, and the frequency of the light emission control signal is at least twice the frequency of the first scan signal within one frame of picture time.

In some embodiments, in a frame of time, a first falling edge of the third scan signal is the same as a falling edge of the first scan signal, and a first rising edge of the third scan signal is the same as a rising edge of the second scan signal.

In some embodiments, in a frame of time, a first rising edge of the third scan signal is the same as a falling edge of the first scan signal, and a first falling edge of the third scan signal is the same as a rising edge of the second scan signal.

In some embodiments, the first falling edge and the first rising edge of the fourth scan signal are the same as the falling edge and the rising edge of the first scan signal in one frame of picture time.

Another aspect of the present invention also provides a display panel, which includes the pixel driving circuit described in any one of the above.

Compared with the prior art, the invention has the beneficial effects that at least:

according to the pixel driving circuit and the display panel, the main components of the emission charge recycling structure and the high-frequency anode resetting structure are formed through the high-frequency third scanning signal, the high-frequency fourth scanning signal, the third transistor and the seventh transistor, so that brightness fluctuation of the display panel caused by defect charge emission is reduced, and picture quality is improved; meanwhile, the influence of the voltage drop of the power supply voltage on the brightness is reduced by storing the potential difference of the gate source and the constant potential as a reference point through a capacitor; in addition, by separating threshold voltage sampling and data storage, full compensation at high refresh rates is realized, and image quality is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is evident that the drawings in the following description are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.

Fig. 1 shows a schematic circuit structure of a display panel of the present invention;

fig. 2 shows a circuit diagram of a first embodiment of the pixel driving circuit of the invention;

fig. 3 shows a waveform diagram when the pixel driving circuit shown in fig. 2 is operated;

FIG. 4 is a schematic diagram showing the operation of the pixel driving circuit at stage t1 in FIG. 3;

FIG. 5 is a schematic diagram showing the operation of the pixel driving circuit at stage t2 in FIG. 3;

FIG. 6 is a schematic diagram showing the operation of the pixel driving circuit at stage t3 in FIG. 3;

FIG. 7 is a schematic diagram showing the operation of the pixel driving circuit at stage t4 in FIG. 3;

FIG. 8 is a schematic diagram showing the operation of the pixel driving circuit at stage t5 in FIG. 3;

FIG. 9 is a schematic diagram showing the operation of the pixel driving circuit at stage t6 in FIG. 3;

FIG. 10 is a schematic diagram showing the operation of the pixel driving circuit at stage t7 in FIG. 3;

FIG. 11 is a schematic diagram showing the operation of the pixel driving circuit at stage t8 in FIG. 3;

fig. 12 shows a circuit diagram of a second embodiment of the pixel driving circuit of the invention;

fig. 13 shows a waveform diagram when the pixel driving circuit shown in fig. 12 is operated;

fig. 14 shows a circuit diagram of a third embodiment of the pixel driving circuit of the invention.

Reference numerals:

10. display panel

11. Display area

111. Pixel driving circuit

121. Data driver

DATA DATA signal

ELVDD first supply voltage

ELVSS second supply voltage

EM light emission control signal

Scan1 first Scan signal

Scan2 second Scan signal

Scan3 third Scan Signal

Scan4 fourth Scan signal

Ref1 first reference voltage

Ref2 second reference voltage

T1 first transistor

T2 second transistor

T3 third transistor

T4 fourth transistor

T5 fifth transistor

T6 sixth transistor

T7 seventh transistor

C1 First capacitor

C2 Second capacitor

N1 first node

N2 second node

N3 third node

N4 fourth node

D light emitting diode

Detailed Description

In order to make the technical problems solved by the present invention, the technical solutions adopted and the technical effects achieved more clear, the technical solutions of the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the disclosed aspects may be practiced without one or more of the specific details, or with other methods, modules, apparatus, steps, etc. In other instances, well-known modules, methods, devices, implementations, steps, or operations have not been shown or described in detail to avoid obscuring aspects of the disclosure.

The present inventors have made intensive studies to provide a solution to the problems existing in the prior art. Fig. 1 shows a schematic circuit structure of a display panel of the present invention. Fig. 2 shows a circuit diagram of a first embodiment of the pixel driving circuit of the invention. Fig. 12 shows a circuit diagram of a second embodiment of the pixel driving circuit of the invention. Fig. 14 shows a circuit diagram of a third embodiment of the pixel driving circuit of the invention. As shown in fig. 1, 2, 12 and 14, the present invention discloses a plurality of pixel driving circuits 111 and a display panel 10, wherein the pixel driving circuits 111 at least comprise: the first transistor to the seventh transistor, the first capacitor to the second capacitor, 1 data signal line, 1 light emission control signal line, 4 scan signal lines. The pixel driving circuit 111 and the display panel 10 of the invention control the third transistor T3 and the seventh transistor T7 through the third Scan signal Scan3 and the fourth Scan signal Scan4 of high frequency to form the main components of the emission charge recycling structure and the high frequency anode resetting structure together, thereby reducing the brightness fluctuation of the display panel caused by the emission of defective charges and improving the picture quality; meanwhile, the influence of the voltage drop of the power supply voltage on the brightness is reduced by storing the potential difference of the gate source and the constant potential as a reference point through the first capacitor C1; in addition, by separating the threshold voltage Vth sampling and the data storage, sufficient compensation at a high refresh rate is realized, and image quality is improved.

The technical scheme of the invention is further described below by the specific embodiments with reference to the accompanying drawings.

As shown in fig. 1, one aspect of the present invention provides a display panel 10, the display panel 10 including a display region 11 and a non-display region. Wherein the scan driving circuit, the light emitting driving circuit and the data driver 121 are located in the non-display area of the display panel 10. The plurality of DATA signal lines are connected to the DATA driver 121, and the DATA driver 121 supplies the DATA signal DATA to the light emitting pixels through the plurality of DATA signal lines. The display area 11 includes light emitting pixels arranged in an array, each having a pixel driving circuit 111 controlling light emission thereof. The light emitting pixels emit light at least by the combined action of the scan driving circuit, the light emitting driving circuit, the pixel driving circuit 111, and the data driver 121.

Based on the same inventive concept, another aspect of the present invention provides some pixel driving circuits 111. As shown in fig. 2, a pixel driving circuit 111 of the first embodiment of the present invention includes: the first transistor T1 to the seventh transistor T7, and the first capacitor C1 to the second capacitor C2. The first transistor T1 has a first pole connected to the DATA signal DATA, a second pole connected to the third node N3, and a gate connected to the second Scan signal Scan2. The first pole of the second transistor T2 is connected to the first node N1, the second pole is connected to the fourth node N4, and the gate is connected to the second node N2. The third transistor T3 has a first pole connected to the third node N3, a second pole connected to the second node N2, and a gate connected to the third Scan signal Scan3. The fourth transistor T4 has a first electrode connected to the first power voltage ELVDD, a second electrode connected to the first node N1, and a gate connected to the emission control signal EM. The fifth transistor T5 has a first electrode connected to the fourth node N4, a second electrode connected to the first electrode of the light emitting diode D, and a gate connected to the emission control signal EM. The sixth transistor T6 has a first pole connected to the third node N3, a second pole connected to the first reference voltage Ref1, and a gate connected to the first Scan signal Scan1. The second pole of the seventh transistor T7 is connected to the fourth node N4, and the gate is connected to the fourth Scan signal Scan4. The first pole of the first capacitor C1 is connected to the second node N2, and the second pole is connected to the first node N1. The first pole of the second capacitor C2 is connected to the first node N1, and the second pole is connected to the emission control signal EM.

In this embodiment, in addition to the above connection relationship, the method further includes: the first pole of the seventh transistor T7 is connected to the second power supply voltage ELVSS. The second diode of the light emitting diode D is connected to the second power voltage ELVSS. The light emitting diode D may be an OLED or an AMOLED (Active-matrix organic light emitting diode, active matrix organic light emitting diode or Active matrix organic light emitting diode), and the first electrode of the light emitting diode D is an anode and the second electrode is a cathode. The first power voltage ELVDD is a positive power voltage, and the second power voltage ELVSS is a negative power voltage, but not limited thereto.

In this embodiment, the first transistor T1 to the seventh transistor T7 are P-type MOS transistors. The P-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is called P-type MOS tube or PMOS tube for short. The control end of the PMOS tube is a grid electrode, the first electrode is a source electrode, the second electrode is a drain electrode, or the first electrode is a drain electrode, and the second electrode is a source electrode. The on level of the PMOS tube is low level, and the off level is high level. In other embodiments, those skilled in the art can easily understand that the pixel driving circuit 111 provided by the present invention can be easily changed to be an N-type MOS transistor or a hybrid CMOS transistor. It should be noted that, the high and low levels of the transistors are exemplified by PMOS transistors in the following, and when other corresponding transistor types are selected according to design requirements, the high and low levels of the transistors are correspondingly changed.

In the present embodiment, the first reference voltage Ref1 is constant and is lower than the lowest potential of the DATA signal DATA. In other embodiments, the first reference voltage Ref1 may be slightly adjusted to meet specific display requirements.

Fig. 3 shows a waveform diagram when the pixel driving circuit shown in fig. 2 is operated. Fig. 4 shows a schematic diagram of an operating state of the pixel driving circuit at the t1 stage in fig. 3. Fig. 5 shows a schematic diagram of an operating state of the pixel driving circuit at the t2 stage in fig. 3. Fig. 6 shows a schematic diagram of an operating state of the pixel driving circuit at the stage t3 in fig. 3. Fig. 7 shows a schematic diagram of an operating state of the pixel driving circuit at the t4 stage in fig. 3. Fig. 8 shows a schematic diagram of an operating state of the pixel driving circuit at the stage t5 in fig. 3. Fig. 9 shows a schematic diagram of an operating state of the pixel driving circuit at the stage t6 in fig. 3. Fig. 10 shows a schematic diagram of an operating state of the pixel driving circuit at the stage t7 in fig. 3. Fig. 11 shows a schematic diagram of an operating state of the pixel driving circuit at the stage t8 in fig. 3.

The pixel driving circuit 111 in the embodiment can operate at a low frequency, wherein the low frequency is that the operation frequency is less than 60Hz, but the lowest operation frequency is 1Hz, but not limited thereto. Specifically, fig. 3 may be a timing chart of the pixel driving circuit 111 of the present invention in the case where the operation frequency is 60Hz, black is interpolated and light is emitted 2 times per frame. Of course, the pixel driving circuit 111 of the present invention may also be black inserted and emit light multiple times in each frame, and only needs to repeat the t5 to t8 phases after the t1 to t4 phases. The following description will be given by taking 2 times as an example only:

as shown in fig. 3, in the present embodiment, the emission control signal EM, the third Scan signal Scan3, and the fourth Scan signal Scan4 each include two falling edges and two rising edges within one frame of the frame time. The first Scan signal Scan1 and the second Scan signal Scan2 each include only one falling edge and one rising edge. That is, in one frame of the screen time, the frequencies of the emission control signal EM, the third Scan signal Scan3, and the fourth Scan signal Scan4 are the same, the frequencies of the first Scan signal Scan1 and the second Scan signal Scan2 are the same, and the frequency of the emission control signal EM is twice the frequency of the first Scan signal Scan1. Specifically, the first falling edge of the third Scan signal Scan3 is the same as the falling edge of the first Scan signal Scan1, and the first rising edge of the third Scan signal Scan3 is the same as the rising edge of the second Scan signal Scan2. The first falling edge and the first rising edge of the fourth Scan signal Scan4 are the same as the falling edge and the rising edge of the first Scan signal Scan1.

As shown in fig. 3, in the present embodiment, the operation of the pixel driving circuit 111 is divided into 8 stages, t1 to t8 respectively, within one frame time of the display screen. Of these 8 processes, the light emitting diode D in the pixel driving circuit 111 described above completes the process from black insertion to light emission twice. Note that, for ease of understanding, "x" in fig. 4 to 11 indicates that the transistor is turned off. The relationship between the input of the pixel driving circuit 111 and the light emission in the above 8 processes is analyzed by combining the waveform diagram of fig. 3 and the circuit diagram of fig. 2:

as shown in fig. 3 and 4, in the t1 stage, the emission control signal EM is inputted with a low level, the first Scan signal Scan1 is inputted with a low level, the second Scan signal Scan2 is inputted with a high level, the third Scan signal Scan3 is inputted with a low level, and the fourth Scan signal Scan4 is inputted with a low level. The first transistor T1 is turned off, and the second to seventh transistors T2 to T7 are turned on. In this stage, since the seventh transistor T7 is turned on, the light emitting diode D is shorted out, and no light is emitted at this time, and this stage is a reset stage. The first reference voltage Ref1 writes a low voltage to the second node N2, i.e. the gate of the second transistor T2, through the sixth transistor T6 and the third transistor T3 to reset the second transistor T2. At the same time, the third transistor T3 is turned on and captures charge from the first reference voltage Ref1 through the sixth transistor T6.

As shown in fig. 3 and 5, at the t2 stage, the emission control signal EM is inputted with a high level, the first Scan signal Scan1 is inputted with a low level, the second Scan signal Scan2 is inputted with a high level, the third Scan signal Scan3 is inputted with a low level, and the fourth Scan signal Scan4 is inputted with a low level. The first, fourth and fifth transistors T1, T4 and T5 are turned off, and the second, third, sixth and seventh transistors T2, T3, T6 and T7 are turned on. In this stage, the light emission control signal EM is inputted to high level to turn off the fourth transistor T4 and the fifth transistor T5, and the light emitting diode D does not emit light. The first reference voltage Ref1 continues to write a low voltage to the second node N2, i.e. the gate of the second transistor T2, through the sixth transistor T6 and the third transistor T3 to record the threshold voltage Vth of the second transistor T2. The potential of the light emission control signal EM is raised by the coupling of the second capacitor C2 at the moment when the potential of the light emission control signal EM changes from low to high. Then, since the gate potential is the first reference voltage Ref1, the second transistor T2 is in an on state, and the second transistor T2 connects the first node N1 and the fourth node N4. Therefore, the potential of the first node N1 decreases to VRef1-Vth, and the potential difference stored in the first capacitor C1 is Vth. At the same time, the third transistor T3 is turned on and continues to capture charge from the first reference voltage Ref1 through the sixth transistor T6.

As shown in fig. 3 and 6, at the t3 stage, the emission control signal EM is inputted with a high level, the first Scan signal Scan1 is inputted with a high level, the second Scan signal Scan2 is inputted with a low level, the third Scan signal Scan3 is inputted with a low level, and the fourth Scan signal Scan4 is inputted with a high level. The fourth to seventh transistors T4 to T7 are turned off, and the first to third transistors T1 to T3 are turned on. In this stage, the light emission control signal EM is inputted to high level to turn off the fourth transistor T4 and the fifth transistor T5, and the light emitting diode D does not emit light. The DATA signal DATA writes a DATA potential to the second node N2, i.e., the gate of the second transistor T2, through the first transistor T1 and the third transistor T3. The potential variation of the second node N2 is Δvn2=vdata-VRef 1, and the potential variation of the corresponding first node N1 is:

the potential difference stored in the first capacitor C1 at this time is vth+Δvn2- Δvn1. By storing the gate-source potential difference instead of the gate potential in the first capacitor C1 and adding the first reference voltage Ref1 as the reference point, the light emission current is independent of the potential value of the first power supply voltage ELVDD, so that the influence of the voltage drop (IR drop) of the first power supply voltage ELVDD on the brightness is reduced, and the brightness unevenness caused by the voltage drop (IR drop) under a large-size panel is improved. Meanwhile, the third transistor T3 is turned on and captures charges from the DATA signal DATA through the first transistor T1. In the stage from T2 to T3, the sampling and data storage of the threshold voltage Vth of the second transistor T2 are separated, so that the threshold voltage Vth compensation can be performed between adjacent rows simultaneously, thereby greatly relaxing the limitation of the number of rows and the high refresh rate on the compensation time, realizing the full compensation under the high refresh rate and improving the image quality.

As shown in fig. 3 and 7, at the t4 stage, the emission control signal EM is inputted with a low level, the first Scan signal Scan1 is inputted with a high level, the second Scan signal Scan2 is inputted with a high level, the third Scan signal Scan3 is inputted with a high level, and the fourth Scan signal Scan4 is inputted with a high level. The first, third, sixth and seventh transistors T1, T3, T6 and T7 are turned off, and the second, fourth and fifth transistors T2, T4 and T5 are turned on. In this stage, the first power voltage ELVDD and the second power voltage ELVSS act on both ends of the light emitting diode D to emit light. At the same time, the third transistor T3 is turned off and charges are emitted into the first capacitor C1, resulting in an increase in the potential of the second node N2, and the brightness of the light emitting diode D gradually decreases, so that the brightness of the display panel decreases.

As shown in fig. 3 and 8, at the t5 stage, the emission control signal EM is inputted with a low level, the first Scan signal Scan1 is inputted with a high level, the second Scan signal Scan2 is inputted with a high level, the third Scan signal Scan3 is inputted with a low level, and the fourth Scan signal Scan4 is inputted with a low level. The first transistor T1 and the sixth transistor T6 are turned off, and the second transistor T2 to the fifth transistor T5 and the seventh transistor T7 are turned on. In this stage, the first power voltage ELVDD and the second power voltage ELVSS act on both ends of the light emitting diode D to emit light. At the same time, the third transistor T3 is turned on again, and charges are trapped in the first capacitor C1, recovering the channel defect tied to the third transistor T3, and lowering the potential of the second node N2.

As shown in fig. 3 and 9, at the t6 stage, the emission control signal EM is inputted with a high level, the first Scan signal Scan1 is inputted with a high level, the second Scan signal Scan2 is inputted with a high level, the third Scan signal Scan3 is inputted with a low level, and the fourth Scan signal Scan4 is inputted with a low level. The first transistor T1 and the fourth to sixth transistors T4 to T6 are turned off, and the second and third to seventh transistors T2, T3 to T7 are turned on. In this stage, the light emission control signal EM is inputted to high level to turn off the fourth transistor T4 and the fifth transistor T5, and the light emitting diode D does not emit light. At the same time, the third transistor T3 remains on and continues to trap charge from the first capacitor C1, recovering the channel defect tied to the third transistor T3, causing the potential of the second node N2 to continue to drop.

As shown in fig. 3 and 10, at the t7 stage, the emission control signal EM is inputted with a high level, the first Scan signal Scan1 is inputted with a high level, the second Scan signal Scan2 is inputted with a high level, the third Scan signal Scan3 is inputted with a low level, and the fourth Scan signal Scan4 is inputted with a high level. The first transistor T1 and the fourth to seventh transistors T4 to T7 are turned off, and the second and third transistors T2 and T3 are turned on. In this stage, the light emission control signal EM is inputted to high level to turn off the fourth transistor T4 and the fifth transistor T5, and the light emitting diode D does not emit light. At the same time, the third transistor T3 remains on and continues to trap charge from the first capacitor C1, recovering the channel defect tied to the third transistor T3, causing the potential of the second node N2 to continue to drop.

As shown in fig. 3 and 11, at the t8 stage, the emission control signal EM is inputted with a low level, the first Scan signal Scan1 is inputted with a high level, the second Scan signal Scan2 is inputted with a high level, the third Scan signal Scan3 is inputted with a high level, and the fourth Scan signal Scan4 is inputted with a high level. The first, third, sixth and seventh transistors T1, T3, T6 and T7 are turned off, and the second, fourth and fifth transistors T2, T4 and T5 are turned on. In this stage, the first power voltage ELVDD and the second power voltage ELVSS act on both ends of the light emitting diode D to emit light, and the luminance reaches the luminance before the third transistor T3 emits charges. At the same time, the third transistor T3 is turned off again and charges are emitted into the first capacitor C1 again, resulting in the potential of the second node N2 rising again.

In the present embodiment, the pixel driving circuit 111 controls the third transistor T3 and the seventh transistor T7 using the third Scan signal Scan3 and the fourth Scan signal Scan4 of high frequency to implement emission charge recycling and high frequency anode resetting, and the charging process thereof is divided into three steps of driving transistor resetting, driving transistor threshold voltage Vth recording and driving transistor data writing, and by reasonably setting the recording time of the first capacitor C1, the second capacitor C2 and the driving transistor threshold voltage Vth, sufficient compensation of the driving transistor threshold voltage Vth can be implemented. Wherein the driving transistor is the second transistor T2. The embodiment can realize the following beneficial effects through the design: first, the recording of the driving transistor threshold voltage Vth and the data writing of the driving transistor threshold voltage Vth are separated, and the compensation process of the driving transistor threshold voltage Vth can be overlapped in adjacent rows, and thus is not limited by the number of rows and the refresh rate, and thus the compensation effect is greatly advantageous in the case of a large-sized high refresh rate. Second, since the compensation time of the driving transistor can be set to be long, the first capacitor C1 can be set to be large, and at this time, errors other than the fluctuation of the threshold voltage Vth of the driving transistor, such as leakage and errors related to capacitive coupling, will be diluted, thereby further improving the compensation effect. Third, the light-emitting brightness of the pixel driving circuit 111 of the present embodiment is determined by the voltage difference between the first reference voltage Ref1 and the DATA signal DATA, and is independent of the first power voltage ELVDD, so that the voltage drop across the first power voltage ELVDD does not affect the brightness of the light-emitting diode D, and the voltage drop (IR drop) is significantly reduced. Fourth, in one frame, after the pixel driving circuit 111 of the present embodiment completes charging, the first capacitor C1 holds the potential difference between the first node N1 and the second node N2, and then whatever factor (such as black insertion) causes the first node N1 to change, the potential of the second node N2 changes in the same direction along with the first node N1, so that there is no longer a long-time fluctuation of the second transistor T2 Vgs in the frame, so that the threshold voltage Vth of the second transistor T2 no longer fluctuates significantly in the frame to cause brightness change, and flicker of the picture caused by the fluctuation of the threshold voltage Vth of the second transistor T2 is eliminated. Fifth, the high frequency signal of the third Scan signal Scan3 can recycle the defect charges slowly emitted after the third transistor T3 is turned off to the channel defect in the stages T5 and T7, and the process can be repeated for a plurality of times in one frame, so that the brightness fluctuation caused by the emitted charges is changed to high frequency, and the flicker degree is reduced. Sixth, the high frequency resetting of the anode of the led D in this embodiment can also reduce the flicker level.

Fig. 12 shows a circuit diagram of a second embodiment of the pixel driving circuit of the invention. Fig. 13 shows a waveform diagram when the pixel driving circuit shown in fig. 12 operates. As shown in fig. 12 and 13, compared with the first embodiment, the pixel driving circuit 111 of the second embodiment of the present invention has the third transistor T3 that is an N-type MOS transistor, i.e. a wide bandgap, low leakage material is used to further reduce the release of charges, such as Indium Gallium Zinc Oxide (IGZO) or amorphous silicon (a-Si), etc. Meanwhile, in a frame of time, the first rising edge of the third Scan signal Scan3 is identical to the falling edge of the first Scan signal Scan1, and the first falling edge of the third Scan signal Scan3 is identical to the rising edge of the second Scan signal Scan2. Other circuit components and connection modes of the present embodiment are the same as those of the first embodiment, and the waveform diagrams only have the differences as described above. Thus, the present embodiment can realize the same working process and advantageous effects as the first embodiment. In addition, the present embodiment changes the third transistor T3 to a low leakage transistor at an ultra-low refresh rate, e.g., 1Hz or less, and can realize an ultra-low refresh rate while reducing the brightness variation due to leakage on the basis of realizing the advantageous effects of the first embodiment.

Fig. 14 shows a circuit diagram of a third embodiment of the pixel driving circuit of the invention. As shown in fig. 14, compared with the first embodiment, the pixel driving circuit 111 of the third embodiment of the present invention has the first electrode of the seventh transistor T7 connected to the second reference voltage Ref2, and the waveforms of other circuit components, connection modes and operation processes are the same as those of the first embodiment. In the present embodiment, the second reference voltage Ref2 is constant and is lower than the lowest potential of the DATA signal DATA. In other embodiments, the first reference voltage Ref1 may be slightly adjusted to meet specific display requirements. The potential of the seventh transistor T7 is changed from the second power supply voltage ELVSS to an independent second reference voltage Ref2, so that on the basis of realizing the beneficial effects of the first embodiment, the Vds voltage-across of the second transistor T2 during charging can be adjusted by utilizing the independent adjustment capability of the second reference voltage Ref2, so as to finely optimize the short-term ghost and compensation effects.

Based on the same inventive concept, the embodiment of the present invention also provides a display device, including the display panel 10 provided by the embodiment of the present invention. The display device may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. The implementation of the display device can be seen in the embodiment of the display panel 10, and the technical scheme and the repeated technical effects are not repeated.

In summary, the pixel driving circuit 111 and the display panel 10 of the present invention control the third transistor T3 and the seventh transistor T7 by the third Scan signal Scan3 and the fourth Scan signal Scan4 with high frequency to form the main components of the emission charge recycling structure and the high frequency anode resetting structure together, thereby reducing the brightness fluctuation of the display panel caused by the emission of defective charges and improving the picture quality; meanwhile, the influence of the voltage drop of the power supply voltage on the brightness is reduced by storing the potential difference of the gate source and the constant potential as a reference point through the first capacitor C1; in addition, by separating the threshold voltage Vth sampling and the data storage, sufficient compensation at a high refresh rate is realized, and image quality is improved.

The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (11)

1. A pixel driving circuit, comprising:

a first transistor having a first electrode connected to the data signal, a second electrode connected to the third node, and a gate connected to the second scan signal;

a second transistor having a first electrode connected to the first node, a second electrode connected to the fourth node, and a gate connected to the second node;

a third transistor having a first electrode connected to the third node, a second electrode connected to the second node, and a gate connected to a third scan signal;

a fourth transistor having a first electrode connected to a first power supply voltage, a second electrode connected to the first node, and a gate connected to a light emission control signal;

a fifth transistor having a first electrode connected to the fourth node, a second electrode connected to the first electrode of the light emitting diode, and a gate connected to the light emission control signal;

a sixth transistor having a first electrode connected to the third node, a second electrode connected to a first reference voltage, and a gate connected to a first scan signal;

a seventh transistor, a second pole of which is connected to the fourth node, and a gate of which is connected to a fourth scan signal;

a first capacitor, a first pole of which is connected to the second node, and a second pole of which is connected to the first node;

and the first electrode of the second capacitor is connected with the first node, and the second electrode of the second capacitor is connected with the light-emitting control signal.

2. The pixel driving circuit according to claim 1, wherein a second diode of the light emitting diode is connected to a second power supply voltage.

3. The pixel driving circuit according to claim 1, wherein the first pole of the seventh transistor is connected to a second power supply voltage.

4. The pixel driving circuit according to claim 1, wherein the first pole of the seventh transistor is connected to a second reference voltage.

5. The pixel driving circuit according to claim 3 or 4, wherein the first transistor to the seventh transistor are P-type MOS transistors.

6. A pixel driving circuit according to claim 3, wherein the first transistor to the second transistor, the fourth transistor to the seventh transistor are P-type MOS transistors, and the third transistor is an N-type MOS transistor.

7. The pixel driving circuit according to claim 1, wherein the frequencies of the light emission control signal, the third scanning signal and the fourth scanning signal are the same, the frequencies of the first scanning signal and the second scanning signal are the same, and the frequency of the light emission control signal is at least twice the frequency of the first scanning signal within one frame of picture time.

8. The pixel driving circuit according to claim 5, wherein a first falling edge of the third scan signal is the same as a falling edge of the first scan signal, and a first rising edge of the third scan signal is the same as a rising edge of the second scan signal within one frame period.

9. The pixel driving circuit according to claim 6, wherein a first rising edge of the third scan signal is at the same timing as a falling edge of the first scan signal and a first falling edge of the third scan signal is at the same timing as a rising edge of the second scan signal within one frame of picture time.

10. The pixel driving circuit according to claim 1, wherein the first falling edge and the first rising edge of the fourth scanning signal are the same as the falling edge and the rising edge of the first scanning signal in one frame period.

11. A display panel comprising a pixel driving circuit according to any one of claims 1 to 10.