CN117157749A - 具有不同cte晶片的精细间距混合键合的方法及所得结构 - Google Patents

具有不同cte晶片的精细间距混合键合的方法及所得结构 Download PDF

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CN117157749A
CN117157749A CN202280028239.2A CN202280028239A CN117157749A CN 117157749 A CN117157749 A CN 117157749A CN 202280028239 A CN202280028239 A CN 202280028239A CN 117157749 A CN117157749 A CN 117157749A
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substrate stack
substrate
conductive bonding
bonding
hybrid
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刘赛锦
欧放
姜彤弼
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Apple Inc
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Apple Inc
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Abstract

本发明描述了混合键合结构和制造方法。在一个实施方案中，混合键合结构包括：第一衬底叠层的第一多个第一导电键合区域，其直接键合到第二衬底叠层的第二多个第二导电键合区域，以及该第一衬底叠层的第一电介质层，其用中间有机粘合剂层键合到该第二衬底叠层的第二电介质层。

Description

具有不同CTE晶片的精细间距混合键合的方法及所得结构
背景技术
相关专利申请
本申请要求2021年4月15日提交的美国临时申请63/175,159号的优先权权益，该美国临时申请以引用方式并入本文。
技术领域
本文所述的实施方案涉及混合键合技术，并且更具体地涉及不同晶片的混合键合。
背景技术
包括金属-金属和氧化物-氧化物键合的混合键合一般被用作用于大规模生产具有超小焊盘间距的高密度输入/输出(I/O)芯片的合适技术。传统的混合键合序列包括三个主要操作，这些操作包括：室温下的氧化物-氧化物初始键合，加热以闭合凹陷间隙，以及随后进一步加热以压缩金属-金属键。在混合键合工艺之后，存在后续的晶片级工艺，包括化学机械抛光(CMP)、重布线层(RDL)形成和/或取决于具体应用的其他器件精加工操作。传统的混合键合技术要求具有相同热膨胀系数(CTE)的晶片才能有效键合。
发明内容
本发明描述了混合键合结构和制造方法，其中可键合具有不同CTE和精细导电键合区域(焊盘)间距的衬底或衬底叠层。具体地，根据实施方案的混合键合序列可包括低温(例如，室温)下的非导电键合操作，然后减薄不匹配的CTE衬底叠层中的一者，以及高温下的后续导电键合操作以接合相对的导电键合区域。可通过在非导电键合操作期间将相对的衬底叠层中的有机粘合剂层和电介质层键合在一起以实现可经受减薄工艺的足够键合表面能来有利于减薄工艺。另外，根据实施方案的减薄工艺在使键合的衬底叠层经受高温工艺之前执行，以便避免由热膨胀差异引起的过度应变。
附图说明
图1是根据一个实施方案的混合键合方法的流程图。
图2是根据一个实施方案的针对非导电键合准备衬底叠层的方法的流程图。
图3A至图3G是根据一个实施方案的混合键合方法的示意性横截面侧视图图示。
具体实施方式
实施方案描述了混合键合结构和制造方法。具体地，实施方案描述了混合键合的所得结构和方法，混合键合可利用通过不同热膨胀系数(CTE)来表征的衬底叠层来实现，并且更具体地利用包括具有不同CTE的块状衬底(例如，晶片)的衬底叠层来实现。在一个特定具体实施中，这可允许将二极管阵列混合键合到硅衬底上，其中二极管阵列生长在诸如GaAs(5.7ppm/℃)或蓝宝石(5.0ppm/℃)的衬底上，它们与硅(2.6ppm/℃)具有显著不同的CTE，其中在室温和更高温度下差异可以是2.0或更大，诸如超过3.0。另外，具有不同CTE叠层的混合键合可以大规模实现，包括晶片到晶片规模或管芯到晶片规模，其中管芯尺寸大于1mm×1mm，例如大于3mm×3mm。
根据本文所述的实施方案的混合键合结构可包括与第二衬底叠层混合键合的第一衬底叠层，第一衬底叠层通过第一CTE来表征并且第二衬底叠层通过不同于第一CTE的第二CTE来表征。在一个实施方案中，第一衬底叠层包括第一电介质层和第一多个第一导电键合区域，第二衬底叠层包括第二电介质层和第二多个第二导电键合区域，第一多个第一导电键合区域直接键合到第二多个第二导电键合区域，并且第一电介质层用中间有机粘合剂层键合到第二电介质层。根据实施方案，在混合键合的第一衬底叠层与第二衬底叠层之间存在键合界面，该键合界面在第一电介质层与中间有机粘合剂层之间延伸(或通过它们的接触而限定)并且在第一多个第一导电键合区域与第二多个第二导电键合区域之间延伸。
根据实施方案的中间有机粘合剂层可在将第一衬底叠层和第二衬底叠层键合在一起之前施加到第一衬底叠层和第二衬底叠层中的一者上，并且在第一衬底叠层和第二衬底叠层中的一者的顶部上至少部分地固化。至少部分固化可将有机粘合剂层粘附到下面的衬底叠层，并且允许诸如CMP的附加处理以与第一多个导电键合区域或第二多个导电键合区域中的一者一起形成平坦的键合表面。在施加有机粘合剂层和任选的进一步处理之后，对应的衬底叠层可随后用于晶片到晶片键合或任选地被切割以用于管芯到晶片键合。
包括有机粘合剂层的衬底叠层将键合到的对应衬底叠层可包括特定成分的电介质层，使得后续键合可在低温诸如室温下进行，同时实现与有机粘合剂层的键合表面能，该表面能将足以用于后续晶片减薄以去除下面的块状衬底(例如，具有不同CTE)。例如，SiCN电介质层可与许多有机粘合剂层诸如聚苯并噁唑(PBO)、聚酰亚胺等实现大于1.7J/m2的键合表面能。在晶片减薄之后，可执行高温退火工艺以完成所对准的导电键合区域的键合(例如，金属-金属键合)。
在一个方面，已观察到当键合具有不同CTE的晶片或衬底叠层(例如，其上具有另外层的晶片或块状衬底)时，键合可在加热和冷却过程期间由于晶片(或块状衬底)之间的应变而损坏。例如，如果键合温度比室温高200℃，则应力可导致衬底叠层中出现分层或损坏，即使混合键合是管芯到晶片并且管芯尺寸比晶片尺寸小得多。
根据实施方案，描述了可允许具有显著不同的CTE(诸如相差2.0或更大，或甚至3.0或更大)的晶片或衬底叠层之间的混合键合的混合键合序列。在一个实施方案中，混合键合的衬底叠层各自具有至少1mm×1mm、或更具体地至少3mm×3mm的最大横向尺寸，并且与全晶片尺寸一样大。实施方案还可包括将不同尺寸的晶片诸如4至6英寸晶片混合键合到12英寸或300mm晶片上。在示例性实施方案中，所得结构可包括直接键合到硅驱动器管芯的微二极管阵列(例如，感测二极管或发光二极管)。可随后将混合键合的结构集成到各种应用中，诸如显示设备、图像传感器器件等。
在各种实施方案中，参照附图来进行描述。然而，可在不具有这些特定细节中的一者或多者的情况下或与其他已知的方法和构造组合地实践某些实施方案。在以下的描述中，示出许多具体细节诸如特定构型、尺寸和工艺等，以提供对实施方案的透彻理解。在其他情况下，未对熟知的半导体工艺和制造技术进行特别详细地描述，以免不必要地模糊实施方案。整个说明书中所提到的“一个实施方案”是指结合实施方案所描述的特定特征、结构、构造或特性被包括在至少一个实施方案中。因此，整个说明书中多处出现短语“在一个实施方案中”不一定是指相同的实施方案。此外，特定特征、结构、构造或特性可以任何适当的方式组合在一个或多个实施方案中。
本文所使用的术语“在...上方”、“到”、“在...之间”和“在...上”可以指一层相对于其他层的相对位置。一层在另一层“上方”或“上”或者结合“到”另一层或者与另一层“接触”可以为直接与其他层接触或可以具有一个或多个居间层。一层在多层“之间”可为直接与该多层接触或可具有一个或多个居间层。
现在参考图1至图2，图1是根据一个实施方案的为混合键合方法提供的流程图，并且图2是根据一个实施方案的针对非导电键合准备衬底叠层的方法的流程图。
另外，图3A至图3G是根据一个实施方案的混合键合方法的示意性横截面侧视图图示。为了清楚和简洁起见，参考图3A至图3G中所示的共同特征来描述图1至图2中所示的处理流程。虽然图3A至图3G中示出的序列具体地示出了用于多个微LED和硅驱动器衬底的混合键合序列，但应当理解，该具体实施是示例性的，并且本文所述的一般混合键合序列适用于微电子工业中的各种晶片到晶片和管芯到晶片应用。
现在参考图1，根据实施方案的一般混合键合序列1000包括在操作1010处准备第一衬底叠层100和在操作1020处准备第二衬底叠层200。如将在以下描述中变得明显的，这可包括将有机粘合剂层240施加到衬底叠层中的一者，并且任选地用有机粘合剂层进一步处理衬底叠层以针对室温下的非导电键合准备衬底叠层。图2包括用于根据一个实施方案的针对非导电键合准备衬底叠层的操作1010序列。如图所示，在操作2010处，可在衬底叠层(例如，第二衬底叠层200)的电介质层220上施加有机粘合剂层240。可随后在操作2020处部分或完全固化有机粘合剂层240，然后在操作2030处任选地抛光有机粘合剂层240和任选的多个导电键合区域230(例如，铜焊盘)(或其阵列)以形成平坦键合表面235。在一个实施方案中，平坦键合表面235具有小于0.5nm的平均表面粗糙度(Ra)。
另一个对应的衬底叠层(例如，第一衬底叠层100)可通过形成电介质层110(诸如SiCN)来单独地针对非导电键合进行准备，该电介质层将在室温下将第二衬底叠层与第一衬底叠层附接之后实现与有机粘合剂层240的大于1.7J/m2的键合表面能。
再次参考图1，在操作1030处，将第一衬底叠层100和第二衬底叠层200放在一起以在室温下进行非导电键合。在这种情况下，一个衬底叠层(例如，第二衬底叠层200)上的有机粘合剂层240将键合到相对的衬底叠层(例如，第一衬底叠层100)的电介质层110。在操作1040处，包括有机粘合剂层240的衬底叠层(例如，第二衬底叠层200)被减薄。例如，该减薄操作可包括将具有与相对衬底叠层的块状衬底102不同的CTE的块状衬底202(例如，生长衬底)进行研磨、蚀刻、激光剥离等。例如，CTE差异可以是2.0或更大，或甚至3.0或更大。一旦去除了具有不同CTE的块状衬底，就可在操作1050处执行高温下的导电键合，以键合/扩散相对衬底叠层的对准导电键合区域120、230(例如，铜焊盘)。可随后在操作1060处执行另外的晶片或器件处理以及任选的切割。
现在参考图3A至图3G，提供了根据一个实施方案的混合键合方法的示意性横截面侧视图图示。如图所示，该序列可从包括形成于生长衬底202上的器件层205的图3A开始。在示例性实施方案中，器件层205是p-n二极管层，其包括至少掺杂有第一掺杂剂类型(例如n型)的第一掺杂层203、掺杂有与第一掺杂剂类型相反的第二掺杂剂类型(例如p型)的第二掺杂层206以及位于第一掺杂层203与第二掺杂层206之间的有源层204。有源层204可包括被屏障层分隔的一个或多个量子阱层。根据实施方案，p-n二极管层205可由基于III-V或II-VI族无机半导体的材料形成，并且被设计成适于在各种主要波长(诸如红色、绿色、蓝色等)下发射。可基于特定发射颜色来选择生长衬底，包括用于基于氮化物的LED(例如发射绿色、蓝色、UV)的蓝宝石或GaN，或用于基于磷的LED(例如，发射红色)的GaAs或GaP。
可随后使用诸如干法蚀刻和/或湿法蚀刻的适当技术来图案化器件层205以形成多个二极管210。二极管210可以是微型二极管，例如最大横向尺寸小于100微米，或更具体地小于20微米或更小，诸如小于10微米、小于5微米，或更具体地小于3微米。虽然仅示出了两个二极管210，但可形成更大的多个二极管210或其阵列，例如具有小于20微米的间距。在一个实施方案中，二极管210以小于10微米的间距隔开，密度大于每3mm×3mm面积90,000个二极管。
在形成二极管210之后，可在二极管210周围形成一个或多个电介质层220，如图3C所示。虽然未单独说明，但可取决于应用而形成多种其他光学特征，诸如围绕二极管210的侧壁211的反射结构。电介质层220可为二极管210提供钝化和/或为后续处理提供阶梯覆盖。电介质层220可使用诸如化学气相沉积(CVD)的适当技术来沉积，或使用诸如喷涂、旋涂、槽式涂布等的技术来涂覆。合适的材料范围从无机氧化物、氮化物等到有机聚合物，诸如丙烯酸、苯并环丁烯(BCB)、PBO等。最上面的电介质层220和二极管210可任选地被抛光/平坦化。可随后在二极管210的暴露表面213上形成多个导电键合区域230。导电键合区域230可以是单层或多层叠层。在一个实施方案中，导电键合区域包括顶部金属层，诸如铜，用于键合到相对衬底叠层上的对应导电键合区域230(并与其相互扩散)。
现在参考图3D，在电介质层220和多个导电键合区域230上施加有机粘合剂层240。例如，这可使用喷涂、旋涂或槽式涂布，然后固化以至少部分地交联有机粘合剂层240来实现。根据实施方案，这可包括完全固化或部分固化(例如，B阶段)以保持粘性。然后(例如，用CMP)任选地抛光有机粘合剂层240和导电键合区域230，以获得适于晶片键合的平坦键合表面235。键合表面235还可在导电键合区域230(焊盘)与有机粘合剂层240之间实现优选的形貌。在此阶段，可任选地将第二衬底叠层200切割成多个管芯250(参考图3E')。
根据实施方案，管芯250可具有大于1mm×1mm或更具体地大于3mm×3mm的最小横向尺寸。在一个实施方案中，二极管210以小于10微米的间距隔开，密度大于每3mm×3mm面积90,000个二极管。具体地，根据实施方案描述的混合键合序列可有利于具有不同CTE的衬底叠层的混合键合，使得能够将较大衬底彼此混合键合，包括晶片到晶片混合键合以及对最大管芯尺寸的要求不太严格以适应由于CTE失配引起的应力的管芯到晶片键合。
由于现在已准备好示例性LED供体衬底叠层200(即，第二衬底叠层)或其管芯250，可用也已准备好的底板衬底叠层100(即，第一衬底叠层)来继续进行混合键合，以包括用于非导电室温键合的电介质层110，如图3E至图3E'所示。具体地，图3E示出了晶片到晶片键合，而图3E'示出了管芯到晶片键合。如图所示，第一衬底叠层100可包括第一块状衬底102和布线层105，该布线层包括第一块状衬底102上的第一电介质层105和第一多个第一导电键合区域120。更具体地，块状衬底102可以是具有任选的顶部外延层的硅衬底，驱动器电路的多个器件(例如，晶体管等)形成于顶部外延层上。布线层105可包括许多电介质层103以及导电(金属)布线104互连线和通孔，以将块状衬底的器件与第一导电键合区域120(例如，铜焊盘)电连接。电介质层110可以是已针对室温下的非导电键合进行处理的最上面的电介质层。
如已经描述的那样，第二衬底叠层200可包括第二块状衬底202(例如，用于二极管的生长衬底)以及第二块状衬底202上的第二电介质层220和第二多个第二导电键合区域230(例如，铜焊盘)。随后在将第二多个导电键合区域230与第一多个导电键合区域120对准时将第一衬底叠层与第二衬底叠层彼此对准，以使用有机粘合剂层240在室温下实现非导电键合。
可随后如图3F所示，使用诸如研磨和抛光的适当技术来去除第二块状衬底202。在该序列期间，有机粘合剂层240与第一电介质层110之间的键合能可大于1.7J/m2，以提供足够的粘附力来经受从第一块状衬底102去除具有不匹配的CTE的第二块状衬底202。在去除第二块状衬底202之后，可在高温下加热所附接的衬底叠层以使第一导电键合区域120和第二导电键合区域230变形(例如，引起相互扩散)并且形成另外具有改进的粘附性和电特性的最终键合接合部，并且形成混合键合结构300。在一个实施方案中，将所附接的衬底叠层加热至高于150℃或甚至高于200℃的温度，以实现导电键合。
根据实施方案，在混合键合的第一衬底叠层100和第二衬底叠层200之间存在键合界面255，该键合界面255在第一电介质层110与中间有机粘合剂层240之间延伸(或通过它们的接触而限定)并且在第一多个第一导电键合区域120与第二多个第二导电键合区域230之间延伸。
在混合键合完成之后，取决于应用，可例如使用晶片级处理来进一步处理混合键合结构300。在图3G所示的实施方案中，穿过叠层结构形成垂直互连件330(例如，铜通孔)以接触导电(金属)布线104。这之后可形成任选的接触焊盘320和透明或半透明的顶部电极层310以将二极管210的顶侧与导电布线104电连接。还可形成另外的结构，诸如微透镜340。在所示的具体实施方案中，举例说明了半球形结构，其中可针对所需的发射分布来选择折射率，然而实施方案不限于此具体应用。在晶片级处理之后，混合键合结构300可任选地被切割成多个单独的管芯。在一个实施方案中，被切割的混合键合结构300内的多个微型二极管210分散在大于1mm×1mm或更具体地大于3mm×3mm的面积中，无论第二衬底叠层200是否在混合键合之前被预先切割成管芯250。
在利用实施方案的各个方面时，对本领域技术人员将变得显而易见的是，对于具有不同CTE的衬底的精细间距混合键合而言，以上实施方案的组合或变型是可能的。尽管以特定于结构特征和/或方法行为的语言对实施方案进行了描述，但应当理解，所附权利要求并不一定限于所描述的特定特征或行为。所公开的特定特征和行为相反应当被理解为用于进行例示的权利要求的实施方案。

Claims (20)

1.一种混合键合结构，包括：
通过第一热膨胀系数(CTE)来表征的第一衬底叠层，所述第一衬底叠层包括第一电介质层和第一多个第一导电键合区域；和
通过不同于所述第一CTE的第二CTE来表征的第二衬底叠层，所述第二衬底叠层包括第二电介质层和第二多个第二导电键合区域；
其中所述第一多个第一导电键合区域直接键合到所述第二多个第二导电键合区域，并且所述第一电介质层用中间有机粘合剂层键合到所述第二电介质层。
2.根据权利要求1所述的混合键合结构，还包括在所述第一衬底叠层与所述第二衬底叠层之间的键合界面，所述键合界面在所述第一电介质层与所述中间有机粘合剂层之间以及在所述第一多个第一导电键合区域与所述第二多个第二导电键合区域之间。
3.根据权利要求2所述的混合键合结构，其中所述第二电介质层包含SiCN。
4.根据权利要求2所述的混合键合结构，其中所述键合界面是在所述第一电介质层与所述中间有机粘合剂层之间以及在所述第一多个第一导电键合区域与所述第二多个第二导电键合区域之间的平坦键合界面。
5.根据权利要求1所述的混合键合结构，其中所述第一衬底叠层包括与所述第一多个第一导电键合区域电连接的金属-氧化物-硅(MOS)电路。
6.根据权利要求5所述的混合键合结构，其中所述第二衬底叠层包括多个二极管，并且所述第二多个第二导电键合区域形成于所述多个二极管上。
7.根据权利要求6所述的混合键合结构，其中所述多个二极管是多个微型二极管，每个微型二极管通过小于100微米的最大横向尺寸来表征。
8.根据权利要求7所述的混合键合结构，其中所述多个微型二极管之间的间距小于20微米。
9.根据权利要求8所述的混合键合结构，其中所述多个微型二极管分散在大于1mm×1mm的面积中。
10.根据权利要求8所述的混合键合结构，其被集成到显示设备中。
11.根据权利要求8所述的混合键合结构，其被集成到图像传感器器件中。
12.一种混合键合方法，包括：
用有机粘合剂层将第二衬底叠层与第一衬底叠层附接，所述有机粘合剂层位于所述第一衬底叠层或所述第二衬底叠层上；
其中：
所述第一衬底叠层包括第一块状衬底以及在所述第一块状衬底上的第一电介质层和第一多个第一导电键合区域；
所述第二衬底叠层包括第二块状衬底以及在所述第二块状衬底上的第二电介质层和第二多个第二导电键合区域；并且
将所述第二衬底叠层与所述第一衬底叠层附接包括将所述第二多个导电键合区域与所述第一多个导电键合区域对准；
去除所述第二块状衬底；以及
在去除所述第二块状衬底之后加热所附接的第一衬底叠层和第二衬底叠层以使所述第二多个导电键合区域与所述第一多个导电键合区域相互扩散。
13.根据权利要求12所述的混合键合方法，还包括：
将所述有机粘合剂层施加在所述第二电介质层和所述第二多个第二导电键合区域上；以及
在将所述第一衬底叠层与所述第二衬底叠层附接之前至少部分地固化所述有机粘合剂层。
14.根据权利要求13所述的方法，还包括抛光所述有机粘合剂层和所述第二多个导电键合区域以形成平坦键合表面。
15.根据权利要求14所述的方法，其中所述平坦键合表面具有小于0.5nm的平均表面粗糙度(Ra)。
16.根据权利要求13所述的方法，其中所述第二衬底叠层与所述第一衬底叠层的所述附接在室温下执行。
17.根据权利要求16所述的方法，其中在室温下执行将所述第二衬底叠层与所述第一衬底叠层附接之后，所述有机粘合剂层与所述第一电介质层的键合表面能大于1.7J/m2。
18.根据权利要求17所述的方法，其中所述第一电介质层包含SiCN。
19.根据权利要求17所述的方法，其中加热所附接的第一衬底叠层和第二衬底叠层以使所述第二多个导电键合区域与所述第一多个导电键合区域相互扩散在高于150℃的温度下执行。
20.根据权利要求17所述的方法，还包括在使所述第二多个导电键合区域与所述第一多个导电键合区域相互扩散之后，将所附接的第一衬底叠层和第二衬底叠层切割成多个管芯。
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