CN117155842A

CN117155842A - Method, system, equipment and medium for implementing double-host route

Info

Publication number: CN117155842A
Application number: CN202311390970.2A
Authority: CN
Inventors: 陈静静; 高娜; 李树青; 孙华锦
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2023-10-25
Filing date: 2023-10-25
Publication date: 2023-12-01
Anticipated expiration: 2043-10-25
Also published as: CN117155842B

Abstract

The present invention relates to the field of communications technologies, and in particular, to a method, a system, an apparatus, and a medium for implementing dual-host routing. The method comprises the following steps: in response to receiving a routing request, wherein a source routing node and a destination routing node through which the routing request passes are located in the same sub-network managed by the same host, binary codes corresponding to the numbers of the source routing node and the destination routing node are respectively obtained, so that a first routing code and a second routing code are obtained; performing bit-wise exclusive OR operation on the first routing code and the second routing code to generate a first routing code; determining the highest bit equal to one in the first path code in response to at least one bit equal to one in the first path code, and determining a target father routing node layer based on the first bit number corresponding to the highest bit equal to one; determining a target father routing node in all routing nodes of a target father routing node layer; and generating a routing path according to the source routing node, the destination routing node and the target father routing node, and executing the routing request by the routing path.

Description

Method, system, equipment and medium for implementing double-host route

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a method, a system, an apparatus, and a medium for implementing dual-host routing.

Background

With the rapid popularization and development of the internet and the continuous deployment of satellite internet constellation plans, more user terminals access to the network, and the internet application in various fields including people production and living is derived. Aiming at the defects of the system on a chip in terms of time delay, clock synchronization, energy consumption, reusability and the like, a network on a chip is provided, and the network on a chip can be used for overcoming the defects of the system on a chip. While the network on chip has been in theoretical research stage from birth to the past decades, it is believed that the network on chip will be a key technology and widely used. In order to improve the performance of the network-on-chip and meet the new application and service requirements which are continuously emerging, the network-on-chip with better performance and a high-performance scheduling algorithm adapted to the network-on-chip are required to be researched.

Accordingly, there is a need for an effective method to solve the above problems.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a method, a system, a device and a medium for implementing dual-host routing.

According to a first aspect of the present invention, there is provided a method for implementing dual-host routing, the method for implementing dual-host routing including:

responding to the received routing request, wherein a source routing node and a destination routing node which are passed by the routing request are positioned in the same sub-network managed by the same host, and binary codes corresponding to the numbers of the source routing node and the destination routing node are respectively obtained to obtain a first routing code and a second routing code;

performing bit-wise exclusive-or operation on the first routing code and the second routing code to generate a first routing code;

determining the highest bit equal to one in the first path code in response to at least one bit equal to one in the first path code, and determining a target father routing node layer based on the first bit number corresponding to the highest bit equal to one;

determining a target father routing node in all routing nodes of the target father routing node layer;

generating a route path according to the source route node, the destination route node and the target father route node, and executing the route request by the route path.

In some embodiments, the step of determining the target parent routing node among all routing nodes of the target parent routing node layer includes:

Performing bitwise exclusive OR operation on binary codes corresponding to all routing node numbers in the target father routing node layer and the first routing codes respectively to generate a plurality of second routing codes;

responding to the condition that the second path code corresponding to the routing node exists in the target father routing node layer to meet a first preset condition, and the routing node meets a second preset condition and a third preset condition, and taking each routing node of the target father routing node layer meeting the preset condition as a preliminary father routing node;

and selecting one of all the preliminary parent routing nodes as a target parent routing node.

In some embodiments, the step of generating a routing path from the source routing node, the destination routing node, and the target parent routing node includes:

and determining a first path according to the source routing node and the target father routing node, determining a second path according to the target routing node and the target father routing node, and taking the first path and the second path as routing paths.

In some embodiments, the step of determining a first path from the source routing node and the target parent routing node includes:

If the first bit number is greater than one, acquiring a binary code corresponding to the number of the target father routing node as a third routing code;

performing bit-wise exclusive OR operation on the first routing code and the third routing code to generate a third routing code, and determining a first intermediate routing node based on the third routing code;

and combining the source terminal node, the source routing node, the first intermediate routing node and the target father routing node to obtain a first path.

In some embodiments, the step of determining the first intermediate routing node based on the third path encoding comprises:

taking the least significant bit of the third path code as a first current bit, taking a routing node layer corresponding to the source routing node as a first current routing node layer, and taking the first routing code as a first current routing code;

judging whether the first current bit is equal to one;

if the first current bit is equal to one, inverting the bit on the bit number corresponding to the first current bit in the first current route code, and taking the inverted result as a binary code corresponding to a first intermediate route node in the upper layer of the first current route node layer;

If the first current bit is not equal to one, the first current route code is used as a binary code corresponding to a first intermediate route node in a layer above the first current route node layer;

and in response to the bit number of the first current bit not reaching the highest significant bit number of the third path code, moving the first current bit leftwards by one bit to obtain a new first current bit, taking the upper layer of the first current routing node layer as a new first current routing node layer, taking the binary code corresponding to a first intermediate routing node in the upper layer as the new first current routing code, and returning to the step of judging whether the first current bit is equal to one or not until the first current bit reaches the highest significant bit number of the third path code.

In some embodiments, the step of combining the source end node, the source routing node, the first intermediate routing node, and the target parent routing node to obtain a first path includes:

respectively taking a source terminal node and the target father routing node as a first starting point and a first ending point of a first path;

and placing the source routing node and all the first intermediate routing nodes between the first starting point and the first ending point according to the generation sequence so as to generate a first path.

In some embodiments, the step of determining a second path from the destination routing node and the target parent routing node includes:

performing bitwise exclusive OR operation on the second routing code and the third routing code to generate a fourth routing code, and determining a second intermediate routing node based on the fourth routing code;

and combining the destination terminal node, the destination routing node, the second intermediate routing node and the target father routing node to obtain a second path.

In some embodiments, the step of determining a second intermediate routing node based on the fourth path encoding comprises:

taking the most significant bit of the fourth route code as a second current bit, taking the target father route node layer as a second current route node layer, and taking the third route code as a second current route code;

judging whether the second current bit is equal to one;

if the second current bit is equal to one, inverting the bit on the bit number corresponding to the second current bit in the second current route code, and taking the inverted result as a binary code corresponding to a second intermediate route node in the next layer of the second current route node layer;

If the second current bit is not equal to one, the second current route code is used as a binary code corresponding to a second intermediate route node in a layer next to the second current route node layer;

and in response to the bit number of the second current bit not reaching the lowest significant bit number of the fourth path code, moving the second current bit rightward by one bit to obtain a new second current bit, taking the next layer of the second current routing node layer as a new second current routing node layer, taking a binary code corresponding to a second intermediate routing node in the next layer as a new second current routing code, and returning to the step of judging whether the second current bit is equal to one or not until the bit number of the second current bit reaches the lowest significant bit number of the fourth path code.

In some embodiments, the step of combining the destination end node, the destination routing node, the second intermediate routing node, and the target parent routing node to obtain a second path includes:

respectively taking the target father routing node and the destination terminal node as a second starting point and a second ending point of a second path;

and placing all the second intermediate routing nodes and the destination routing nodes between the second starting point and the second ending point according to the generation sequence so as to generate a second path.

In some embodiments, the step of having the second path code corresponding to the routing node in the target parent routing node layer meet a first preset condition includes:

and determining that the second path code meets a first preset condition in response to the fact that the bit number corresponding to the highest bit equal to one in the second path code is smaller than or equal to the first bit number or that all bits equal to zero in the second path code.

In some embodiments, the step of the routing node meeting a second preset condition includes:

and in response to the existence of the routing node of the target father routing node layer and the source routing node being located in the same sub-network, determining that the routing node of the target father routing node layer meets a second preset condition.

In some embodiments, the step of the routing node meeting a third preset condition includes:

and in response to the existence of the next layer of routing nodes connected with the routing nodes of the target father routing node layer and the source routing node are all located in the same sub-network, determining that the routing nodes of the target father routing node layer meet a third preset condition.

In some embodiments, the implementation method of dual host routing further includes:

And if the first bit number is equal to one, combining the source terminal node, the source routing node and the target father routing node to obtain a first path.

and if the first bit number is equal to one, combining the destination terminal node, the destination routing node and the target father routing node to obtain a second path.

In some embodiments, the step of determining the target parent routing node layer based on the first number of bits corresponding to the most significant bit equal to one includes:

and taking the result of adding one to the first bit number as a target layer number, and taking a routing node layer corresponding to the target layer number as a target father routing node layer.

and in response to all bits in the first path code being equal to zero, confirming that the source routing node and the destination routing node are the same routing node, and executing the routing request inside the same routing node.

taking a routing node connected with a source terminal node in the routing request as a source routing node;

And taking the routing node connected with the destination terminal node in the routing request as a destination routing node.

In some embodiments, the most significant number of bits of the third path code or the fourth path code corresponds to the first number of bits.

According to a second aspect of the present invention, there is provided a dual host routing implementation system, the system comprising:

the system comprises an acquisition unit, a first routing code and a second routing code, wherein the acquisition unit is used for respectively acquiring binary codes corresponding to the numbers of a source routing node and a destination routing node which are received a routing request and pass through by the routing request, and the source routing node and the destination routing node are positioned in the same sub-network managed by the same host;

a generating unit, configured to perform a bitwise exclusive-or operation on the first routing code and the second routing code to generate a first routing code;

the target father routing node layer determining unit is used for determining the highest bit equal to one in the first path code in response to the fact that at least one bit in the first path code is equal to one, and determining the target father routing node layer based on the first bit number corresponding to the highest bit equal to one;

a target father routing node determining unit, configured to determine a target father routing node from all routing nodes in the target father routing node layer;

And the execution unit is used for generating a routing path according to the source routing node, the destination routing node and the target father routing node, and executing the routing request by the routing path.

In a third aspect of the embodiment of the present invention, there is also provided a switching device, including: at least one processor; and a memory storing a computer program executable on the processor, which when executed by the processor, performs the steps of the method as above.

In a fourth aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium storing a computer program which, when executed by a processor, implements the method steps as above.

According to the method for realizing the double-host routing, if the received routing request is used for executing the same sub-network, the binary codes corresponding to the source routing node number and the destination routing node number bits which are passed through by the routing request are respectively processed by performing bitwise exclusive OR operation to generate a first routing code, the number of the target father routing node layer is determined according to the numerical value at each position in the first routing code to obtain the target father routing node, and finally, the routing paths which are used for executing the routing request corresponding to the internal routing request of the same sub-network are generated according to the source routing node, the destination routing node and the target father routing node, so that the sub-networks respectively controlled by the double hosts can not interfere each other to route and independently transmit data packets when the internal source terminal nodes mutually transmit the data packets.

In addition, the invention also provides a system for realizing the double-host routing, a switching device and a computer readable storage medium, which can also realize the technical effects and are not repeated here.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention and that other embodiments may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an embodiment of a topology of a network on chip according to the present invention;

FIG. 2 is a diagram illustrating an embodiment of a fat tree network topology supporting dual hosts according to the present invention;

FIG. 3 is a schematic diagram of an embodiment of a dual-host routing implementation method according to the present invention;

FIG. 4 is a schematic diagram of an embodiment of a dual host routing implementation system according to the present invention;

fig. 5 is a schematic structural diagram of an embodiment of a switching device according to the present invention;

Fig. 6 is a schematic structural diagram of an embodiment of a computer readable storage medium according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.

It should be noted that, in the embodiments of the present invention, all the expressions "first" and "second" are used to distinguish two entities with the same name but different entities or different parameters, and it is noted that the "first" and "second" are only used for convenience of expression, and should not be construed as limiting the embodiments of the present invention, and the following embodiments are not described one by one.

As described above, the network on chip has a better development prospect, and the advantages are as follows:

(1) The network-on-chip uses the network structure of the computer network as a reference, the whole network-on-chip is connected by a plurality of point-to-point lines, the lines cannot interfere with each other, and the requirements of a plurality of users for communication are well met.

(2) The network on chip adopts a global asynchronous and local synchronous mode to solve the problem of clock synchronization, namely, the local network in the network on chip works under the self time oscillation frequency, so that the global synchronization problem of the clock is avoided, the clock offset problem is solved, and the network power consumption is effectively reduced.

(3) The network-on-chip supports multipoint parallel data transmission, namely, the data transmission of various lines can be completed at the same time, and the addressing of the network-on-chip is completed in the local network, so that the influence of the expansion of the network scale on the addressing is avoided, and the utilization rate of the bandwidth is improved.

(4) The network on chip uses a random arbitration mechanism, so that the problem of larger time delay caused by unified management of line usage rights by using a central decision unit in a bus structure is avoided.

(5) The network on chip adopts a local decision strategy, an independent functional unit in the line is completed in a distributed manner, and the routing equipment in the network on chip can be used in various environments, so that the network on chip has the characteristics of good reusability, high cohesion and low coupling, and good expandability and portability, effectively shortens the system development time and improves the system development efficiency.

The invention only aims to solve the problem that the communication efficiency is reduced due to mutual interference of opposite sub-networks when the source terminal nodes of the same sub-network controlled by the same host in the network-on-chip topological structure supporting the double hosts are communicated.

Fig. 1 is a schematic diagram of an embodiment of a topology of a network on chip according to the present invention. The network on chip as shown in fig. 1 is a fat tree network in which each link port between an end node and a routing node is bi-directional, as is a link port between a routing node and a routing node. Each link in fig. 1 is also bidirectional data transmission, a box in fig. 1 is a terminal node, a circle is a routing node, 16 terminal nodes and 8 routing nodes of a layer 3 are all used, and two terminal nodes are hung on the routing node at the bottom layer. The terminal nodes are responsible for sending and collecting the data packets, can mutually send the data packets, and are forwarded by the routing nodes.

The on-chip network topology supporting dual hosts is described below by taking the fat tree network supporting dual hosts as an example, but the on-chip network is not limited to the fat tree network.

The above-mentioned support dual hosts refer to linking two hosts on a network topology, each host controlling a terminal node of a part to divide a network on chip into two different sub-networks. In one example, a fat tree network topology supporting dual hosts is presented based on the fat tree network topology shown in fig. 1. As shown in fig. 2, the routing node 0, the routing node 1, the routing node 2, and the terminal nodes 0, the terminal nodes 1, the terminal nodes 2, the terminal nodes 3, the terminal nodes 4, and the terminal nodes 5 linked with the routing node 1 and the routing node are controlled by a first host, and all belong to a first sub-network. The routing node 3, the routing node 4, the routing node 5, the routing node 6 and the routing node 7 and the terminal nodes 6, 7, 8, 9, 10, 11, 12, 13, 14 and 15 linked by the routing node 7 are controlled by a second host, and all belong to a second sub-network.

The traditional shortest route implementation method comprises the following steps: and randomly selecting a nearest father routing node F between a terminal node s and a terminal node d, and firstly, from s to F and then from F to d.

In the case of mutual transmission of data packets between two hosts linked by a network on chip, the above-mentioned conventional implementation method of shortest route may still be used. In fact, the source terminal nodes inside the two hosts linked by the network on chip perform mutual transmission of the data packets more frequently than the case, so that there is a need for the subnets controlled by the two hosts to be not interfered with each other, and the conventional shortest route implementation method cannot meet the need.

In an example, it is assumed that when the end node 12 of the second subnetwork in fig. 2 transmits a data packet to the end node 6, if a conventional shortest route implementation method is used, a route path may exist as follows: terminal node 12→routing node 6 (first layer) →routing node 6 (second layer) →routing node 6 (third layer) →routing node 6 (fourth layer) →routing node 2 (third layer) →routing node 2 (second layer) →routing node 3 (fourth layer) →terminal node 6.

The routing path from the routing node 2 (third layer) to the routing node 2 (second layer) belongs to the first sub-network, that is, the routing node and the path of the first sub-network are used when the second sub-network of the above example transmits data, so that the routing resource of the first sub-network is occupied, and interference is caused to the first sub-network.

Based on the above objects, in a first aspect of the embodiments of the present invention, an embodiment of a method for implementing dual-host routing is provided. As shown in fig. 3, the implementation method of the dual-host routing includes the following steps:

step 101, in response to receiving a routing request, and the source routing node and the destination routing node through which the routing request passes are located in the same sub-network managed by the same host, binary codes corresponding to the numbers of the source routing node and the destination routing node are respectively obtained, so as to obtain a first routing code and a second routing code.

In some embodiments, the method for implementing dual-host routing further includes: taking a routing node connected with a source terminal node in the routing request as a source routing node; and taking the routing node connected with the destination terminal node in the routing request as a destination routing node.

In some embodiments, the routing request refers to a communication request of two terminal nodes, for example, it may be assumed that when the terminal node 0 needs to send data to the terminal node 3 in a certain scenario, the routing request is generated to plan the routing nodes that the terminal node 0 passes through to the terminal node 3, it should be noted that the routing request is directional, the terminal node sending the data packet is a source terminal node, the terminal node receiving the data packet is a destination terminal node, the routing node connected to the source terminal node is a source routing node, and the routing node connected to the routing node nearest to the destination terminal node is a destination routing node. The peer end node 3 may also send a data packet to end node 0, where a request is made to plan the routing nodes through which end node 3 to end node 0 pass. It should be noted that, in the routing request in this embodiment, the number of the terminal node is only used for illustration, and should not be construed as limiting the scheme of the present invention, and the needs of the source terminal node and the destination terminal node may be flexibly changed according to the specific service scenario in the specific implementation process.

In some specific implementation processes, the network topology may be a fat tree network topology, but is not limited to a fat tree network topology, and the dual-host routing implementation method provided by the invention can realize that the source terminal nodes of the same sub-network controlled by the same host in the on-chip network topology supporting dual hosts do not interfere with each other when the network topology meets the following conventions: the terminal nodes controlled by the two hosts are all adjacent terminal nodes, and the terminal nodes with small numbers in the network topology structure on chip divided by the two hosts are the terminal nodes in the first sub-network controlled by the first host, namely, the terminal node numbers of the first sub-network are smaller than the terminal node numbers of the second sub-network, as shown in fig. 2.

In some embodiments, each routing node, terminal node in the network topology has a respective corresponding number.

Step 102, performing bit-wise exclusive-or operation on the first routing code and the second routing code to generate a first routing code.

In some embodiments, the number of binary digits corresponding to the number of binary digits of the largest terminal node number in the network topology, for example, the binary digits comprise 16 terminal nodes, the largest terminal node number is equal to 16, and the 16 required 4 binary digits represent each terminal node number, it may be assumed that the source terminal node terminal number is equal to 2, the destination terminal node number is equal to 15, and the first routing code is denoted as "0010" and the second routing code is denoted as "1111". It should be noted that, the number of bits of the binary code corresponding to the terminal node is set according to the number of nodes included in the network topology, for example, if a certain network topology only includes 32 terminal nodes, the first routing code and the second routing code can be represented by adopting five-bit binary codes at this time, and at this time, 4-bit binary codes are not needed to be used for representing.

In some embodiments, the number of routing nodes depends on the number of the terminal nodes, and satisfies the relationship of the exponent power of 2, that is, if 32 terminal nodes are used, 16 routing nodes are needed, if 31 terminal nodes are used, 16 routing nodes are needed, each two terminal nodes are mounted on one routing node, and a bidirectional two-way data connection channel is established between the routing nodes.

In some embodiments, for a total of 14 end nodes of fig. 4, we use 4 bits to represent each end node, such as: 0000 denotes terminal node 0, 0001 denotes terminal node 1, … …,1110 denotes terminal node 14. In fig. 4, a total of 8 routing nodes, the other bits except the lowest bit in the binary code corresponding to the terminal node are used as the binary codes corresponding to the routing nodes, and the lowest bit refers to the rightmost bit in the binary code, for example, the first 3 bits of 4 bits are used to represent the routing nodes, for example, 000_represents the routing node 0, 001_represents the routing node 1, … …, 110_represents the routing node 6, and 111_represents the routing node 7. The rightmost bit of the first path encoding calculation does not participate in the calculation, and for example, the portion of the routing node 1 participating in the calculation is denoted as "001" and the portion of the routing node 2 participating in the calculation is denoted as "010". The bitwise exclusive-or operation means that the numerical values of the corresponding bits of the first routing code and the second routing code are subjected to exclusive-or rules such as: and if the values of the corresponding bits are the same, the corresponding bit value in the first path code is generated and is marked as 0, if the values of the corresponding bits are different, the corresponding bit value on the first path code is generated and is marked as 1, and the first path code generated by bitwise exclusive or of '001' and '010' is expressed as '011' according to the calculation rule.

Step 103, in response to at least one bit in the first path code being equal to one, determining a highest bit in the first path code being equal to one, and determining the target parent routing node layer based on a first number of bits corresponding to the highest bit being equal to one.

In some embodiments, the most significant bit of one in the first path code is 1 and is located at the leftmost bit, and the first number of bits is the position number of the most significant bit of one in the first path code when the number of bits is from low to high, for example, when the first path code is "011", the most significant bit of one is "_1_", and the first number of bits is 2.

In some embodiments, the target parent routing node layer is the routing node layer where the nearest available parent routing node is located.

Step 104, determining the target father routing node in all routing nodes of the target father routing node layer.

In some embodiments, at least one available parent routing node may be determined in the same target parent routing node layer, with any one of several available parent routing nodes being selected as the target parent routing node.

And 105, generating a routing path according to the source routing node, the destination routing node and the target father routing node, and executing the routing request by the routing path.

According to the method for realizing the double-host routing, according to the received routing request for executing under the same sub-network, the binary codes corresponding to the source routing node number and the destination routing node number bit through which the routing request passes are respectively used for generating the first routing code by bit exclusive OR operation, the number of the target father routing node layer is determined according to the numerical value at each position in the first routing code so as to obtain the target father routing node, finally, the routing paths corresponding to the routing request for executing in the same sub-network are generated according to the source routing node, the destination routing node and the target father routing node, the obtained routing paths ensure that the sub-networks controlled by the double hosts do not interfere each other to route and independently transmit data packets when the internal source terminal nodes mutually transmit the data packets.

In some embodiments, the step 104, determining the target parent routing node among all routing nodes of the target parent routing node layer, includes:

responding to the condition that a second path code corresponding to a routing node exists in a target father routing node layer to meet a first preset condition, and the routing node meets a second preset condition and a third preset condition, and taking each routing node of the target father routing node layer meeting the preset condition as a preliminary father routing node;

one of all the preliminary parent routing nodes is selected as a target parent routing node, for example, any one is selected.

In some embodiments, the preliminary parent routing node is an available parent routing node in the target parent routing node layer.

In some embodiments, each routing node in the target parent routing node layer can be used as an available parent routing node after the following three preset conditions are satisfied:

the method comprises the steps that 1, the bit number of each bit equal to 1 in the result of exclusive-or of binary codes corresponding to the routing nodes and binary codes corresponding to the source routing nodes is smaller than or equal to a first bit number, or each bit in the result of exclusive-or is equal to 0;

The condition 2, the routing node and the source routing node are the routing node under the same sub-network;

and 3, if no routing node under another sub-network exists in the routing nodes connected in the next layer of the routing nodes.

In some embodiments, the step of having the second path code corresponding to the routing node in the target parent routing node layer satisfies the first preset condition includes: and determining that the second path code meets the first preset condition in response to the fact that the number of bits corresponding to the highest bit equal to one in the second path code is smaller than or equal to the first number of bits or all bits equal to zero in the second path code.

In some embodiments, the step of the routing node meeting a second preset condition includes: and determining that the routing node of the target father routing node layer meets a second preset condition in response to the fact that the routing node of the target father routing node layer and the source routing node are located in the same sub-network.

In some embodiments, the step of the routing node meeting a third preset condition includes: and determining that the routing node of the target father routing node layer meets a third preset condition in response to the fact that the next routing node connected with the routing node of the target father routing node layer is located in the same sub-network as the source routing node.

According to the method for realizing the double-host route, the second path coding is used for combining with the preset condition to screen the available father route nodes in the target father route node layer, the selected target father route nodes, the source route nodes and the destination route nodes can be guaranteed to be in the same sub-network, the problem that the route is paused in the other sub-network due to the fact that the route is paused in the other sub-network can be avoided through the route obtained based on the fact, the route is easy to realize, and the route is easy to obtain.

In some embodiments, the foregoing step 105, the step of generating a routing path according to the source routing node, the destination routing node, and the target parent routing node, includes:

According to the implementation method of the double-host route, the obtained target father route node, the source route node and the destination route node are all determined to be located in the same sub-network, so that the first path and the second path can be ensured to be located in the same sub-network, and the problem that the route path is interfered with the other route through the other sub-network is solved.

In some embodiments, the step of determining the first path from the source routing node and the target parent routing node comprises:

and combining the source terminal node, the source routing node, the first intermediate routing node and the target parent routing node to obtain a first path.

According to the implementation method of the dual-host route, different methods for determining and obtaining the shortest first path based on the first bit number are adopted, under the condition that the first path has intermediate route nodes, the first path with the minimum number passing through the intermediate route nodes can be indicated through the third path coding, the first path can be guaranteed to be the shortest path, and the time consumption caused by the long route path is reduced.

the least significant bit of the third path code is used as a first current bit, a routing node layer corresponding to the source routing node is used as a first current routing node layer, and the first routing code is used as a first current routing code;

Judging whether the first current bit is equal to one;

and in response to the bit number of the first current bit not reaching the highest significant bit number of the third path code, moving the first current bit leftwards by one bit to obtain a new first current bit, taking the upper layer of the first current routing node layer as a new first current routing node layer, taking the binary code corresponding to the first intermediate routing node in the upper layer as the new first current routing code, and returning to the step of judging whether the first current bit is equal to one or not until the first current bit reaches the highest significant bit number of the third path code.

According to the implementation method of the double-host route, values are sequentially obtained from low to high in the third path code bit by bit, binary codes of corresponding route nodes are processed according to the values on each bit to find a plurality of first intermediate nodes with sequences, each first intermediate route node passing through the first path is determined according to the third path code obtained by calculation of the source route node and the target father route node, the determined first intermediate route nodes are all in the same sub-network as the source route node, each first intermediate route node is uniquely determined in the intermediate route node layer, and high accuracy is achieved.

respectively taking a source terminal node and a target father routing node as a first starting point and a first ending point of a first path;

the source routing node and all first intermediate routing nodes are placed between a first start point and a first end point in the order of generation to generate a first path.

The implementation method of the dual-host route in the embodiment sets a specific combination sequence for all the determined route nodes, specifically takes the source terminal node as a starting point, takes the target father route node as an ending point, and inserts the target father route node between the starting point and the ending point according to the determined generation sequence of the intermediate route node.

In some embodiments, the step of determining the second path from the destination routing node and the target parent routing node comprises:

performing bit-wise exclusive OR operation on the second routing code and the third routing code to generate a fourth routing code, and determining a second intermediate routing node based on the fourth routing code;

According to the implementation method of the dual-host route, different methods for determining and obtaining the shortest second path based on the first bit number are adopted, when the first bit number is greater than one, intermediate routing nodes exist in the first path, and at the moment, the second path also has the intermediate routing nodes, the second path which passes through the intermediate routing nodes and is the least in number and is unique in path can be indicated through fourth path coding, the second path can be guaranteed to be the shortest path, and time consumption caused by the long routing path is reduced.

In some embodiments, the step of determining the second intermediate routing node based on the fourth path encoding comprises:

Judging whether the second current bit is equal to one;

if the second current bit is equal to one, inverting the bit on the bit number corresponding to the second current bit in the second current routing code, and taking the inverted result as a binary code corresponding to a second intermediate routing node in the next layer of the second current routing node layer;

if the second current bit is not equal to one, the second current route code is used as a binary code corresponding to a second intermediate route node in a next layer of the second current route node layer;

and in response to the number of bits of the second current bit not reaching the minimum significant number of the fourth path code, moving the second current bit rightward by one bit to obtain a new second current bit, taking the next layer of the second current routing node layer as a new second current routing node layer, taking the binary code corresponding to a second intermediate routing node in the next layer as the new second current routing code, and returning to the step of judging whether the second current bit is equal to one or not until the second current bit reaches the minimum significant number of the fourth path code.

According to the implementation method of the double-host route, values are sequentially obtained from high to low in the fourth route code bit by bit, binary codes of corresponding route nodes are processed according to the values on each bit to find a plurality of second intermediate nodes with sequences, each second intermediate route node passing through the second route is determined according to the fourth route code obtained by calculation of the target route node and the target father route node, the determined second intermediate route nodes are all in the same sub-network as the target route node, each second intermediate route node is uniquely determined in the intermediate route node layer, and the accuracy is high.

In some embodiments, the step of combining the destination end node, the destination routing node, the second intermediate routing node, and the target parent routing node to obtain the second path comprises:

respectively taking the target father route node and the target terminal node as a second starting point and a second ending point of a second path;

all second intermediate routing nodes and destination routing nodes are placed between the second starting point and the second ending point in the generating order to generate a second path.

The implementation method of the dual-host route in the embodiment sets a specific combination sequence for all the determined routing nodes, specifically takes the father routing node as a starting point, takes the destination routing node as an ending point, and inserts the destination routing node between the starting point and the ending point according to the determined generation sequence of the intermediate routing node.

In some embodiments, the method for implementing dual-host routing further includes: and if the first bit number is equal to one, combining the source terminal node, the source routing node and the target father routing node to obtain a first path.

In some embodiments, the method for implementing dual-host routing further includes: and if the first bit number is equal to one, combining the destination terminal node, the destination routing node and the destination father routing node to obtain a second path.

In some embodiments, the step 103, determining the target parent routing node layer based on the first number of bits corresponding to the most significant bit equal to one, includes: and taking the result of adding one to the first number of bits as a target layer number, and taking a routing node layer corresponding to the target layer number as a target father routing node layer.

In some embodiments, the method for implementing dual-host routing further includes: and in response to all bits in the first path code being equal to zero, confirming that the source routing node and the destination routing node are the same routing node, and executing the routing request inside the same routing node.

In order to facilitate understanding of the scheme of the present invention, taking a fat tree network for supporting dual hosts as an example, the implementation method of the dual-host routing of the present invention is described in detail, and the implementation principle is that the topology structure of the fat tree network, and a implementation manner of the routing for avoiding mutual interference between two sub-networks when communication is performed between source terminal nodes in the same sub-network is provided, and the specific implementation process is as follows:

Taking fig. 2 as an example, assuming that a source routing node is S and a destination routing node is D, the following describes a method for implementing dual-host routing:

the first step: the source routing node S and the destination routing node D are subjected to exclusive OR, and the exclusive OR result is marked as I; the highest bit position of "1" in I is seen from low to high to be the kth bit, and the valid bit of I is the low k bit. For example, assuming that S is "001_", D is "010_", bitwise exclusive or followed by I is "011", the highest bit position of "1" in I is seen from the lower to the upper bit, at bit 2, i.e., the first number of bits is 2, and the valid bit of I is the lower 2 bits;

and a second step of: checking each bit of the I, if each bit of the I is 0, proving that the source terminal node and the target terminal node are in the same routing node, and directly routing in the routing node, wherein the routing is finished; if each bit of I is not 0, entering a third step;

and a third step of: the number of layers in which the nearest parent routing node is located is determined. Looking at the position of the highest bit of 1 in I from low to high, and at the kth bit, the nearest father routing node is at the k+1th layer; for example, I is "011", and the highest bit of "1" in I is at bit 2 from low to high, then the nearest parent routing node is at layer 3;

Fourth step: the parent routing nodes available in the nearest parent routing node layer are determined. Thirdly, knowing that the nearest father routing node is in the k+1th layer, the following three conditions are required to be satisfied in all routing nodes in the k+1th layer:

condition 1: the bit of the bit exclusive OR result of the S is in low k bit, or the bit exclusive OR result is 0;

condition 2: routing nodes belonging to the same sub-network of S;

condition 3: among the routing nodes connected to the next layer, no routing node of another sub-network exists;

the three conditions are that the S same sub-network routes available father nodes;

for example, for the routing request of the first subnetwork, assuming that S is "001_", D is "010_", I is "011" after bitwise exclusive or, the highest bit of "1" in I is at bit 2, then the I valid bit is low 2, I can be updated to "_11", then the nearest parent routing nodes of S and D are at the third layer, and the routing node satisfying condition one in the third layer is 0/1/2/3, the routing node satisfying condition two is 0/1/2, the condition 3 is 0/2, then 0/2 is the available parent routing node;

fifth step: s routes to an available father node F meeting the fourth step; continuing with the illustration in the fourth step, S routes to an available parent node F in 0/2, assuming F is "010_";

5.1: the routing node S and the father node F are exclusive-ored according to the bit, and the result is recorded as I1; the significant bit of I1 is the low k bit; continuing with the illustration in the fourth step, I1 is "011", the low 2 bits of I1 are the valid bits, and I1 is updated to "_11":

5.2: the valid bit in the I1 starts from a low bit, the bit corresponding to S is inverted at the position of the I1 of '1', a routing node of the route of the upper layer is obtained, and the route directly jumps to the upper layer at the position of the I1 of '0'; for example:

001 of the first layer (_11) →000 of the second layer (_1_) →010 of the third layer (___)

5.3: reaching an available father node F, and entering a sixth step;

sixth step: the father routing node F routes to the destination routing node D;

6.1: the father routing node F and the routing node D are exclusive-ored according to the bit, and the result is recorded as I2; the effective bit of I2 is low k bit; continuing with the illustration in the fourth step, I2 is "000", the low 2 bits of I1 are the valid bits, and I2 is updated to "_00":

6.2: the valid bit in I2 starts from the high position, the bit corresponding to S is inverted at the position of I2 being 1, a routing node for routing to the next layer is obtained, and the position of I2 being 0 is directly jumped to the next layer; then, entering a seventh step; continuing the illustration in step 6.2, i2= _00 is skipped directly twice and reaches 010 of the first layer; for example:

001 of the third layer (_00) →010 of the second layer (__ 0) →010 of the first layer (___)

Seventh step: and routing the routing information to the destination terminal node according to the last bit of the D.

In the above example, the direct upward jump refers to the route node directly jumping upward to the route node with the same number of the higher layer; direct downward jump refers to the route node directly jumping downward to the route node with the same number of the lower layer; the upward route refers to the route node to route to the route node with different numbers of the higher layer according to the method of the double-host route realization of the invention; downward routing: the routing node is routed to the routing node with different numbers of the lower layer according to the method for realizing the double-host routing.

The implementation method of the dual-host routing, which is applied to the fat-tree network supporting the dual hosts, provides a routing mode for avoiding mutual interference of two sub-networks during communication between source terminal nodes in the same sub-network, limits routing paths, ensures that the obtained routing paths pass through only one sub-network, avoids the ongoing routing suspension in the other sub-network caused by the routing paths passing through the other sub-network when the data are transmitted in the sub-network, maintains the stability of the routing of the whole network, and greatly improves the stability and communication efficiency of the whole network by independently carrying out the routing in each sub-network.

In some embodiments, referring to fig. 4, the present invention further provides a dual-host routing implementation system, where the dual-host routing implementation system includes:

an obtaining unit 110, configured to, in response to receiving a routing request, where a source routing node and a destination routing node through which the routing request passes are located in a same sub-network managed by a same host, respectively obtain binary codes corresponding to numbers of the source routing node and the destination routing node, so as to obtain a first routing code and a second routing code;

a generating unit 120, configured to perform a bitwise exclusive-or operation on the first routing code and the second routing code to generate a first routing code;

a target parent routing node layer determining unit 130, configured to determine, in response to at least one bit in the first path code being equal to one, a highest bit in the first path code being equal to one, and determine a target parent routing node layer based on a first number of bits corresponding to the highest bit being equal to one;

a target parent routing node determining unit 140, configured to determine a target parent routing node among all routing nodes of the target parent routing node layer;

the execution unit 150 is configured to generate a routing path according to the source routing node, the destination routing node, and the destination parent routing node, and execute the routing request by the routing path.

According to the system for realizing the double-host routing, according to the received routing request for executing under the same sub-network, the binary codes corresponding to the source routing node number and the destination routing node number bit through which the routing request passes are respectively processed by bitwise exclusive OR operation to generate a first routing code, the number of a target father routing node layer is determined according to the numerical value at each position in the first routing code to obtain the target father routing node, finally, the routing paths corresponding to the routing request for executing in the same sub-network are generated according to the source routing node, the destination routing node and the target father routing node, the obtained routing paths ensure that the sub-networks controlled by the double hosts do not interfere each other to route and independently transmit data packets when the internal source terminal nodes mutually transmit data packets, the system for realizing the routing is simple, no additional operation (such as discarding certain routing ports or cutting off certain paths) is needed by hardware, the hardware implementation is easy, the whole routing in another sub-network is prevented from being paused due to the fact that the routing path passes through the other sub-network when the internal data is transmitted, the whole internal sub-network is maintained, the overall routing efficiency of the internal sub-network is greatly improved, and the stability of the internal sub-network is greatly improved, and the internal stability of the routing network is greatly realized.

It should be noted that, for specific limitation of the implementation system of the dual-host route, reference may be made to the limitation of the implementation method of the dual-host route hereinabove, and the description thereof is omitted herein. The modules in the dual host routing implementation system described above may be implemented in whole or in part by software, hardware, and combinations thereof. The above modules may be embedded in hardware or independent of a processor in the electronic device, or may be stored in software in a memory in the electronic device, so that the processor may call and execute operations corresponding to the above modules.

According to another aspect of the present invention, as shown in fig. 5, an embodiment of the present invention further provides a switching device 30, where the switching device 30 includes a processor 310 and a memory 320, and the memory 320 stores a computer program 321 that can be run on the processor, and the processor 310 executes the steps of the method as described above when executing the program.

According to another aspect of the present invention, as shown in fig. 6, based on the same inventive concept, an embodiment of the present invention also provides a computer-readable storage medium 40, the computer-readable storage medium 40 storing a computer program 410 which when executed by a processor performs the above method.

Embodiments of the application may also include corresponding computer devices. The computer device includes a memory, at least one processor, and a computer program stored on the memory and executable on the processor, the processor executing any one of the methods described above when the program is executed.

The memory is used as a non-volatile computer readable storage medium, and can be used for storing non-volatile software programs, non-volatile computer executable programs and modules, such as program instructions/modules corresponding to the network resource coordination method in the embodiment of the application. The processor executes various functional applications of the device and data processing by running non-volatile software programs, instructions and modules stored in the memory, i.e. implements the network resource coordination method of the above method embodiments.

The memory may include a memory program area and a memory data area, wherein the memory program area may store an operating system, at least one application program required for a function; the storage data area may store data created according to the use of the device, etc. In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory optionally includes memory remotely located relative to the processor, the remote memory being connectable to the local module through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

Finally, it should be noted that, as will be appreciated by those skilled in the art, all or part of the procedures in implementing the methods of the embodiments described above may be implemented by a computer program for instructing relevant hardware, and the program may be stored in a computer readable storage medium, and the program may include the procedures of the embodiments of the methods described above when executed. The storage medium of the program may be a magnetic disk, an optical disk, a read-only memory (ROM), a random-access memory (RAM), or the like. The computer program embodiments described above may achieve the same or similar effects as any of the method embodiments described above.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the invention, and many other variations of the different aspects of the embodiments of the invention as described above exist, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.

Claims

1. The implementation method of the double-host route is characterized by comprising the following steps:

2. The method for implementing dual host routing according to claim 1, wherein said step of determining a target parent routing node among all routing nodes of said target parent routing node layer comprises:

3. The method according to claim 1, wherein the step of generating a routing path according to the source routing node, the destination routing node, and the target parent routing node comprises:

4. A method of implementing dual host routing according to claim 3, wherein the step of determining a first path from the source routing node and the target parent routing node comprises:

5. The method of dual host routing implementation of claim 4, wherein the step of determining a first intermediate routing node based on the third path encoding comprises:

judging whether the first current bit is equal to one;

6. The method according to claim 5, wherein the step of combining the source end node, the source routing node, the first intermediate routing node, and the target parent routing node to obtain a first path comprises:

And placing the source routing node and all the first intermediate routing nodes between the first starting point and the first ending point according to the generation sequence so as to generate the first path.

7. A method of implementing dual host routing according to claim 3, wherein the step of determining a second path from the destination routing node and the target parent routing node comprises:

performing a bitwise exclusive OR operation on the second routing code and the third routing code to generate a fourth routing code, and determining a second intermediate routing node based on the fourth routing code;

8. The method of dual host routing implementation of claim 7, wherein the step of determining a second intermediate routing node based on the fourth path code comprises:

Judging whether the second current bit is equal to one;

9. The method according to claim 8, wherein the step of combining the destination terminal node, the destination routing node, the second intermediate routing node, and the target parent routing node to obtain the second path includes:

Respectively taking the target father routing node and the target terminal node as a second starting point and a second ending point of a second path;

and placing all the second intermediate routing nodes and the destination routing nodes between the second starting point and the second ending point according to the generation sequence so as to generate the second path.

10. The method for implementing dual-host routing according to claim 2, wherein the step of having the second path code corresponding to the routing node in the target parent routing node layer satisfies a first preset condition includes:

11. The method for implementing dual-host routing according to claim 2, wherein the step of the routing node meeting a second preset condition includes:

12. The method for implementing dual-host routing according to claim 2, wherein the step of the routing node meeting a third preset condition includes:

13. The method for implementing dual host routing according to claim 4, wherein the method for implementing dual host routing further comprises:

14. The method for implementing dual host routing according to claim 7, wherein the method for implementing dual host routing further comprises:

15. The method according to claim 1, wherein the step of determining the target parent routing node layer based on the first number of bits corresponding to the highest bit equal to one comprises:

16. The method for implementing dual host routing according to claim 1, wherein the method for implementing dual host routing further comprises:

17. The method for implementing dual host routing according to claim 1, wherein the method for implementing dual host routing further comprises:

18. The method of claim 5, wherein the most significant number of bits encoded by the third path corresponds to the first number of bits.

19. The method of claim 7, wherein the most significant number of bits of the fourth path code corresponds to the first number of bits.

20. A system for implementing dual host routing, comprising:

21. A switching device, comprising:

at least one processor; and

a memory storing a computer program executable on the processor, wherein the processor performs the steps of the method of any one of claims 1 to 19 when the program is executed.

22. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor performs the steps of the method according to any one of claims 1 to 19.