CN117155539B - Confusion of analog radio frequency circuit netlist, restoration method, device, terminal and medium thereof - Google Patents

Confusion of analog radio frequency circuit netlist, restoration method, device, terminal and medium thereof Download PDF

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Publication number
CN117155539B
CN117155539B CN202311427424.1A CN202311427424A CN117155539B CN 117155539 B CN117155539 B CN 117155539B CN 202311427424 A CN202311427424 A CN 202311427424A CN 117155539 B CN117155539 B CN 117155539B
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confusion
circuit
file
netlist
radio frequency
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CN117155539A (en
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侯宇轩
陈华
周旻
郁发新
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Zhejiang University ZJU
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Zhejiang University ZJU
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/002—Countermeasures against attacks on cryptographic mechanisms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H04L9/0894—Escrow, recovery or storing of secret information, e.g. secret key escrow or cryptographic key storage
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/30—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
    • H04L9/3006—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy underlying computational problems or public-key parameters
    • H04L9/302—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy underlying computational problems or public-key parameters involving the integer factorization problem, e.g. RSA or quadratic sieve [QS] schemes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/04—Masking or blinding
    • H04L2209/043—Masking or blinding of tables, e.g. lookup, substitution or mapping
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/16—Obfuscation or hiding, e.g. involving white box

Abstract

The invention provides a confusion and restoration method, a device, a terminal and a medium for simulating a radio frequency circuit netlist, and aims to establish a corresponding secondary diagram model by utilizing a circuit design schematic diagram, quantize element node importance based on structural information of the diagram, carry out white-box confusion encryption on elements in a circuit according to the quantized node importance, encrypt a white-box decryption lookup table based on asymmetric encryption, ensure the safety of a confusion restoration file, namely the white-box decryption lookup table in a transmission process, ensure that only a process where a corresponding simulator is located can read the confusion-free circuit netlist based on process control, ensure the safety of an execution environment, solve the problems that RSA black-box encryption circuit details are invisible and the safety of circuit performance locking based on keys is low, and effectively prevent reverse engineering in a collaborative design process of a simulation circuit.

Description

Confusion of analog radio frequency circuit netlist, restoration method, device, terminal and medium thereof
Technical Field
The present invention relates to the technical field of mixing and recovering analog radio frequency circuit netlists, and in particular, to a method, a device, a terminal and a medium for mixing and recovering analog radio frequency circuit netlists.
Background
The data interaction necessary for the co-design of analog rf circuits is contradictory to its core data protection, and for highly integrated chips, the use of IP for third party design to achieve overall system functionality has become a necessary trend. The multiparty collaborative design can promote the sharing of resources of all parties, thereby reducing the design cost and improving the efficiency.
In the collaborative design process, various design data need to be exchanged between the chip research and development party and the collaborative party, and in the process, the high-value IP shared by the third party has the risk of reverse engineering by the IP user, so that the rights and interests of the IP provider can be damaged. How to effectively protect the core part in the circuit design while ensuring that each co-designer can exert the design level and application potential of the co-designer becomes a key problem of the co-designer.
In the process of collaborative design of an analog circuit, each collaborative designer generally uses a netlist corresponding to the circuit design as a medium to perform data interaction so as to realize circuit IP sharing. After the co-party completes the design of the circuit IP to be provided for the designer, the corresponding netlist is generated through EDA software, the netlist is transmitted to the total designer, the total designer uses the netlist to generate a corresponding circuit schematic diagram in the EDA software, and subsequent overall design and simulation are performed on the basis.
Aiming at the potential intellectual property leakage and theft problems in the collaborative research and development process, the prior solution is to encrypt the black box of the circuit netlist based on encryption algorithms such as RSA and the like and realize the intellectual property protection of the circuit IP by two ways of performing performance locking in the circuit by using a mesh transistor confusion technology based on a secret key.
(1) The RSA black box encryption is to generate a corresponding netlist after finishing circuit design corresponding to IP through EDA software, generate a messy code invisible file after black box encryption is carried out on the netlist, take the messy code file as IP to a research and development party, establish Symbol in EDA software and correspond the code in the messy code form to the netlist, refer to the IP through Symbol, finish secondary design on the basis, and finally finish decryption of the encrypted netlist implicitly by an EDA simulator during simulation to obtain simulation results.
(2) The key-based confusion mode is to lock the circuit performance by replacing a single transistor in the circuit design with a plurality of transistors connected in series and parallel, each transistor has a corresponding switch to control whether the transistor is connected into the circuit, and the 01 key-based switch control ensures that the circuit can achieve the original performance only when the correct switch key is input.
However, the above prior art techniques, which are based on encryption algorithms such as RSA encrypting the black box of the circuit netlist and by performing both performance locking in the circuit by using key-based mesh transistor aliasing techniques, have the following drawbacks.
Firstly, the encryption protection of the black box based on the RSA encryption algorithm can ensure that the design data of the black box is not seen by others through the encryption protection of core parameters, but the most effective interaction of information cannot be achieved, namely, a co-designer needs to know the internal design principle of the black box to better integrate and match the peripheral design of the black box, rather than a black box system only knowing the input and the output.
Secondly, the mode of performing performance locking through a multi-transistor serial-parallel connection mode aims at a pirate without professional circuit expertise, a small number of transistors are replaced by using mesh transistors, the circuit topology is still reserved, and a designer with rich experience can perform reverse engineering reduction circuit according to the method. The potential transmission leakage problem of the key in the transmission process does not take effective protective measures.
Therefore, there is a need in the art for a solution that is more secure and visible to the circuit design.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present application is to provide a method, an apparatus, a terminal and a medium for confusion of a simulated radio frequency circuit netlist and restoration thereof, which are used for solving the technical problems that the most effective information interaction and the risk of reverse engineering restoration still cannot be achieved in the existing confusion technology.
To achieve the above and other related objects, a first aspect of the present application provides a method for confusion and restoration of an analog radio frequency circuit netlist, comprising: the IP sharing party generates an analog radio frequency circuit netlist corresponding to the IP after the EDA software completes the design of the analog radio frequency circuit; the simulation radio frequency circuit netlist is used as input of a confusion program to be confused, and confusion circuit data and confusion-removing files are respectively obtained; the confusion-removed file is asymmetrically encrypted through an IP user public key, so that only an IP user designated by a sharing party can decrypt the confusion-removed file by using a private key of the IP user to obtain an original confusion-removed file; the IP user receives the confusion circuit data shared by the sharing party and the asymmetrically encrypted confusion file, obtains an original confusion file by using a private key, imports the confusion circuit data into EDA software, performs subsequent design and then outputs secondary design with a confusion sub-circuit; taking the secondary design with the confusion sub-circuit and the original confusion file as the input of a confusion program to obtain the original circuit file; and inputting the original circuit file into EDA software for design to obtain a real simulation result.
In some embodiments of the first aspect of the present application, the process of obfuscating and reducing the analog radio frequency circuit netlist includes the following: reading and analyzing the simulation radio frequency circuit netlist and constructing a corresponding first-level bipartite graph model and a corresponding second-level graph model; calculating the weight of each wire net based on the first-level bipartite graph model for topology confusion; calculating the weight of each component for component parameter confusion based on the secondary graph model; storing the original information of the confused device into a confused file in KV format; firstly encrypting the confusion-removed file through a public key built in a confusion program, and then carrying out secondary encryption through an IP user public key; after the IP user obtains the confusion circuit data and the confusion de-file, the private key of the IP user is used for decrypting the confusion de-file, and then the confusion de-file and the confusion circuit netlist are input into a confusion de-program; the confusion removing program decrypts the original confusion removing file according to the embedded private key; and searching and replacing the confusion circuit according to KV information to obtain a confused circuit netlist.
In some embodiments of the first aspect of the present application, the process of reading and parsing the analog radio frequency circuit netlist and constructing a corresponding circuit second level diagram model includes: reading a simulation radio frequency circuit netlist, and performing netlist analysis through a netlist analyzer to establish each level of data structure corresponding to the circuit; and establishing a set of circuit modules to be confused based on the analyzed data structures of all levels to generate a first-level bipartite graph model of the components and the wire network, and establishing a corresponding second-level graph model based on the first-level bipartite graph model.
In some embodiments of the first aspect of the present application, the reading the analog radio frequency circuit netlist and performing netlist parsing by a netlist parser includes reading the analog radio frequency circuit netlist by rows and performing netlist parsing, and specifically includes: reading and storing relevant file paths and setting information of a model used in the simulation radio frequency circuit netlist, and expressing that the model file paths and the setting information are completely analyzed by a specific prefix when the current time is analyzed; analyzing each sub-circuit module and a circuit top layer design module from the current row; and analyzing devices contained in each sub-circuit module and the top layer design module in sequence according to a preset grammar rule.
In some embodiments of the first aspect of the present application, the distinguishing manner between the sub-circuit module and the circuit top-layer design module includes the following: after three rows of module position related information with prefixes of// Library name,// Cell name,// View name are read, the current row is a sub-circuit module if a subekt keyword is used as a prefix, and is a top-layer design module if no subekt keyword is used as a prefix.
In some embodiments of the first aspect of the present application, the computing weights for each net based on the first-order bipartite graph model is used for topology confusion; and calculating weights for each component for component parameter confusion based on the secondary graph model, comprising: the weight of each wire net is calculated in the first-level bipartite graph model and used for topology confusion; and the reconstructed secondary graph model obtains the weight of each component according to calculation, and all the components are ordered in descending order according to the weight for component parameter confusion.
In some embodiments of the first aspect of the present application, the obfuscation procedure is as follows: after the establishment of the secondary graph model corresponding to the circuit is completed, quantifying the importance degree of the network nodes through the connection density of the network and the components in the primary bipartite graph model; in the first-level graph model, firstly, calculating the sum of the weights of all edges connected with the wire nets to serve as the weight of each wire net, and then, calculating the sum of the weights of all the wire nets connected with each component to serve as the wire net centrality corresponding to each component; then, in the second-level graph model, obtaining the centrality of each component by calculating the sum of the weights of the edges of the component nodes; respectively normalizing the two components and summing to obtain importance weights corresponding to the nodes of each component; the calculation process is as follows:
；
Wherein,representation +.>Connected set of device nodes +.>Representing a network nodeAnd device node->Is a side weight of (2); calculating the centrality of the degree of the centrality of all the components, and obtaining a component node in a second-level graph model +.>Importance of->Sum all the connected ownership rights; centrality of wire mesh of componentImportance of the net connected to the current component in the first-level diagram model +.>And (3) summing; />Representing a network node set in a primary graph model; />Represented in the set of line network nodes in the first level graph model, index +.>Is->；/>Representing that in the edge set of the first level bipartite graph model, there are components +.>Network nodeConnected edges->；/>Subscript in the first level graph model is +.>The importance weight is calculated according to the network connected with the element nodes and calculated after normalization; />The centrality of the net representing the component means the importance of the net connected with the current component in the first-level diagram model +.>And (3) summing; />Representing the centrality of the wire mesh of the component; />A set of nodes representing a first level graph model; />Subscript in the second level graph model +.>Component node passing of (2)Normalizing the importance weight obtained after calculation; / >、/>Respectively representing the subscript +_ in the second level graph model>The centrality of the component nodes; />Representing subscripts ++in the two-level graph model>Component importance of->And the weights of the net nodes connected to it in the first level diagram model and the resulting net importance corresponding to it +.>And, as the final importance weight of the component.
In some embodiments of the first aspect of the present application, the parameter confusion process includes the following: random noise which obeys Gaussian distribution, uniform distribution and Poisson distribution is generated based on to-be-confused parameters of the current components, and corresponding weights of the random noise are generated for each distribution through the uniform distribution; generating noise of Gaussian distribution, uniform distribution and Poisson distribution, multiplying the noise by weight obtained randomly, and accumulating the noise to obtain a final confusion proportion; and multiplying the confusion proportion by the original value, and adding the obtained value to the original data to obtain a parameter value after confusion.
In some embodiments of the first aspect of the present application, the topology confusion process is as follows: randomly distributing all the wire networks to ports of all the components so as to disturb the original topological connection relationship; for each port of the component to be confused, randomly generating a list table formed by all wire nets by uniformly distributing the wire nets as the wire nets which are randomly distributed; and mixing all selected components to be mixed in a random mixing mode to execute mixing of the corresponding topological structure.
To achieve the above and other related objects, a second aspect of the present application provides a device for confusing and recovering a simulated radio frequency circuit netlist, comprising: the netlist generation module is used for generating an analog radio frequency circuit netlist corresponding to the IP after the EDA software completes the design of the analog radio frequency circuit by the IP sharing party; the confusion module is used for carrying out confusion on the analog radio frequency circuit netlist as the input of a confusion program to respectively obtain confusion circuit data and a confusion de-file; the asymmetric encryption module is used for carrying out asymmetric encryption on the confusion-removed file through an IP party public key so that only an IP party appointed by a sharing party can decrypt the confusion-removed file by using a private key of the IP party appointed by the sharing party to obtain an original confusion-removed file; the system comprises an confusion removing module, a confusion removing module and a public key, wherein the confusion removing module is used for enabling an IP user to receive confusion circuit data shared by a sharing party and an asymmetrically encrypted confusion removing file, obtaining an original confusion removing file by using a private key, importing the confusion circuit data into EDA software, performing subsequent design and then outputting a secondary design with a confusion sub-circuit; taking the secondary design with the confusion sub-circuit and the original confusion file as the input of a confusion program to obtain the original circuit file; and the simulation module is used for inputting the original circuit file into EDA software for design to obtain a real simulation result.
To achieve the above and other related objects, a third aspect of the present application provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method of obfuscating and recovering the simulated radio frequency circuit netlist.
To achieve the above and other related objects, a fourth aspect of the present application provides an electronic terminal, including: a processor and a memory; the memory is used for storing a computer program, and the processor is used for executing the computer program stored in the memory so that the terminal executes the confusion and restoration method of the simulation radio frequency circuit netlist.
As described above, the confusion and restoration method, device, terminal and medium of the simulation radio frequency circuit netlist have the following beneficial effects: the invention mainly utilizes a circuit design schematic diagram to establish a corresponding second-level diagram model, quantifies the node importance of components based on the structural information of the diagram, carries out white-box confusion encryption on the components in the circuit according to the quantified node importance, encrypts a white-box decryption lookup table based on asymmetric encryption, ensures the safety of a confusion restoration file, namely the white-box decryption lookup table in the transmission process, ensures that only a process where a corresponding simulator is located can read a defuzzified circuit netlist, ensures the safety of an execution environment based on process control, solves the problems of invisible details of an RSA black-box encryption circuit and lower safety of circuit performance locking based on a secret key, and effectively prevents reverse engineering in the collaborative design process of an analog circuit.
Drawings
FIG. 1 is a flow chart of a method for mixing and recovering a simulated RF circuit netlist according to an embodiment of the present application.
Fig. 2 is a schematic diagram of an implementation flow of an application scenario of a method for simulating confusion and restoration of a radio frequency circuit netlist in an embodiment of the present application.
FIG. 3 is a schematic diagram of a process for confusing and recovering an analog RF circuit netlist in accordance with one embodiment of the present application.
FIG. 4 is a schematic diagram of a process for confusing and recovering an analog RF circuit netlist in accordance with one embodiment of the present application.
Fig. 5 is a schematic diagram of a simple differential amplifier circuit before confusion in an embodiment of the present application.
FIG. 6 is a first-level bipartite diagram of a simple differential amplifier circuit according to an embodiment of the present application.
Fig. 7 is a two-level undirected graph of a simple differential amplifier circuit according to an embodiment of the present application.
Fig. 8 is a circuit diagram of a simple differential amplifier according to an embodiment of the present application after confusion.
FIG. 9 is a schematic diagram of a device for simulating the confusion and restoration of a radio frequency circuit netlist according to an embodiment of the present application.
Fig. 10 is a schematic structural diagram of an electronic terminal according to an embodiment of the present application.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the present disclosure, when the following description of the embodiments is taken in conjunction with the accompanying drawings. The present application may be embodied or carried out in other specific embodiments, and the details of the present application may be modified or changed from various points of view and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It is noted that in the following description, reference is made to the accompanying drawings, which describe several embodiments of the present application. It is to be understood that other embodiments may be utilized and that mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description is not to be taken in a limiting sense, and the scope of embodiments of the present application is defined only by the claims of the issued patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Spatially relative terms, such as "upper," "lower," "left," "right," "lower," "upper," and the like, may be used herein to facilitate a description of one element or feature as illustrated in the figures as being related to another element or feature.
In this application, unless specifically stated and limited otherwise, the terms "mounted," "connected," "secured," "held," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" specify the presence of stated features, operations, elements, components, items, categories, and/or groups, but do not preclude the presence, presence or addition of one or more other features, operations, elements, components, items, categories, and/or groups. The terms "or" and/or "as used herein are to be construed as inclusive, or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a, A is as follows; b, a step of preparing a composite material; c, performing operation; a and B; a and C; b and C; A. b and C). An exception to this definition will occur only when a combination of elements, functions or operations are in some way inherently mutually exclusive.
In order to solve the problems in the background art, the invention aims at the IP data protection problem in the collaborative design process of the analog circuit, provides a white box encryption method for carrying out parameter and topological connection relation confusion on a self-structural characteristic selection device based on the circuit design, ensures the safety of circuit data of a mixed encryption circuit, makes the circuit design visible, and ensures the safety of decryption files in the transmission process by carrying out secondary symmetric encryption on a mixed restoration lookup table and controlling the progress of the restored circuit netlist. The method effectively protects core parameters and topological relation in circuit design, and prevents intellectual property theft and reverse engineering problems of an IP provider in the cooperative process.
In order to make the objects, technical solutions and advantages of the present invention more apparent, further detailed description of the technical solutions in the embodiments of the present invention will be given by the following examples with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Before explaining the present invention in further detail, terms and terminology involved in the embodiments of the present invention are explained, and the terms and terminology involved in the embodiments of the present invention are applicable to the following explanation.
<1> rsa encryption algorithm: is one of the public key encryption algorithms widely used in computer science. The RSA encryption algorithm is based on a mathematical insolubility problem, using a pair of keys: public and private keys. The public key can be made public to anyone and the private key can only be held by a particular user.
<2> obfuscation procedure: code obfuscation is the conversion of the code of a computer program into a functionally equivalent but difficult to read and understand form; the obfuscation procedure may protect the procedure from reverse to some extent. Common confusion methods include symbol confusion, control flow confusion, computation confusion, virtual machine confusion, and the like.
<3> degree centrality (Degree Centrality) is the most direct measure of node centrality characterized in network analysis. The greater the degree of a node, the more centrality the node is, and the more important the node is in the network.
The embodiment of the invention provides a confusion and restoration method of a simulation radio frequency circuit netlist, a system of the confusion and restoration method of the simulation radio frequency circuit netlist and a storage medium storing an executable program for realizing the confusion and restoration method of the simulation radio frequency circuit netlist. With respect to the implementation of the confusion and restoration method of the analog radio frequency circuit netlist, the embodiments of the present invention will describe an exemplary implementation scenario of the confusion and restoration of the analog radio frequency circuit netlist.
Referring to FIG. 1, a flow diagram of a method for confusing and recovering a simulated radio frequency circuit netlist in an embodiment of the invention is shown. Fig. 2 shows a schematic implementation flow diagram of an application scenario of the method for simulating the confusion and restoration of the radio frequency circuit netlist in the embodiment of the invention. The confusion of the analog radio frequency circuit netlist and the restoration method thereof in the embodiment of the invention will be explained with reference to fig. 1 and 2.
Step S11: the IP sharing party generates an analog radio frequency circuit netlist corresponding to the IP after the EDA software completes the design of the analog radio frequency circuit; the simulation radio frequency circuit netlist is used as input of a confusion program to be confused, and confusion circuit data and confusion-removing files are respectively obtained; and carrying out asymmetric encryption on the confusion-removed file through the public key of the IP user so that only the IP user designated by the sharing party can decrypt the confusion-removed file by using the private key of the IP user to obtain the original confusion-removed file.
According to the flow in fig. 2: the IP sharing party completes the corresponding simulation design in EDA software, and the EDA software outputs the corresponding netlist. The netlist is then input to a obfuscation program, which outputs obfuscation circuit data and a defrobation look-up table (i.e., a defrobation file). The method comprises the steps that an anti-confusion lookup table is subjected to asymmetric encryption through an IP (Internet protocol) using party public key, the anti-confusion lookup table after the asymmetric encryption is subjected to trusted storage together with the data of the confusion circuit, and an IP using party designated by a sharing party can use a private key to decrypt to obtain an original anti-confusion file.
Step S12: the IP user receives the confusion circuit data shared by the sharing party and the asymmetrically encrypted confusion file, obtains an original confusion file by using a private key, imports the confusion circuit data into EDA software, performs subsequent design and then outputs secondary design with a confusion sub-circuit; taking the secondary design with the confusion sub-circuit and the original confusion file as the input of a confusion program to obtain the original circuit file; and inputting the original circuit file into EDA software for design to obtain a real simulation result.
According to the flow in fig. 2: the IP user inputs the received data of the garbled circuit into EDA software to design, and a secondary design with garbled sub-circuit is obtained. The IP user decrypts the asymmetrically encrypted confusion de-lookup table (i.e., the confusion de-file) using the private key to obtain the original confusion de-lookup table. And inputting the secondary design with the confusion sub-circuit and the original confusion lookup table into a confusion program together for confusion treatment, thereby obtaining an original circuit file. And finally, inputting the original circuit file into EDA software for simulation design to obtain a final simulation result.
In the embodiment of the present invention, the process of confusion and restoration of the analog rf circuit netlist is shown in fig. 3, and specifically includes the following steps:
step S21: and reading and analyzing the simulation radio frequency circuit netlist and constructing a corresponding first-level bipartite graph model and a corresponding second-level graph model.
Specifically, the steps of reading and analyzing the analog radio frequency circuit netlist and constructing a corresponding circuit secondary diagram model specifically include the following steps:
step S21A: and reading the simulated radio frequency circuit netlist, and performing netlist analysis through a netlist analyzer to establish each level of data structure corresponding to the circuit.
Specifically, the analog radio frequency circuit netlist is read in rows and netlist analysis is performed.
Firstly, reading and storing relevant file paths and setting information of a model used in a simulation radio frequency circuit netlist, and expressing that the model file paths and the setting information are completely resolved by a specific prefix when the current line is resolved. For example, the setting information such as the model-related file path and the device parameter unit in the netlist is read and stored, and the setting information is directly stored, and when the current line is analyzed to be prefixed by// Library name, the model file path and the setting information are completely analyzed.
And secondly, analyzing each sub-circuit module and the circuit top layer design module from the current row. The distinguishing mode between the sub-circuit module and the circuit top layer design module comprises the following steps: after three rows of module position related information with prefixes of// Library name,// Cell name,// View name are read, the current row is a sub-circuit module if a subekt keyword is used as a prefix, and is a top-layer design module if no subekt keyword is used as a prefix.
And sequentially analyzing devices contained in each sub-circuit module and the top layer design module according to a preset grammar rule. Illustratively, if the sub-circuit module is a sub-circuit module, the first row of the device contained in the sub-circuit module has 4 character indents, and the first row of the device contained in the top-level design module has no indents; the port of each device is included by brackets after the device name, each port is separated by a space, the first information indicated by the space separation after the port is the call library unit (CellView) where the device is located, and then each parameter information is located behind the port by the space separation. And analyzing the device information contained in each sub-circuit and the top layer design module in turn according to the grammar rule.
Finally, the setting information of the current circuit simulation is read and stored according to the row.
Step S21B: and establishing a set of circuit modules to be confused based on the analyzed data structures of all levels to generate a first-level bipartite graph model of the components and the wire network, and establishing a corresponding second-level graph model based on the first-level bipartite graph model.
Specifically, after a first-level bipartite graph model is built, the bipartite graph is reconstructed according to the mode that components connected to the same network are connected and all relay networks through which the two components are connected are represented to obtain a second-level graph model.
Illustratively, the primary graph model is denoted as G 1 <V 1 ,E 1 >Wherein node V is divided into two mutually disjoint setsRepresenting the components and net, respectively, the edges being present only +.>And->And edges exist between the nodes, namely, the components and the network nodes when the components are connected to the network through ports, and the weight of the edges is the sum of the number of the components connected with the network. The second level graph model of the circuit is built on the basis of the first level graph model of the circuit, denoted as G 2 <V 2 ,E 2 >The nodes are components in the circuit, and the existence of edges between the two components represents that the two components are connected in a bipartite graph of the first-level graph model through a wire mesh; the calculation mode of the side weight is as follows:
；
wherein,representing the side weight of the side represented by the interconnection of the component i and the component j in the two-level graph model; / >Representing the edge weights of the connection between component i and net k, i.e. two components<i,j>In the first-level graph model, the two devices are connected, and the edge weight of the two devices is the sum of the weights of the edges of all intermediate network nodes passing through the first-level bipartite graph model, so that all graph models for confusion are constructed.
Step S22: calculating the weight of each wire net based on the first-level bipartite graph model for topology confusion; and calculating the weight of each component for component parameter confusion based on the secondary graph model.
Specifically, calculating the weight of each wire net in the first-level bipartite graph model for topology confusion; and the reconstructed secondary graph model obtains the weight of each component according to calculation, and all the components are ordered in descending order according to the weight for component parameter confusion.
The confusion process is specifically described as follows: after the establishment of the secondary graph model corresponding to the circuit is completed, the importance degree of the network nodes is quantified through the connection density of the network and the components in the primary bipartite graph model. For a certain network nodeComputing the sum of the edge weights of all the device nodes connected to it +.>As the center value of the degree of the net node, namely the sum of the weights of all the edges connected with the device node, the specific calculation mode is as follows:
Wherein,representation +.>Connected set of device nodes +.>Representing a wire mesh node->And device node->Is a side weight of (1).
Calculating the centrality of the degree of all the components, and calculating the component nodes in the second-level graph modelImportance of (2)Is the sum of all its contiguous ownership rights. Centrality of wire mesh of component->Importance of the net connected to the current component in the first-level diagram model +.>And (2) sum:
wherein,representing a set of component nodes in a second level graph model,/->Represented in the set of line network nodes in the first level graph model, index +.>Is->，/>Representing that in the edge set of the first level bipartite graph model, there are components +.>And wire net node->Connected edges->。
After the importance of the wire net and the element are obtained in the two modes, respectively normalizing the wire net and the element to unify dimensions, and calculating the duty ratio of the weight of the wire net or the element in the weight of the wire net or the element to normalize the weight:
wherein,representing a set of component nodes in a second level graph model.
Calculating to obtain the centrality normalized weight of the component nodes in the whole circuit diagram, and adding the centrality normalized weight and the centrality normalized weight to obtain the importance score of the component:
it should be noted that, the above formula (7) obtains the importance score of the components by direct addition, the degree centrality of the computing node only counts the connection compactness of the current component in the first-order neighborhood of the current component, and the importance of the component in the full graph Gao Jielin domain is measured by not aggregating the information of the current component node in the full graph. Different edges connected with the ports of each component in the circuit are wire nets, and the centrality of the current component on the whole graph is quantized by accumulating the corresponding weights of the wire nets connected with the ports of the component, and the two parts occupy the same weight on the importance measurement of the component, so that the importance score of the component is obtained in a direct addition mode.
Preferably, in order to avoid the situation that the scores are the same, a random value is generated for each component, a data structure of the scores and the random values is formed, the random values are arranged in descending order for the second keywords according to the scores as the first keywords, a plurality of components in front are selected through a given confusion proportion, when each obtained component is mixed, a random number which is uniformly distributed is generated, the random number is randomly selected in the rest components to be used as a mixing object, and parameter confusion and topology structure confusion are respectively carried out.
Specifically, a random value is generated for each component to form<Score i , Random i >Is then according to the Score i As the first keyword, random i The second key words are arranged in a descending order, and the first rho multiplied by n devices are mixed by a given mixing proportion rho, so that a uniformly distributed shorthand number form ([ 0, 1) is generated when each obtained device is mixed]) At the present period<And 0.1, randomly selecting the components in the rest components as confusion objects, and respectively carrying out the following parameter confusion and topology confusion.
In some examples, the specific process of parameter confusion includes the following: random noise which obeys Gaussian distribution, uniform distribution and Poisson distribution is generated based on to-be-confused parameters of the current components, and corresponding weights of the random noise are generated for each distribution through the uniform distribution; generating noise of Gaussian distribution, uniform distribution and Poisson distribution, multiplying the noise by weight obtained randomly, and accumulating the noise to obtain a final confusion proportion; and multiplying the confusion proportion by the original value, and adding the obtained value to the original data to obtain a parameter value after confusion.
In particular, conventional disturbance-based data is typically implemented by adding a piece of noise data that follows a certain distribution. For the single probability distribution noise, the approximation density distribution of the original noise can be obtained through certain sampling and mathematical derivation, namely, the original data can be mined even if a larger probability exists. Thus for a componentParameters to be confusedRandom noise which is subjected to Gaussian distribution, uniform distribution and Poisson distribution is generated respectively, and corresponding weight is generated for each distribution through the uniform distribution>：
Then generating Gaussian distribution, uniform distribution and Poisson distribution noise, multiplying the Gaussian distribution noise with randomly obtained weights, and accumulating the multiplied noise to obtain a final confusion ratio; the confusion ratio is multiplied by the original value and then added to the original data to be used as a parameter value after confusion, and the method is concretely as follows:
wherein each distribution generates a random number of (0, 0.5) corresponding to its confusion ratio.
In some examples, the specific process of topology confusion is as follows: randomly distributing all the wire networks to ports of all the components so as to disturb the original topological connection relationship; for each port of the component to be confused, randomly generating a list table formed by all wire nets by uniformly distributing the wire nets as the wire nets which are randomly distributed; and mixing all selected components to be mixed in a random mixing mode to execute mixing of the corresponding topological structure.
In particular, the confusion of the topology structure of the circuit refers to that the structure of the circuit becomes complex and disordered by modifying the layout and connection lines of the circuit, thereby increasing the difficulty of reverse engineering. The specific implementation is to randomly distribute all the nets to the ports of each component to disturb the original topological connection relationship. For each Port of the component to be confused, randomly generating a subscript of a list { Net } formed by all nets by uniformly distributing the subscripts as the nets which are randomly distributed. And carrying out confusion on all selected components to be confused in the random scrambling mode to complete confusion of the corresponding topological structure.
Illustratively, the algorithmic content of the circuit obfuscation pseudocode is as follows:
/>
/>
it should be noted that, assuming that n devices are mixed together, each device has k ports, m parameters, t bus networks, and p bits of each parameter are different from the original parameters, the complexity of obtaining the original device parameters and topology by the brute force search method is aboutThe magnitude is extremely large and difficult to crack.
Step S23: storing the original information of the confused device into a confused file in KV format; firstly encrypting the confusion-removed file through a public key built in a confusion program, and then carrying out secondary encryption through an IP user public key; after the IP user obtains the confusion circuit data and the confusion de-file, the private key of the IP user is used for decrypting the confusion de-file, and then the confusion de-file and the confusion circuit netlist are input into a confusion de-program; the confusion removing program decrypts the original confusion removing file according to the embedded private key; and searching and replacing the confusion circuit according to KV information to obtain a confused circuit netlist.
Specifically, after the netlist analysis is completed to obtain a data structure corresponding to the circuit, and before corresponding parameter confusion and topology confusion are carried out on the data structure, a confusion reduction file described in the form of < Key: value > is generated and used as a reduction lookup table for white box confusion. It should be understood that < Key: value > is a format of storing data in Key-Value pairs, similar to a map in Java, the entire database can be understood as a large map, with each Key corresponding to a unique Value. It should be understood that the confusion restore file in the present invention may also be referred to as a defrobulated file, and hereinafter the defrobulated file will be synonymous with the confusion restore file herein.
For the obfuscated IP to generate its unique ID as Key in the obfuscated file through its Library and CellView, the original port and device parameter list is Value. The encryption is carried out by an asymmetric encryption method, a pair of public keys are respectively built in the confusion program and the confusion de-program, the confusion program encrypts the confusion restored file by using the built-in public keys before generating the confusion restored file, and only the confusion restored file is ensured to be decrypted. Each IP user generates a corresponding public key and a private key through a non-array encryption algorithm, the IP user stores each private key, when the IP shared by the sharing party is needed to be used, the public key is given to the corresponding sharing party, and the sharing party encrypts the encrypted confusion restored file through the private key, so that only the IP user authorized by the IP sharing party can acquire the restored file by using the private key.
After the IP user decrypts the private Key to obtain the confusion circuit file, the IP user firstly reads the confusion file to obtain the data in the format < Key: value > which is required for confusion. In the netlist analysis process, for each SUBCKT block, obtaining a corresponding unique ID, searching whether the ID exists in the restored data, namely checking whether the SUBCKT is an confusion module, if so, replacing the corresponding Value restored data, otherwise, not processing. Through process control, only the process where the spectrum simulator is located can read the original circuit data, and the netlist is used as the input of the spectrum simulator to obtain the simulation result corresponding to the true circuit design of the confusing IP.
Illustratively, the pseudocode of the defrobulation process is as follows:
to facilitate a better understanding of the technical solution of the present invention, a process for confusing and recovering an analog rf circuit netlist will be further explained with reference to the specific embodiment in fig. 4, which specifically includes the following steps:
step S301: reading a circuit netlist, and establishing all levels of data structures corresponding to the circuit through a netlist parser.
Step S302: and establishing a set of circuit modules to be confused according to the data structure obtained by analysis, wherein the set of circuit modules to be confused are a first-level bipartite graph model of the components and the wire network respectively.
Step S303: and establishing a connecting edge according to the components connected to the same network, namely connecting two component nodes to the same network node in a first-level bipartite graph model, wherein the network node serves as a relay node connected with the two components, and the edge weights are calculated to meet the sum of the edge weights of all relay networks connected with the two components, so that the bipartite graph is reconstructed to obtain a second-level graph model.
Step S304: the weight of each wire net is calculated in the first-level bipartite graph model and used for topology confusion; and (3) obtaining the weight of each component according to the calculated reconstructed secondary diagram, and sequencing all the components in a descending order according to the weight for device parameter confusion.
Step S305: and according to the confusion proportion rho, parameter topological connection relation confusion is sequentially carried out on the front rho multiplied by n devices after sequencing, a random number t obeying uniform distribution is generated when each device is mixed, when t <0.1 is met, one is randomly selected from the rest devices to carry out the next confusion operation, and otherwise, the devices are mixed.
Step S306: for the current confusion device, firstly adding a random noise to all parameters of the current confusion device to complete confusion of the parameters of the current confusion device; and then randomly selecting one of all net lists obtained by sequentially analyzing the netlist for replacing the port of the device to realize confusion of the topological structure of the device.
Step S307: the original information of the confused device is stored as a confused file in KV format, the confused file is firstly encrypted by a public key arranged in a confusion program, and then secondary encryption is carried out by an IP user public key, so that only the private key of an authorized IP user can decrypt to obtain the original information.
Step S308: after the IP user obtains the confusion circuit and the confusion file, firstly, the private key of the IP user decrypts the confusion file, then, the confusion file and the confusion circuit netlist are input into a confusion program, the confusion program firstly decrypts the confusion file according to the embedded private key to obtain the original confusion file, and then, the confusion circuit is searched and replaced according to KV to obtain the confusion circuit netlist.
Step S309: program control is carried out on the circuit netlist after confusion, so that only the process where the simulator is located has read authority on the netlist, and simulation is carried out to obtain a simulation result.
Further, in order to facilitate a better understanding of the technical solution of the present invention and the technical effects thereof by those skilled in the art, the following description will be further provided with reference to fig. 5, 6, 7 and 8. The simple differential amplifier circuit in fig. 5 forms a corresponding first-stage bipartite graph shown in fig. 6, and then forms a corresponding second-stage undirected graph shown in fig. 7. Fig. 8 shows a circuit diagram of a simple differential amplifier after aliasing.
Specifically, as seen in conjunction with fig. 5 and 6, the circles in the right column in fig. 6 correspond to the partial wiring in the circuit diagram of fig. 5, respectively. Net1 in fig. 6 corresponds to the wiring between a1 and a2, between a3 and a4, between a5 and a6 in fig. 5; net2 in fig. 6 corresponds to the wiring between b1 and b2, and between b3 and b4 in fig. 5; net3 in fig. 6 corresponds to the wiring between c1 and c2 in fig. 5; gnd ≡ in FIG. 6! Corresponding to the wiring between d1 and d2, between d3 and d4, between d5 and d6, between d7 and d8, between d9 and d10 in FIG. 5; vdd-! Corresponding to the wiring between e1 and e2, between e2 and e5, between e5 and e3, between e3 and e4, between e5 and e6 in FIG. 5; VOUT in fig. 6 corresponds to the wiring between f1 and f2, the wiring between f3 and f4, the wiring between f4 and f5, and the wiring between f5 and VOUT in fig. 5; VIN1 in FIG. 6 corresponds to the connection between VIN1 and g1 in FIG. 5; VIN2 in FIG. 6 corresponds to the connection between VIN2 and h1 in FIG. 5.
For the simple amplifier circuit shown in fig. 5, the circuit diagram and the established two-level diagram model are shown in fig. 7, the importance of the circuit components is calculated according to the diagram model, and the confusion of parameters and topological structures is sequentially carried out on the circuit components to obtain the confusion circuit shown in fig. 8. For the garbled circuit, the calculation order of the cracking by means of violent search is 。
Specifically, the garbled circuit in fig. 8, net1 corresponds to the wiring between j1 and j2, the wiring between j2 and j3, the wiring between j2 and j4, the wiring between j4 and j5, the wiring between j5 and j7, the wiring between j5 and j6, the wiring between j5 and j8, the wiring between j8 and j9, the wiring between j8 and j11, the wiring between j9 and j12, and the wiring between j9 and j 10. net2 corresponds to the wiring between k1 and k2, the wiring between k2 and k3, the wiring between k2 and k 4. net3 corresponds to the wiring between L1 and L2. net4 corresponds to the wiring between m1 and m2, the wiring between m2 and m3, the wiring between m3 and m6, the wiring between m2 and m5, the wiring between m7 and m8, the wiring between m8 and m 9. net5 corresponds to the wiring between n1 and n2, between n2 and n3, between n2 and n4, between n4 and n5, between n4 and n6, between n7 and n 8. net6 corresponds to the wiring between o1 and o2, the wiring between o2 and o3, the wiring between o2 and o4, the wiring between o2 and VOUT. Net7 corresponds to the wiring between VIN1 and p1, the wiring between p1 and p2, the wiring between p1 and p 3. Net8 corresponds to the wiring between q1 and VIN 2.
It should be noted that the circuit diagrams in fig. 5 and 8 are only used to illustrate the circuit diagrams before and after confusion, and the structure and principle of the circuit are not the protection of the present patent.
In the above, the confusion and restoration method of the analog radio frequency circuit netlist provided by the invention are explained in detail. The following describes the confusing and recovering device, terminal and medium of the simulation RF circuit netlist with reference to the embodiments and the drawings.
Referring to FIG. 9, a schematic diagram of a device for simulating the confusion and restoration of a radio frequency circuit netlist according to an embodiment of the invention is shown. The device 900 for mixing and recovering the analog radio frequency circuit netlist in the embodiment of the invention comprises a netlist generating module 901, a mixing module 902, an asymmetric encryption module 903, a defrobbing module 904 and a simulation module 905.
The netlist generating module 901 is configured to generate an analog radio frequency circuit netlist corresponding to the IP after the EDA software completes the design of the analog radio frequency circuit.
The confusion module 902 is configured to confusion the analog radio frequency circuit netlist as an input of a confusion program, so as to obtain confusion circuit data and a confusion de-file respectively.
The asymmetric encryption module 903 is configured to perform asymmetric encryption on the defrobulated file by using an IP user public key, so that only an IP user designated by the sharing party can decrypt the defrobulated file by using its private key to obtain an original defrobulated file.
The confusion removing module 904 is configured to receive the confusion circuit data shared by the sharing party and the confusion removing file that is asymmetrically encrypted by the IP user, obtain an original confusion removing file by using a private key, import the confusion circuit data into EDA software, perform subsequent design, and output a secondary design with a confusion sub-circuit; and taking the secondary design with the confusion sub-circuit and the original confusion file as the input of a confusion program to obtain the original circuit file.
The simulation module 905 is configured to input the original circuit file into EDA software for design to obtain a real simulation result.
It should be noted that: the confusion and restoration apparatus 900 for a simulated radio frequency circuit netlist provided in the above embodiment is only exemplified by the above-mentioned division of each program module when the confusion and restoration of the simulated radio frequency circuit netlist are performed, and in practical application, the above-mentioned process allocation may be performed by different program modules according to needs, i.e. the internal structure of the apparatus is divided into different program modules, so as to complete all or part of the above-mentioned processes. In addition, the confusion and restoration device of the analog radio frequency circuit netlist provided in the above embodiment and the confusion and restoration method embodiment of the analog radio frequency circuit netlist belong to the same concept, and the specific implementation process is detailed in the method embodiment, and will not be repeated here.
Referring to fig. 10, an optional hardware structure schematic diagram of an electronic terminal 1000 according to an embodiment of the present invention is shown, where the terminal 1000 may be a mobile phone, a computer device, a tablet device, a personal digital processing device, a factory background processing device, and the like. The electronic terminal 1000 includes: at least one processor 1001, memory 1002, at least one network interface 1004, and a user interface 1006. The various components in the device are coupled together by a bus system 1005. It is to be appreciated that the bus system 1005 is employed to enable connective communication between these components. The bus system 1005 includes a power bus, a control bus, and a status signal bus in addition to the data bus. But for clarity of illustration the various buses are labeled as bus systems in fig. 10.
The user interface 1006 may include, among other things, a display, keyboard, mouse, trackball, click gun, keys, buttons, touch pad, or touch screen, etc.
It is to be appreciated that memory 1002 can be either volatile memory or nonvolatile memory, and can include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read Only Memory (ROM), a programmable Read Only Memory (PROM, programmable Read-Only Memory), which serves as an external cache, among others. By way of example, and not limitation, many forms of RAM are available, such as static random Access Memory (SRAM, staticRandom Access Memory), synchronous static random Access Memory (SSRAM, synchronous Static RandomAccess Memory). The memory described by embodiments of the present invention is intended to comprise, without being limited to, these and any other suitable types of memory.
The memory 1002 in embodiments of the present invention is used to store various categories of data to support the operation of the electronic terminal 1000. Examples of such data include: any executable programs for operating on electronic terminal 1000, such as operating system 10021 and application programs 10022; the operating system 10021 contains various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and handling hardware-based tasks. The application 10022 may include various application programs such as a media player (MediaPlayer), a Browser (Browser), etc. for implementing various application services. The confusion and restoration method for the simulated radio frequency circuit netlist provided by the embodiment of the invention can be contained in the application program 10022.
The method disclosed in the above embodiment of the present invention may be applied to the processor 1001 or implemented by the processor 1001. The processor 1001 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in the processor 1001 or by instructions in the form of software. The processor 1001 may be a general purpose processor, a digital signal processor (DSP, digital Signal Processor), or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. The processor 1001 may implement or execute the methods, steps and logic blocks disclosed in the embodiments of the present invention. The general purpose processor 1001 may be a microprocessor or any conventional processor or the like. The steps of the accessory optimization method provided by the embodiment of the invention can be directly embodied as the execution completion of the hardware decoding processor or the execution completion of the hardware and software module combination execution in the decoding processor. The software modules may be located in a storage medium having memory and a processor reading information from the memory and performing the steps of the method in combination with hardware.
In an exemplary embodiment, electronic terminal 1000 can be implemented by one or more application specific integrated circuits (ASIC, application Specific Integrated Circuit), DSP, programmable logic device (PLD, programmable Logic Device), complex programmable logic device (CPLD, complex Programmable LogicDevice) for performing the methods described above.
Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the method embodiments described above may be performed by computer program related hardware. The aforementioned computer program may be stored in a computer readable storage medium. The program, when executed, performs steps including the method embodiments described above; and the aforementioned storage medium includes: various media that can store program code, such as ROM, RAM, magnetic or optical disks.
In the embodiments provided herein, the computer-readable storage medium may include read-only memory, random-access memory, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, U-disk, removable hard disk, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. In addition, any connection is properly termed a computer-readable medium. For example, if the instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. It should be understood, however, that computer-readable and data storage media do not include connections, carrier waves, signals, or other transitory media, but are intended to be directed to non-transitory, tangible storage media. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.
In summary, the present application provides a method, an apparatus, a terminal and a medium for confusion and restoration of an analog radio frequency circuit netlist, which mainly uses a circuit design schematic diagram to establish a corresponding second-level diagram model, quantizes node importance of components based on structural information of the diagram, performs white-box confusion encryption on the components in a circuit according to the quantized node importance, encrypts a white-box decryption lookup table based on asymmetric encryption, ensures security of a confusion restoration file, namely, the white-box decryption lookup table in a transmission process, ensures that only a process where a corresponding simulator is located can read the confused circuit netlist, ensures security of an execution environment based on process control, solves the problems that details of an RSA black-box encryption circuit are invisible and security of circuit performance locking based on a secret key is low, and effectively prevents reverse engineering in a collaborative design process of an analog circuit. Therefore, the method effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles of the present application and their effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those of ordinary skill in the art without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications and variations which may be accomplished by persons skilled in the art without departing from the spirit and technical spirit of the disclosure be covered by the claims of this application.

Claims (12)

1. A method for simulating confusion and restoration of a radio frequency circuit netlist, comprising:
the IP sharing party generates an analog radio frequency circuit netlist corresponding to the IP after the EDA software completes the design of the analog radio frequency circuit; the simulation radio frequency circuit netlist is used as input of a confusion program to be confused, and confusion circuit data and confusion-removing files are respectively obtained; the confusion-removed file is asymmetrically encrypted through an IP user public key, so that only an IP user designated by a sharing party can decrypt the confusion-removed file by using a private key of the IP user to obtain an original confusion-removed file;
the IP user receives the confusion circuit data shared by the sharing party and the asymmetrically encrypted confusion file, obtains an original confusion file by using a private key, imports the confusion circuit data into EDA software, performs subsequent design and then outputs secondary design with a confusion sub-circuit; taking the secondary design with the confusion sub-circuit and the original confusion file as the input of a confusion program to obtain the original circuit file; inputting an original circuit file into EDA software for design to obtain a real simulation result;
the process of obfuscating the analog radio frequency circuit netlist includes the following: reading and analyzing the simulation radio frequency circuit netlist and constructing a corresponding first-level bipartite graph model and a corresponding second-level graph model; calculating the weight of each wire net based on the first-level bipartite graph model for topology confusion; calculating the weight of each component for component parameter confusion based on the secondary graph model; storing the original information of the confused device into a confused file in KV format; firstly encrypting the confusion-removed file through a public key built in a confusion program, and then carrying out secondary encryption through an IP user public key.
2. The method of confusing and recovering an analog radio frequency circuit netlist as claimed in claim 1, wherein the process of recovering the analog radio frequency circuit netlist comprises:
after the IP user obtains the confusion circuit data and the confusion de-file, the private key of the IP user is used for decrypting the confusion de-file, and then the confusion de-file and the confusion circuit netlist are input into a confusion de-program; the confusion removing program decrypts the original confusion removing file according to the embedded private key; and searching and replacing the confusion circuit according to KV information to obtain a confused circuit netlist.
3. The method for confusing and recovering a simulated radio frequency circuit netlist according to claim 2, wherein the steps of reading and analyzing the simulated radio frequency circuit netlist and constructing a corresponding circuit second level diagram model include:
reading a simulation radio frequency circuit netlist, and performing netlist analysis through a netlist analyzer to establish each level of data structure corresponding to the circuit;
and establishing a set of circuit modules to be confused based on the analyzed data structures of all levels to generate a first-level bipartite graph model of the components and the wire network, and establishing a corresponding second-level graph model based on the first-level bipartite graph model.
4. The method for confusing and recovering a simulated radio frequency circuit netlist according to claim 3, wherein the steps of reading the simulated radio frequency circuit netlist and performing netlist analysis by a netlist analyzer include reading the simulated radio frequency circuit netlist by rows and performing netlist analysis, and specifically include:
Reading and storing relevant file paths and setting information of a model used in the simulation radio frequency circuit netlist, and expressing that the model file paths and the setting information are completely analyzed by a specific prefix when the current time is analyzed;
analyzing each sub-circuit module and a circuit top layer design module from the current row;
and analyzing devices contained in each sub-circuit module and the top layer design module in sequence according to a preset grammar rule.
5. The method of claim 4, wherein the distinguishing between the sub-circuit modules and the top-level design module comprises: after three rows of module position related information with prefixes of// Library name,// Cell name,// View name are read, the current row is a sub-circuit module if a subekt keyword is used as a prefix, and is a top-layer design module if no subekt keyword is used as a prefix.
6. The method of claim 2, wherein the computing weights for each net based on the first-order bipartite graph model is used for topology confusion; and calculating weights for each component for component parameter confusion based on the secondary graph model, comprising: the weight of each wire net is calculated in the first-level bipartite graph model and used for topology confusion; and the reconstructed secondary graph model obtains the weight of each component according to calculation, and all the components are ordered in descending order according to the weight for component parameter confusion.
7. The method of mixing and recovering a simulated radio frequency circuit netlist as claimed in claim 6 wherein the mixing process is as follows:
after the establishment of the secondary graph model corresponding to the circuit is completed, quantifying the importance degree of the network nodes through the connection density of the network and the components in the primary bipartite graph model; in the first-level graph model, firstly, calculating the sum of the weights of all edges connected with the wire nets to serve as the weight of each wire net, and then, calculating the sum of the weights of all the wire nets connected with each component to serve as the wire net centrality corresponding to each component; then, in the second-level graph model, obtaining the centrality of each component by calculating the sum of the weights of the edges of the component nodes; respectively normalizing the two components and summing to obtain importance weights corresponding to the nodes of each component; the calculation process is as follows:
representing the importance of the network connected in the first-level graph model; />Representation and->A set of connected device nodes; />Represented in the first level graph model, net node with subscript j ++>Component node ++with subscript i>An edge weight corresponding to the connected edge of the frame;
representing the component node in the second level graph model +.>Meaning the sum of all the contiguous ownership rights; / >The side weight between the component nodes i and j in the second-level graph model is represented, and the superscript 2 is used for indicating that the graph is the second-level graph model; v (V) 2 Representing a set of component nodes in a second level graph model;
the centrality of the net representing the component means the importance of the net connected with the current component in the first-level diagram model +.>And (3) summing; />Representing a network node set in a primary graph model; />Representing the net nodes with index j in the net node set of the first-level graph model> Representing the presence of components in the edge set of the first level bipartite graph modelAnd wire net node->Connected edges->
The component node with the subscript j in the first-level graph model is calculated according to the connected wire network and is subjected to normalization to calculate the obtained importance weight; />The centrality of the net representing the component means the importance of the net connected with the current component in the first-level diagram model +.>And (3) summing; />Representing the centrality of the wire mesh of the component; v (V) 1 A set of nodes representing a first level graph model;
representing importance weights obtained by normalized calculation of component nodes with subscript j in the second-level graph model; />Respectively representing the centrality of component nodes with subscripts i and j in the second-level graph model; Representing the importance of a component with subscript i in the two-level graph model>And the weights of the net nodes connected to it in the first level diagram model and the resulting net importance corresponding to it +.>And, as the final importance weight of the component.
8. The method of claim 2, wherein the process of parameter confusion comprises: random noise which obeys Gaussian distribution, uniform distribution and Poisson distribution is generated based on to-be-confused parameters of the current components, and corresponding weights of the random noise are generated for each distribution through the uniform distribution; generating noise of Gaussian distribution, uniform distribution and Poisson distribution, multiplying the noise by weight obtained randomly, and accumulating the noise to obtain a final confusion proportion; and multiplying the confusion proportion by the original value, and adding the obtained value to the original data to obtain a parameter value after confusion.
9. The method for confusing and recovering a simulated radio frequency circuit netlist according to claim 2, wherein the topology confusing process is as follows: randomly distributing all the wire networks to ports of all the components so as to disturb the original topological connection relationship; for each port of the component to be confused, randomly generating a list table formed by all wire nets by uniformly distributing the wire nets as the wire nets which are randomly distributed; and mixing all selected components to be mixed in a random mixing mode to execute mixing of the corresponding topological structure.
10. A device for simulating confusion and restoration of a radio frequency circuit netlist, comprising:
the netlist generation module is used for generating an analog radio frequency circuit netlist corresponding to the IP after the EDA software completes the design of the analog radio frequency circuit by the IP sharing party;
the confusion module is used for carrying out confusion on the analog radio frequency circuit netlist as the input of a confusion program to respectively obtain confusion circuit data and a confusion de-file; the process of obfuscating the analog radio frequency circuit netlist includes the following: reading and analyzing the simulation radio frequency circuit netlist and constructing a corresponding first-level bipartite graph model and a corresponding second-level graph model; calculating the weight of each wire net based on the first-level bipartite graph model for topology confusion; calculating the weight of each component for component parameter confusion based on the secondary graph model; storing the original information of the confused device into a confused file in KV format; firstly encrypting the confusion-removed file through a public key built in a confusion program, and then carrying out secondary encryption through an IP user public key;
the asymmetric encryption module is used for carrying out asymmetric encryption on the confusion-removed file through an IP party public key so that only an IP party appointed by a sharing party can decrypt the confusion-removed file by using a private key of the IP party appointed by the sharing party to obtain an original confusion-removed file;
The system comprises an confusion removing module, a confusion removing module and a public key, wherein the confusion removing module is used for enabling an IP user to receive confusion circuit data shared by a sharing party and an asymmetrically encrypted confusion removing file, obtaining an original confusion removing file by using a private key, importing the confusion circuit data into EDA software, performing subsequent design and then outputting a secondary design with a confusion sub-circuit; taking the secondary design with the confusion sub-circuit and the original confusion file as the input of a confusion program to obtain the original circuit file;
and the simulation module is used for inputting the original circuit file into EDA software for design to obtain a real simulation result.
11. A computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements the method of confusing and recovering a simulated radio frequency circuit netlist according to any of claims 1 to 9.
12. An electronic terminal, comprising: a processor and a memory;
the memory is used for storing a computer program;
the processor is configured to execute the computer program stored in the memory, so that the terminal performs the method for confusing and recovering the simulated radio frequency circuit netlist as claimed in any one of claims 1 to 9.
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