CN117153911A

CN117153911A - Solar cell and photovoltaic module

Info

Publication number: CN117153911A
Application number: CN202311405011.3A
Authority: CN
Inventors: 刘照轩; 张博; 金井升; 张彼克; 徐梦微; 郭子齐; 秦佳妮
Original assignee: Jinko Solar Haining Co Ltd
Current assignee: Jinko Solar Haining Co Ltd
Priority date: 2023-10-26
Filing date: 2023-10-26
Publication date: 2023-12-01

Abstract

The application provides a solar cell and a photovoltaic module, wherein the solar cell comprises a semiconductor substrate, and the semiconductor substrate comprises a first surface and a second surface which are oppositely arranged; a texture structure on the second surface of the semiconductor substrate, wherein the texture structure is provided with a first area corresponding to the metalized area, a second area corresponding to the non-metalized area and a third area positioned between the first area and the second area, the first area is internally provided with a plurality of first sub-textures, the second area is internally provided with a plurality of second sub-textures, the third area is internally provided with a plurality of third sub-textures, the size of the first sub-textures is smaller than that of the third sub-textures, and the size of the third sub-textures is smaller than that of the second sub-textures; a first passivation layer on the first surface of the semiconductor substrate; and the second passivation layer is positioned on the second surface of the semiconductor substrate. According to the application, the texture structure with gradually changed size is formed on the second surface of the battery, so that the conversion efficiency of the battery can be improved.

Description

Solar cell and photovoltaic module

Technical Field

The application relates to the technical field of photovoltaic production, in particular to a solar cell and a photovoltaic module.

Background

In the preparation process of the solar cell, the semiconductor substrate is generally required to be subjected to treatment processes such as cleaning, texturing, diffusion, polishing and etching, a textured structure is formed on the semiconductor substrate through texturing, and the reflectivity of a cell piece is reduced, however, the existing textured structure has uniform size and morphology, so that the cell can not meet the requirement of improving the current collection efficiency, and meanwhile, has a good passivation effect, and the conversion efficiency of the cell is limited.

Therefore, how to reduce the light reflectivity of the solar cell and improve the passivation effect of the cell by texturing is also an urgent problem to be solved by the photovoltaic industry.

Disclosure of Invention

The application provides a solar cell and a photovoltaic module, which can improve the light absorption of back sunlight, simultaneously ensure that the cell has good passivation effect and improve the conversion efficiency of the cell.

In a first aspect, an embodiment of the present application provides a solar cell, including:

a semiconductor substrate including a first surface and a second surface disposed opposite to each other;

a texture structure on the second surface of the semiconductor substrate, the texture structure having a first region corresponding to a metalized region, a second region corresponding to a non-metalized region, and a third region between the first region and the second region, the first region having a plurality of first sub-textures therein, the second region having a plurality of second sub-textures therein, the third region having a plurality of third sub-textures therein, the first sub-textures having a size smaller than the size of the third sub-textures, the third sub-textures having a size smaller than the size of the second sub-textures;

A first passivation layer located on the first surface of the semiconductor substrate;

and the second passivation layer is positioned on the second surface of the semiconductor substrate.

In a second aspect, an embodiment of the present application provides a photovoltaic module, including:

a battery string formed by connecting a plurality of solar cells according to the first aspect;

the packaging adhesive film is used for covering the surface of the battery string;

and the cover plate is used for covering the surface of the packaging adhesive film, which is away from the battery strings.

The technical scheme provided by the application can achieve the following beneficial effects:

according to the texture structure, the sizes of the texture structures are sequentially increased along the directions of the first area, the third area and the second area, wherein the first area corresponds to the metalized area, the size of the first sub-texture structure in the first area is minimum, the contact resistance can be reduced, the current collection efficiency of the battery is improved, and the filling factor is improved, so that the conversion efficiency of the battery is improved, the second area corresponds to the non-metalized area, the size of the second sub-texture structure in the second area is maximum, more sunlight can be reflected when sunlight on the back is reflected to the second sub-texture structure, the reflectivity of the light is increased, the absorption of the battery to the sunlight is improved, and the passivation effect of the battery is improved. Compared with the first sub-texture structure and the second sub-texture structure, the third sub-texture structure in the third area is moderate in size, size gradient can be formed between the first sub-texture structure and the second sub-texture structure, the problem that the battery passivation effect is poor due to direct contact of the first sub-texture structure and the second sub-texture structure with larger size difference is avoided, and meanwhile deposition and uniformity of a battery back surface film layer are facilitated. According to the solar cell, the texture structure with gradually changed size is formed on the second surface of the cell, so that the solar cell has a good passivation effect while light absorption of back sunlight is improved, and the conversion efficiency of the cell is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.

Drawings

Fig. 1 is a schematic structural diagram of a solar cell according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a texture structure according to an embodiment of the present application;

FIG. 3 is an SEM image of a texture structure provided by an embodiment of the present application;

fig. 4 is a schematic structural diagram of a TOPcon battery according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of an IBC battery according to an embodiment of the present application;

fig. 6 is a flowchart of a preparation of a solar cell according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a first process for preparing a texture feature according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a second process for preparing a texture feature according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a third process for preparing a texture feature according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of a photovoltaic module according to an embodiment of the present application.

Reference numerals:

1-a semiconductor substrate;

2-texture;

21-a first region;

22-a second region;

23-a third region;

24-a first sub-texture;

25-a second sub-texture;

26-a third sub-texture;

3-a first passivation layer;

4-a second passivation layer;

a 5-tunneling oxide layer;

6-doping the conductive layer;

7-a first electrode;

8-a second electrode;

9-a third electrode;

10-pre-texturing;

101-a first pre-texture;

102-a second pre-texture;

103-a third pre-texture;

11-a mask layer;

111-a first mask layer;

112-a second mask layer;

113-a third mask layer;

114-a first mask region;

115-a second mask region;

116-a third mask region;

1000-photovoltaic module;

100-solar cell;

200-a first cover plate;

300-a first packaging adhesive layer;

400-a second packaging adhesive layer;

500-second cover plate.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

In the description of the present application, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance unless explicitly specified or limited otherwise; the term "plurality" means two or more, unless specified or indicated otherwise; the terms "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, integrally connected, or electrically connected; can be directly connected or indirectly connected through an intermediate medium. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.

In the description of the present specification, it should be understood that the terms "upper", "lower", and the like used in the embodiments of the present application are described in terms of the angles shown in the drawings, and should not be construed as limiting the embodiments of the present application. In the context of this document, it will also be understood that when an element is referred to as being "on" or "under" another element, it can be directly on the other element or be indirectly on the other element through intervening elements.

In the prior art, texturing and polishing treatment are generally required to be carried out on the back surface of the battery so as to increase the light reflectivity of the back surface of the battery and reduce the recombination rate of the carrier surface, thereby improving the conversion efficiency of the battery.

In view of this, an embodiment of the present application provides a solar cell 100, fig. 1 is a schematic structural diagram of the solar cell 100 of the present application, fig. 2 is a schematic structural diagram of a portion of a texture structure of the present application, and as shown in fig. 1 and 2, the solar cell 100 includes:

a semiconductor substrate 1, the semiconductor substrate 1 including a first surface and a second surface disposed opposite to each other;

a texture structure 2 located on the second surface of the semiconductor substrate 1, the texture structure 2 having a first region 21 corresponding to the metallized region, a second region 22 corresponding to the non-metallized region, and a third region 23 located between the first region 21 and the second region 22, the first region 21 having a plurality of first sub-textures 24 therein, the second region 22 having a plurality of second sub-textures 25 therein, the third region 23 having a plurality of third sub-textures 26 therein, the first sub-textures 24 having a size smaller than the size of the third sub-textures 26, the third sub-textures 26 having a size smaller than the size of the second sub-textures 25;

a first passivation layer 3 located on the first surface of the semiconductor substrate 1;

a second passivation layer 4 on the second surface of the semiconductor substrate 1.

In the above scheme, in the texture structure 2 of the present application, the dimensions of the texture structure 2 are sequentially increased along the directions of the first region 21, the third region 23 and the second region 22, where the first region 21 corresponds to a metallized region, the dimension of the first sub-texture structure 24 in the first region 21 is minimum, the total area of the top surface of the first sub-texture structure 24, and the region corresponding to the back electrode is the first region, which is favorable for reducing the contact resistance, improving the current collection efficiency of the battery, and improving the filling factor, thereby improving the conversion efficiency of the battery, and the second region 22 corresponds to a non-metallized region, and the dimension of the second sub-texture structure 25 of the second region 22 is maximum, so that more sunlight can be reflected when the sunlight on the back surface is reflected to the second sub-texture structure 25, the reflectivity of the light is increased, the absorption of the battery to the sunlight is improved, and the passivation effect of the battery is improved. The third sub-texture 26 in the third region 23 has a moderate size compared to the first sub-texture 24 and the second sub-texture 25, and is capable of forming a size gradient between the first sub-texture 24 and the second sub-texture 25, so that the problem that the battery passivation effect is poor due to direct contact between the first sub-texture 24 and the second sub-texture 25 with larger size difference is avoided, and the deposition and uniformity of the battery backside film layer are facilitated. According to the solar cell 100, the texture structure 2 with gradually changed size is formed on the second surface of the cell, so that the solar cell has a good passivation effect while light absorption of back sunlight is improved, and the conversion efficiency of the cell is improved.

In the present application, a "texture" refers to a micro-nano-sized structure that can scatter or reflect light to enhance light absorption.

It will be understood that, as shown in fig. 2, the first region 21 corresponds to a metalized region, the second region 22 corresponds to a non-metalized region, and in the process of manufacturing the solar cell 100, a region contacting with an electrode is usually required to be preset on the semiconductor substrate 1, in order to ensure that the electrode paste can be fully contacted with the semiconductor substrate 1 to form a connection, the width of the preset region is usually greater than the width of the electrode, and the width of the preset region is about twice as wide as the width of the electrode, in the preset region, a part of the region, which is not contacted with the electrode, of the semiconductor substrate 1 will exist, is defined as a third region 23, that is, the preset region includes the first region 21 and the third region 23 of the present application, and in this way, by setting a third sub-texture 26 with a size between the first sub-texture 24 and the second sub-texture 25 in the third region 23, the present application can utilize a third sub-texture 26 with a moderate size in the region not contacted with the electrode to form a size gradient texture structure, and can promote the reflectivity of the back surface 21 and the subsequent solar cell can be promoted, and the solar cell can further promote the uniformity of solar cell film deposition effect. If the third sub-texture 26 is not provided, the first sub-texture 24 with a smaller size is provided in the preset area, and the second sub-texture 25 with a larger size is provided in the area other than the preset area on the surface of the semiconductor substrate 1, since the electrode is only in contact with the semiconductor substrate 1 in a partial area in the preset area, the texture 2 in the area not in contact with the electrode is smaller in size in the preset area, the absorption efficiency of the back sunlight is poor, and the matching problem of the subsequent film layer is also affected.

It can be understood that the number of the first region 21, the second region 22 and the third region 23 in the present application is plural, and the plural first region 21, second region 22 and third region 23 together form a complete region where the texture structure 2 is located, and no substantial distinguishing interface exists between the first region 21, the second region 22 and the third region 23, which is merely a region defined by a human division manner at different positions on the second surface of the semiconductor substrate 1.

In some embodiments, the first surface of the semiconductor substrate 1 may be the front surface of the solar cell 100 or may be the back surface of the solar cell 100, and when the first surface of the semiconductor substrate 1 is the front surface of the solar cell 100, the second surface of the semiconductor substrate 1 is the back surface of the solar cell 100; accordingly, when the first surface of the semiconductor substrate 1 is the back surface of the solar cell 100, the second surface of the semiconductor substrate 1 is the front surface of the solar cell 100, and it is understood that the front surface of the solar cell 100 is the surface facing the sun (i.e., the light receiving surface), and the back surface of the solar cell 100 is the surface facing away from the sun (i.e., the back surface). Hereinafter, the first surface of the semiconductor substrate 1 is referred to as the front surface of the solar cell 100, and the second surface of the semiconductor substrate 1 is referred to as the back surface of the solar cell 100.

In some embodiments, the semiconductor substrate 1 is an N-type crystalline silicon substrate (or silicon wafer), and may also be a P-type crystalline silicon substrate (silicon wafer). The crystalline silicon substrate (silicon substrate) is, for example, one of a polycrystalline silicon substrate, a single crystal silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate, and the specific type of the semiconductor substrate 1 is not limited in the embodiment of the present application. When the semiconductor substrate 1 is an N-type base, the doping element may be a V-group element such As phosphorus (P), arsenic (As), tellurium (Te), or the like; when the semiconductor substrate 1 is a P-type base, the doping element may be a group iii element such as boron (B) element, aluminum (Al) element, gallium (Ga), or the like.

In some embodiments, the thickness of the semiconductor substrate 1 is 60 μm to 240 μm, specifically 60 μm, 80 μm, 90 μm, 100 μm, 120 μm, 150 μm, 200 μm, 240 μm, or the like, and is not limited herein.

In some embodiments, fig. 3 is an SEM image of a partial region of the texture feature 2 of the present application, as can be seen in fig. 3: the first sub-texture 24 in the first region 21 has a smaller size than the third sub-texture 26 in the third region 23, and the third sub-texture 26 in the third region 23 has a smaller size than the second sub-texture 25 in the second region 22. The "size" may refer to length, width, height, projected area and volume, etc. The first sub-texture 24, the second sub-texture 25, and the third sub-texture 26 may be implemented by at least one of the above-described length, width, height, projected area, and volume, and will be described below by taking the length, width, height, and projected area as examples.

In some embodiments, the ratio of the area of the second surface of the semiconductor substrate 1 to the projected area of the third region 23 on the semiconductor substrate 1 is 1: (0.01-0.1), specifically may be 1:0.01, 1:0.03, 1:0.05, 1:0.08 or 1:0.1, etc., within the above-described limit, it is possible to ensure that a certain number of third sub-textures 26 can be provided, thereby forming a texture 2 in which the size gradient is set, and it is possible to enhance the absorption of back side sunlight without affecting the contact between the electrode and the semiconductor substrate 1.

In some embodiments, the ratio of the area of the second surface of the semiconductor substrate 1 to the projected area of the first region 21 on the semiconductor substrate 1 is 1: (0.01-0.1), specifically may be 1:0.01, 1:0.03, 1:0.05, 1:0.08 or 1:0.01, etc., and within the above-described limit, it is possible to ensure that an appropriate amount of electrodes are provided, which are brought into contact with the semiconductor substrate 1, thereby improving the current collection efficiency of the battery.

In some embodiments, the ratio of the area of the second surface of the semiconductor substrate 1 to the projected area of the second region 22 on the semiconductor substrate 1 is 1: (0.8-0.99), specifically may be 1:0.8, 1:0.85:1:0.9, 1:0.93, 1:0.95 or 1:0.99, etc., in the above-described limit, a large number of large-sized second sub-textures 25 can be provided, the back reflectivity of the battery can be increased, and the passivation effect of the battery can be improved.

In some embodiments, the first sub-texture 24 has a length of 2 μm to 15 μm, which may be specifically 2 μm, 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, or the like.

In some embodiments, the width of the first sub-texture 24 is 2 μm to 15 μm, which may be 2 μm, 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, or the like.

Within the above-defined range, the first sub-texture 24 has a suitable length and width, which is advantageous for reducing the contact resistance, and it is understood that the length and width of the first sub-texture 24 should not be too large, which may affect the integrity and uniformity of the films on the surfaces of the third region 23 and the second region 22, and reduce the internal reflection of light, thereby being disadvantageous for improving the carrier surface recombination rate and the photoelectric conversion efficiency of the solar cell 100.

In some embodiments, the height of the first sub-texture 24 is 50nm to 1000nm, which may be 50nm, 100 nm, 300 nm, 500 nm, 800 nm or 1000 nm.

In some embodiments, the third sub-texture 26 has a length of 6 μm to 18 μm, which may be 6 μm, 8 μm, 10 μm, 12 μm, 15 μm, 18 μm, or the like.

In some embodiments, the width of the third sub-texture 26 is 6 μm to 18 μm, which may be 6 μm, 8 μm, 10 μm, 12 μm, 15 μm, 18 μm, or the like.

Within the above-described limitations, the third sub-texture 26 has a suitable length and width, which can coordinate the light reflectivity and current collection efficiency of the back surface of the cell, and is beneficial to improving the overall performance of the cell, and it is understood that the length and width of the third sub-texture 26 should not be too large, which may affect the integrity and uniformity of the film on the surface of the second region 22, and reduce the internal reflection of light, thereby adversely improving the recombination rate of the carrier surface and the photoelectric conversion efficiency of the solar cell 100.

In some embodiments, the height of the third sub-texture 26 is 50nm to 1000nm, which may be 50nm, 100 nm, 300 nm, 500 nm, 800 nm or 1000 nm.

In some embodiments, the length of the second sub-texture 25 is 13 μm to 20 μm, which may be 13 μm, 15 μm, 17 μm, 19 μm, 20 μm, or the like.

In some embodiments, the width of the second sub-texture 25 is 13 μm to 20 μm, which may be 13 μm, 15 μm, 17 μm, 19 μm, 20 μm, or the like.

In some embodiments, the height of the second sub-texture structure 25 is 50nm to 1000nm, which may be 50nm, 100 nm, 300 nm, 500 nm, 800 nm or 1000 nm.

Within the above-mentioned limit, the second sub-textures 25 have suitable length, height and width, and the number of the second sub-textures 25 occupies a relatively large amount of the total number of the textures 2, which is beneficial to improving the internal reflection of the backlight and improving the light utilization rate of the battery.

In some embodiments, the size of the third sub-texture 26 of the texture structure 2 near the first region 21 is smaller than the size of the third sub-texture 26 near the second region 22, so that in the third region 23, the size of the third sub-texture 26 gradually increases along the direction of the first region 21 toward the second region 22, and in the region near the first sub-texture 24, the size is smaller, which is beneficial for improving the contact of the electrode paste with the semiconductor substrate 1, the filling factor is improved, and in the region near the second sub-texture 25, the size is larger, and the reflectivity of the third sub-texture 26 is higher, which is beneficial for passivation effect of the battery.

In some embodiments, the topography of at least one of the first sub-texture 24, the second sub-texture 25, and the third sub-texture 26 comprises at least one of pyramid, prism, sphere, and pen. It will be appreciated that the topography of the first sub-texture 24, the second sub-texture 25 and the third sub-texture 26 may be the same or may be different. In the prior art, the pyramid structure is usually formed by texturing, the pyramid structure has a single appearance and a larger bottom area, the top is a pointed structure, the pyramid structure is arranged on the surface of the semiconductor substrate 1, the reflection effect on backlight is general, and the subsequent film deposition is unfavorable, the first sub-texture structure 24 can be arranged into pyramid-shaped, prism-shaped and other appearances with larger surface area according to the requirement, the third sub-texture structure 26 can be arranged into pyramid-shaped, sphere-shaped, pen-shaped and other appearances with higher reflectivity, and the specific appearances of the first sub-texture structure 24, the second sub-texture structure 25 and the third sub-texture structure 26 can be designed through a localized process by a laser method or a mask method.

In some embodiments, the roughness of the first sub-texture 24 is less than the roughness of the third sub-texture 26, and the roughness of the third sub-texture 26 is less than the roughness of the second sub-texture 25. The number of the first sub-textures 24 with smaller roughness in the first area is larger, so that the total area of the top surface of the formed first sub-textures 24 is larger, and the corresponding areas of the back electrodes are all the first areas, thereby being beneficial to reducing the contact resistance and improving the current collection efficiency. The second sub-texture 25 with larger roughness has larger light reflectivity, can improve light absorption efficiency of the back of the battery, and the third sub-texture 26 with moderate roughness can prevent the problem of poor passivation effect caused by direct contact between the first sub-texture 24 and the second sub-texture 25, and does not cause larger loss of reflectivity of the battery.

In some embodiments, since the size of the first sub-texture 24 is smaller than the size of the third sub-texture 26, the size of the third sub-texture 26 is smaller than the size of the second sub-texture 25, the larger the size of the texture, the higher the light reflectivity, such that the reflectivity of solar light on the back of the cell is less on the first sub-texture 24 than on the third sub-texture 26, and the reflectivity of solar light on the third sub-texture 26 is less than on the second sub-texture 25.

In some embodiments, the reflectivity of the sunlight on the first sub-texture 24 is 20% -35%, specifically may be 20%, 25%, 28%, 30%, 32% or 35%, which is beneficial to reducing the contact resistance and improving the current collection efficiency. It will be appreciated that during use of the cell, the first sub-texture 24 is obscured by the electrode and is not effective in using back side sunlight.

In some embodiments, the reflectivity of sunlight on the third sub-texture 26 is 25% -40%, and may specifically be 25%, 28%, 32%, 35%, 38%, 40%, or the like. In the above-mentioned limited range, the contact resistance can be reduced while the light reflectivity of the battery is improved, so that the passivation effect and the current collection efficiency of the battery are in a relatively balanced state.

In some embodiments, the reflectivity of the sunlight on the second sub-texture structure 25 is 35% -45%, and may specifically be 35%, 38%, 40%, 42% or 45%, etc. In the above-mentioned limited range, since the second sub-texture structure 25 occupies a relatively large amount on the battery, the light reflectivity of the battery can be effectively improved, and the passivation effect of the battery can be improved.

In some embodiments, in the texture structure 2 of the present application, the light utilization of the back sunlight, the contact with the electrode and the arrangement of the subsequent film layer mainly affect the performance of the battery, and in the texture structure 2, the ratio of the total surface area of the side surface of the texture structure 2 facing away from the semiconductor substrate 1 to the orthographic projection area of the first area 21 on the semiconductor substrate 1 is greater than the ratio of the total surface area of the side surface of the third sub-texture structure 26 facing away from the semiconductor substrate 1 to the orthographic projection area of the third area 23 on the semiconductor substrate 1, the ratio of the total surface area of the side surface of the third sub-texture structure 26 facing away from the semiconductor substrate 1 to the orthographic projection area of the third area 23 on the semiconductor substrate 1 is greater than the ratio of the total surface area of the side surface of the second sub-texture structure 25 facing away from the semiconductor substrate 1 to the orthographic projection area of the second area 22 on the semiconductor substrate 1, so that the number of the first sub-texture structures 24 is greater, the size is smaller, the number of the third sub-texture structures 26 is smaller, and the size is larger than the second sub-size is larger.

In some embodiments, the ratio of the total surface area of the side surface of the plurality of first sub-textures 24 facing away from the semiconductor substrate 1 to the orthographic projection area of the first region 21 on the semiconductor substrate 1 is (1.5 to 3.0): 1, which may be specifically 1.5: 1. 1.7: 1. 2.0: 1. 2.5:1 and 3.0:1, etc., if the ratio of the total surface area of the side surface of the plurality of first sub-textures 24 facing away from the semiconductor substrate 1 to the orthographic projection area of the first region 21 on the semiconductor substrate 1 is too large, the surface area of the semiconductor substrate 1 is excessively large, the surface defect sites of the semiconductor substrate 1 are increased, and the passivation effect of the battery is reduced; if the ratio of the total surface area of the side surface of the plurality of first sub-textures 24 facing away from the semiconductor substrate 1 to the orthographic projection area of the first region 21 on the semiconductor substrate 1 is too small, this results in a too small surface area of the semiconductor substrate 1 and in a larger contact resistance of the cell.

In some embodiments, the ratio of the total surface area of the side surface of the plurality of third sub-textures 26 facing away from the semiconductor substrate 1 to the orthographic projection area of the third region 23 on the semiconductor substrate 1 is (1.2 to 2.5): 1, which may be specifically 1.2: 1. 1.5: 1. 1.8: 1. 2.0: 1. 2.3:1 or 2.5:1, and so on, if the ratio of the total surface area of the side surface of the third sub-textures 26 facing away from the semiconductor substrate 1 to the orthographic projection area of the third region 23 on the semiconductor substrate 1 is too large or too small, the textures 2 cannot form a natural transition surface, which affects the deposition of a subsequent film layer and reduces the performance of the battery.

In some embodiments, the ratio of the total surface area of the side surface of the plurality of second sub-textures 25 facing away from the semiconductor substrate 1 to the orthographic projection area of the second region 22 on the semiconductor substrate 1 is (1.0 to 1.8): 1, which may be specifically 1.0: 1. 1.2: 1. 1.5:1, 1.7:1, or 1.8:1, if the ratio of the total surface area of the plurality of second sub-textures 25 facing away from the side surface of the semiconductor substrate 1 to the orthographic projection area of the second region 22 on the semiconductor substrate 1 is too small, a textured structure cannot be formed, and if the ratio of the total surface area of the plurality of second sub-textures 25 facing away from the side surface of the semiconductor substrate 1 to the orthographic projection area of the second region 22 on the semiconductor substrate 1 is too large, the light utilization rate of the back surface of the battery is reduced, and the passivation effect of the battery is reduced.

In some embodiments, the solar cell 100 of the present application may be a TOPcon cell (Tunnel Oxide Passivated Contact solar cell, TOPcon), and a schematic structural diagram of the TOPcon cell is shown in fig. 4, that is, the cell structure further includes: a first electrode 7 on the surface of the first passivation layer 3 and a second electrode 8 on the surface of the second passivation layer 4. The TOPCon battery can form a passivation contact structure on the back of the battery, provide good interface passivation on the back of the battery, and improve the photoelectric conversion efficiency of the battery.

In some embodiments, when the solar cell 100 of the present application is a TOPcon cell, an emitter (the emitter is not shown in fig. 1) is further provided on the first surface of the semiconductor substrate 1, and the emitter may be an emitter structure having a uniform doping depth, or may be a selective emitter structure having different doping concentrations and doping depths, specifically, the selective emitter is a heavily doped emitter region corresponding to a metal electrode, and the other regions are lightly doped emitter regions. The emitter region may be located in the surface of the semiconductor substrate 1, or may be located outside the surface of the semiconductor substrate 1 to form a separate emitter structure. When the semiconductor substrate 1 is of an N type, the emitter is of a P type, and the semiconductor substrate 1 and the emitter form a PN junction.

In some embodiments, when the solar cell 100 of the present application is a TOPcon cell, as shown in fig. 4, a tunneling oxide layer 5 and a doped conductive layer 6 are further disposed between the second surface of the semiconductor substrate 1 and the second passivation layer 4, where the tunneling oxide layer 5 and the doped conductive layer are distributed on the surfaces of the first region 21, the second region 22 and the third region 23, and the second electrode 8 is in direct contact with the doped conductive layer 6, so that the passivation effect is good, and meanwhile, the carrier recombination on the back surface can be reduced, and the utilization rate of the sunlight on the back surface can be improved. The tunneling oxide layer 5 is made of dielectric materials with tunneling effect, such as silicon oxide, silicon nitride, silicon oxynitride, intrinsic amorphous silicon, and intrinsic polysilicon, and any one of ozone oxidation, high temperature thermal oxidation, and nitric acid oxidation may be used to oxidize the second surface of the semiconductor substrate 1 to obtain the tunneling oxide layer 5. The material of the doped conductive layer 6 includes, but is not limited to, at least one of polysilicon, amorphous silicon and silicon carbide, and the doping element in the doped conductive layer 6 includes at least one of boron, gallium, phosphorus and arsenic. The doped conductive layer 6 may be formed using one or more of low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) or plasma enhanced chemical vapor deposition.

In some embodiments, the solar cell 100 of the present application may be a back contact cell (Interdigitated Back Contact, IBC cell), the structure of which is shown in fig. 5, the cell structure further comprising: and a third electrode 9 positioned on the surface of the second passivation layer 4. The IBC battery is characterized in that positive and negative electrodes of the battery are prepared on the back of the battery, so that a photovoltaic module with high efficiency, high reliability, low cost, more attractive appearance and environmental protection is obtained, shielding of the front electrode of the battery can be eliminated, incident light is utilized to the maximum extent, optical loss is reduced, and photoelectric conversion efficiency of the battery is effectively improved.

In some embodiments, when the solar cell 100 of the present application is an IBC cell, two different doped regions are further provided on the second surface of the semiconductor substrate 1: an emitter and a back field region (the emitter and the back field region are not shown in fig. 1), and by way of example, when the substrate adopts an N-type semiconductor substrate, the emitter is a p+ emitter, the back field region is an n+ back surface field, two adjacent p+ emitters and n+ back surface fields are arranged at intervals, the p+ emitters and the n+ back surface fields are arranged in an interdigital manner on a second surface of the N-type semiconductor substrate, and the p+ emitters can form a P-N junction with the N-type semiconductor substrate, so that carriers can be effectively split; the N+ back surface field can form a high-low junction with the N-type semiconductor substrate, and the separation capability of carriers is enhanced. Wherein, a third electrode 9 is disposed corresponding to the p+ emitter and the n+ back surface field (the third electrode 9 is in an interdigital structure), the region is defined as a first region, a spacing region between two adjacent p+ emitters and the n+ back surface field is defined as a second region, the third region is a region between the first region and the second region, and the third region is a region which is not contacted with the third electrode in a preset region of the third electrode.

The emitter region may be located in the surface of the semiconductor substrate 1, or may be located outside the surface of the semiconductor substrate 1 to form a separate emitter structure.

Hereinafter, a method of manufacturing the solar cell 100 according to the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application, and the described embodiments are only some embodiments of the present application, not all embodiments.

Fig. 6 is a flowchart of a preparation process of a solar cell 100 according to an embodiment of the present application, and as shown in fig. 6, the solar cell 100 includes the following steps:

step 100, providing a semiconductor substrate 1, wherein the semiconductor substrate 1 comprises a first surface and a second surface which are oppositely arranged.

In some embodiments, the first surface of the semiconductor substrate 1 corresponds to the front surface of the cell, which is the surface facing the sun (i.e. the light-receiving surface), and the second surface of the semiconductor substrate 1 corresponds to the back surface of the cell, which is the surface facing away from the sun (i.e. the back surface).

In some embodiments, the semiconductor substrate 1 is a silicon substrate, which may be a polycrystalline silicon substrate, a monocrystalline silicon substrate, or a monocrystalline-like silicon substrate.

In some embodiments, the semiconductor substrate 1 may be an N-type substrate, and the solar cell 100 prepared therefrom is a TOPcon cell or an IBC cell.

Step S200, forming a texture structure 2 on the second surface of the semiconductor substrate 1, where the texture structure 2 has a first region 21 corresponding to the metallized region, a second region 22 corresponding to the non-metallized region, and a third region 23 located between the first region 21 and the second region 22, the first region 21 has a plurality of first sub-textures 24 therein, the second region 22 has a plurality of second sub-textures 25 therein, the third region 23 has a plurality of third sub-textures 26 therein, the size of the first sub-textures 24 is smaller than the size of the third sub-textures 26, and the size of the third sub-textures 26 is smaller than the size of the second sub-textures 25.

Specifically, the texture structure prepared by the method comprises the following three methods, wherein the sizes of the texture structures sequentially increase from the first area 21 to the second area 22:

firstly, preparing a pre-textured structure 10 with uniform size and shape through texturing, then carrying out laser processing on the pre-textured structure 10, and obtaining a texture structure 2 through controlling parameters of laser processing of different areas of the pre-textured structure 10, wherein a schematic diagram of the conversion structure of the pre-textured structure 10 to the texture structure 2 is shown in fig. 7.

In step S201, the semiconductor substrate 1 is subjected to a texturing process to form a pre-textured structure 10, and the obtained structure is shown in fig. 7 (a), where the pre-textured structure 10 includes a first pre-textured structure 101 corresponding to the first area 21, a second pre-textured structure 102 corresponding to the second area 22, and a third pre-textured structure 103 corresponding to the third area, where the structures of the first pre-textured structure 101, the second pre-textured structure 102, and the third pre-textured structure 103 are the same, i.e., the pre-textured structure 10 has a uniform size and morphology.

Step S202, performing a first laser processing on the first pre-texture structure 101, performing a second laser processing on the second pre-texture structure 102, and performing a third laser processing on the third pre-texture structure 103, so that the first pre-texture structure 101 is converted into a first sub-texture structure 24, the second pre-texture structure 102 is converted into a second sub-texture structure 25, and the third pre-texture structure 103 is converted into a third sub-texture structure 26, resulting in a texture structure 2, as shown in fig. 7 (b), the texture structure 2 includes the first sub-texture structure 24, the second sub-texture structure 25, and the third sub-texture structure 26, and the first sub-texture structure 24, the second sub-texture structure 25, and the third sub-texture structure 26 are located at different positions on the texture structure 2.

In some embodiments, the laser wavelengths of the first, second, and third laser treatments are different, in particular, the first laser treatment wavelength is greater than the third laser treatment wavelength, and the third laser treatment wavelength is greater than the second laser treatment wavelength.

In some embodiments, the first laser treatment, the second laser treatment, and the third laser treatment are different in time, and in particular, the first laser treatment is longer than the third laser treatment, and the third laser treatment is longer than the second laser treatment.

In some embodiments, the energy of the first laser treatment, the second laser treatment, and the third laser treatment are different, and in particular, the energy of the first laser treatment is greater than the energy of the third laser treatment for a time period that is greater than the energy of the second laser treatment.

The first pre-texture 101 is converted to a first sub-texture 24, the second pre-texture 102 is converted to a second sub-texture 25, and the third pre-texture 103 is converted to a third sub-texture 26 by adjusting at least one of the energy, time, and wavelength of the first, second, and third laser treatments, the first sub-texture 24 being smaller in size than the third sub-texture 26, and the third sub-texture 26 being smaller in size than the second sub-texture 25.

Secondly, preparing a pre-textured structure 10 with uniform size and shape through texturing, preparing a mask layer on the surface of the pre-textured structure 10, wherein the thicknesses of the mask layer in different areas are different, and finally polishing to obtain the texture structure 2, wherein the schematic diagram of the conversion structure from the pre-textured structure 10 to the texture structure 2 is shown in fig. 8.

In step S201, a pre-textured structure 10 is formed by performing a texturing process on the semiconductor substrate 1, and the pre-textured structure 10 has a uniform size and morphology as shown in fig. 8 (a).

Step S202, forming a first mask layer 111 by pre-setting the first region 21, the second region 22 and the third region 23 of the texture structure 2, coating the pre-texture structure 10 corresponding to the first region 21 with a first mask material, coating the pre-texture structure 10 corresponding to the second region 22 with a second mask material to form a second mask layer 112, and coating the pre-texture structure 10 corresponding to the third region 23 with a third mask material to form a third mask layer 113, wherein the thickness of the first mask layer 111 is greater than the thickness of the third mask layer 113, and the thickness of the third mask layer 113 is greater than the thickness of the second mask layer 112, and the resulting structure is shown in (b) of fig. 8.

In some embodiments, at least one of the first mask material, the second mask material, and the third mask material comprises at least one of sodium silicate, a water-soluble resin, and an amino acid based compound. The first mask material, the second mask material, and the third mask material may be the same material or different materials may be selected. In some embodiments, the first mask material, the second mask material, and the third mask material are dissolved in an organic solvent to form a paste, and the paste is coated on the semiconductor substrate 1 to form a mask layer.

In step S203, the mask layer is polished, and since the etching rate of the region with the thicker mask layer is slow and the etching rate of the region with the thinner mask layer is fast, the unified polishing is performed on the mask layer with uneven thickness distribution, so that the first mask layer 111 and the pre-texture 10 located in the first region are converted into the first sub-texture 24, the third mask layer 113 and the pre-texture 10 located in the third region are converted into the third sub-texture 26, and the second mask layer 112 and the pre-texture 10 located in the second region are converted into the second sub-texture 25, and the resulting structure is shown in (c) of fig. 8.

In some embodiments, in this step, the process parameters of the polishing process for the first, second, and third mask layers 111, 112, and 113 at different positions in the mask layers are the same.

And thirdly, preparing a pre-textured structure 10 with uniform size and shape through texturing, preparing a mask layer on the surface of the pre-textured structure 10, wherein the thicknesses of the mask layer in different areas are the same, and finally polishing to obtain the texture structure 2 by controlling the parameters of polishing in different areas, wherein the schematic diagram of the conversion structure from the pre-textured structure 10 to the texture structure 2 is shown in fig. 9.

In step S201, a pre-textured structure 10 is formed by performing a texturing process on the semiconductor substrate 1, and the pre-textured structure 10 has a uniform size and morphology as shown in fig. 9 (a).

In step S202, a mask material is coated on the surface of the pre-textured structure 10 to form a mask layer 11, where the mask layer 11 has a first mask region 114 corresponding to a metallized region, a second mask region 115 corresponding to a non-metallized region, and a third mask region 116 located between the first mask region 114 and the second mask region 115, and the resulting structure is shown in fig. 9 (b), where the mask layer 11 is a flat layer, that is, the mask layer 11 is parallel to a horizontal plane in a plane away from the semiconductor substrate 1.

In some embodiments, the masking material comprises at least one of sodium silicate, a water soluble resin, an amino acid based compound. In some embodiments, the mask material is dissolved in an organic solvent to form a slurry, and the slurry is coated on the semiconductor substrate 1 to form a mask layer.

Step S203, performing a first polishing process on the mask layer 11 located in the first mask region 114 and the pre-texture structure 10 located in the first region, so that the mask layer 11 located in the first mask region 114 and the pre-texture structure 10 located in the first region are converted into the first sub-texture structure 24, performing a third polishing process on the mask layer 11 located in the third mask region 116 and the pre-texture structure 10 located in the third region, so that the mask layer located in the third mask region 116 and the pre-texture structure 10 located in the third region are converted into the third sub-texture structure 26, and performing a second polishing process on the mask layer 11 located in the second mask region 115 and the pre-texture structure 10 located in the second region, so that the mask layer 11 located in the second mask region 115 and the pre-texture structure 10 located in the second region are converted into the second sub-texture structure 25, and the resulting structure is as shown in (c) of fig. 9.

In some embodiments, the time of the first polishing process is less than the time of the third polishing process, which is less than the time of the second polishing process.

In some embodiments, before the texturing process, the method further includes forming an emitter on the surface of the semiconductor substrate 1 by any one or more of high-temperature diffusion, slurry doping, or ion implantation, where the fabricated battery is a TOPcon battery, the emitter is fabricated on the first surface (i.e., front surface) of the semiconductor substrate 1. When the fabricated battery is an IBC battery, the emitter is fabricated on the second surface (i.e., the back surface) of the semiconductor substrate 1. Illustratively, when the semiconductor substrate 1 is an N-type crystalline silicon substrate, the emitter is formed by diffusing boron atoms by a boron source. The boron source may be, for example, diffusion treated with boron tribromide such that the microcrystalline silicon phase of crystalline silicon is converted to the polycrystalline silicon phase.

In some embodiments, the emitter may be an emitter structure having a uniform doping depth, or may be a selective emitter structure having different doping concentrations and doping depths.

Step S300, forming a first passivation layer 3 on the first surface of the semiconductor substrate 1, and forming a second passivation layer 4 on the second surface of the semiconductor substrate 1.

In some embodiments, at least one of the first passivation layer 3 and the second passivation layer 4 may include, but is not limited to, a single-layer oxide layer or a multi-layer structure of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like. Of course, other types of passivation layers may be used, and the specific materials of the first passivation layer 3 and the second passivation layer 4 are not limited in the present invention, and the first passivation layer 3 and the second passivation layer 4 can generate good passivation and anti-reflection effects on the semiconductor substrate 1, which is helpful for improving the conversion efficiency of the battery.

In some embodiments, the first passivation layer 3 and the second passivation layer 4 may be deposited by a plasma enhanced chemical vapor deposition method, although other methods, such as an organic chemical vapor deposition method, may be used.

In some embodiments, the thickness of the first passivation layer 3 ranges from 10nm to 100nm, specifically, 10nm, 20nm, 30nm, 42nm, 50nm, 60nm, 70nm, 80nm, 90nm, or 100nm, or the like, but other values within the above range are also possible, and the present invention is not limited thereto.

In some embodiments, the thickness of the second passivation layer 4 ranges from 10nm to 100nm, specifically, 10nm, 20nm, 30nm, 42nm, 50nm, 60nm, 70nm, 80nm, 90nm, or 100nm, or the like, but other values within the above range are also possible, and the present invention is not limited thereto.

In step S400, a first electrode 7 is formed on the surface of the first passivation layer 3, and a second electrode 8 is formed on the surface of the second passivation layer 4, thereby obtaining a TOPcon battery.

In some embodiments, the front main grid and the front auxiliary grid are printed on the front surface of the semiconductor substrate 1 by using slurry, and are dried to form the corresponding first electrode 7, the back main grid and the back auxiliary grid are printed on the back surface of the semiconductor substrate 1 by using slurry, and are dried to form the corresponding second electrode 8, and finally the dried battery piece is sintered to obtain the solar cell 100.

The specific materials of the first electrode 7 and the second electrode 8 are not limited in the embodiment of the present application. For example, the first electrode 7 is a silver electrode or a silver/aluminum electrode, and the second electrode 8 is a silver electrode or a silver/aluminum electrode.

In some embodiments, step S400 is: a third electrode 9 is formed on the surface of the second passivation layer 4 to obtain an IBC cell.

In some embodiments, the third electrode 9 is formed on the back surface of the battery using at least one of a metal evaporation method, a screen printing method, and an electroplating method.

In some embodiments, the material of the third electrode 9 includes at least one of aluminum, gold, copper, silver, and platinum.

In a third aspect, an embodiment of the present application provides a photovoltaic module 1000, including a cell string formed by electrically connecting solar cells as described above.

Specifically, referring to fig. 10, the photovoltaic module 1000 includes a first cover plate 200, a first encapsulation adhesive layer 300, a solar cell string, a second encapsulation adhesive layer 400, and a second cover plate 500.

In some embodiments, the solar cell string includes a plurality of solar cells 100 as described above connected by conductive tapes, and the solar cells 100 may be connected by partial lamination or splicing.

In some embodiments, the first and second cover plates 200, 500 may be transparent or opaque cover plates, such as glass cover plates, plastic cover plates.

Two sides of the first encapsulation glue layer 300 are respectively contacted and attached with the first cover plate 200 and the battery string, and two sides of the second encapsulation glue layer 400 are respectively contacted and attached with the second cover plate 500 and the battery string. The first and second encapsulation adhesive layers 300 and 400 may be an ethylene-vinyl acetate copolymer (EVA) adhesive film, a polyethylene octene co-elastomer (POE) adhesive film, or a polyethylene terephthalate (PET) adhesive film, respectively.

The photovoltaic module 1000 may also be packaged with a side edge completely surrounded, that is, the side edge of the photovoltaic module 1000 is completely encapsulated with a packaging adhesive tape, so as to prevent the photovoltaic module 1000 from generating a lamination offset phenomenon in the lamination process.

The photovoltaic module 1000 also includes a sealing member fixedly encapsulated to a portion of the edge of the photovoltaic module 1000. The edge sealing member may be fixedly packaged to an edge of the photovoltaic module 1000 near a corner. The edge sealing member may be a high temperature resistant tape. The high-temperature-resistant adhesive tape has excellent high-temperature resistance, can not be decomposed or fall off in the lamination process, and can ensure reliable packaging of the photovoltaic module 1000. Wherein, both ends of the high temperature resistant tape are fixed to the second cover plate 500 and the first cover plate 200, respectively. The two ends of the high temperature resistant adhesive tape can be respectively adhered to the second cover plate 500 and the first cover plate 200, and the middle part of the high temperature resistant adhesive tape can limit the side edges of the photovoltaic module 1000, so that the photovoltaic module 1000 is prevented from generating lamination offset in the lamination process.

The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A solar cell, comprising:

2. The solar cell of claim 1, further comprising: a first electrode located on the surface of the first passivation layer and a second electrode located on the surface of the second passivation layer.

3. The solar cell of claim 1, further comprising: and the third electrode is positioned on the surface of the second passivation layer.

4. A solar cell according to any one of claims 1-3, wherein the ratio of the area of the second surface of the semiconductor substrate to the projected area of the third region on the semiconductor substrate is 1: (0.01 to 0.1).

5. A solar cell according to any one of claims 1-3, wherein the ratio of the area of the second surface of the semiconductor substrate to the projected area of the first region on the semiconductor substrate is 1: (0.01 to 0.1).

6. A solar cell according to any one of claims 1-3, wherein the ratio of the area of the second surface of the semiconductor substrate to the projected area of the second region on the semiconductor substrate is 1: (0.8 to 0.99).

7. A solar cell according to any of claims 1-3, wherein the size of the third sub-texture adjacent to the first region is smaller than the size of the third sub-texture adjacent to the second region.

8. A solar cell according to any one of claims 1-3, wherein the length of the first sub-texture is 2-15 μm; and/or the width of the first sub-texture structure is 2-15 μm; and/or the height of the first sub-texture structure is 50 nm-1000 nm.

9. A solar cell according to any one of claims 1-3, wherein the length of the third sub-texture is 6-18 μm; and/or the width of the third sub-texture structure is 6-18 μm; and/or the height of the third sub-texture structure is 50 nm-1000 nm.

10. A solar cell according to any one of claims 1-3, wherein the second sub-texture has a length of 13-20 μm; and/or the width of the second sub-texture structure is 13-20 μm; and/or the height of the second sub-texture structure is 50-1000 nm.

11. The solar cell of any one of claims 1-3, wherein the morphology of at least one of the first sub-texture, the second sub-texture, and the third sub-texture comprises at least one of pyramid, prism, sphere, and pen.

12. The solar cell of any one of claims 1-3, wherein the roughness of the first sub-texture is less than the roughness of the third sub-texture, and the roughness of the third sub-texture is less than the roughness of the second sub-texture.

13. The solar cell of any one of claims 1-3, wherein a reflectance of sunlight on the first sub-texture is less than a reflectance of sunlight on the third sub-texture, and wherein a reflectance of sunlight on the third sub-texture is less than a reflectance of sunlight on the second sub-texture.

14. The solar cell of claim 13, wherein the reflectivity of sunlight on the first sub-texture is 20% -35%; and/or the reflectivity of sunlight on the third sub-texture structure is 25% -40%; and/or the reflectivity of sunlight on the second sub-texture structure is 35% -45%.

15. A solar cell according to any one of claims 1-3, wherein the ratio of the total surface area of the plurality of first sub-textures facing away from the side surface of the semiconductor substrate to the orthographic projection area of the first region on the semiconductor substrate is greater than the ratio of the total surface area of the plurality of third sub-textures facing away from the side surface of the semiconductor substrate to the orthographic projection area of the third region on the semiconductor substrate, and the ratio of the total surface area of the plurality of third sub-textures facing away from the side surface of the semiconductor substrate to the orthographic projection area of the third region on the semiconductor substrate is greater than the ratio of the total surface area of the plurality of second sub-textures facing away from the side surface of the semiconductor substrate to the orthographic projection area of the second region on the semiconductor substrate.

16. The solar cell of claim 15, wherein a ratio of a total surface area of a side surface of the plurality of first sub-textures facing away from the semiconductor substrate to an orthographic projection area of the first region on the semiconductor substrate is (1.5-3.0): 1, a step of; and/or

The ratio of the total surface area of the side surface of the plurality of third sub-textures facing away from the semiconductor substrate to the orthographic projection area of the third region on the semiconductor substrate is (1.2-2.5): 1, a step of; and/or

The ratio of the total surface area of the side surface of the plurality of second sub-textures facing away from the semiconductor substrate to the orthographic projection area of the second region on the semiconductor substrate is (1.0-1.8): 1.

17. a photovoltaic module, comprising:

a battery string formed by connecting a plurality of solar cells according to any one of claims 1 to 16;