CN117153847A - Thin film transistor array substrate and method of manufacturing the same - Google Patents

Thin film transistor array substrate and method of manufacturing the same Download PDF

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Publication number
CN117153847A
CN117153847A CN202210569891.7A CN202210569891A CN117153847A CN 117153847 A CN117153847 A CN 117153847A CN 202210569891 A CN202210569891 A CN 202210569891A CN 117153847 A CN117153847 A CN 117153847A
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China
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layer
metal layer
transparent electrode
thin film
film transistor
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许庭毓
陈蔚宗
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Transcend Optronics Technology Yangzhou Co ltd
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Transcend Optronics Technology Yangzhou Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/166—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect
    • G02F1/167—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect by electrophoresis
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/1675—Constructional details
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/1675—Constructional details
    • G02F1/1676—Electrodes
    • G02F1/16766—Electrodes for active matrices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

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  • Thin Film Transistor (AREA)

Abstract

A thin film transistor array substrate and a manufacturing method thereof are provided, wherein the thin film transistor array substrate comprises a bottom plate, a first metal layer, an insulating layer, a semiconductor layer, a second metal layer and a transparent electrode layer. The first metal layer is positioned on the bottom plate and provided with a first part and a second part. The insulating layer covers the bottom plate and the first metal layer. The semiconductor layer is positioned on the insulating layer and overlapped with the first part of the first metal layer. The second metal layer has a first portion on the semiconductor layer and a second portion on the insulating layer, and the second portion of the second metal layer overlaps the second portion of the first metal layer. The transparent electrode layer has a first portion and a second portion, wherein the first portion of the transparent electrode layer is disposed along the first portion of the second metal layer, and the second portion of the transparent electrode layer is disposed along the second portion of the second metal layer. The thin film transistor array substrate and the manufacturing method thereof can reduce one photomask, can be applied to electronic paper displays with lower resolution requirements, and can be used as an etching stop layer on the second part of the transparent electrode layer.

Description

Thin film transistor array substrate and method of manufacturing the same
Technical Field
The disclosure relates to a thin film transistor array substrate and a manufacturing method thereof.
Background
In general, a thin film transistor Array (TFT Array) substrate for an electronic paper display requires seven or eight mask lines. For example, the number of masks may include patterned gates, gate spacers (insulators), semiconductor films, source/drain electrodes, passivation (Passivation) layers, planarization layers, and transparent electrode layers, and it is also possible to form another patterned metal layer after forming the planarization layers and before forming the transparent electrode layers. The array function of driving the electronic ink layer can be completed through the number of the mask channels of the seven channels or the eight channels.
Therefore, the period (Cycle time) for producing the thin film transistor array substrate is difficult to be shortened, and the cost of the photomask is expensive, which is not beneficial to the electronic paper display with lower resolution requirement.
Disclosure of Invention
One aspect of the present disclosure is a thin film transistor array substrate.
According to some embodiments of the present disclosure, a thin film transistor array substrate includes a base plate, a first metal layer, an insulating layer, a semiconductor layer, a second metal layer, and a transparent electrode layer. The first metal layer is positioned on the bottom plate and provided with a first part and a second part. The insulating layer covers the bottom plate and the first metal layer. The semiconductor layer is positioned on the insulating layer and overlapped with the first part of the first metal layer. The second metal layer has a first portion on the semiconductor layer and a second portion on the insulating layer, and the second portion of the second metal layer overlaps the second portion of the first metal layer. The transparent electrode layer has a first portion and a second portion, wherein the first portion of the transparent electrode layer is disposed along the first portion of the second metal layer, and the second portion of the transparent electrode layer is disposed along the second portion of the second metal layer.
In some embodiments, the transparent electrode layer directly contacts the second metal layer.
In some embodiments, the bottom surface of the transparent electrode layer is coplanar with the top surface of the second metal layer.
In some embodiments, the transparent electrode layer extends from a top surface of the second metal layer to a sidewall of the second metal layer.
In some embodiments, the first portion of the second metal layer has two separate sections, each section extending from the top surface of the semiconductor layer along a sidewall of the semiconductor layer to the top surface of the insulating layer.
In some embodiments, the thin film transistor array substrate further includes a passivation layer and a planarization layer. The passivation layer covers the insulating layer, the second metal layer and the transparent electrode layer. The planarization layer covers the passivation layer. The planarization layer and the passivation layer each have an opening, and the transparent electrode layer on the second portion of the second metal layer is located in the two openings.
Another aspect of the present disclosure is a method for manufacturing a thin film transistor array substrate.
According to some embodiments of the present disclosure, a method for manufacturing a thin film transistor array substrate includes sequentially forming a first metal layer, an insulating layer and a semiconductor layer on a bottom plate, wherein the first metal layer has a first portion and a second portion, the insulating layer covers the bottom plate and the first metal layer, and the semiconductor layer is located on the insulating layer and overlaps the first portion of the first metal layer; forming a second metal layer on the semiconductor layer and the insulating layer; forming a transparent electrode layer on the second metal layer; patterning the transparent electrode layer such that a first portion of the transparent electrode layer is disposed along a first portion of the second metal layer, and a second portion of the transparent electrode layer is disposed along a second portion of the second metal layer, wherein the second portion of the second metal layer overlaps the second portion of the first metal layer; and patterning the second metal layer.
In some embodiments, the patterning the transparent electrode layer includes forming a photoresist layer on the transparent electrode layer; and etching the transparent electrode layer using the photoresist layer.
In some embodiments, the patterning the second metal layer includes: the second metal layer is etched using the photoresist layer such that a first portion of the second metal layer is separated from a second portion, and the first portion of the second metal layer has two separated segments, each segment extending from a top surface of the semiconductor layer along a sidewall of the semiconductor layer to a top surface of the insulating layer.
In some embodiments, the method further includes removing the photoresist layer after etching the second metal layer by using the photoresist layer.
In some embodiments, the method further includes removing the photoresist layer, and heating to crystallize the transparent electrode layer.
In some embodiments, the method further includes removing the photoresist layer after etching the transparent electrode layer with the photoresist layer.
In some embodiments, the method further includes removing the photoresist layer, and heating to crystallize the transparent electrode layer.
In some embodiments, the patterning the second metal layer includes etching the second metal layer with the crystallized transparent electrode layer to separate a first portion of the second metal layer from a second portion, and the first portion of the second metal layer has two separate segments, each segment extending from a top surface of the semiconductor layer along a sidewall of the semiconductor layer to a top surface of the insulating layer.
In some embodiments, the method further includes forming a passivation layer covering the insulating layer, the second metal layer and the transparent electrode layer; and etching the passivation layer over the second portion of the second metal layer to form an opening, wherein the second portion of the transparent electrode layer is an etch stop layer.
In some embodiments, the method further includes forming a planarization layer covering the passivation layer, wherein the planarization layer has an opening, and the transparent electrode layer on the second portion of the second metal layer is located in the opening of the planarization layer and the opening of the passivation layer.
In the above embodiments of the present disclosure, since the transparent electrode layer is formed on the second metal layer after the second metal layer is formed on the semiconductor layer and the insulating layer, the transparent electrode layer and the second metal layer below the transparent electrode layer may be sequentially patterned by the same photoresist layer, or the patterned transparent electrode layer may be used as a mask to pattern the second metal layer. As such, a first portion of the transparent electrode layer may be disposed along a first portion of the second metal layer, and a second portion of the transparent electrode layer may be disposed along a second portion of the second metal layer. The manufacturing method of the thin film transistor array substrate can reduce one photomask, and can be applied to electronic paper displays with lower resolution requirements. In addition, the second portion of the transparent electrode layer can be used as an etching stop layer in a subsequent process.
Drawings
The aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawing figures. Note that the various features are not drawn to scale in accordance with standard practices in the industry. Indeed, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIG. 1 is a flow chart of a method for manufacturing a thin film transistor array substrate according to an embodiment of the disclosure;
fig. 2 to 6 are sectional views illustrating steps of a method for fabricating a thin film transistor array substrate according to an embodiment of the present disclosure;
fig. 7 and 8 are cross-sectional views of a method for manufacturing a thin film transistor array substrate according to another embodiment of the present disclosure after the step of fig. 3.
[ symbolic description ]
100:thin film transistor array substrate
105 floor board
110 first metal layer
112 first part
114 second part
120 insulating layer
130 semiconductor layer
140 second metal layer
142 first part
143 section(s)
144 second part
145 section(s)
150 transparent electrode layer
152 first part
154 second part
160 passivation layer
170 flat layer
P: photoresist layer
O1, O2 opening
S1, S2, S3, S4, S5 step
Detailed Description
The following disclosure of embodiments provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. Of course, these examples are merely examples and are not intended to be limiting. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Spatially relative terms, such as "below … …," "below … …," "lower," "above … …," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Fig. 1 is a flowchart illustrating a method for manufacturing a thin film transistor array substrate according to an embodiment of the disclosure. The manufacturing method of the thin film transistor array substrate comprises the following steps. In step S1, a first metal layer, an insulating layer and a semiconductor layer are sequentially formed on a bottom plate, wherein the first metal layer has a first portion and a second portion, the insulating layer covers the bottom plate and the first metal layer, and the semiconductor layer is located on the insulating layer and overlaps the first portion of the first metal layer. Next, in step S2, a second metal layer is formed on the semiconductor layer and the insulating layer. Then, in step S3, a transparent electrode layer is formed on the second metal layer. Subsequently in step S4, the transparent electrode layer is patterned such that a first portion of the transparent electrode layer is disposed along a first portion of the second metal layer, and a second portion of the transparent electrode layer is disposed along a second portion of the second metal layer, wherein the second portion of the second metal layer overlaps the second portion of the first metal layer. Next, in step S5, the second metal layer is patterned. The method of manufacturing the thin film transistor array substrate is not limited to the steps S1 to S5, for example, in some embodiments, other steps may be further included between the two steps, or other steps may be further included before the step S1 and after the step S5.
In the following description, each step of the method for manufacturing a thin film transistor array substrate will be described in detail.
Fig. 2 to 6 are cross-sectional views of a method for manufacturing a thin film transistor array substrate 100 (see fig. 6) according to an embodiment of the present disclosure. Referring to fig. 2, a first metal layer 110, an insulating layer 120, and a semiconductor layer 130 may be sequentially formed on the bottom plate 105. The bottom plate 105 may be a glass plate or a plastic substrate. The first metal layer 110 and the semiconductor layer 130 may be formed by a patterning process, such that the first metal layer 110 has a first portion 112 and a second portion 114. Herein, the patterning process may include exposure, development, etching, and the like. The insulating layer 120 covers the bottom plate 105 and the first metal layer 110. The first portion 112 of the first metal layer 110 may serve as a gate of the thin film transistor, and the insulating layer 120 may serve as a gate spacer (Insulator). The semiconductor layer 130 is located on the insulating layer 120 and overlaps the first portion 112 of the first metal layer 110. Further, the insulating layer 120 overlapping the second portion 114 of the first metal layer 110 is free of the semiconductor layer 130. In some embodiments, the material of the first metal layer 110 may include aluminum or molybdenum, the material of the insulating layer 120 may include silicon nitride or silicon dioxide, and the material of the semiconductor layer 130 may include amorphous silicon or Indium Gallium Zinc Oxide (IGZO), but is not limited to the disclosure.
After the semiconductor layer 130 is formed, a second metal layer 140 may be formed on the semiconductor layer 130 and the insulating layer 120. Then, a transparent electrode layer 150 may be formed on the second metal layer 140. The second metal layer 140 and the transparent electrode layer 150 may be formed by deposition, such as Physical Vapor Deposition (PVD). In this way, the transparent electrode layer 150 can directly contact the second metal layer 140. In other words, the bottom surface of the transparent electrode layer 150 is coplanar with the top surface of the second metal layer 140. In some embodiments, the material of the transparent electrode layer 150 includes Indium Tin Oxide (ITO). In addition, the second metal layer 140 has a first portion 142 on the semiconductor layer 130 and a second portion 144 on the insulating layer 120, the first portion 142 of the second metal layer 140 overlapping the first portion 112 of the first metal layer 110, and the second portion 144 of the second metal layer 140 overlapping the second portion 114 of the first metal layer 110.
Referring to fig. 3, after the transparent electrode layer 150 is formed, the transparent electrode layer 150 may be patterned such that the first portion 152 of the transparent electrode layer 150 is disposed along the first portion 142 of the second metal layer 140, the second portion 154 of the transparent electrode layer 150 is disposed along the second portion 144 of the second metal layer 140, and the first portion 152 of the transparent electrode layer 150 forms two separate segments. In the step of patterning the transparent electrode layer 150, the photoresist layer P of fig. 3 may be formed on the transparent electrode layer 150, and the transparent electrode layer 150 is etched by using the photoresist layer P as a mask. Through this step, the second metal layer 140 that is not overlapped with the first metal layer 110 is exposed, and the transparent electrode layer 150 may extend from the top surface of the second metal layer 140 to the sidewall of the second metal layer 140.
In this embodiment, after the second metal layer 140 is formed on the semiconductor layer 130 and the insulating layer 120, the transparent electrode layer 150 is formed on the second metal layer 140, so that the transparent electrode layer 150 and the second metal layer 140 thereunder can be patterned sequentially from the same photoresist layer P. Therefore, the manufacturing method of the thin film transistor array substrate can reduce one photomask (for example, the yellow light and etching steps of the traditional transparent electrode can be omitted), and can be applied to electronic paper displays with lower resolution requirements.
Referring to fig. 4, after etching the transparent electrode layer 150, the photoresist layer P may be remained, and the second metal layer 140 may be further patterned. In the step of patterning the transparent electrode layer 150, the second metal layer 140 can be etched using the photoresist layer P as a mask, such that the first portion 142 and the second portion 144 of the second metal layer 140 are separated, and the first portion 142 of the second metal layer 140 has two separated sections 143, 145. Each segment 143, 145 may extend from the top surface of the semiconductor layer 130 along a sidewall of the semiconductor layer 130 to the top surface of the insulating layer 120. The two sections 143, 145 of the first portion 142 of the second metal layer 140 can serve as the source and drain of the thin film transistor, respectively. Through this step, the insulating layer 120 that is not overlapped with the first metal layer 110 is exposed.
Referring to fig. 5, after etching the second metal layer 140 using the photoresist layer P, the photoresist layer P may be removed. Then, a high temperature crystallization step is performed, and the temperature is raised to crystallize the transparent electrode layer 150, so that the transparent electrode layer 150 has the characteristics of etching resistance and bombardment resistance. In addition, the stacked structure from the first portion 112 of the first metal layer 110 to the first portion 142 of the second metal layer 140 on the left side of fig. 5 can be regarded as a thin film transistor, and the stacked structure from the second portion 114 of the first metal layer 110 to the second portion 144 of the second metal layer 140 on the right side of fig. 5 can be regarded as a storage capacitor.
Referring to fig. 6, after the transparent electrode layer 150 is crystallized at a high temperature, a passivation layer 160 may be formed to cover the insulating layer 120, the second metal layer 140 and the transparent electrode layer 150. The material of the passivation layer 160 may include nitride or oxide, and may be formed using Chemical Vapor Deposition (CVD). Next, the passivation layer 160 over the second portion 144 of the second metal layer 140 may be etched to form an opening O1, wherein the second portion 154 of the transparent electrode layer 150 may act as an Etch stop layer because the transparent electrode layer 150 already has Etch-resistant properties. After the passivation layer 160 is formed, a planarization layer 170 is formed to cover the passivation layer 160, wherein the planarization layer 170 has an opening O2, and the transparent electrode layer 150 on the second portion 144 of the second metal layer 140 is located in the opening O2 of the planarization layer 170 and the opening O1 of the passivation layer 160. The material of the planarization layer 170 may be an organic height Wen Guangzu, and may be formed by Coating (Coating) method.
Through the above steps, the thin film transistor array substrate 100 of fig. 6 can be obtained.
It should be appreciated that the connection relationships, materials and functions of the elements described above will not be repeated, and are described in detail. In the following description, another method for manufacturing a thin film transistor array substrate will be described.
Fig. 7 and 8 are cross-sectional views of a method for manufacturing a thin film transistor array substrate 100 according to another embodiment of the present disclosure after the step of fig. 3. In this embodiment, the steps of fig. 2 to 3 are as described above, and the detailed description is not repeated. Referring to fig. 3 and 7, after patterning the transparent electrode layer 150 (i.e., after etching the transparent electrode layer 150 with the photoresist layer P), the photoresist layer P is removed. Then, after the photoresist layer P is removed, a high temperature crystallization step is performed, and the temperature is raised to crystallize the transparent electrode layer 150, so that the transparent electrode layer 150 has the characteristics of etching resistance and bombardment resistance.
Referring to fig. 8, after the transparent electrode layer 150 is crystallized, the second metal layer 140 may be patterned. In this embodiment, the second metal layer 140 may be etched using the patterned and crystallized transparent electrode layer 150 such that the first portion 142 of the second metal layer 140 is separated from the second portion 144, and the first portion 142 of the second metal layer 140 has two separated sections 143, 145, each section 143, 145 extending from the top surface of the semiconductor layer 130 along the sidewalls of the semiconductor layer 130 to the top surface of the insulating layer 120.
In the present embodiment, after the second metal layer 140 is formed on the semiconductor layer 130 and the insulating layer 120, the transparent electrode layer 150 is formed on the second metal layer 140, so that the second metal layer 140 can be patterned by using the patterned transparent electrode layer 150 as a mask. Therefore, the manufacturing method of the thin film transistor array substrate can reduce one photomask (for example, the traditional yellow light and etching steps of the second metal layer can be omitted), and can be applied to electronic paper displays with lower resolution requirements. In addition, due to the anti-etching and anti-bombardment properties of the transparent electrode layer 150, the transparent electrode layer 150 can help the second metal layer 140 to have a self-alignment effect during etching, so as to prevent the conventional photoresist pattern from becoming smaller during the metal dry etching process, and further avoid the critical dimension loss (Critical dimension loss; CD loss) from being too large.
Subsequent steps such as the step of fig. 6, after etching the second metal layer 140 using the patterned transparent electrode layer 150, the passivation layer 160 and the planarization layer 170 may be sequentially formed. Through the above steps, the thin film transistor array substrate 100 of fig. 6 can be obtained.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (16)

1. A thin film transistor array substrate, comprising:
a bottom plate;
a first metal layer on the bottom plate and having a first portion and a second portion;
an insulating layer covering the bottom plate and the first metal layer;
a semiconductor layer on the insulating layer and overlapping the first portion of the first metal layer;
a second metal layer having a first portion on the semiconductor layer and a second portion on the insulating layer, wherein the second portion of the second metal layer overlaps the second portion of the first metal layer; and
the transparent electrode layer is provided with a first part and a second part, wherein the first part of the transparent electrode layer is arranged along the first part of the second metal layer, and the second part of the transparent electrode layer is arranged along the second part of the second metal layer.
2. The thin film transistor array substrate of claim 1, wherein the transparent electrode layer directly contacts the second metal layer.
3. The thin film transistor array substrate of claim 1, wherein the bottom surface of the transparent electrode layer is coplanar with the top surface of the second metal layer.
4. The thin film transistor array substrate of claim 1, wherein the transparent electrode layer extends from a top surface of the second metal layer to a sidewall of the second metal layer.
5. The thin film transistor array substrate of claim 1, wherein the first portion of the second metal layer has two separated sections, each of the two sections extending from a top surface of the semiconductor layer along a sidewall of the semiconductor layer to a top surface of the insulating layer.
6. The thin film transistor array substrate according to claim 1, further comprising:
a passivation layer covering the insulating layer, the second metal layer and the transparent electrode layer; and
and a planarization layer covering the passivation layer, wherein the planarization layer and the passivation layer each have an opening, and the transparent electrode layer on the second portion of the second metal layer is located in the two openings.
7. A method for manufacturing a thin film transistor array substrate, comprising:
sequentially forming a first metal layer, an insulating layer and a semiconductor layer on a bottom plate, wherein the first metal layer is provided with a first part and a second part, the insulating layer covers the bottom plate and the first metal layer, and the semiconductor layer is positioned on the insulating layer and overlapped with the first part of the first metal layer;
forming a second metal layer on the semiconductor layer and the insulating layer;
forming a transparent electrode layer on the second metal layer;
patterning the transparent electrode layer such that a first portion of the transparent electrode layer is disposed along the first portion of the second metal layer, and a second portion of the transparent electrode layer is disposed along a second portion of the second metal layer, wherein the second portion of the second metal layer overlaps the second portion of the first metal layer; and
patterning the second metal layer.
8. The method of manufacturing a thin film transistor array substrate according to claim 7, wherein patterning the transparent electrode layer comprises:
forming a photoresist layer on the transparent electrode layer; and
the transparent electrode layer is etched using the photoresist layer.
9. The method of claim 8, wherein patterning the second metal layer comprises:
the second metal layer is etched using the photoresist layer such that the first portion of the second metal layer is separated from the second portion, and the first portion of the second metal layer has two separated segments, each of which extends from the top surface of the semiconductor layer along the sidewalls of the semiconductor layer to the top surface of the insulating layer.
10. The method of manufacturing a thin film transistor array substrate according to claim 9, further comprising:
after etching the second metal layer by using the photoresist layer, the photoresist layer is removed.
11. The method of manufacturing a thin film transistor array substrate according to claim 10, further comprising:
after removing the photoresist layer, heating to crystallize the transparent electrode layer.
12. The method of manufacturing a thin film transistor array substrate according to claim 8, further comprising:
after the transparent electrode layer is etched by using the photoresist layer, the photoresist layer is removed.
13. The method of manufacturing a thin film transistor array substrate according to claim 12, further comprising:
after removing the photoresist layer, heating to crystallize the transparent electrode layer.
14. The method of claim 13, wherein patterning the second metal layer comprises:
the second metal layer is etched using the crystallized transparent electrode layer to separate the first portion from the second portion of the second metal layer, and the first portion of the second metal layer has two separated segments, each of which extends from the top surface of the semiconductor layer along the sidewalls of the semiconductor layer to the top surface of the insulating layer.
15. The method of manufacturing a thin film transistor array substrate according to claim 7, further comprising:
forming a passivation layer to cover the insulating layer, the second metal layer and the transparent electrode layer; and
the passivation layer over the second portion of the second metal layer is etched to form an opening, wherein the second portion of the transparent electrode layer is an etch stop layer.
16. The method of manufacturing a thin film transistor array substrate according to claim 15, further comprising:
a planarization layer is formed to cover the passivation layer, wherein the planarization layer has an opening, and the transparent electrode layer on the second portion of the second metal layer is located in the opening of the planarization layer and the opening of the passivation layer.
CN202210569891.7A 2022-05-24 2022-05-24 Thin film transistor array substrate and method of manufacturing the same Pending CN117153847A (en)

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