CN117153215A - Control circuit and memory - Google Patents
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
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- G11C—STATIC STORES
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- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
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- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
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- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
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Abstract
The embodiment of the disclosure discloses a control circuit and a memory. Wherein the control circuit includes: the device comprises a command decoding module, a command identification signal generating module and a channel selecting module. And the command decoding module is configured to decode at least one group of coded commands into at least one function subcommand and determine the corresponding function command according to the at least one function subcommand. The command identification signal generation module is configured to generate a command identification signal according to the first line subcommand; the first row of subcommand is the function subcommand with the forefront time sequence in each function command. The channel selection module is configured to select one sub-channel to transmit the function command according to the command identification signal in the first transmission mode, and transmit the function command through all sub-channels in the second transmission mode.
Description
Technical Field
The present disclosure relates to, but is not limited to, a control circuit and a memory.
Background
With the development of semiconductor technology, the integration level of the memory is required to be higher and the performance standard is higher. HBM (High Bandwidth Memory) the memory chips are packaged after a plurality of memory chips are stacked together, so that a high-capacity, high-bit-width memory can be obtained.
Disclosure of Invention
In view of the above, the embodiments of the present disclosure provide a control circuit and a memory, which can simplify coding commands and related data lines.
The technical scheme of the embodiment of the disclosure is realized as follows:
the disclosed embodiments provide a control circuit including: the command decoding module is configured to receive at least one group of coded commands, decode at least one group of coded commands into at least one function subcommand, and determine corresponding function commands according to at least one function subcommand; the command identification signal generation module is electrically connected with the command decoding module and is configured to receive and generate a command identification signal according to the first row subcommand; the first line subcommand is the function subcommand with the forefront time sequence in each function command; the channel selection module is electrically connected with the command decoding module, the command identification signal generation module and the plurality of sub-channels and is configured to receive and select one sub-channel to transmit the function command according to the command identification signal in a first transmission mode, and transmit the function command through all the sub-channels in a second transmission mode.
In the above solution, the command decoding module includes: a plurality of first D flip-flops, a plurality of second D flip-flops, a first decoder, and a second decoder; the data input end of each first D trigger correspondingly receives one bit of data in a group of coding commands; the first decoder comprises a plurality of input ends and a plurality of output ends, each input end of the first decoder is correspondingly connected with an in-phase output end of the first D trigger, and each output end of the first decoder correspondingly outputs one function subcommand; the data input end of each second D trigger correspondingly receives one bit of data in a group of coding commands; the second decoder comprises a plurality of input ends and a plurality of output ends, each input end of the second decoder is correspondingly connected with an in-phase output end of the second D trigger, and each output end of the second decoder correspondingly outputs one function subcommand.
In the above scheme, the clock input ends of the plurality of first D flip-flops all receive clock signals; the clock input ends of the plurality of second D flip-flops all receive the clock signals after the phase inversion.
In the above solution, the command decoding module further includes: and the function command control module is electrically connected with the first decoder and the second decoder respectively and is configured to receive and determine and output the corresponding function command according to at least one function subcommand.
In the above scheme, the function command control module is further electrically connected to the command identification signal generating module and the channel selection module, and is further configured to receive and continuously receive the function subcommand according to the command identification signal until a tail row subcommand is received, and send a reset command to the channel selection module; the tail line subcommand is the function subcommand with the last time sequence in each function command.
In the above solution, the channel selection module includes: the channel selection command generation module is electrically connected with the command identification signal generation module and is configured to receive and generate a corresponding channel selection command according to the command identification signal; a mode enable signal generation module configured to generate a mode enable signal; the value of the mode enable signal characterizes the first transmission mode or the second transmission mode; and the command transmission switch module is electrically connected with the channel selection command generation module and the mode enabling signal generation module respectively and is configured to receive and select one sub-channel to transmit the function command according to the mode enabling signal and the channel selection command, or transmit the function command through all the sub-channels.
In the above aspect, the channel selection command generating module is further electrically connected to the function command control module, and is further configured to receive and respond to the reset command, and reset the value of the channel selection command.
In the above solution, the command identification signal includes: a first command identification signal and a second command identification signal; the channel selection command includes: a first channel selection command and a second channel selection command; the channel selection command generation module includes: a first SR latch, a second SR latch, a first AND gate, a second AND gate, a first inverter and a second inverter; a first input end of the first AND gate receives the first command identification signal, and a second input end of the first AND gate is electrically connected with an output end of the first inverter; the first input end of the second AND gate receives the second command identification signal, and the second input end of the second AND gate is electrically connected with the output end of the second inverter; a first input end of the first SR latch receives the reset command, a second input end of the first SR latch is electrically connected with an output end of the first AND gate, and a first output end of the first SR latch is electrically connected with an input end of the first inverter; the first output end of the first SR latch outputs the first channel selection command; the first input end of the second SR latch receives the reset command, the second input end of the second SR latch is electrically connected with the output end of the second AND gate, and the first output end of the second SR latch is electrically connected with the input end of the second inverter; the first output of the second SR latch outputs the second channel select command.
In the above aspect, the mode enable signal generating module includes: a channel register configured to store a mode value; the mode value is used to characterize the first transmission mode or the second transmission mode; the input end of the third inverter is connected with the channel register to acquire the mode value; a first or gate, a first input end of which is connected with the third inverter, and a second input end of which is used for receiving a special command by the function command control module; the special command is used to force the second transmission mode to be initiated.
In the above solution, the plurality of sub-channels includes: a first sub-channel and a second sub-channel; the command transmission switch module includes: a second or gate, a first input end of which receives the mode enabling signal, and a second input end of which receives a first command identification signal; a third or gate, a first input terminal of which receives the mode enable signal, and a second input terminal of which receives a second command identification signal; the first input ends of the third AND gates are electrically connected with the output ends of the second OR gates, the second input end of each third AND gate correspondingly receives one functional command, and the output end of each third AND gate is correspondingly connected with one data line in the first sub-channel; and the first input ends of the fourth AND gates are electrically connected with the output end of the third OR gate, the second input end of each fourth AND gate correspondingly receives one functional command, and the output end of each fourth AND gate is correspondingly connected with one data line in the second sub-channel.
In the above solution, the command identification signal generating module includes: a fourth or gate; the fourth OR gate comprises a plurality of input ends, and each input end of the fourth OR gate correspondingly receives one first-row subcommand; the fourth or gate outputs the command identification signal.
The embodiment of the disclosure also provides a memory, which comprises the control circuit in the scheme.
It can be seen that the disclosed embodiments provide a control circuit and memory. Wherein the control circuit includes: the device comprises a command decoding module, a command identification signal generating module and a channel selecting module. The command decoding module is configured to receive at least one set of encoded commands, decode the at least one set of encoded commands into at least one function subcommand, and determine a corresponding function command according to the at least one function subcommand. The command identification signal generation module is electrically connected with the command decoding module and is configured to receive and generate a command identification signal according to the first row subcommand; the first row of subcommand is the function subcommand with the forefront time sequence in each function command. The channel selection module is electrically connected with the command decoding module, the command identification signal generation module and the plurality of sub-channels and is configured to receive and select one sub-channel to transmit the function command according to the command identification signal in a first transmission mode and transmit the function command through all the sub-channels in a second transmission mode.
It can be understood that the command identification signal generating module generates a command identification signal according to the first line subcommand in the function subcommand; furthermore, the channel selection module selects one sub-channel to transmit the function command according to the command identification signal in the first transmission mode. In this way, no separate data need be provided in the encoded command to identify the sub-channel to be selected, i.e. no additional data lines are occupied to identify the sub-channel for transmitting data, thereby simplifying the encoded command and the associated data lines.
Drawings
Fig. 1 is a schematic structural diagram of an HBM memory chip in the related art;
fig. 2 is a schematic structural diagram of a control circuit according to an embodiment of the disclosure;
fig. 3 is a schematic structural diagram of a command decoding module in a control circuit according to an embodiment of the disclosure;
FIG. 4 is a schematic diagram of signals for sampling subcommands in a control circuit according to an embodiment of the present disclosure;
FIG. 5A is a schematic diagram of a decoder in a control circuit according to an embodiment of the disclosure;
FIG. 5B is a second schematic diagram of a decoder in a control circuit according to an embodiment of the disclosure;
FIG. 6 is a schematic diagram of the logic of the function command control module in the control circuit according to the embodiment of the disclosure;
Fig. 7 is a schematic structural diagram of a channel selection module in a control circuit according to an embodiment of the disclosure;
fig. 8 is a schematic structural diagram of a channel selection command generating module in a control circuit according to an embodiment of the disclosure;
FIG. 9A is a schematic diagram of an SR latch in a control circuit provided by an embodiment of the disclosure;
FIG. 9B is a second schematic diagram of an SR latch in a control circuit in accordance with the disclosed embodiments;
fig. 10 is a schematic structural diagram of a mode enable signal generating module in a control circuit according to an embodiment of the present disclosure;
fig. 11 is a schematic structural diagram of a command transmission switch module in a control circuit according to an embodiment of the disclosure;
fig. 12 is a schematic structural diagram of a command identification signal generating module in a control circuit according to an embodiment of the present disclosure;
fig. 13 is a schematic structural diagram of a memory according to an embodiment of the present disclosure.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present disclosure more apparent, the technical solutions of the present disclosure are further elaborated below in conjunction with the drawings and the embodiments, and the described embodiments should not be construed as limiting the present disclosure, and all other embodiments obtained by those skilled in the art without making inventive efforts are within the scope of protection of the present disclosure.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.
If a similar description of "first/second" appears in the application document, the following description is added, in which the terms "first/second/third" merely distinguish similar objects and do not represent a specific ordering of the objects, it being understood that "first/second/third" may, where allowed, interchange a specific order or precedence, to enable embodiments of the disclosure described herein to be practiced otherwise than as illustrated or described herein.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.
In a storage system, channels (channels) are used to transfer data. The transmission rate of the channels and the number of the channels affect the transmission rate of the data; in general, the greater the number of channels, the faster the transmission rate of a single channel, the faster the transmission rate of data. Further, each Channel may be divided into a plurality of Sub-channels (Sub channels). During operation of the chip, individual sub-channels in each channel may be employed to transmit data as desired.
Referring to fig. 1, taking HBM (High Bandwidth Memory) as an example of a memory chip, HBMs are typically stacked together by a plurality of DRAM particles and a baseband (Base) particle, where each DRAM particle includes a plurality of channels (channels 0-3), each having an independent command interface and data interface.
Meanwhile, with continued reference to fig. 1, each channel in the hbm may be divided into two independent sub-channels (i.e., sub-channel 0 and sub-channel 1), where the two sub-channels share a command bus and have separate data buses. Aiming at the condition that the application scale requirement of the read-write page is smaller, the HBM also supports a pseudo channel mode; specifically, in the pseudo-channel mode, one sub-channel may be selected to transmit data.
However, in the related art, additional command bits are required to identify a sub-channel for transmitting data, and reading or writing data of the sub-channel is not flexible enough.
Fig. 2 is a schematic diagram of an alternative configuration of the control circuit provided by the present disclosure, and as shown in fig. 2, the control circuit 80 includes: a command decoding module 10, a command identification signal generation module 20 and a channel selection module 30. The command decoding module 10 is configured to receive at least one set of encoded command CODEs, decode the at least one set of encoded command CODEs into at least one function subcommand (hereinafter may be simply referred to as "subcommand") sub_cmd, and determine a corresponding function command CMD according to the at least one function subcommand sub_cmd. A command identification signal generating module 20 electrically connected to the command decoding module 10 and configured to receive and generate a command identification signal cmd_flag according to a first row Sub-command Sub-cmd_1 of the function Sub-commands sub_cmd; the first row subcommand sub_cmd_1 is the function subcommand sub_cmd with the forefront time sequence in each function command CMD. The channel selection module 30, which is electrically connected to the command decoding module 10, the command identification signal generation module 20, and the plurality of sub-channels SC1 and SC2, is configured to receive and select one sub-channel to transmit a function command CMD according to the command identification signal cmd_flag in the first transmission mode, and to transmit the function command (hereinafter, may be simply referred to as "command") CMD through all sub-channels in the second transmission mode.
In the disclosed embodiment, referring to FIG. 2, the multi-bit data is included in the encoded command CODE received by command decoding module 10. And, each bit of data is transmitted to the command decoding module 10 by a separate one of the data lines; that is, the input of the command decoding module 10 includes a plurality of data lines for receiving multi-bit data in the encoded command CODE.
With continued reference to fig. 2, the command decoding module 10 may decode a corresponding one of the function subcommands sub_cmd based on the values of the set of encoded command CODEs, that is, different values of the set of encoded command CODEs correspond to different function subcommands sub_cmd. Meanwhile, each function subcommand sub_cmd is transmitted by a separate one of the data lines, that is, the command decoding module 10 includes a plurality of data lines for transmitting different function subcommands sub_cmd.
With continued reference to fig. 2, each function command CMD may include one function subcommand sub_cmd, or may include a plurality of function subcommand sub_cmd; meanwhile, the function Sub-commands sub_cmd included in different function commands CMD are different from each other. The command decoding module 10 may determine the corresponding function command CMD according to the decoded function subcommand sub_cmd. Also, each of the function commands CMD is transmitted by a single data line, that is, the output terminal of the command decoding module 10 includes a plurality of data lines for outputting different function commands CMD.
Table 1 shows a truth table (Row Commands Truth Table) of row commands in the HBM, table 2 shows a truth table (Column Commands Truth Table) of column commands in the HBM, and reference is made to the JEDEC standard manual for details.
TABLE 1
TABLE 2
Referring to Table 1, for a row command, a set of CODE command CODE includes 10 bits of data R0-R9. Further, from the values of the 10-bit data R0 to R9, the corresponding function subcommand sub_CMD can be decoded; for example, if R0-R3 are all H (High, high level) and R4-R9 are all V (Valid, high level or low level), then the subcommand PDX/SRX can be decoded; for another example, if R0, R2 and R3 are L (Low), R4-R9 are V, then the subcommand SRE1 can be decoded.
With continued reference to Table 1, for the row command, a different function subcommand sub_CMD corresponds to a different function command CMD. Wherein the partial function command CMD includes a plurality of function Sub-commands sub_cmd, for example, the command ACT includes Sub-commands ACT1, ACT2, and ACT3; the partial function command CMD includes only one function subcommand sub_cmd, for example, the command RNOP includes only subcommand RNOP.
Similarly, referring to Table 2, for column commands, a set of CODE command CODE includes 8 bits of data C0-C7; further, from the values of the 8-bit data C0-C7, the corresponding function subcommand sub_CMD can be decoded; different function subcommands sub_cmd correspond to different function commands CMD.
In an embodiment of the present disclosure, referring to fig. 2, the command identification signal generating module 20 may generate the command identification signal cmd_flag according to the first row Sub-command sub_cmd_1. The first row subcommand sub_cmd_1 is the function subcommand sub_cmd with the forefront time sequence in each function command CMD. Specifically, for a function command CMD including a plurality of function subcommands sub_cmd, only the function subcommand sub_cmd having the forefront timing is the first row subcommand sub_cmd_1, and the remaining function subcommand sub_cmd is not the first row subcommand sub_cmd_1; for a function command CMD containing only one function subcommand sub_cmd, the only one function subcommand sub_cmd is the first one in timing, i.e., the only one function subcommand sub_cmd is the first row subcommand sub_cmd_1.
Referring to table 1, taking a row command in the HBM as an example, for example, out of 3 sub-commands ACT1, ACT2, and ACT3 included in the command ACT, the sub-command ACT1 is a first row sub-command, and the ACT2 and ACT3 are not first row sub-commands; as another example, the command PDX/SRX includes only one subcommand PDX/SRX, then subcommand PDX/SRX is the top row subcommand. Similarly, in connection with Table 2, taking the column commands in the HBM as an example, for example, of the 2 subcommands RD1 and RD2 included in the command RD, subcommand RD1 is the first line subcommand, RD2 is not the first line subcommand.
In the embodiment of the disclosure, referring to fig. 2, the channel selection module 30 may receive and select one sub-channel from the sub-channels SC1 and SC2 according to the command identification signal cmd_flag in the first transmission mode to transmit the function command CMD; that is, in the first transmission mode, the sub-channels SC1 and SC2 do not simultaneously transmit the same data, and only one sub-channel is used for transmitting the function command CMD at the same time. In addition, the channel selection module 30 may also transmit the function command CMD through all the sub-channels (C1 and C2) in the second transmission mode; that is, in the second transmission mode, the sub-channels SC1 and SC2 simultaneously transmit the same data, and the sub-channels SC1 and SC2 are commonly used to transmit the function command CMD.
In the embodiment of the disclosure, the first transmission mode may be a pseudo channel mode, and correspondingly, the second transmission mode does not adopt the pseudo channel mode. That is, the control circuit 80 may be used in the HBM for controlling the transmission of data, and the switching of modes.
It can be understood that the command identification signal generating module generates a command identification signal according to the first line subcommand in the function subcommand; furthermore, the channel selection module selects one sub-channel to transmit the function command according to the command identification signal in the first transmission mode. In this way, no separate data need be provided in the encoded command to identify the sub-channel to be selected, i.e. no additional data lines are occupied to identify the sub-channel for transmitting data, thereby simplifying the encoded command and the associated data lines.
In some embodiments of the present disclosure, referring to fig. 3, the command decoding module 10 includes: a plurality of first D flip-flops DFF1, a plurality of second D flip-flops DFF2, a first decoder Dec1, and a second decoder Dec2.
In the disclosed embodiment, referring to fig. 3, the data input terminal D of each first D flip-flop DFF1 correspondingly receives one bit of data in a set of encoded command CODEs; thus, a plurality of first D flip-flops DFF1 may buffer a set of CODE commands CODEs and output by the in-phase output Q. The number of the first D flip-flops DFF1 is set according to the number of data bits that need to be received, for example, referring to table 1 and table 2, 18 first D flip-flops DFF1 may be set, where 10 first D flip-flops DFF1 are used to cache 10 bits of data R0 to R9 in a row command, and 8 first D flip-flops DFF1 are used to cache 8 bits of data C0 to R7 in a column command.
With continued reference to fig. 3, the first decoder Dec1 includes a plurality of input terminals and a plurality of output terminals, each input terminal of the first decoder Dec1 is correspondingly connected to the in-phase output terminal Q of the first D flip-flop DFF1, and each output terminal of the first decoder Dec1 correspondingly outputs a function Sub-command sub_cmd. That is, the first decoder Dec1 may decode the function Sub-command sub_cmd according to the encoded command CODE sampled by the plurality of first D flip-flops DFF 1.
For example, in connection with table 1 and fig. 5A, the first decoder Dec1 may be used for decoding of row commands. The first decoder Dec1 may include 10 input terminals for receiving the data R0 to R9, respectively, and the first decoder Dec1 has a plurality of output terminals for outputting the function Sub-command sub_cmd in the row command; the function Sub command sub_cmd output from the first decoder Dec1 may include: subcommands RNOP, ACT1/2/3, … …, SRE2 or PDX/SRX, etc. After decoding a certain subcommand in the row command, the first decoder Dec1 may output the subcommand using a corresponding one of the output terminals.
As another example, in connection with table 2 and fig. 5B, the first decoder Dec1 is a decoder for decoding a column command. In this case, the first decoder Dec1 may include 8 input terminals for receiving the data C0 to C7, respectively, and the first decoder Dec1 has a plurality of output terminals for outputting the function Sub-command sub_cmd in the column command; the function Sub command sub_cmd output from the first decoder Dec1 may include: subcommands CNOP1/2, RD1/2, … …, MRS1/2, etc. After decoding a subcommand in the columnar command, the first decoder Dec1 may output the subcommand using a corresponding one of the output terminals.
In the disclosed embodiment, referring to fig. 3, the data input D of each second D flip-flop DFF2 correspondingly receives one bit of data in a set of encoded command CODEs; in this way, a plurality of second D flip-flops DFF2 can buffer a set of coded commands CODE and output by the in-phase output Q. Wherein the number of second D flip-flops DFF2 is set according to the number of data bits that need to be received, the second D flip-flops DFF2 have the same number as the first D flip-flops DFF 1.
With continued reference to fig. 3, the second decoder Dec2 includes a plurality of input terminals and a plurality of output terminals, each input terminal of the second decoder Dec2 is correspondingly connected to the in-phase output terminal Q of one second D flip-flop DFF2, and each output terminal of the second decoder Dec2 correspondingly outputs one function Sub-command sub_cmd. That is, the second decoder Dec2 may decode the function Sub-command sub_cmd according to the encoded command CODE sampled by the plurality of second D flip-flops DFF 2. Referring to fig. 5A and 5B, the second decoder Dec2 has similar inputs and outputs as the second decoder Dec1, and the second decoder Dec2 and the second decoder Dec1 have similar functions.
In addition, two first decoders Dec1 and two second decoders Dec2 may be provided, respectively, wherein one first decoder Dec1 and one second decoder Dec2 are used for decoding a row command, and the other first decoder Dec1 and the other second decoder Dec2 are used for decoding a column command.
It should be noted that the decoder in the embodiments of the present disclosure may be implemented by a conventional decoder, for example, may be implemented by conventional combinational logic.
In some embodiments of the present disclosure, referring to fig. 3, the clock inputs CK of the plurality of first D flip-flops DFF1 each receive a clock signal CKT; the clock input terminals CK of the plurality of second D flip-flops DFF2 each receive the inverted clock signal CKT. That is, the clock input terminals CK of the plurality of first D flip-flops DFF1 directly receive the clock signal CKT from the output terminal of the receiver Rec2, and the clock input terminals CK of the plurality of second D flip-flops DFF2 receive the clock signal CKT through the inverter INV.
In the embodiment of the disclosure, referring to fig. 3 and 4, a plurality of first D flip-flops DFF1 trigger sampling by a rising edge of a clock signal CKT, and finally obtain a command CMD1; the second D flip-flops DFF2 are triggered by the falling edge of the clock signal CKT to sample and finally obtain the command CMD2. The "first D flip-flop dff1+first decoder dec1" and the "second D flip-flop dff2+second decoder dec2" are completely duplicated circuits, and the only difference is that: the first decoder Dec1 and the second decoder Dec2 alternately operate on rising and falling edges of the clock signal CKT. For example, on a rising edge of the clock signal CKT, the first D flip-flop DFF1 samples the first subcommand, the first decoder Dec1 operates, and the decoded first subcommand is output; on the falling edge of the clock signal CKT, the second D flip-flop DFF2 samples the second subcommand, the second decoder Dec2 operates, and the decoded second subcommand is output; then, on the next rising edge of the clock signal CKT, the first D flip-flop DFF1 samples the third subcommand, the first decoder Dec1 operates, outputs the decoded third subcommand, and so on.
It will be appreciated that two sets of circuits are used to alternately sample and decode the subcommand on the rising and falling edges of the clock signal CKT. In this way, the frequency of the clock signal CKT for sampling can be reduced, that is, a lower frequency clock signal CKT can be used without changing the transmission rate and the total amount of transmission of data. Therefore, the sampling error caused by the high-frequency clock signal is avoided while the data transmission quantity is ensured, and the accuracy of the data is improved.
In some embodiments of the present disclosure, referring to fig. 3, the command decoding module 10 further includes: the function command control module 101. The function command control module 101 is electrically connected to the first decoder Dec1 and the second decoder Dec2, respectively, and is configured to receive and determine a corresponding function command CMD according to at least one function subcommand sub_cmd.
In some embodiments of the present disclosure, in conjunction with fig. 2 and 3, the functional command control module 101 is further electrically connected to the command identification signal generating module 20 and the channel selection module 30, respectively, and is further configured to receive and continuously receive the functional subcommand Sub-command Sub-CMD until the tail line subcommand is received according to the command identification signal cmd_flag1 or cmd_flag2, and to send a reset command Rst to the channel selection module 30. The tail line subcommand is the function subcommand with the last time sequence in each function command. Referring to table 1, taking a row command in HBM as an example, for example, out of 3 sub-commands ACT1, ACT2, and ACT3 included in the command ACT, the sub-command ACT3 is a tail row sub-command; as another example, the command PDX/SRX includes only one subcommand PDX/SRX, then subcommand PDX/SRX is a tail row subcommand. Similarly, in connection with Table 2, taking the column commands in the HBM as an example, for example, of the 2 subcommands RD1 and RD2 included in the command RD, subcommand RD2 is a tail row subcommand.
It should be noted that, referring to fig. 3, the command identification signal cmd_flag1 corresponds to a "first D flip-flop dff1+first decoder dec1" decoding path; that is, on the rising edge of the clock signal, the decoding path of the "first D flip-flop dff1+first decoder dec1" runs, and at this time, the generated command identification signal is cmd_flag1. The command identification signal cmd_flag2 corresponds to a "second D flip-flop dff2+second decoder dec2" decoding path; that is, on the falling edge of the clock signal, the decoding path of the "second D flip-flop dff2+the second decoder dec2" runs, and at this time, the generated command identification signal is cmd_flag2. The function command control module 101 may determine from which decoding path the received function subcommand sub_cmd comes according to the received command identification signal being cmd_flag1 or cmd_flag2.
In the disclosed embodiment, the function command control module 101 may operate according to the operating logic shown in fig. 6.
Referring to fig. 6, when the function command control module 101 receives the command identification signal cmd_flag1 or cmd_flag2, it indicates that the function Sub-command sub_cmd received by the function command control module 101 at this time is a first line Sub-command, that is, the function command control module 101 is about to output a new function command CMD.
With continued reference to fig. 6, first, the function command control module 101 needs to determine whether the function subcommand sub_cmd received at this time corresponds to the special command sp_cmd. The special command sp_cmd can force to open two sub-channels, i.e., the special command sp_cmd can force to start the second transmission mode. For example, in Table 1, subcommands PDE1 and PDX1 for power-down and recovery, and subcommands SRE1 and SRX for self-refresh entry and exit, all correspond to the special command Sp_CMD; as another example, in table 2, subcommand MRS1 for setting the mode register settings also corresponds to special command sp_cmd; then, when the function command control module 101 receives these subcommands, a special command sp_cmd of the active state may be issued to force the second transmission mode to be started.
With continued reference to fig. 6, further, after receiving the first line subcommand, the function command control module 101 may sequentially determine whether a subsequent subcommand needs to be received according to the received first line subcommand. For example, referring to table 1, if the received first line subcommand is subcommand ACT1, then subcommand ACT2 and ACT3 need to be continuously received, that is, the function command control module 101 needs to receive three subcommands in total, so as to be able to output the corresponding function command CMD; if the received first line subcommand is subcommand PDE1, then subcommand PDE2 needs to be continuously received, that is, the function command control module 101 needs to receive two subcommands in total, so as to output the corresponding function command CMD; if the received first line subcommand is subcommand SRX, the subcommand is the only subcommand in the command SRX, so that other subcommands are not required to be received any more, and the corresponding function command CMD can be directly output. Meanwhile, the function command control module 101 may output a reset command Rst after outputting the function command CMD; the reset command Rst may be a pulse signal, and the reset command Rst may reset the relevant signal in the channel selection module 30.
With continued reference to fig. 6, in addition, from receiving the second subcommand, the functional command control module 101 may determine whether the received multiple subcommand may be properly parsed; if an illegal or unresolved subcommand occurs, the function command control module 101 may interrupt operation, return to the idle state, and output a reset command Rst. Referring to table 1, for example, if the first subcommand received by the function command control module 101 is ACT1, the second subcommand received is PDE2, and the two subcommands do not correspond to the same function command CMD, then illegal or unresolved subcommands occur.
In some embodiments of the present disclosure, the functional command control module 101 may be implemented by a state machine circuit, thereby implementing the working logic shown in fig. 6. In other embodiments of the present disclosure, the functional command control module 101 may also be implemented by combinational logic, for example, may include a plurality of and gates, thereby implementing the operational logic shown in fig. 6.
It will be appreciated that the function command control module 101 may flexibly execute various logic functions according to the actual situation of the received subcommand, for example, stop continuing to receive the subcommand, output the reset command Rst, and issue the special command sp_cmd. Therefore, the efficiency of generating the function command CMD can be improved, the waste of performance is avoided, the method can be suitable for various conditions, and the robustness is improved.
In some embodiments of the present disclosure, referring to fig. 7, the channel selection module 30 includes: a channel selection command generation module 301, a mode enable signal generation module 302, and a command transmission switching module 303. The channel selection command generating module 301, the electrical connection command identification signal generating module 20, is configured to receive and generate a corresponding channel selection command PC0 or PC1 according to the command identification signal cmd_flag1 or cmd_flag2. A mode enable signal generation module 302 configured to generate a mode enable signal En; the value of the mode enable signal En characterizes either the first transmission mode or the second transmission mode. The command transmission switch module 303 is electrically connected to the channel selection command generating module 301 and the mode enable signal generating module 302, respectively, and is configured to receive and select one sub-channel transmission function command CMD according to the mode enable signal En and the channel selection command PC0 or PC1, or to transmit the function command CMD through all sub-channels.
In some embodiments of the present disclosure, referring to fig. 7, the channel selection command generation module 301 is further electrically connected to the functional command control module 101 and is further configured to receive and reset the values of the channel selection commands PC0 and PC1 in response to the reset command Rst.
In some embodiments of the present disclosure, referring to fig. 8, the command identification signal includes: a first command identification signal cmd_flag1 and a second command identification signal cmd_flag2. The channel selection command includes: a first channel selection command PC0 and a second channel selection command PC1. The channel selection command generation module 301 includes: the first AND second AND gates AND1, AND2, the first AND second inverters INV1 AND INV2 are connected to the first AND second SR latches S/R1 AND S/R2. A first input terminal of the first AND gate AND1 receives the first command identification signal cmd_flag1, AND a second input terminal of the first AND gate AND1 is electrically connected to an output terminal of the first inverter INV 1. The first input terminal of the second AND gate AND2 receives the second command identification signal cmd_flag2, AND the second input terminal of the second AND gate AND2 is electrically connected to the output terminal of the second inverter INV2. The first input end of the first SR latch S/R1 receives the reset command Rst, the second input end of the first SR latch S/R1 is electrically connected with the output end of the first AND gate AND1, AND the first output end of the first SR latch S/R1 is electrically connected with the input end of the first inverter INV 1. The first output terminal of the first SR latch S/R1 outputs the first channel selection command PC0, AND the second input terminal of the first SR latch S/R1 receives the signal IN1 from the output terminal of the first AND gate AND 1. The first input end of the second SR latch S/R2 receives the reset command Rst, the second input end of the second SR latch S/R2 is electrically connected with the output end of the second AND gate AND2, AND the first output end of the second SR latch S/R2 is electrically connected with the input end of the second inverter INV2. The first output terminal of the second SR latch S/R2 outputs the second channel selection command PC1, AND the second input terminal of the second SR latch S/R2 receives the signal IN2 from the output terminal of the second AND gate AND 2.
In the embodiment of the present disclosure, referring to fig. 8, the channel selection command generation module 301 may be understood as: of the SR latches of one outer layer (large SR latch is composed of a first AND gate AND1, a second AND gate AND2, a first inverter INV1, AND a second inverter INV 2), the SR latches of two inner layers (i.e., a first SR latch S/R1 AND a second SR latch S/R2) are included. In the initial state, PC0 and PC1 are set to 0 (low level). If the first command identification signal cmd_flag1 jumps to 1 (high level) first, the first channel selection command PC0 is 1 (high level) and the second channel selection command PC1 is 0 (low level); accordingly, if the second command identification signal cmd_flag2 first jumps to 1 (high level), the second channel selection command PC1 is 1 (high level), and the first channel selection command PC0 is 0 (low level). Also, the values of the first and second channel selection commands PC0 and PC1 are latched, and even if the first and second command identification signals cmd_flag1 and cmd_flag2 are subsequently 1 (high level), the values of the first and second channel selection commands PC0 and PC1 are not updated.
Referring to fig. 3, when the decoding path of the "first D flip-flop dff1+the first decoder dec1" is operated, the first command identification signal cmd_flag1 is generated (i.e., the first command identification signal cmd_flag1 jumps to 1), and thus, the first channel selection command PC0 is 1. Accordingly, when the decoding path of the "second D flip-flop dff2+the second decoder dec2" is operated, the second command identification signal cmd_flag2 is generated (i.e., the second command identification signal cmd_flag2 jumps to 1), and thus, the second channel selection command PC1 is 1.
Further, with continued reference to fig. 8, when the reset command Rst is 1 (high level), the first channel selection command PC0 is set to 0 (low level). When the reset command Rst is 0 (low level) and the signal IN1 (first to signal IN 2) is input 1 (high level), the first channel selection command PC0 outputs 1 (high level). In this way, the reset of the first channel selection command PC0 is achieved by the reset command Rst.
Further, with continued reference to fig. 8, for the SR latch of the outer layer, after either the first channel selection command PC0 or the second channel selection command PC1 is set to 1 (high level), it is inverted to 0 (low level), AND then enters the AND gate (first AND gate AND1 or second AND gate AND 2), so that the AND gate outputs 0 (low level), AND the latter one of the signals IN1 or IN2 is disabled (disabled).
In the disclosed embodiment, referring to fig. 9A and 9B, the first SR latch S/R1 and the second SR latch S/R2 may each be composed of two nor gates. Initially, the first channel selection command PC0 and the second channel selection command PC1 are input-free (i.e., 0), and the signals IN1 and IN2 are controlled by the first command identification signal cmd_flag1 and the second command identification signal cmd_flag2.
In some embodiments of the present disclosure, referring to fig. 10, the mode enable signal generation module 302 includes: a channel register Reg, a third inverter INV3, and a first OR gate OR1. A channel register Reg configured to store a mode value P; the mode value P is used to characterize the first transmission mode or the second transmission mode. The input end of the third inverter INV3 is connected to the channel register Reg to obtain the mode value P. A first OR gate OR1, a first input end of the first OR gate OR1 is connected with the third inverter INV3, and a second input end of the first OR gate OR1 receives the special command sp_cmd from the functional command control module 101; the special command sp_cmd is used to force the second transmission mode to be initiated.
In the embodiment of the present disclosure, referring to fig. 10, taking HBM as an example, a register of each channel of HBM may be preconfigured by a controller to configure whether to use a pseudo channel mode. The control logic inside each channel controls whether the pseudo channel mode is turned on or not based on the mode value P stored in the channel register Reg. Wherein a pseudo channel mode is turned on, i.e. "in a first transmission mode"; accordingly, the pseudo channel mode is not turned on, i.e. "in the second transmission mode".
In the embodiment of the disclosure, with continued reference to fig. 10, when the special command sp_cmd is 0, the mode enable signal En output by the first and gate OR1 is determined by the value of the mode value P; specifically, when the pseudo channel mode is turned on, the channel register Reg outputs a mode value P of 1 (high level), and the mode enable signal En of 0 (low level); when the dummy channel mode is not turned on, the channel register Reg outputs a mode value P of 0 (low level), and the mode enable signal En is 1 (high level). However, when the special command sp_cmd is 1, the mode enable signal En output from the first and gate OR1 is 1, i.e., the two sub-channels are forcibly turned on, regardless of the magnitude of the value of the mode value P, while the function command CMD is transmitted using the two sub-channels at the same time.
In some embodiments of the present disclosure, referring to fig. 11, the plurality of sub-channels includes: a first subchannel SC1 and a second subchannel SC2. The command transmission switch module 303 includes: a second OR gate OR2, a third OR gate OR3, a plurality of third AND gates AND3 AND a plurality of fourth AND gates AND4. The second OR gate OR2, a first input terminal of the second OR gate OR2 receives the mode enable signal En, and a second input terminal of the second OR gate OR2 receives the first channel selection command PC0. The third OR gate OR3, the first input terminal of the third OR gate OR3 receives the mode enable signal En, and the second input terminal of the third OR gate OR3 receives the second channel selection command PC1. The first input ends of the third AND gates AND3 are electrically connected to the output ends of the second OR gate OR2, the second input end of each third AND gate AND3 correspondingly receives a function command CMD, AND the output end of each third AND gate AND3 correspondingly connects to a data line in the first sub-channel SC 1. The first input ends of the fourth AND gates AND4 are electrically connected to the output end of the third OR gate OR3, the second input end of each fourth AND gate AND4 correspondingly receives a function command CMD, AND the output end of each fourth AND gate AND4 correspondingly connects to a data line in the second sub-channel SC2.
In the embodiment of the present disclosure, referring to fig. 11, when the pseudo channel mode is turned on, that is, when the mode enable signal En is 0 (low level), it is decided by the first channel selection command PC0 and the second channel selection command PC1 to which sub-channel the function command CMD is transmitted; specifically, when the first channel selection command PC0 is 1 (high level), the function command CMD enters the first sub-channel SC1 through the third AND gate AND 3; when the second channel selection command PC1 is 1 (high level), the function command CMD enters the second sub-channel SC2 through the fourth AND gate AND 4. However, when the dummy channel mode is not turned on, i.e., the mode enable signal En is 1 (high level), the second OR gate OR2 AND the third OR gate OR3 output 1 regardless of the values of the first channel selection command PC0 AND the second channel selection command PC1, AND thus the function command CMD passes through the third AND gate AND3 AND the fourth AND gate AND4 while simultaneously entering the first sub-channel SC1 AND the second sub-channel SC2.
In the disclosed embodiment, in conjunction with fig. 3 and 7, the decoding path of the "first D flip-flop dff1+first decoder dec1" runs on the rising edge of the clock signal CKT; further, the command identification signal generation module generates a first command identification signal cmd_flag1; further, the channel selection command generation module 301 generates a first channel selection command PC0; further, the first sub-channel SC1 may be selected to transmit the function command CMD in the first transmission mode (i.e., the dummy channel mode). Accordingly, on the falling edge of the clock signal CKT, the decoding path of the "second D flip-flop dff2+the second decoder dec2" runs; further, the command identification signal generation module generates a second command identification signal cmd_flag2; further, the channel selection command generation module 301 generates a second channel selection command PC1; further, the second sub-channel SC2 may be selected to transmit the function command CMD in the first transmission mode (i.e., the dummy channel mode).
Note that, referring to table 1, a sub-channel for transmitting a command is selected according to the value of the PC of R3 in the pseudo channel mode, which is specified in the current JEDEC standard manual. In the embodiment of the present disclosure, the sub-channel for transmitting the command does not need to be selected according to the value of the PC of R3, but may be selected according to the rising edge or the falling edge of the clock signal CKT (described with reference to the previous paragraph). Thus, in the disclosed embodiments, there is no need to set separate data (e.g., the value of the PC of R3) in the encoding command to identify the sub-channel to be selected.
It can be appreciated that the channel selection module 30 can flexibly select whether to enter the first transmission mode (i.e., the pseudo channel mode) according to various situations; and, in the first transmission mode, the channel selection module 30 may flexibly select a sub-channel for transmission. In this way, no separate data need be provided in the encoded command to identify the sub-channel to be selected, i.e. no additional data lines are occupied to identify the sub-channel for transmitting data, thereby simplifying the encoded command and the associated data lines.
In some embodiments of the present disclosure, referring to fig. 12, the command identification signal generation module 20 includes: fourth OR gate OR4. The fourth OR gate OR4 comprises a plurality of input ends, and each input end of the fourth OR gate OR4 correspondingly receives a first row subcommand; the fourth OR gate OR4 outputs a command identification signal cmd_flag1 OR cmd_flag2.
In the embodiment of the disclosure, referring to fig. 12, two fourth OR gates OR4 may be provided for receiving the first row subcommand in the row command; wherein, referring to table 1, the first row subcommand in the row command may include: subcommands RNOP, ACT1, … …, SRE1, PDX/SRX. Referring to fig. 3 and 12, the 1 st fourth OR gate OR4 may receive a first row subcommand of the row commands from an output terminal of the first decoder Dec1 and output a first command identification signal cmd_flag1; the 2 nd fourth OR gate OR4 may receive the first row subcommand of the row command from the output terminal of the second decoder Dec2 and output the second command identification signal cmd_flag2.
Accordingly, two fourth OR gates OR4 may be provided for receiving the first row subcommand in the column command, and the structure of these two fourth OR gates OR4 may be understood with reference to fig. 12. Wherein, referring to table 2, the first row subcommand in the column command may include: subcommands CNOP1, RD1, … …, WRA1, MRS1.
In the disclosed embodiment, referring to FIG. 12, the top row subcommand is active high; after any one of the fourth OR gates OR4 receives the first row subcommand with a high level, a command identification signal with a high level (i.e., a valid command identification signal) is output.
It should be noted that, in conjunction with table 1, table 2 and fig. 12, the input terminal of each fourth OR gate OR4 receives only the first row subcommand of the function subcommand sub_cmd. The first row subcommand is a function subcommand sub_cmd with the forefront time sequence in each function command CMD. Specifically, for a function command CMD including a plurality of function subcommands sub_cmd, only the first function subcommand sub_cmd in timing is the first row subcommand, for example, subcommand ACT1 in the command ACT; for a function command CMD that contains only one function subcommand Sub-CMD, the only one function subcommand Sub-CMD is the top row subcommand Sub-cmd_1, e.g., subcommand PDX/SRX in command PDX/SRX.
It will be appreciated that the command identification signal generation module 20 generates a command identification signal based on the first line subcommand of the function subcommands. In this way, no separate data need be provided in the encoded command to identify the sub-channel to be selected, i.e. no additional data lines are occupied to identify the sub-channel for transmitting data, thereby simplifying the encoded command and the associated data lines.
Fig. 13 is a schematic structural diagram of a memory according to an embodiment of the present disclosure, and as shown in fig. 13, a memory 90 includes a control circuit 80. The control circuit 80 includes the structure of the foregoing embodiment.
In some embodiments of the present disclosure, referring to fig. 13, memory 90 may be an HBM memory chip.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment. The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure.
Claims (12)
1. A control circuit, comprising:
the command decoding module is configured to receive at least one group of coded commands, decode at least one group of coded commands into at least one function subcommand, and determine corresponding function commands according to at least one function subcommand;
the command identification signal generation module is electrically connected with the command decoding module and is configured to receive and generate a command identification signal according to the first row subcommand; the first line subcommand is the function subcommand with the forefront time sequence in each function command;
the channel selection module is electrically connected with the command decoding module, the command identification signal generation module and the plurality of sub-channels and is configured to receive and select one sub-channel to transmit the function command according to the command identification signal in a first transmission mode, and transmit the function command through all the sub-channels in a second transmission mode.
2. The control circuit of claim 1, wherein the command decoding module comprises: a plurality of first D flip-flops, a plurality of second D flip-flops, a first decoder, and a second decoder;
the data input end of each first D trigger correspondingly receives one bit of data in a group of coding commands;
the first decoder comprises a plurality of input ends and a plurality of output ends, each input end of the first decoder is correspondingly connected with an in-phase output end of the first D trigger, and each output end of the first decoder correspondingly outputs one function subcommand;
the data input end of each second D trigger correspondingly receives one bit of data in a group of coding commands;
the second decoder comprises a plurality of input ends and a plurality of output ends, each input end of the second decoder is correspondingly connected with an in-phase output end of the second D trigger, and each output end of the second decoder correspondingly outputs one function subcommand.
3. The control circuit of claim 2, wherein,
the clock input ends of the plurality of the first D flip-flops all receive clock signals;
the clock input ends of the plurality of second D flip-flops all receive the clock signals after the phase inversion.
4. The control circuit of claim 2, wherein the command decoding module further comprises:
and the function command control module is electrically connected with the first decoder and the second decoder respectively and is configured to receive and determine and output the corresponding function command according to at least one function subcommand.
5. The control circuit of claim 4, wherein the control circuit comprises a logic circuit,
the function command control module is further electrically connected with the command identification signal generation module and the channel selection module respectively, and is further configured to receive and continuously receive the function subcommand according to the command identification signal until a tail line subcommand is received, and send a reset command to the channel selection module; the tail line subcommand is the function subcommand with the last time sequence in each function command.
6. The control circuit of claim 5, wherein the channel selection module comprises:
the channel selection command generation module is electrically connected with the command identification signal generation module and is configured to receive and generate a corresponding channel selection command according to the command identification signal;
A mode enable signal generation module configured to generate a mode enable signal; the value of the mode enable signal characterizes the first transmission mode or the second transmission mode;
and the command transmission switch module is electrically connected with the channel selection command generation module and the mode enabling signal generation module respectively and is configured to receive and select one sub-channel to transmit the function command according to the mode enabling signal and the channel selection command, or transmit the function command through all the sub-channels.
7. The control circuit of claim 6, wherein the control circuit comprises a logic circuit,
the channel selection command generation module is further electrically connected to the function command control module and is further configured to receive and reset a value of the channel selection command in response to the reset command.
8. The control circuit of claim 7, wherein the command identification signal comprises: a first command identification signal and a second command identification signal; the channel selection command includes: a first channel selection command and a second channel selection command; the channel selection command generation module includes: a first SR latch, a second SR latch, a first AND gate, a second AND gate, a first inverter and a second inverter;
A first input end of the first AND gate receives the first command identification signal, and a second input end of the first AND gate is electrically connected with an output end of the first inverter;
the first input end of the second AND gate receives the second command identification signal, and the second input end of the second AND gate is electrically connected with the output end of the second inverter;
a first input end of the first SR latch receives the reset command, a second input end of the first SR latch is electrically connected with an output end of the first AND gate, and a first output end of the first SR latch is electrically connected with an input end of the first inverter; the first output end of the first SR latch outputs the first channel selection command;
the first input end of the second SR latch receives the reset command, the second input end of the second SR latch is electrically connected with the output end of the second AND gate, and the first output end of the second SR latch is electrically connected with the input end of the second inverter; the first output of the second SR latch outputs the second channel select command.
9. The control circuit of claim 6, wherein the mode enable signal generation module comprises:
A channel register configured to store a mode value; the mode value is used to characterize the first transmission mode or the second transmission mode;
the input end of the third inverter is connected with the channel register to acquire the mode value;
a first or gate, a first input end of which is connected with the third inverter, and a second input end of which is used for receiving a special command by the function command control module; the special command is used to force the second transmission mode to be initiated.
10. The control circuit of claim 6, wherein a plurality of the sub-channels comprise: a first sub-channel and a second sub-channel;
the command transmission switch module includes:
a second or gate, a first input end of which receives the mode enabling signal, and a second input end of which receives a first command identification signal;
a third or gate, a first input terminal of which receives the mode enable signal, and a second input terminal of which receives a second command identification signal;
the first input ends of the third AND gates are electrically connected with the output ends of the second OR gates, the second input end of each third AND gate correspondingly receives one functional command, and the output end of each third AND gate is correspondingly connected with one data line in the first sub-channel;
And the first input ends of the fourth AND gates are electrically connected with the output end of the third OR gate, the second input end of each fourth AND gate correspondingly receives one functional command, and the output end of each fourth AND gate is correspondingly connected with one data line in the second sub-channel.
11. The control circuit according to any one of claims 1 to 10, wherein the command identification signal generation module includes: a fourth or gate;
the fourth OR gate comprises a plurality of input ends, and each input end of the fourth OR gate correspondingly receives one first-row subcommand; the fourth or gate outputs the command identification signal.
12. A memory, characterized in that the memory comprises a control circuit according to any one of claims 1 to 11.
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