CN117151011A - Clock switching system, method and device, computer equipment and storage medium - Google Patents
Clock switching system, method and device, computer equipment and storage medium Download PDFInfo
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Abstract
The invention relates to the technical field of computers and discloses a clock switching system, a method, a device, computer equipment and a storage medium, wherein the clock switching system comprises a feedback control module, a combination control module and a plurality of synchronous gating clock generation modules; the feedback control module is used for updating the output multi-path latch signal to be identical to the received multi-path switching signal when detecting that the received multi-path feedback signal is all zero; the combining control module is used for receiving the primary clock signals output by each synchronous gating clock generation module and performing OR operation to obtain target clock signals; the synchronous gating clock generation module is used for performing AND operation on the received switching signal, the latch signal and the original clock signal to obtain and output one path of primary clock signal, and is also used for performing AND operation on the received switching signal and the latch signal to obtain and output one path of feedback signal. The invention solves the problem that the complexity of the clock switching circuit is higher and higher along with the increase of the number of clock paths.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a clock switching system, a clock switching method, a clock switching device, a clock switching computer device, and a clock switching storage medium.
Background
In the development of modern technology, chips become an indispensable basic element in various fields, and have the advantages of small size, low power consumption, high performance and the like. In a chip, a clock is a key component, precise synchronous operation among all components is realized by providing a unified time reference, and the clock plays a crucial role in the chip and is the basis of the cooperative work of all functional modules in the chip. In order to save power consumption, the chip is designed to adopt a multi-clock working mode with variable frequency, a high-frequency clock is used when the high performance is required, a low-frequency clock is used when the task is simple, and the clock is turned off when the task is not working, so that the multi-channel clock switching technology is not separated. The simple clock switching can be realized through a multiplexer, but the method can not realize the dynamic switching of clocks, is easy to generate burrs, causes the logic circuit driven by the output clock to have functional errors, and further causes system breakdown. In order to solve the problem of burrs generated in the process of dynamically switching multiple clocks, a clock gating signal is generally generated by AND operation of a clock selection signal and feedback enable synchronous signals generated by other paths, the output of the clock signals of all paths is controlled, and then the clock gating signals of all paths are OR operated to obtain the finally output clock signals. However, as the number of clock paths increases, the complexity of the circuit for generating the feedback enable synchronization signal increases, and the circuit area increases rapidly, which results in a great compromise in the scalability and reusability of the circuit design.
Disclosure of Invention
In view of the above, the present invention provides a clock switching system, method, apparatus, computer device and storage medium, so as to solve the problem that the complexity of clock switching circuit is higher and higher with the increase of clock path number.
In a first aspect, the present invention provides a clock switching system comprising: the system comprises a feedback control module, a combining control module and a plurality of synchronous gating clock generation modules; the feedback control module comprises a switching signal input end, a feedback signal input end and a latch signal output end, and is used for updating the output multipath latch signals to be identical to the received multipath switching signals when detecting that the received multipath feedback signals are all zero; the combining control module comprises a primary clock signal input end and a target clock signal output end, and is used for receiving the primary clock signals output by each synchronous gating clock generation module, performing OR operation on each received primary clock signal, and taking the OR operation result as an output target clock signal; the synchronous gating clock generation module comprises a switching signal input end, a latch signal input end, an original clock signal input end, a primary clock signal output end and a feedback signal output end, each synchronous gating clock generation module is used for receiving one path of switching signals, one path of latch signals and one path of original clock signals in the plurality of paths of switching signals, one path of latch signals and one path of original clock signals, the latch signals received by each synchronous gating clock generation module are one path of signals corresponding to the received switching signals in the feedback control module, the synchronous gating clock generation module is used for performing AND operation on the received switching signals, the latch signals and the original clock signals to obtain and output one path of primary clock signals, the synchronous gating clock generation module is used for performing AND operation on the received switching signals and the latch signals to obtain and output one path of feedback signals, and the synchronous gating clock generation module is also used for performing delay triggering on the switching signals.
According to the technical means, the embodiment of the invention utilizes the independently arranged feedback control module to receive the switching signal and output the latching signal completely consistent with the switching signal, so that the latching signal and the switching signal are input into the synchronous gating clock generation module together as the switching signal of the synchronous gating clock generation module, and the purpose of switching clocks by the synchronous gating clock generation modules is achieved. In order to achieve the function of eliminating burrs, in this embodiment, feedback signals generated by all synchronous gating clock generation modules are fed back to a feedback control module, and the feedback control module synchronously updates a latch signal according to the change generated by a switching signal only when detecting that all feedback signals are zero, and combines the delay function in the synchronous gating clock generation module, because all feedback signals received by the feedback control module can be delayed to be all zero, an output latch signal can synchronously update the switching signal to be a new latch signal after the previous clock is cancelled, so that the output latch signal and the switching signal are input into the synchronous gating clock generation module together to enable a new clock, and the function of eliminating burrs is achieved.
In an alternative embodiment, the clock switching system further includes a single thermal encoding module for outputting the multiple switching signals.
According to the technical means, the single-heat coding module is adopted to expand various switching signals, so that the number of paths of the clock switching circuit is greatly expanded, and hardware support is provided.
In an alternative embodiment, the synchronous gating clock generation module comprises an and gate module, a synchronization unit and an integrated clock gating module; the AND gate module comprises the switching signal input end, the latch signal input end and a first intermediate switching signal output end, and is used for performing AND operation on the input switching signal and the latch signal to obtain and output a first intermediate switching signal; the synchronization unit comprises a first intermediate switching signal input end, a second intermediate switching signal output end, the feedback signal output end and the original clock signal input end, and is used for performing AND operation on the input first intermediate switching signal and the original clock signal to obtain and delay output the second intermediate switching signal and the feedback signal; the integrated clock gating module comprises a second intermediate switching signal input end, the original clock signal input end and the primary clock signal output end, and is used for performing AND operation on the input second intermediate switching signal and the original clock signal to obtain and output the primary clock signal.
In an alternative embodiment, the synchronization unit includes a primary positive edge triggered latch and a secondary negative edge triggered latch; the first-stage positive edge triggering latch comprises a steady-state switching signal output end, a first original clock signal input end and a first intermediate switching signal input end, and is used for triggering the first intermediate switching signal to be converted into a steady-state switching signal through the positive edge of the input original clock signal and outputting the steady-state switching signal; the second-stage negative edge trigger latch comprises a steady-state switching signal input end, a second original clock signal input end and a second intermediate switching signal output end, and is used for triggering the steady-state switching signal to be output as the second intermediate switching signal in a delay manner through the negative edge of the input original clock signal.
In an alternative embodiment, the integrated clock gating module includes a three stage negative edge triggered latch and a second AND gate module; the three-stage negative edge triggering latch comprises a third intermediate switching signal output end, a third original clock signal input end and a second intermediate switching signal input end, and is used for triggering the second intermediate switching signal to be delayed and output into the third intermediate switching signal through the negative edge of the input original clock signal; the second AND gate module comprises a third intermediate switching signal input end, a fourth original clock signal input end and the primary clock signal output end, and is used for performing AND operation on the input original clock signal and the third intermediate switching signal to obtain and output the primary clock signal.
In a second aspect, the present invention provides a computer device comprising a crystal oscillator, a phase locked loop, a frequency divider, one or more processors, a memory, and a clock switching system; the crystal oscillator is in communication connection with the phase-locked loop, the phase-locked loop is in communication connection with the frequency divider, a plurality of output channels of the frequency divider are sequentially connected with original clock signal input ends of synchronous gating clock generation modules in the clock switching system, a target clock signal output end of the clock switching system is connected to the processor, and the processor is in communication connection with the memory.
In an alternative embodiment, the processor is communicatively connected to a single thermal encoding module in the clock switching system for controlling the single thermal encoding module to output different switching signals.
In a third aspect, the present invention provides a clock switching method, where the method is applied to a feedback control module, and the method includes: receiving a multi-path switching signal and outputting a multi-path latch signal which is identical to the multi-path switching signal; receiving multiple paths of feedback signals; when the multi-path switching signal changes, detecting whether the numerical value of the multi-path feedback signal is all zero; and when the values of the multipath feedback signals are all zero, the multipath switching signals which are output are regulated to be identical to the multipath switching signals after the change.
In a fourth aspect, the present invention provides a clock switching apparatus, the apparatus being applied to a feedback control module, the apparatus comprising: the signal initialization module is used for receiving the multipath switching signals and outputting multipath latch signals which are identical to the multipath switching signals; the feedback receiving module is used for receiving the multipath feedback signals; the feedback detection module is used for detecting whether the numerical value of the multipath feedback signal is all zero or not when the multipath switching signal changes; and the output adjusting module is used for adjusting the output multi-path switching signal and the changed multi-path switching signal to be identical signals when the numerical value of the multi-path feedback signal is zero.
In a fifth aspect, the present invention provides a computer readable storage medium having stored thereon computer instructions for causing a computer to perform the method of the third aspect.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a related art clock switching circuit;
FIG. 2 is a timing diagram of a clock of the related art;
FIG. 3 is a schematic diagram of another related art clock switching circuit;
FIG. 4 is another clock timing diagram of the related art;
FIG. 5 is a schematic diagram of a related art clock switching circuit;
FIG. 6 is a schematic diagram of a clock switching system according to an embodiment of the invention;
FIG. 7 is another schematic diagram of a clock switching system according to an embodiment of the invention;
FIG. 8 is a schematic diagram of yet another configuration of a clock switching system according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of yet another configuration of a clock switching system according to an embodiment of the present invention;
FIG. 10 is a flow chart of a clock switching method according to an embodiment of the invention;
FIG. 11 is a schematic diagram of a clock switching apparatus according to an embodiment of the present invention;
fig. 12 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the related art, the CLOCK switching circuit generates a glitch when the CLOCK is switched if it is not processed, for example, as shown in fig. 1, in which the switching signal SELECT may be input with 0 or 1, the circuit includes two CLOCKs CLK0 and CLK1, respectively, and the output CLOCK is OUT CLOCK. As shown in fig. 2, when SELECT is 0, CLK1 and SELECT are anded, CLK1 is inactive, SELECT is anded with CLK0 through the not gate to 1, so CLK0 is active, CLK0 and SELECT are anded, the high level position is reserved, so OUT CLOCK outputs CLK0, when SELECT is switched from 0 to 1, it is assumed that the timing of SELECT switch is exactly half of the high level output of CLK0, OUT CLOCK outputs half of the high level of CLK0, and then CLK1 is output instead at the first rising edge of CLK1, so that glitches occur, resulting in unstable CLOCK switching.
To solve this problem, as shown in fig. 3, the clock switching circuit widely used in the related art takes two-way clock switching as an example, wherein clk_sel_0 and clk_sel_1 are switching signals, wherein only one of clk_sel_0 and clk_sel_1 is 1, the other is 0, and cannot be 1 or 0 at the same time, and as the number of ways of the clock switching circuit is more than two, only one way of switching signal is 1, and the other ways are 0. The sync_0 and the sync_1 are feedback signals output by two paths of clock circuits respectively, wherein each path of input is only input with a switching signal and feedback signals of other paths, and is not input with own feedback signals, for example, the first path is only input with the switching signal clk_sel_0 and the feedback signal sync_1 of the other path, and is not input with own feedback signal sync_0. Wherein the first path clock is clkin_0 and the second path clock is clkin_1. Wherein the synchronization unit acts as a delay for asserting the signals en_0 and en_1 output by the preceding and gates on the falling edge of the clock.
The operation of this circuit is as shown in fig. 4, assuming that clk_sel_0 is 1 and clk_sel_1 is 0 in the initial state, the result of the logic operation of clk_sel_1 and sync_0 of the second and gate is still 0, so that clkin_1 is deactivated. In addition, the second path switching signal clk_sel_1 is also output as 0 through the following synchronization unit, and the output 0 passes through the not gate to obtain sync_1 as 1, so that both the sync_1 and the clk_sel_0 input in the first path are 1, the output en_0 is 1, the en_0 is output as 1 through the synchronization unit, and because the output of the synchronization unit of the first path is 1, the 1 output by the synchronization unit of the first path and the clock clkin_0 need to pass through the and gate, so that the first path clock clkout_0 and the input clock clkin_0 finally output are consistent, and the first path clock clkin_0 is valid. Meanwhile, the 1 output by the first path of synchronous unit is subjected to NOT gate to obtain sync_0 as 0, which accords with the fact that the second path of clock clkin_1 is invalid, so that the second path of finally output clock clkout_1 is kept as 0. Finally, clkout_0 and clkout_1 are ored to obtain the final output clk_out of the whole circuit, and clkout_0=clkin_0 because clkout_1 is continuously 0, so that the result of the ored operation is clkin_0.
The above process is a working state before clock switching, when the clock switching is required, the switching signal clk_sel_0 becomes 0 and clk_sel_1 becomes 1, the clock clkin_0 of the first path is now valid, the effect of the synchronization unit is that the falling edge trigger, that is, the first falling edge of the current clock triggers the change of the switching signal, and the old switching signal is also pressed before the falling edge. Thus, when the switching signal clk_sel_0 changes from 1 to 0 (at the same time, clk_sel_1 changes from 0 to 1), as shown in fig. 4, clkin_0 has not yet reached the first falling edge, so this change is not validated temporarily, the clock clk_out or clkin_0 output by the whole circuit is still clkin_0, and when clkin_0 input to the synchronizing unit in the first path reaches one falling edge, the change of the switching signal is validated, so the synchronizing unit outputs clk_sel_0 and sync_1 and the operation result, because clk_sel_0 has changed to 0, the first path synchronizing unit outputs 0, the first path synchronizing unit and clkin_0 continue the and operation, so clkout_0 has changed to 0, and the first path clock fails.
After clkout_0 goes to 0, clkout_1 does not go to clkin_1 immediately either, which is the effect of the second path synchronization unit. Since the sync_0 is changed to 1 through the not gate when the first path synchronizing unit outputs 0, en_1 obtained by performing the and operation of the sync_0 and clk_sel_1 input to the second path is also changed to 1. However, since the synchronization unit of the second path is a falling edge trigger, the signal output by the synchronization unit has not yet become 1 together with en_1. Referring to fig. 4, the second path clock clkin_1 is not triggered by the synchronization unit before the first falling edge passes, so in fig. 4, clk_out is continuously output as 0 at one end and is not immediately switched to clkin_1, when the first falling edge of clkin_1 triggers the second path synchronization unit, the signal output by the synchronization unit is consistent with en_1 and also becomes 1, when the output of the second path synchronization unit is 1, the output 1 and clkin_1 pass through an and gate, clkout_1=clkin_1, and finally clkout_0 and clkout_1 perform an or operation to obtain the final output clkout of the whole circuit, because clkout_1 becomes clkin_1 and clkout_0 becomes 0, the or operation result is clkin_1, and thus the second path clock is valid. Through the scheme, the old clock is canceled at the first falling edge of the old clock through the falling edge delay function of the synchronous unit, the new clock is regenerated at the first falling edge of the new clock, and clock switching is realized and burrs generated by clock switching are removed.
However, this type of scheme has a serious problem in that the circuit becomes very complicated when the number of clocks to be switched is very large. As shown in fig. 5, it is assumed that n clocks are provided, each of which inputs a very large number of feedback signals, and the lines of the feedback signals sync_0 to sync_n are very large, so as the number of clock lines increases, the complexity of the feedback signal generating circuit is higher and higher, the circuit area is also increased rapidly, which results in greatly reduced expandability and reusability of the circuit design, and reduces the design efficiency of the clock multiple selection burr-free dynamic switching circuit.
In order to solve the above problems, the embodiment of the present invention provides a new clock switching scheme, which is specifically as follows.
According to an embodiment of the present invention, there is provided a clock switching system, as shown in fig. 6. The clock switching system provided by the embodiment of the invention comprises the following components: the system comprises a feedback control module, a combining control module and a plurality of synchronous gating clock generation modules.
The feedback control module comprises a switching signal input end, a feedback signal input end and a latch signal output end, and is used for updating the output multipath latch signals to be identical to the received multipath switching signals when detecting that the received multipath feedback signals are all zero;
The combining control module comprises a primary clock signal input end and a target clock signal output end, and is used for receiving the primary clock signals output by each synchronous gating clock generation module, performing OR operation on each received primary clock signal, and taking the OR operation result as an output target clock signal;
the synchronous gating clock generation module comprises a switching signal input end, a latch signal input end, an original clock signal input end, a primary clock signal output end and a feedback signal output end, each synchronous gating clock generation module is used for receiving one path of switching signals, one path of latch signals and one path of original clock signals in the plurality of paths of switching signals, one path of latch signals and one path of original clock signals, the latch signals received by each synchronous gating clock generation module are one path of signals corresponding to the received switching signals in the feedback control module, the synchronous gating clock generation module is used for performing AND operation on the received switching signals, the latch signals and the original clock signals to obtain and output one path of primary clock signals, the synchronous gating clock generation module is used for performing AND operation on the received switching signals and the latch signals to obtain and output one path of feedback signals, and the synchronous gating clock generation module is also used for performing delay triggering on the switching signals.
Specifically, as shown in fig. 6, in the clock switching system provided by the embodiment of the present application, a plurality of synchronous gating clock generating modules are deployed first, each synchronous gating clock generating module is responsible for one path of original clock signal, and each synchronous gating clock generating module has a delay triggering function, that is, when a switching signal is changed, the change delay of the switching signal is enabled to be effective, that is, the falling edge of the clock is enabled to be effective instead of the rising edge. Each synchronous gating clock generation module is also responsible for performing AND operation on the switching signal, the latching signal and the original clock signal which are input in the current path, and finally outputting the clock signal in the current path. And the feedback signal is the result of the AND operation of the switching signal and the latch signal.
In this embodiment, a feedback control module is further separately disposed, and the essential function of the feedback control module is to directly input the input switching signal as a latch signal, and then input the latch signal and the switching signal into each synchronous gating clock generation module together, where the latch signal can be analogically the feedback signal in the related art, and the main difference is that the related art directly inputs the feedback signals of other paths into the current path, and the feedback signal in the present application is only used as a judgment basis for judging when the latch signal changes along with the change of the switching signal, and each synchronous gating clock generation module only needs to input one path of latch signal, and the input path of latch signal and the input path of switching signal have a corresponding relationship with each other, and does not need to input multiple paths of feedback signals to the synchronous gating clock generation module, thereby significantly reducing the complexity of the circuit. It should be noted that, when the switching signal is changed, the latch signal cannot be changed immediately, and all the input feedback signals must be detected to be all zero, so that the feedback control module changes the latch signal in a one-to-one correspondence manner according to the switching signal.
In fig. 6, symbols clk_sel_0 to clk_sel_n represent switching signals, and only one position 1 and the other position 0 in the n-bit signals are used for switching signals, so that the switching signals are changed first; the symbols clk_sw_0-clk_sw_n represent n paths of latch signals output by the feedback control module, and the symbols clkin_0-clkin_n represent n paths of input different original clock signals; clk_en_sync_0 to clk_en_sync_n represent n feedback signals to be output; clkout_0 to clkout_n represent primary clock signals which are respectively output by each synchronous gating clock module after switching, and clkout represents the result obtained by OR operation of n primary clock signals by the combining control module, namely a target clock signal finally output by the whole system.
Based on the above circuit structure, in order to facilitate understanding of the scheme, it is assumed that there are only two original clock signals, and the clock switching principle of the present application is illustrated below:
assuming that the first path of switching signal clk_sel_0 is 1 and the second path of switching signal clk_sel_1 is 0 in the initial state, the second path of clock clkin_1 is inactive because the result of the operation is 0 if there is only 0 in the AND operation. Since clk_sel_0 is 1, both clk_en_sync_0 and clk_en_sync_1 are 0 in the initial state that the feedback control module just started, clk_sw_0=clk_sel_0 is also 1, and clk_sw_1=clk_sel_1 is 0.
Looking back at the synchronous gated clock generation module, because clk_sel_0 and clk_sw_0 of the first path are both 1, clk_sel_0, clk_sw_0, and clkin_0 are ANDed, resulting in clkin_0. Meanwhile, clk_sel_0 and clk_sw_0 are both 1, and the result of the operation is 1, so the first path of feedback signal clk_en_sync_0 is changed to 1, and the feedback signal received by the feedback control module is 10.
And then looking at the combination control module, because the clock output by the first path of synchronous gating clock generation module is clkin_0, the clock output by the second path of synchronous gating clock generation module is invalid, namely, 0 is kept. The two are ored, and 1 is only needed, so the final output target clock signal clkout=clkin_0.
When the switching signal changes, that is, the first path of switching signal clk_sel_0 changes to 0, and the second path of switching signal clk_sel_1 changes to 1, although clk_sel_0 changes to 0 from 1, the synchronous gating clock generation module has a function of delay triggering (falling edge triggering), so 0 calculated by clk_sel_0 and clk_sw_0 does not change clk_en_sync_0 yet, clk_en_sync_0 is still 1, so the feedback signal received by the feedback control module is still 10 and is not in an all-zero state, when the switching signal changes, the feedback control module cannot change the latch signal to be the same as the switching signal, the current latch signal needs to be kept, and clock switching is avoided in the process of clk in_0 high level. When clkin_0 reaches the first falling edge, the last high clock indicating clkin_0 is completed, thereby triggering clken_sync_0 to change from 1 to 0, disabling the first path clock. At the same time, the feedback signal received by the feedback control module becomes 00 and is in an all-zero state, and the feedback control module adjusts the output clk_sw_0 and clk_sw_1 to be identical to clk_sel_0 and clk_sel_1, namely, clk_sw_0=0 and clk_sw_1=1.
Thereafter, the and operation of clk_sel_1 and clk_sw_1 becomes 1, so the second path clock clkin_1 starts to be enabled, but clkin_1 is not yet immediately enabled because the function of the synchronous gating clock generation module is to wait until the first falling edge of clkin_1 to trigger the and operation result of clk_sel_1 and clk_sw_1 equal to 1, and the and operation result of clk_sel_1 and clk_sw_1 is still old 0 before the first falling edge of clkin_1 is not reached. Thereafter, when the first falling edge of clkin_1 is reached, the result of the addition of clk_sel_1 and clk_sw_1 becomes 1, and the addition of three of clk_sel_1, clk_sw_1 and clkin_1 is equal to clkin_1, thereby letting clkin_1 be effective, i.e., clkout_1=clkin_1.
Finally, clkout_1 and clkout_0 are subjected to OR operation to obtain a switched clock signal clkin_1.
Through the above process, the clock burr-free switching can be realized, namely, the effect is the same as that of fig. 4. Meanwhile, the embodiment of the invention avoids that feedback signals of each path are input into other paths through the circuit improvement of the feedback control module, obviously reduces the complexity of the circuit and improves the development efficiency of the circuit board on the premise of ensuring the burr-free switching of clocks.
As shown in fig. 7, in some alternative implementations, the clock switching system provided by the embodiments of the present invention further includes a single thermal encoding module, where the single thermal encoding module is configured to output the multiple switching signals.
Specifically, the one-hot encoding technique is also known as one-bit efficient encoding, which uses an N-bit status register to encode N states, each with its own register bit, and at any time, only one of the bits is valid. According to the embodiment, the function circuit is automatically instantiated and signal interconnection among modules is automatically completed according to macro parameter definition (clock path number), and then a user issues a clock selection configuration parameter sel_cfg and transmits the configuration parameter sel_cfg to a single-heat coding module; the single-heat coding module receives the user configuration parameter sel_cfg, uses the N-bit state register to code N states, each state has independent register bits, only has one bit to be effective at any time, and sends the coding output result to the feedback control module and the synchronization and gating clock generation module, thereby obviously improving the coding efficiency and the output efficiency of the switching signal, avoiding programming a large number of codes for changing the switching signal and adjusting the complexity of changing the switching signal.
As shown in fig. 8, in some alternative embodiments, the synchronous gating clock generation module includes an and gate module, a synchronization unit, and an integrated clock gating module;
the AND gate module comprises the switching signal input end, the latch signal input end and a first intermediate switching signal output end, and is used for performing AND operation on the input switching signal and the latch signal to obtain and output a first intermediate switching signal;
The synchronization unit comprises a first intermediate switching signal input end, a second intermediate switching signal output end, the feedback signal output end and the original clock signal input end, and is used for performing AND operation on the input first intermediate switching signal and the original clock signal to obtain and delay output the second intermediate switching signal and the feedback signal;
the integrated clock gating module comprises a second intermediate switching signal input end, an original clock signal input end and a primary clock signal output end, and is used for performing AND operation on the input second intermediate switching signal and the original clock signal to obtain and output the primary clock signal.
Specifically, the synchronous gating clock generation module provided by the embodiment of the invention mainly includes an and gate module, a synchronization unit and an integrated clock gating module, taking the first path of synchronous gating clock generation module as an example, where the and gate module is used to perform an and operation on the switching signal clk_sel_0 and the latch signal clk_sw_0, so as to obtain a first intermediate switching signal en_0. The first intermediate switching signal is only 1 when both the switching signal and the latch signal are 1. And then the first intermediate switching signal en_0 and the original clock signal clkin_0 enter a synchronous unit, and the switching signal after the change is triggered and validated in the synchronous unit through the falling edge delay of the clock. The specific principle of the synchronization unit is described with reference to the foregoing related art, and will not be described herein. The signal output by the synchronization unit is divided into two parts, and one part is output as a feedback signal clk_en_sync_0; the other part is to output a second intermediate switching signal, which is used for being input to the integrated clock gating module to perform an AND operation with the original clock signal clkin_0, so as to output a final primary clock signal clkout_0. It should be noted that, in this embodiment, since the feedback signal performs the detection and determination function, the feedback signal needs to be input into the feedback control module to detect whether the feedback signal is all zero, instead of directly using the inverse of the feedback signal to enable or disable other synchronous gating clock generation modules, in this embodiment, no "not gate" is provided in the line outputting the feedback signal, which is a key difference compared with the related art, and it is necessary to ensure that the levels of the output feedback signal clk_en_sync_0 and the switching signal clk_sel_0 are consistent, so that the function of adjusting the latch signal by the feedback control module can be realized.
As shown in fig. 9, in some alternative embodiments, the synchronization unit provided by the real-time example of the present invention includes: a primary positive edge trigger latch and a secondary negative edge trigger latch;
the first-stage positive edge triggering latch comprises a steady-state switching signal output end, an original clock signal input end and a first intermediate switching signal input end, and is used for triggering the first intermediate switching signal to be converted into a steady-state switching signal through the positive edge of the input original clock signal and outputting the steady-state switching signal;
the second-stage negative edge trigger latch comprises a steady-state switching signal input end, an original clock signal input end and a second intermediate switching signal output end, and is used for triggering the steady-state switching signal to be output as the second intermediate switching signal in a delayed mode through the negative edge of the input original clock signal.
Specifically, in the embodiment of the invention, the synchronization unit is composed of two stages of trigger latches, wherein the two stages of negative edge trigger latches are negative edge trigger, so that the function of delay and effectiveness of switching signals is realized. The principle description of the two-stage negative edge trigger latch is the same as that of the negative edge delay trigger of the related art, and is not repeated here. In addition, this embodiment further sets a positive edge triggered one-stage positive edge triggered latch, and since in the practical application scenario, the frequencies of the two clocks are generally not related, and asynchronous behavior may come from the switching signal, a positive edge triggered latch with an active rising edge is inserted into each clock source selection path to avoid metastable states. The selection signal is registered by the first-stage positive edge trigger latch, so that the metastable state caused by the asynchronous switching signal is reduced, meanwhile, the second-stage negative edge trigger latch is matched with the second-stage negative edge trigger latch, the second-stage negative edge trigger latch receives the steady-state switching signal output by the first-stage positive edge trigger latch, the switching signal is delayed to take effect, the clock switching is carried out at the clock low level, and the probability of burr generation is reduced.
As shown in fig. 9, in some alternative embodiments, the integrated clock gating module includes a three-stage negative edge triggered latch and a second and gate module;
the three-stage negative edge triggering latch comprises a third intermediate switching signal output end, a third original clock signal input end and a second intermediate switching signal input end, and is used for triggering the second intermediate switching signal to be delayed and output into the third intermediate switching signal through the negative edge of the input original clock signal;
the second AND gate module comprises a third intermediate switching signal input end, a fourth original clock signal input end and the primary clock signal output end, and is used for performing AND operation on the input original clock signal and the third intermediate switching signal to obtain and output the primary clock signal.
Specifically, the embodiment of the invention utilizes the integrated clock gating module to realize the function of an AND gate, and performs AND operation on the second intermediate switching signal and the original clock signal output by the synchronous unit, thereby obtaining the primary clock signal. In the integrated clock gating module, a three-level negative edge trigger latch is further arranged in front of the second AND gate module, and in other circuits, the enabling signal and the clock signal enter the three-level negative edge trigger latch to control the on-off of the clock signal. In this embodiment, the falling edge trigger mechanism of the three-stage negative edge trigger latch further aligns the second intermediate switching signal with the original clock signal in time sequence, so as to output a more accurate third intermediate switching signal to the second and gate module at the back, and further improve the accuracy of the primary clock signal at the back.
In accordance with an embodiment of the present invention, there is also provided a clock switching method embodiment, it being noted that the steps shown in the flowchart of the figures may be performed in a computer system, such as a set of computer executable instructions, and, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in an order other than that shown or described herein.
In this embodiment, a clock switching method is provided, which may be used in the feedback control module described above, and fig. 10 is a flowchart of the clock switching method according to an embodiment of the present invention, where the flowchart includes the following steps:
step S101, receiving a multi-path switching signal and outputting a multi-path latch signal which is identical to the multi-path switching signal.
Step S102, receiving multiple feedback signals.
Step S103, detecting whether the value of the multiple feedback signals is all zero when the multiple switching signals are changed.
And step S104, when the value of the multipath feedback signal is zero, the output multipath switching signal and the changed multipath switching signal are adjusted to be identical signals.
Specifically, the feedback control module provided by the embodiment of the invention can realize the control logic of a pure hardware circuit through an FPGA, and can also realize the control logic of an instruction code through a chip of an X86 architecture. When the feedback control module adopts the X86 architecture, the switching signal is changed to the latch signal by arranging the instruction in the feedback control module, so that the clock switching is realized. The method for detecting whether the numerical value of the multi-path feedback signal is all zero is executed through an instruction, and when the numerical value of the multi-path feedback signal is detected to be all zero, the output multi-path switching signal and the changed multi-path switching signal are adjusted to be identical signals. For a detailed principle description of the method, reference may be made to the above system embodiments, which are not repeated here. The feedback control module provided by the embodiment of the invention further executes a corresponding detection method and a signal updating method, so that the complexity of a circuit structure is reduced.
In some other embodiments, when the FPGA implements the detection function of the feedback control module by means of pure hardware, the or gate may be used to perform an or operation on the multiple switching signals, then the or operation is negated, and then the and operation is performed with the negated result and each switching signal. That is, only when the multi-path switching signals are all zero, the result of the OR operation is 0, the result of the OR operation is 1,1 after the NOT gate and each path of switching signals are subjected to AND operation, the output gate locking signal can be updated to the current switching signal, otherwise, the output gate locking signal is not updated.
In this embodiment, a clock switching device is further provided, and the device is used to implement the foregoing embodiments and preferred embodiments, and will not be described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
The present embodiment provides a clock switching apparatus, which is applied to a feedback control module, as shown in fig. 11, and includes:
the signal initialization module 1101 is configured to receive the multiple switching signals and output multiple latch signals identical to the multiple switching signals. For details, refer to the related description of step S101 in the above method embodiment, and no further description is given here.
The feedback receiving module 1102 is configured to receive multiple feedback signals. For details, refer to the related description of step S102 in the above method embodiment, and no further description is given here.
The feedback detection module 1103 is configured to detect whether the value of the multiple feedback signals is all zero when the multiple switching signals change. For details, see the description of step S103 in the above method embodiment, and the details are not repeated here.
And the output adjustment module 1104 is configured to adjust the output multiple switching signals and the changed multiple switching signals to be identical signals when the values of the multiple feedback signals are all zero. For details, refer to the related description of step S104 in the above method embodiment, and no further description is given here.
Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.
The clock switching apparatus in this embodiment is presented in the form of functional units, where the units refer to ASIC (Application Specific Integrated Circuit ) circuits, processors and memories executing one or more software or fixed programs, and/or other devices that can provide the above described functionality.
An embodiment of the present invention further provides a computer device, please refer to fig. 12, fig. 12 is a schematic structural diagram of a computer device provided in an alternative embodiment of the present invention, and as shown in fig. 12, the computer device includes: one or more processors 10, memory 20, crystal oscillator 40, phase locked loop 50, frequency divider 60, and clock switching system 70 provided by the foregoing embodiments, as well as interfaces for connecting the components, including high speed interfaces and low speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the computer device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 12.
The crystal oscillator 40 is in communication connection with the phase-locked loop 50, the phase-locked loop 50 is in communication connection with the frequency divider 60, a plurality of output paths of the frequency divider 60 are sequentially connected with original clock signal input ends of respective synchronous gating clock generation modules in the clock switching system 70, a target clock signal output end of the clock switching system is connected to the processor 10, and the processor 10 is in communication connection with the memory 20. In addition, the processor is also in communication connection with the single thermal coding module in the clock switching system, and besides the single thermal coding module is controlled by the processor 10 of the current computer equipment, the single thermal coding module can be controlled to output different switching signals.
The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.
Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform the methods shown in implementing the above embodiments.
The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.
The computer device also includes a communication interface 30 for the computer device to communicate with other devices or communication networks.
The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.
Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.
Claims (10)
1. A clock switching system, the clock switching system comprising: the system comprises a feedback control module, a combining control module and a plurality of synchronous gating clock generation modules;
the feedback control module comprises a switching signal input end, a feedback signal input end and a latch signal output end, and is used for updating the output multipath latch signals to be identical to the received multipath switching signals when detecting that the received multipath feedback signals are all zero;
the combining control module comprises a primary clock signal input end and a target clock signal output end, and is used for receiving the primary clock signals output by each synchronous gating clock generation module, performing OR operation on each received primary clock signal, and taking the OR operation result as an output target clock signal;
the synchronous gating clock generation module comprises a switching signal input end, a latch signal input end, an original clock signal input end, a primary clock signal output end and a feedback signal output end, each synchronous gating clock generation module is used for receiving one path of switching signals, one path of latch signals and one path of original clock signals in the plurality of paths of switching signals, one path of latch signals and one path of original clock signals, the latch signals received by each synchronous gating clock generation module are one path of signals corresponding to the received switching signals in the feedback control module, the synchronous gating clock generation module is used for performing AND operation on the received switching signals, the latch signals and the original clock signals to obtain and output one path of primary clock signals, the synchronous gating clock generation module is used for performing AND operation on the received switching signals and the latch signals to obtain and output one path of feedback signals, and the synchronous gating clock generation module is also used for performing delay triggering on the switching signals.
2. The clock switching system of claim 1, further comprising a single thermal encoding module configured to output the multiple switching signals.
3. The clock switching system of claim 1, wherein the synchronous gating clock generation module comprises an and gate module, a synchronization unit, and an integrated clock gating module;
the AND gate module comprises the switching signal input end, the latch signal input end and a first intermediate switching signal output end, and is used for performing AND operation on the input switching signal and the latch signal to obtain and output a first intermediate switching signal;
the synchronization unit comprises a first intermediate switching signal input end, a second intermediate switching signal output end, the feedback signal output end and the original clock signal input end, and is used for performing AND operation on the input first intermediate switching signal and the original clock signal to obtain and delay output the second intermediate switching signal and the feedback signal;
the integrated clock gating module comprises a second intermediate switching signal input end, the original clock signal input end and the primary clock signal output end, and is used for performing AND operation on the input second intermediate switching signal and the original clock signal to obtain and output the primary clock signal.
4. The clock switching system of claim 3, wherein the synchronization unit comprises a primary positive edge triggered latch and a secondary negative edge triggered latch;
the first-stage positive edge triggering latch comprises a steady-state switching signal output end, a first original clock signal input end and a first intermediate switching signal input end, and is used for triggering the first intermediate switching signal to be converted into a steady-state switching signal through the positive edge of the input original clock signal and outputting the steady-state switching signal;
the second-stage negative edge trigger latch comprises a steady-state switching signal input end, a second original clock signal input end and a second intermediate switching signal output end, and is used for triggering the steady-state switching signal to be output as the second intermediate switching signal in a delay manner through the negative edge of the input original clock signal.
5. The clock switching system of claim 3, wherein the integrated clock gating module comprises a three stage negative edge triggered latch and a second and gate module;
the three-stage negative edge triggering latch comprises a third intermediate switching signal output end, a third original clock signal input end and a second intermediate switching signal input end, and is used for triggering the second intermediate switching signal to be delayed and output into the third intermediate switching signal through the negative edge of the input original clock signal;
The second AND gate module comprises a third intermediate switching signal input end, a fourth original clock signal input end and the primary clock signal output end, and is used for performing AND operation on the input original clock signal and the third intermediate switching signal to obtain and output the primary clock signal.
6. A computer device comprising a crystal oscillator, a phase locked loop, a frequency divider, one or more processors, a memory, and a clock switching system as provided in any one of claims 1-5;
the crystal oscillator is in communication connection with the phase-locked loop, the phase-locked loop is in communication connection with the frequency divider, a plurality of output channels of the frequency divider are sequentially connected with original clock signal input ends of synchronous gating clock generation modules in the clock switching system, a target clock signal output end of the clock switching system is connected to the processor, and the processor is in communication connection with the memory.
7. The computer device of claim 6, wherein the processor is communicatively coupled to a single thermal encoding module in the clock switching system for controlling the single thermal encoding module to output different switching signals.
8. A clock switching method, wherein the method is applied to a feedback control module, the method comprising:
receiving a multi-path switching signal and outputting a multi-path latch signal which is identical to the multi-path switching signal;
receiving multiple paths of feedback signals;
when the multi-path switching signal changes, detecting whether the numerical value of the multi-path feedback signal is all zero;
and when the values of the multipath feedback signals are all zero, the multipath switching signals which are output are regulated to be identical to the multipath switching signals after the change.
9. A clock switching apparatus, the apparatus being applied to a feedback control module, the apparatus comprising:
the signal initialization module is used for receiving the multipath switching signals and outputting multipath latch signals which are identical to the multipath switching signals;
the feedback receiving module is used for receiving the multipath feedback signals;
the feedback detection module is used for detecting whether the numerical value of the multipath feedback signal is all zero or not when the multipath switching signal changes;
and the output adjusting module is used for adjusting the output multi-path switching signal and the changed multi-path switching signal to be identical signals when the numerical value of the multi-path feedback signal is zero.
10. A computer readable storage medium having stored thereon computer instructions for causing a computer to perform the method of claim 8.
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