CN117151001A

CN117151001A - Routing path processing method based on time sequence driving

Info

Publication number: CN117151001A
Application number: CN202311114684.3A
Authority: CN
Inventors: 邵中尉; 张吉锋; 周思远
Original assignee: Shanghai Sierxin Technology Co ltd
Current assignee: Shanghai Sierxin Technology Co ltd
Priority date: 2023-08-30
Filing date: 2023-08-30
Publication date: 2023-12-01

Abstract

The application relates to the field of route path processing, in particular to a route path processing method based on time sequence driving, which comprises the following steps: s1, performing time sequence driving segmentation processing by using input data to obtain input data time sequence driving segmentation data; s2, using the input data time sequence driving segmentation data to establish a time sequence driving path to complete time sequence driving route processing, properly cutting a path book with large establishment time margin, avoiding cutting a path with small establishment time, ensuring the time sequence requirement of the time sequence path to the maximum extent after considering the time sequence requirement, and improving the system performance by considering the time sequence to consider the weight of the cut path.

Description

Routing path processing method based on time sequence driving

Technical Field

The application relates to the technical field of integrated circuits, in particular to a routing path processing method based on time sequence driving.

Background

With the increasing scale of the user chip design, in the prototype verification process, a single FPGA is far more difficult to accommodate the scale of the user design, and for large user designs, a verification system composed of hundreds of large-capacity FPGAs is often required to cooperatively verify the user design. The user design must therefore be split into different parts, each downloaded to run in a different FPGA, to verify the user design.

In a verification system composed of a plurality of FPGAs, the FPGAs are connected through interconnecting lines (physical connecting lines). However, the larger the signal delay on the interconnect, the smaller the setup time margin in order to meet the hold time requirement.

In the current technology, the segmentation process mainly focuses on the weight of the logic signals cut in the user design, but ignores the time sequence requirement, so that the establishment time of a plurality of time sequence paths crossing the FPGA is smaller than a set value, and the time sequence logic cannot guarantee to work correctly; and in the process of routing (routing) after segmentation, the selection of the routing path mainly considers the maximum distance and the total jump distance of all logic signals (net) for jumping the FPGA in routing, and does not consider the time sequence requirement of the time sequence path, so that a plurality of time sequence paths cannot meet the set-up time. As can be seen, the current technology causes that the verification system cannot meet the specified time sequence requirement, so that the processing efficiency and accuracy of the verification system are low.

Disclosure of Invention

Aiming at the defects of the prior art, the application provides a routing path processing method based on time sequence driving, which establishes a reasonable routing path through multiple iterations and improves the processing efficiency and accuracy.

In order to achieve the above object, the present application provides a routing path processing method based on time sequence driving, including:

s1, performing time sequence driving segmentation processing by using input data to obtain input data time sequence driving segmentation data;

s2, using the input data time sequence driving dividing data to establish a time sequence driving path to finish time sequence driving route processing.

Preferably, the performing the time-series driving dividing process by using the input data to obtain the time-series driving dividing data of the input data includes:

s1-1, establishing an input data hypergraph by utilizing a connection endpoint corresponding to the input data;

s1-2, acquiring a delay critical path of the input data;

s1-3, obtaining a corresponding time allowance according to the delay critical path of the input data, and carrying out weight updating processing to obtain delay critical path updating data of the input data;

s1-4, carrying out distribution processing on a path corresponding to the delay critical path update data and an input data hypergraph by utilizing the delay critical path update data to obtain a path distribution processing result;

s1-5, carrying out weight iterative update processing by utilizing the path allocation processing result to obtain iterative update weight data;

s1-6, updating the delay critical path of the input data by utilizing the iterative updating weight data to obtain a path updating processing result;

s1-7, judging whether the path updating processing result meets the screening requirement, if so, outputting the current path updating processing result as input data time sequence driving segmentation data, otherwise, returning to S1-5;

wherein, the screening requirement is a fixed cycle number.

Further, the calculation formula of the delay critical path update data of the input data is as follows, wherein the calculation formula is that the corresponding time allowance is obtained according to the delay critical path of the input data, and the weight update processing is carried out to obtain the delay critical path update data of the input data:

wherein wt_0 is a weight update result, tsetup is an establishment time margin, dmax is a maximum value of delay in K time sequence paths, W is an edge weight of an original time sequence path, and α and r are parameters larger than 1.

Further, performing allocation processing on the paths corresponding to the delay critical path update data and the input data hypergraph to obtain a path allocation processing result includes:

s1-4-1, acquiring nodes corresponding to the input data hypergraph;

s1-4-2, distributing corresponding paths of delay critical path update data according to nodes corresponding to the input data hypergraph;

s1-4-3, judging whether the node corresponding to the input data hypergraph has a wheel space or not, if so, returning to S1-4-2, otherwise, completing the allocation processing to obtain a path allocation processing result;

and the wheel space is the corresponding path of the input data hypergraph corresponding node, and the corresponding delay critical path updating data does not exist.

Further, the calculation formula for obtaining the iterative update weight data by carrying out the iterative update processing of the weights by using the path allocation processing result is as follows:

Wn＝Wn-1+α×(setup_slack _set -setup_slack _n-1 )

wherein Wn is new weight adjusted by next iteration, wn-1 is weight of last round, setup_slot is setup time set value according to system time sequence requirement, setup_slot-1 is setup time allowance of path of adjacent last round.

Further, the time-series driving route processing of establishing a time-series driving path by using the input data time-series driving divided data includes:

s2-1, obtaining a connection relation of the input data time sequence driving segmentation data corresponding to a networking FPGA, and performing route selection to obtain a route selection result of the input data time sequence driving segmentation data;

s2-2, calculating the cost value of the corresponding time sequence driving path according to the routing result;

s2-3, obtaining a corresponding maximum value of the cost value of the time sequence driving path;

s2-4, calculating an iterative optimization target according to the maximum value corresponding to the time sequence path cost value;

s2-5, establishing an iteration optimization target corresponding array according to the iteration optimization target;

s2-6, calculating the exchange position probability of the array elements according to the array corresponding to the iterative optimization target;

s2-7, completing time sequence driving route processing according to the array element exchange position probability.

Further, a calculation formula for calculating the cost value of the corresponding time sequence driving path according to the routing result is as follows:

where C is the cost value of the timing paths, setup_slot is the setup time margin for each timing path, and max_setup_slot is the maximum value among setup_slots for all timing paths of all nets.

8. The routing path processing method based on time sequence driving as claimed in claim 6, wherein a calculation formula for calculating an iterative optimization target according to the maximum value of the time sequence path cost value is as follows:

Target＝α×R+β×T

the target is an iterative optimization target, R is the radius of a routing path, T is the sum of the number of gaps of the routing path crossing the FPGA, and alpha and beta are adjustment parameters.

Further, the calculation formula for calculating the array element exchange position probability according to the iteration optimization target corresponding array is as follows:

wherein P (i-j) is the probability of the exchange position, max_diff is the maximum difference value among L elements, i and j are array subscripts respectively, i Ci-Cj is used for measuring the cost difference degree between two elements, i-j is used for measuring the distance degree between two elements, and alpha and beta are adjusting parameters.

Further, completing the timing driving route processing according to the array element exchange position probability includes:

exchanging elements in the array corresponding to the iterative optimization target according to the array element exchange position probability;

after filtering the iteration optimization target corresponding array, deleting connecting lines of first elements in the iteration optimization target corresponding array to establish isolated points;

establishing an update route path by utilizing the isolated points to obtain an update route selection result;

and judging whether the cost value of the time sequence driving path corresponding to the updated route selection result is the same as that of the time sequence driving path corresponding to the updated route selection result immediately before, if so, completing time sequence driving route processing, otherwise, reserving the current updated route selection result, and returning to S2-2.

Compared with the closest prior art, the application has the following beneficial effects:

and the path book with large setup time margin is properly cut, the path with small setup time is prevented from being cut, the time sequence requirement of the time sequence path can be ensured to the maximum extent after the time sequence requirement is considered, and meanwhile, the system performance is improved by considering the time sequence and considering the weight of the cut path.

Drawings

Fig. 1 is a flowchart of a routing path processing method based on time sequence driving provided by the application;

fig. 2 is a schematic diagram of a first connection relationship of a routing path processing method based on time sequence driving according to the present application;

FIG. 3 is a schematic diagram of a second connection relationship of a routing path processing method based on time sequence driving according to the present application;

fig. 4 is a schematic diagram of a third connection relationship of a routing path processing method based on time sequence driving according to the present application;

FIG. 5 is a schematic diagram of a fourth connection relationship of a routing path processing method based on time sequence driving according to the present application;

fig. 6 is a schematic diagram of a fifth connection relationship of a routing path processing method based on time sequence driving according to the present application;

fig. 7 is a schematic diagram of a sixth connection relationship of a routing path processing method based on time sequence driving according to the present application;

FIG. 8 is a schematic diagram of a seventh connection relationship of a routing path processing method based on time-series driving according to the present application;

fig. 9 is a schematic structural diagram of a routing path processing device based on time sequence driving according to the present application.

Detailed Description

The following describes the embodiments of the present application in further detail with reference to the drawings.

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

Example 1:

the application provides a routing path processing method based on time sequence driving, as shown in figure 1, comprising the following steps:

S1 specifically comprises:

s1-2, acquiring a delay critical path of the input data;

wherein, the screening requirement is a fixed cycle number.

The calculation formula of S1-3 is as follows:

S1-4 specifically comprises:

s1-4-1, acquiring nodes corresponding to the input data hypergraph;

The calculation formula of S1-5 is as follows:

Wn＝Wn-1+α×(setup_slack _set -setup_slack _n-1 )

S2 specifically comprises:

The calculation formula of S2-2 is as follows:

where C is the cost value of the timing paths, setup_slot is the setup time margin for each timing path, and max_setup_slot is the maximum value among setup_slots for all timing paths of all nets. And net refers to all logic signals, including cut logic signals and uncut logic signals; specifically, the load driving of the cut logic signals as logic signals spans different FPGAs; the load driving of the logic signals which are not cut into the logic signals are all in the same FPGA.

The calculation formula of S2-4 is as follows:

Target＝α×R+β×T

The calculation formula of S2-6 is as follows:

S2-7 specifically comprises:

s2-7-1, exchanging elements in the array corresponding to the iterative optimization target according to the array element exchange position probability;

s2-7-2, after filtering the iteration optimization target corresponding array, deleting connecting lines of first elements in the iteration optimization target corresponding array to establish isolated points;

s2-7-3, establishing an update route path by utilizing the isolated points to obtain an update route selection result;

s2-7-4, judging whether the cost value of the time sequence driving path corresponding to the updated route selection result is the same as the cost value of the time sequence driving path corresponding to the updated route selection result immediately before, if so, completing time sequence driving route processing, otherwise, reserving the current updated route selection result, and returning to S2-2.

In this embodiment, a routing path processing method based on time sequence driving is applied in real time as follows:

A：

1. hypergraph modeling:

inputting user design, wherein the user design is usually described by RTL or netlist, and then is analyzed and modeled by a parser to generate hypergraph G (V, E) composed of nodes and connecting lines (net), wherein the nodes represent circuit modules, and meanwhile, the circuit modules are time sequence devices or combination devices, signal delay time length of the devices and the like; net represents a connection line between circuits, and because there are a plurality of endpoints on one net, a graph in which there is a superside is called a supergraph.

2. K key paths are selected

Because the user design usually has a huge number of time sequence paths, iteration is needed in the segmentation stage, namely, the segmentation is optimized for a plurality of times, the complexity of the algorithm is improved and the time for establishing each time sequence path is calculated, and a large amount of time is consumed, so that K key paths with the largest delay sum are needed to be screened out in the first step of the algorithm to update the weight, the delay time of the time sequence paths in the initial stage is the sum of the delay times of the combinational logic passed by the time sequence paths, and the experimental time of each net is set to be a fixed constant T_net for the net among the combinational logic. The value of K is related to the number of FPGAs in the networking and the number of time sequence paths of the user design, the time sequence performance requirements and the like.

2. Initial segmentation

And calculating the setup slots of the K time sequence paths, updating the weights of the K time sequence paths, and keeping the weights of other time sequence paths (common paths) unchanged.

Wherein wt_0 is a weight update result, t_setup is an establishment time margin, d_max is a maximum value of delay in K timing paths, W is an edge weight of an original timing path, and α, r is a parameter greater than 1. As can be seen from the formula, when t_setup is smaller, the timing requirement of the path is more severe, the weight of wt_0 is amplified, the probability of cutting the path during the splitting process is reduced, and when t_setup is larger, the timing requirement of the path is more relaxed, the weight of wt_0 is greatly reduced compared with the path with W smaller than t_setup, and compared with the common path with K paths, the probability of cutting the path is higher than that of the common path and lower than that of the path with severe timing. The ratio of d_max to t_setup describes the relative relationship of the setup time margin of the current timing path to the magnitude of the currently selected K critical paths, so as to adjust the degree of weight amplification, because if the weight amplification is excessive, the common path is easily divided into paths with severe timing, otherwise, the division cannot well meet the timing requirement, and α, r is a variable parameter set according to the timing performance requirement designed by the user.

It is assumed that there are N FPGAs in the networking, that is, the hypergraph will be divided into N parts. The resource constraint is required to be met in the segmentation process, namely the sum of various resources allocated to the nodes on the FPGA is smaller than the set proportion a% of the total amount of various resources of the FPGA. The amount of resources per node in the hypergraph is larger or smaller and is not consistent.

As shown in fig. 2, first, fix nodes designated by the user are put into corresponding FPGAs. The Fix node is a node for designating a dividing position for a user, and is generally a specific circuit module. And randomly selecting one hypergraph node in the user design for each other FPGA without the fix node in the networking, namely, each FPGA obtains at least one hypergraph node. Then, each unassigned hypergraph node is traversed in the order of from large to small in terms of resources, which has the advantage that the positions should be assigned first for the hypergraph nodes with large resources, otherwise the situation that one large node cannot be accommodated because of the large resources on each FPGA, or the cost of a large cut path weight (cut size) has to be generated because of the resource constraint to be complied with, is left over last. And (3) assuming the first node as a node A, calculating the weight sum of the time sequence paths of the node A and the distributed nodes on each FPGA in the networking, assuming the weight sum of all time sequence paths between A-FPGAs 1 as W_sum1, A-FPGAs 2 as W_sum2 and A-FPGAs 3 as W_sum3, comparing all the weight sums, taking the FPGA with the largest weight sum, such as FPGA1, and arranging the node A in the FPGA 1. And similarly, placing the following nodes in turn. In the above process, compared with the prior art, not only the cut size is taken into consideration, but also the factors of the time sequence requirement are added, and the factors are unified and fused into the same optimization target.

Here, there is a detail of calculating the cut size, as shown in fig. 3, it is assumed that there are two timing paths on one net, path1 and path2, respectively, driven by corresponding weights w1 and w2, a, B, and C, respectively. If the cutting position occurs at cut3, the corresponding cut size is w1; if the cutting position occurs at cut2, the corresponding cut size is w2; if the cut position occurs at cut1, then the calculation of the cut size is determined by the position of B, C, if B, C are in different FPGAs, then the resulting cut size for cut1 is w1+w2, if B, C are in the same FPGA, then the resulting cut size for cut1 takes the maximum of w1 and w 2.

3. And (3) iterative adjustment:

after the primary segmentation, the position of each node in the hypergraph in the networking and all the cut time sequence paths can be obtained, an additional data path transmission delay_cut is added for all the cut time sequence paths, and due to the change of the Delay time, all the time sequence paths in the hypergraph are required to be reordered according to the Delay time, new K key paths are selected, and the weight of each time sequence path in the K key paths is updated according to the following formula.

Wn＝Wn-1+α×(setup_slack _set -setup_slack _n-1 )

Where Wn is the new weight for the next iteration adjustment, wn-1 is the weight for the previous iteration, setup_slice_set is the setup time set value according to the system timing requirement, and setup_slice_n-1 is the setup time margin for the path for the previous iteration.

And (3) carrying out weight updating on the K newly selected time sequence paths, and entering the next round of optimization iteration until the set requirement is met or the iteration meets the designated times.

The cut size values between all FPGAs are updated first in each iteration, as the weights on some of the timing paths change, tuning for FPGAs with max cut size, such as FPGA1 and FPGA 2: traversing all time sequence paths between two FPGAs, such as path1 and path2, obtaining a driving end and a load end of each time sequence path, selecting one node in the FPGA1 and one node in the FPGA2 to form a node pair, noting that the selected node must be the end point of the time sequence path crossing the FPGAs, as shown in figures 4 and 5, { A, C } and { B, D }, exchanging the positions of the node pair without violating resource constraints, such as putting the node A into the FPGA2, putting the node D into the FPGA1, and calculating the reduction amplitude of cut size brought by exchanging, namely that the original cut size is the sum of weights of the path1 and the path2, and the exchanged node is the sum of the weights of the path3, the path4 and the path 5. All possible node pairs are calculated, and the node pair with the largest cut size reduction amplitude is selected for real position exchange. And then proceeds to the next round of iterative optimization.

B：

1. Concept of routing:

the limitation of connection relation between FPGAs in the networking is not considered when the user design is split, namely the splitting process only considers dividing the hypergraph representing the user design into N copies, and does not consider how to route the signal transmission between FPGAs without direct interconnection line connection, as shown in fig. 6, three nodes on one net are distributed to different FPGAs, and the connection relation of the nodes is as shown in the diagram, so that the nodes a to B and C need to be transferred through an intermediate FPGA. In addition, the dividing process and the routing process are divided into two stages, so that although the two processes are put together to be processed to obtain a theoretically better solution, the difficulty and complexity of an algorithm are greatly increased, and in practical engineering application, better results can be obtained when complex problems are decomposed and solved one by one.

2. Generating an initial routing path for each net requiring routing:

for each net (hereinafter, net refers to net requiring routing), obtaining driving nodes and all load nodes of the net and FPGA positions of the load nodes, and performing initial routing according to FPGA connection relations in networking. The initial Routing method is that starting from the driving node, each load node is reached in the networking according to the shortest path, namely, the shortest distance and the path between two nodes are respectively calculated, and the obtained initial Routing path has the smallest radius, wherein the radius refers to the maximum value of the cost in each load node starting from the driving node. It should be noted that although the radius is small, the total cost value, that is, the sum of the lengths of all the timing paths of net, may be relatively large, because the initial routing method does not consider that the paths on the same path may merge and share one transmission line, so as to reduce the cut size, and save the wiring resources. As shown in fig. 7, the left-hand route results in the smallest radius, the right-hand radius, although it is larger, the total path length is reduced, s represents the drive, and l represents the load. The left structure has smaller delay and better timing performance, but needs to pay larger cut size, i.e. needs to consume more wiring resources, so a balance needs to be found between them.

3. Updating the cost of the time sequence path in the net according to the routing result:

along the route of each time sequence path, if M FPGA gaps need to be crossed on the route, the time Delay length of M times delay_cross is increased for the time sequence path, and delay_cross is a constant set according to networking characteristics and time sequence requirements. And then, after performing timing analysis (invoking a timing analysis tool) on each timing path, a setup_slice of each timing path can be obtained, wherein the margin is closely related to the delay length of the timing path, that is, the number of the timing paths crossing the FPGA gap, and the cost of each timing path is defined as,

in the formula, C is the cost value of a time sequence path, setup_slot is the set-up time allowance of each time sequence path, max_setup_slot is the maximum value of setup_slots of all time sequence paths of all net, the ratio is the scale for balancing and controlling the amplification of path cost affected by setup_slot among all time sequence paths of net, and alpha is an adjustable parameter for adjusting amplification amplitude. The cost calculation mode combines the cut size of the net and the time sequence requirements of all time sequence paths of the net, and leads a better routing result.

4. Iterative optimization routing path:

setting an optimization target as follows:

Target＝α×R+β×T

r is the radius of a routing path, namely the maximum cost value of the path between a driving node and a load node, T is the sum of the number of gaps of the routing path crossing the FPGA, and alpha and beta are adjusting parameters.

And ordering the timing paths in the initial routing result from big to small according to the cost, for example, K timing paths exist in net, the cost is an array { C1, C2,. The..Ck }, and a sliding filter with the length of L is designed for disturbing the cost array so as to avoid breaking iteration due to the fact that the local sub-good result is trapped and missing the best result. L < =k, L being a positive integer. The magnitude of L controls the thickness degree of disturbance, and the larger L is, the larger the disturbance degree of the sequence is, the coarser the disturbance degree is, and conversely, the smaller and the more limited the disturbance range is.

The filter starts to slide towards the head of the array at the tail of the array, moving one element at a time, for elements in the cost array in the corresponding L, randomly matching pairs of elements, exchanging each pair of elements for each other's position in the array according to the following probability. Where P (i-j) is the probability of the swap position, max_diff is the maximum difference of all matching combinations among L elements, and when the maximum difference is 0, the filter skips the process, moving one element directly to the left. i and j are array subscripts, respectively, |Ci-cj| is used for measuring the degree of cost difference between two elements, and|i-j| is used for measuring the degree of distance between two elements.

As shown in fig. 8, after filtering, the first element in the array is taken, the connection line with the node is deleted, at this time, the corresponding load node becomes an isolated point, the isolated point and other nodes on the net try to be newly connected in the network according to the shortest path, so as to form a new route path, after updating the cost of the time sequence path according to the calculation formula of C, the Target value of the net is recalculated, and the connection mode with the maximum increase of the corresponding Target is selected, so as to change the route. Repeating the above procedure to Target can not be reduced any more. The process starts from the Rmin, gradually increases the radius, reduces the total cut size, and finally achieves the balance and balance of the Rmin and the Rmin.

Having described the method of an exemplary embodiment of the present application, next, a timing-drive-based routing path processing apparatus of an exemplary embodiment of the present application will be described with reference to fig. 9, the apparatus including:

a dividing unit 901 for performing time-series driving dividing processing by using the input data to obtain input data time-series driving dividing data;

a setting unit 902 for setting up a timing driving path to complete the timing driving route processing by using the input data timing driving split data obtained by the splitting unit 901.

As an alternative embodiment, the manner in which the dividing unit 901 performs the time-series driving dividing process using the input data to obtain the time-series driving divided data of the input data may specifically be:

establishing an input data hypergraph by utilizing the corresponding connection end point of the input data;

acquiring a delay critical path of the input data;

according to the delay critical path of the input data, obtaining a corresponding time allowance, and carrying out weight updating processing to obtain delay critical path updating data of the input data;

carrying out distribution processing on the corresponding paths of the delay critical path update data and the input data hypergraph to obtain a path distribution processing result;

performing weight iterative update processing by using the path allocation processing result to obtain iterative update weight data;

updating the delay critical path of the input data by using the iterative updating weight data to obtain a path updating processing result;

judging whether the path updating processing result meets the screening requirement, if yes, outputting the current path updating processing result as input data time sequence driving segmentation data, otherwise, executing the iterative updating processing of the weights by using the path allocation processing result to obtain iterative updating weight data, updating the delay critical path of the input data by using the iterative updating weight data to obtain the path updating processing result, and judging whether the path updating processing result meets the screening requirement; wherein, the screening requirement is a fixed cycle number.

In the embodiment of the application, the calculation formula of the delay critical path update data of the input data is as follows, wherein the calculation formula is that the corresponding time allowance is obtained according to the delay critical path of the input data, and the weight update processing is carried out to obtain the delay critical path update data of the input data:

As an optional implementation manner, the manner in which the dividing unit 901 performs the allocation processing on the path corresponding to the delay critical path update data and the input data hypergraph to obtain the path allocation processing result may specifically be:

acquiring a node corresponding to the input data hypergraph;

distributing the corresponding paths of the delay critical path update data according to the nodes corresponding to the input data hypergraph;

judging whether the input data hypergraph corresponding node has a wheel space or not, if so, executing the steps of distributing the delay critical path update data corresponding path according to the input data hypergraph corresponding node, and judging whether the input data hypergraph corresponding node has the wheel space or not, otherwise, completing the distribution processing to obtain a path distribution processing result; and the wheel space is the corresponding path of the input data hypergraph corresponding node, and the corresponding delay critical path updating data does not exist.

In the embodiment of the application, the calculation formula for obtaining the iterative update weight data by carrying out the iterative update processing of the weights by utilizing the path allocation processing result is as follows:

Wn＝Wn-1+α×(setup_slack _set -setup_slack _n-1 )

As an optional implementation manner, the establishing unit 902 may specifically use the input data timing driving dividing data to establish a timing driving path to complete the timing driving routing processing:

acquiring a connection relation of the input data time sequence driving segmentation data corresponding to the networking FPGA, and performing route selection to obtain a route selection result of the input data time sequence driving segmentation data;

calculating the cost value of the corresponding time sequence driving path according to the route selection result;

acquiring a corresponding maximum value of a time sequence driving path cost value;

calculating an iterative optimization target according to the maximum value corresponding to the time sequence path cost value;

establishing an iteration optimization target corresponding array according to the iteration optimization target;

calculating the exchange position probability of the array elements according to the array corresponding to the iterative optimization target;

and finishing time sequence driving route processing according to the array element exchange position probability.

In the embodiment of the application, the calculation formula for calculating the cost value of the corresponding time sequence driving path according to the routing result is as follows:

In the embodiment of the application, the calculation formula for calculating the iterative optimization target according to the maximum value corresponding to the cost value of the time sequence path is as follows:

Target＝α×R+β×T

In the embodiment of the application, the calculation formula for calculating the exchange position probability of the array elements according to the array corresponding to the iterative optimization target is as follows:

As an optional implementation manner, the manner in which the establishing unit 902 completes the timing driving routing processing according to the array element exchange position probability may specifically be:

and judging whether the cost value of the time sequence driving path corresponding to the updated route selection result is the same as the cost value of the time sequence driving path corresponding to the updated route selection result at the last moment, if so, completing time sequence driving route processing, otherwise, reserving the current updated route selection result, executing the steps of calculating the cost value of the corresponding time sequence driving path according to the route selection result, acquiring the maximum value corresponding to the cost value of the time sequence driving path, calculating an iterative optimization target according to the maximum value corresponding to the cost value of the time sequence path, establishing an iterative optimization target corresponding array according to the iterative optimization target, and calculating the exchange position probability of the array elements according to the iterative optimization target corresponding array.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

Finally, it should be noted that: the above embodiments are only for illustrating the technical aspects of the present application and not for limiting the same, and although the present application has been described in detail with reference to the above embodiments, it should be understood by those of ordinary skill in the art that: modifications and equivalents may be made to the specific embodiments of the application without departing from the spirit and scope of the application, which is intended to be covered by the claims.

Claims

1. A timing drive-based routing path processing method, comprising:

2. The method of claim 1, wherein the performing the time-series driving splitting process using the input data to obtain the input data time-series driving splitting data comprises:

s1-2, acquiring a delay critical path of the input data;

wherein, the screening requirement is a fixed cycle number.

3. The routing path processing method based on time sequence driving as claimed in claim 2, wherein the calculation formula of the delay critical path update data of the input data obtained by performing weight update processing according to the corresponding time margin obtained by the delay critical path of the input data is as follows:

4. The method for processing routing paths based on time sequence driving as claimed in claim 2, wherein the step of performing the distribution processing on the paths corresponding to the delay critical path update data and the input data hypergraph to obtain the path distribution processing result comprises the steps of:

s1-4-1, acquiring nodes corresponding to the input data hypergraph;

5. The method for processing routing paths based on time sequence driving according to claim 2, wherein the calculation formula for obtaining the iterative update weight data by performing the iterative update processing of the weights by using the path allocation processing result is as follows:

Wn＝Wn-1+α×(setup_slack _set -setup_slack _n-1 )

6. The routing path processing method based on time series driving as claimed in claim 2, wherein establishing a time series driving path using the input data time series driving division data to complete time series driving routing processing comprises:

7. The routing path processing method based on time series driving as set forth in claim 6, wherein a calculation formula for calculating a corresponding time series driving path cost value according to the routing result is as follows:

Target＝α×R+β×T

9. The method of claim 6, wherein the calculation formula for calculating the array element exchange position probability according to the iteration optimization target corresponding array is as follows:

10. The timing drive-based routing path processing method of claim 6, wherein completing timing drive routing processing according to the array element switch position probability comprises: