CN117149672A

CN117149672A - Disk array card cache configuration and reading methods and devices and disk array card

Info

Publication number: CN117149672A
Application number: CN202311426765.7A
Authority: CN
Inventors: 李飞龙; 马艳; 许永良; 王磊; 康佳; 孙明刚
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2023-10-31
Filing date: 2023-10-31
Publication date: 2023-12-01
Anticipated expiration: 2043-10-31
Also published as: CN117149672B

Abstract

The invention relates to the technical field of computers, and discloses a disk array card cache configuration and reading method and device and a disk array card, wherein the configuration method comprises the following steps: dividing the cache of the disk array card into a plurality of cache lines, wherein each cache line is divided into the same number of cache lines; and establishing a mapping relation for each cache way and each disk address set, wherein the mapping relation is established for the current cache way and each disk address set through a plurality of rounds of establishment tasks, the current cache way is the cache way which is currently establishing the mapping relation with each disk address set, in each round of establishment tasks, a disk address set which is not repeated is sequentially allocated for each cache line in the current cache way, and the disk address sets allocated among the rounds of establishment tasks are not repeated until all the disk address sets are allocated to the current cache way. The invention reduces the occurrence frequency of buffer bump.

Description

Disk array card cache configuration and reading methods and devices and disk array card

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a method and an apparatus for configuring and reading a cache of a disk array card, and a disk array card.

Background

A redundant array of independent disks (Redundant Array of Independent Disks, RAID) is a technology of combining a plurality of independent hard disks (physical hard disks) into a hard disk group (logical hard disk) with a huge capacity, thereby providing higher storage performance than a single hard disk and providing data backup, simply referred to as a disk array. At present, the industry has a soft RAID storage technology and a hard RAID storage technology, the soft RAID storage technology is realized by using software for managing stripes and blocks in RAID, and the hard RAID storage technology is realized by giving some algorithms, data management and some functions in the soft RAID storage technology to hardware management, namely RAID cards (disk array cards), wherein the disk array cards are the most key component units of the hard disk array storage technology so as to improve the I/O performance and the data security of a storage system. The disk array card is a functional board card for organizing the hard disks connected with the server into a plurality of disk arrays according to the disk array level, and the cache is used as an important component of a disk array card controller, so that the storage performance can be greatly improved, and the read-write response can be accelerated. The cache is a small part of space in the disk array card, and the space can store some data, so that when external equipment sends a request for reading data, the disk array card controller firstly checks whether the requested data is stored in the cache or not, and if the data is stored in the cache, the disk array card controller does not need to extract the data from the disk, and only needs to acquire the data from the cache, so that the speed for reading the data can be obviously improved. However, a common approach in the related art is to divide the cache of the disk array card into a plurality of cache lines with the same capacity, and then configure a disk address set corresponding to one cache line, where a disk address set includes a plurality of disk addresses, and each disk address in the set has a mapping relationship with the corresponding cache line. Because the number of disk address sets is far greater than the number of cache lines, after all cache lines and a part of disk address sets are correspondingly completed, all the cache lines and another part of disk address sets are correspondingly performed in a new round until all the address correspondences are completed. Therefore, one cache line corresponds to a plurality of disk address sets, that is, each disk address set corresponding to one cache line has the right to cache data to the cache line, and thus when executing a data reading policy, the problem of cache thrashing frequently occurs, so that a method is needed to reduce the occurrence frequency of cache thrashing.

Disclosure of Invention

In view of the above, the present invention provides a method and apparatus for configuring and reading a disk array card cache, and a disk array card, so as to solve the problem of frequent cache jolt.

In a first aspect, the present invention provides a method for configuring a cache of a disk array card, where the method includes: dividing the cache of the disk array card into a plurality of cache lines, wherein each cache line is divided into the same number of cache lines; establishing a mapping relation between a current cache way and each disk address set through multiple rounds of establishment tasks, wherein the current cache way is the cache way which is currently establishing the mapping relation with each disk address set, in each round of establishment tasks, the disk address sets which are sequentially allocated to each cache line in the current cache way are not repeated, and the disk address sets which are allocated among the rounds of establishment tasks are not repeated; and taking the next cache way as the current cache way, and repeatedly executing the step of establishing the mapping relation between the current cache way and each disk address set through multiple rounds of establishment tasks until each cache way and each disk address set establish the mapping relation so as to complete the cache configuration of the disk array card.

According to the technical means provided by the embodiment of the invention, the disk array card is cached into a plurality of cache ways, each cache way is divided into the same number of cache lines, and for each cache way, the cache lines in the cache way and all the disk address sets are sequentially mapped, so that one disk address set can correspond to a plurality of cache lines and not only corresponds to one cache line, thus the data of one disk address set can be cached in any cache line which is mapped with the corresponding cache line, when a user needs to read the data, the disk array card controller can sequentially judge whether each cache line which is mapped with the target address has corresponding cache data according to the target address of the data to be read, and can not judge that the read data is missed as long as one cache line stores the data, so that the frequency of the missing can be obviously reduced, the occurrence frequency of cache bump problem can be obviously reduced, and the cache performance of the disk array can be improved.

In an alternative embodiment, the mapping relation between the current cache way and each disk address set is established through multiple rounds of establishment tasks, including: generating a disk address set sequence according to the addressing sequence of each disk address set; sequencing the cache lines in the current cache way to obtain a cache line sequence; aligning one end of the cache line sequence and one end of the disk address set sequence; starting from one aligned end of the disk address set sequence, sliding the sliding window by taking the number of cache lines in the cache line sequence as the width of the sliding window and taking the number of cache lines as the sliding step length of the sliding window, selecting disk address sets with the same number as the width of the sliding window from the disk address set sequence before each sliding, and mapping each selected disk address set into each cache line according to a one-to-one corresponding position relation until all disk address sets in the disk address set sequence are mapped.

According to the technical means provided by the embodiment of the invention, the disk address sets are arranged according to the addressing sequence of each disk address set to generate the disk address set sequence, then each ordered cache way is used as a sliding window, the number of cache lines in the cache way is used as a sliding step length, each time the cache way slides, a mapping relation is established between the cache lines in the cache way and a part of the disk address sets in the disk address set sequence, when the sliding window slides to the tail part of the disk address set sequence, the corresponding mapping relation between all the disk address sets and the cache lines in each cache way can be established, the efficiency of creating the mapping relation is obviously improved, and the complexity of creating the mapping relation is reduced.

In an alternative embodiment, the method further comprises: setting corresponding numbers according to the same number rule for cache lines in each cache way, and setting offset bits, index bits and flag bits for the disk addresses in each disk address set, wherein the mapping relation established between the disk address sets and the cache lines is represented by the association relation between the index bits of the disk addresses and the cache line numbers; when the data of the target disk address is read, the offset bit is used for determining the position of the read data byte in the cache line, the index bit is used for matching with the serial number of the cache line to determine the position of the read cache line, and the flag bit is used for comparing with the flag bit information stored in the cache line to verify that the data cached in the cache line is the data of the target disk address.

According to the technical means provided by the embodiment of the invention, offset bits, index bits and flag bits are set for the disk addresses in the disk address set, and the cache lines in each cache way are numbered, wherein the numbers of the cache lines and the index bits of the disk addresses are numbers with association relations. Therefore, when data is read, the disk array card controller can accurately position which cache lines and the current disk address have a mapping relation according to the index bit, then determine which cache data in the cache lines are actually corresponding data in the current disk address according to the flag bit, and then determine which byte of data is specifically read by the read request according to the offset bit, so that the flexibility and accuracy of data reading are remarkably improved.

In an alternative embodiment, when the capacity of the disk array card cache is 64 bytes, the capacity of the partition cache line is 8 bytes.

According to the technical means provided by the embodiment of the invention, the capacity of the disk array card cache of some commonly used disk array cards is 64 bytes, so that when the disk array card with the capacity is adopted, each cache line needs a flag bit to occupy a certain space although the capacity of the cache line can be large or small, and if the space of the cache line is too small, the cache space of data is wasted because a large number of flag bits are saved, therefore, the embodiment of the invention defines that the capacity of the cache line is 8 bytes, the cache line cannot be too large or too small, the data cache requirement of a common application scene can be better met, and the cache performance is improved.

In an alternative embodiment, the disk array card cache is divided into a plurality of cache ways, each of the cache ways being divided by the same number of cache lines, including: the disk array card cache is divided into 2 cache ways, and each cache way comprises 4 cache lines.

According to the technical means provided by the embodiment of the invention, when the access amount of the user to each disk address is relatively balanced, 2 cache ways are adopted, and each cache way comprises 4 cache lines, so that the data in the cache can be stored for a longer time, and the secondary reading of the user is facilitated.

In an alternative embodiment, the offset bit, index bit, flag bit are set for the disk address by: starting from the lowest bit of each disk address, the first bit to the third bit are set as offset bits, the fourth bit to the fifth bit are set as index bits, and the remaining bits of each disk address are set as flag bits.

According to the technical means provided by the embodiment of the invention, when the disk array card cache is divided into 2 cache ways, and each cache way comprises 4 cache lines, the index bit can traverse the numbers of all the cache lines in one way only by setting the index bit into two bits, so that the aim of accurate matching is achieved, more bits are prevented from being wasted as index bits, more adaptation scenes of the zone bit are improved, and the method is suitable for different data of different types.

In an alternative embodiment, the disk array card cache is divided into a plurality of cache ways, each of the cache ways being divided by the same number of cache lines, including: the disk array card cache is divided into 8 cache ways, and each cache way comprises 1 cache line.

In an alternative embodiment, the offset bit, index bit, flag bit are set for the disk address by: starting from the lowest bit of each disk address, the first bit to the third bit are set as offset bits, the index bit is set to be null, and the remaining bit number of each disk address is set as flag bit.

According to the technical means provided by the embodiment of the invention, when the access amount of a user to a small part of disk addresses is large and other disk addresses are rarely accessed, 8 cache ways are adopted, each cache way comprises a partition mode of 1 cache line, so that the frequently accessed disk addresses have larger occupation weight to the cache lines, data in the frequently accessed disk addresses can be read out more quickly, redundant occupation of the rarely accessed disk addresses to the cache lines is reduced, and secondary reading of the data by the user is facilitated. In addition, the index bit is not needed in the dividing mode, so that more bits are prevented from being wasted as the index bit, more adaptation scenes of the flag bit are improved, and the method is suitable for different data of different types.

In an alternative embodiment, the cache line includes a status flag to indicate whether the data in the cache line has been altered and a change flag to indicate whether the data in the cache line is valid data.

According to the technical means provided by the embodiment of the invention, whether the data in the cache line is valid or not is also indicated by the state mark, so that misreading of the data by the disk array controller is avoided, whether the data in the cache line is changed or not is indicated by the change mark, and the problem that the data is tampered maliciously and is not found is avoided.

The second aspect of the present invention provides a method for reading a cache of a disk array card, which is characterized in that the method is applied to the disk array card configured by the method for configuring the cache of the disk array card provided by any one of the optional embodiments of the first aspect, and the method includes: receiving a data reading request, and responding to the data reading request to acquire a target disk address of data to be read; determining at least one entry target cache line which establishes a mapping relation with a target disk address; and reading the data corresponding to the target disk address from at least one target cache line.

According to the technical means provided by the embodiment of the invention, when a user needs to read data, the disk array card controller can sequentially judge whether each target cache line establishing a mapping relation with the target disk address has corresponding cache data according to the target disk address of the data to be read, and only if one cache line stores the corresponding data, the read data cannot be judged to be missing, so that the number of missing times can be obviously reduced, the occurrence frequency of cache bump problems is obviously reduced, and the cache performance of the disk array is improved.

In an alternative embodiment, determining at least one entry cache line that has a mapping relationship with a target disk address includes: extracting a target index bit from a target disk address; matching the target index bit with the cache line number in each cache way to obtain a target cache line number with an association relation with the target index bit; a target cache line marked by a target cache line number is determined in each cache way.

According to the technical means provided by the embodiment of the invention, when data is read, the disk array card controller can accurately position which cache lines and the current disk address have a mapping relation according to the index bit, so that the target cache line is determined, and the accuracy of cache line searching is ensured.

In an alternative embodiment, reading data corresponding to a target disk address from at least one target cache line includes: extracting a target zone bit from a target disk address; comparing the target zone bit with zone bit information stored in each target cache line in sequence; when the flag bit information in the current target cache line is consistent with the target flag bit comparison, reading data corresponding to the target disk address from the current target cache line.

In an alternative embodiment, when the flag bit information in the current target cache line is consistent with the target flag bit comparison, reading the data corresponding to the target disk address from the current target cache line includes: extracting a target offset bit from a target disk address; starting from the lowest bit of a cache data area in a current target cache line, searching to the high bit according to the target offset bit, and acquiring a target data byte position; corresponding data is read from the target data byte position.

According to the technical means provided by the embodiment of the invention, when data is read, the disk array card controller can accurately position which cache lines and the current disk address have a mapping relation according to the index bit, then determine which cache line cache data are actually corresponding data in the current disk address according to the flag bit, and then determine which byte data are specifically read by the read request according to the offset bit, so that the flexibility and accuracy of data reading are obviously improved.

In an alternative embodiment, when the flag bit information in each target cache line is inconsistent with the target flag bit alignment, the method further includes: and reading corresponding data from the position of the target disk address in the redundant array of independent disks, and placing the read data into a target cache line.

In an alternative embodiment, reading corresponding data from a location of a target disk address in the redundant array of independent disks, and placing the read data into a target cache line, including: after corresponding data is read from the position of a target disk address in the redundant array of independent disks, a data writing sequence is obtained, wherein the data writing sequence is used for representing a preset sequence of alternately writing cache data into each target cache line; determining the target cache line which should be written with the cache data at this time from all target cache lines according to the bit sequence of the target cache line which is written with the cache data at the last time in the data writing sequence; and placing the read data into a target cache line which should be written with the cache data at the time.

According to the technical means provided by the embodiment of the invention, when the data corresponding to the target disk address is not cached in the cache, the disk array controller needs to read the corresponding data from the corresponding disk address and store the corresponding data in a target cache line with a built mapping relation, so that the data can be read in the cache at the next time to a certain extent, and the data can be read quickly. In addition, in order to avoid that the read data is covered too fast, a strategy of alternately writing is adopted when each cache line stores the data, and new data is written in a mode that the new data covers the old data of each cache line only after each cache line is written once, so that the problem of cache jolt is further reduced.

In an alternative embodiment, reading corresponding data from a location of a target disk address in the redundant array of independent disks, and placing the read data into a target cache line, including: after corresponding data is read from the position of a target disk address in the redundant array of independent disks, judging a data storage process corresponding to the target disk address according to a disk address set where the target disk address is located, wherein the data storage process comprises a first process and a second process, the first process is used for managing the disk address set with the even number of the head address, and the second process is used for managing the disk address set with the odd number of the head address; acquiring a data writing sequence, wherein the data writing sequence is used for representing a preset sequence of alternately writing the cache data into each target cache line; determining the target cache line which should be written with the cache data at this time from all target cache lines according to the bit sequence of the target cache line which is written with the cache data at the last time in the data writing sequence; and the read data is put into a target cache line which should be written with the cache data through the first process or the second process.

Meanwhile, the embodiment of the invention provides two data storage processes, the disk address sets are grouped, the disk address set with the head address being even number is divided into one group, the disk address set with the head address being odd number is divided into another group, and the disk addresses in the disk address sets in each group are still arranged according to the addressing sequence. The first process is used for managing the disk address set with the even number of the head address, and the second process is used for managing the disk address set with the odd number of the head address.

In a third aspect, the present invention provides a disk array card cache configuration apparatus, where the apparatus includes: the cache way dividing module is used for dividing the cache of the disk array card into a plurality of cache ways, and each cache way is divided with cache lines with the same quantity; the cache way mapping module is used for establishing a mapping relation for each cache way and each disk address set, wherein the mapping relation is established for the current cache way and each disk address set through a plurality of rounds of establishment tasks, the current cache way is the cache way which is currently establishing the mapping relation with each disk address set, in each round of establishment tasks, a disk address set which is not repeated is sequentially allocated for each cache line in the current cache way, and the disk address sets allocated among the rounds of establishment tasks are not repeated until all the disk address sets are allocated to the current cache way.

In a fourth aspect, the present invention provides a disk array card cache reading device, which is applied to a disk array card configured by any one of the disk array card cache configuration methods in the first aspect, where the device includes: the target disk address module is used for receiving the data reading request and responding to the data reading request to acquire a target disk address of data to be read; the target cache line matching module is used for determining at least one item of target cache line which establishes a mapping relation with a target disk address; and the data reading module is used for reading the data corresponding to the target disk address from at least one target cache line.

In a fifth aspect, the present invention provides a disk array card, which is configured to perform a method provided by any one of the optional embodiments of the first aspect or the second aspect.

In an alternative embodiment, a disk array card includes: the system comprises a disk array card controller, a disk array card cache, a disk group, a monitoring module, a processor, a network interface and a firmware unit, wherein the processor is in communication connection with an external host, the firmware unit is in communication connection with the processor, the processor is in communication connection with the disk array card controller, the disk array card controller is in communication connection with the disk array card cache, the disk group and the monitoring module respectively, computer instructions are stored in the disk array card controller, and the method provided by the optional implementation of any one of the first aspect or the second aspect is executed by executing the computer instructions.

In a sixth aspect, the present invention provides a computer readable storage medium having stored thereon computer instructions for causing a computer to perform the method of the first aspect or any of its corresponding embodiments.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a related art point-to-point cache mapping method;

FIG. 2 is a flowchart of a method for configuring a cache of a disk array card according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a cache mapping structure of a method for configuring a cache of a disk array card according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of another cache mapping structure of a method for configuring a cache of a disk array card according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of another cache mapping structure of a method for configuring a cache of a disk array card according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a disk address configuration structure of a method for configuring a cache of a disk array card according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of another configuration structure of a disk address of a method for configuring a cache of a disk array card according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a disk address configuration when a cache way is not partitioned, according to an embodiment of the invention;

FIG. 9 is a schematic diagram of another configuration structure of a disk address of a method for configuring a cache of a disk array card according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of a configuration of status flags and change flags of a disk array card cache configuration method according to an embodiment of the present invention;

FIG. 11 is a flowchart of a method for reading a cache of a disk array card according to an embodiment of the present invention;

FIG. 12 is a schematic diagram of a disk array card cache configuration device according to an embodiment of the present invention;

FIG. 13 is a schematic diagram of a disk array card cache reading apparatus according to an embodiment of the present invention;

FIG. 14 is a schematic diagram of a disk array card according to an embodiment of the present invention;

fig. 15 is a schematic view of a mounting structure of a disk array card according to an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The disk array card cache is used as an important component of the disk array card controller, so that the storage performance can be greatly improved, and the read-write response can be accelerated. The disk array card cache is a small part of space in the disk array card, and the space can store some data, so that when external equipment sends a request for reading data, the disk array card controller firstly checks whether the requested data is stored in the cache or not, if the data is stored in the cache, the disk array card controller does not need to extract the data from the disk, and only needs to acquire the data from the cache, so that the data reading speed can be obviously improved.

And according to the use requirement of the user, the disk array card cache can have different use modes, for example, the common write data strategies based on the disk array card cache in the related art comprise two types:

1. the policy of writing the I/O data is a WB policy (Write Back mode), the Write I/O data requested by the host is temporarily stored in the disk array card cache, and after the I/O data is written into the disk array card cache, the disk array card immediately sends a data Write-in completion signal to the host (i.e. immediately responds to the host), so that the response delay of the host can be greatly reduced.

2. The strategy for writing I/O data is a WT strategy (Write Through mode), and for a Write event, the data writing cache does not respond first, and after the IO data is written into a storage medium of the disk array, the host responds; for a read event, after the data is read from the storage medium of the disk array, the host is responded, so that the read-write reliability is improved.

However, a common approach in the related art is to divide the cache of the disk array card into a plurality of cache lines with the same capacity, then configure a disk address set corresponding to one cache line, where one disk address set includes a plurality of disk addresses, and each disk address in the set has a mapping relationship with the currently corresponding cache line. Therefore, one cache line corresponds to a plurality of disk address sets, that is, each disk address set corresponding to one cache line has the right to cache data to the cache line, and thus when executing a data reading strategy, the problem of cache jolt frequently occurs.

The point-to-point mapping cache is simpler in hardware design, and therefore, the cost is lower, and according to the working mode of the point-to-point mapping cache, for example, as shown in fig. 1, a cache distribution diagram corresponding to the addresses 0x00-0x88 of the main memory address is shown, in this example, each address block in the diagram is a disk address set, and one disk address set includes eight addresses, for example, the first address block is the disk addresses 0x00-0x 07.

It can be seen that the data corresponding to the disk addresses 0x00-0x 3f can cover the whole disk array card cache. The data of the 0x 40-0 x7f disk addresses also cover the whole disk array card cache. Assuming that in a specific scenario, a program attempts to access disk addresses 0x00, 0x40, and 0x80 in sequence, it is first known from fig. 1 that the cache lines mapped by addresses 0x00, 0x40, and 0x80 are identical, so if the cache lines currently store 0x40 data, but the data is read in the order of 0x00, 0x40, and 0x80, there is no data in the cache when accessing the 0x00 address, resulting in the problem of cache miss. Although the data will be loaded from the disk array into the cache line of the 0 th line in the cache, when the 0x40 address is continuously accessed, the data is still indexed into the cache line of the 0 th line in the cache, and because the data corresponding to the address 0x00 address is stored in the cache line at this time, the problem of cache miss still occurs at this time, and then the data of the 0x40 address is loaded from the main memory into the cache line of the first line. Similarly, continuing to access the 0x80 address may still result in a cache miss. Therefore, the data is read from the disk array in each access, so the existence of the cache does not improve the performance, and when the next address is accessed, the data cached in the last address is replaced, which is called cache thrashing (cache thrashing). The phenomenon not only reduces the cache performance of the disk array card, but also causes the on-line capacity expansion and on-line capacity contraction processes of the disk array to be slow, influences the user service, and causes the user experience to be reduced.

Aiming at the problem, the embodiment of the invention provides the following method for greatly reducing the buffer bump possibility so as to greatly improve the buffer performance of the disk array card on the premise of not increasing the hardware cost.

According to an embodiment of the present invention, there is provided an embodiment of a disk array card cache configuration method, it should be noted that, steps illustrated in the flowchart of the drawings may be performed in a computer system such as a set of computer executable instructions, and although a logical order is illustrated in the flowchart, in some cases, steps illustrated or described may be performed in an order different from that herein.

In this embodiment, a method for configuring a cache of a disk array card is provided, which may be used for the disk array card described above, and fig. 2 is a flowchart of a method for configuring a cache of a disk array card according to an embodiment of the present invention, where the flowchart includes the following steps:

in step S101, the disk array card is cached and divided into a plurality of cache ways, and each cache way is divided into the same number of cache lines.

Specifically, the size of a disk array card cache (cache) is called a cache size (cache size), which represents the size of the largest data that the disk array card cache can cache. The disk array card cache is equally divided into a number of equal blocks, each block size being referred to as a cache line. Such as a 64 byte sized disk array card cache. If 64 bytes are equally divided into 64 blocks, 1 byte for a total of 64 lines, and if 64 bytes are equally divided into 8 blocks, 8 bytes for a total of 8 lines. If two different addresses go through the point-to-point mapping cache, the same cache line is found, and when the disk array card controller finds the cache line, only the data corresponding to the accessed address may exist in the cache line, but the cache line may also be the data corresponding to other addresses. In the embodiment of the invention, the concept of defining ways (ways) is defined, the cache of the disk array card is divided into a plurality of parts, each part is a cache way, each part is further divided into blocks with the same size, each block is a cache line, and thus each cache way is divided into the same number of cache lines. For example: the cache line of the disk array card cache partition with the size of 64 bytes is 8 bytes, and when the partition is divided into two paths, each path comprises 4 cache lines.

Step S102, a mapping relation is built between a current cache way and each disk address set through a plurality of rounds of building tasks, wherein the current cache way is the cache way which is currently building the mapping relation with each disk address set, in each round of building tasks, the disk address sets which are sequentially allocated to each cache line in the current cache way are not repeated, and the disk address sets which are allocated among the rounds of building tasks are not repeated.

And step S103, taking the next cache way as the current cache way, and repeatedly executing the step of establishing the mapping relation between the current cache way and each disk address set through multiple rounds of establishment tasks until each cache way and each disk address set establish the mapping relation so as to complete the cache configuration of the disk array card.

Specifically, the embodiment of the invention establishes a mapping relation for each cache way and each disk address set, and for each way, a part of disk address sets with the same number as that of cache lines in the current cache way are required to be selected from all disk address sets, the selected part of disk address sets and the cache lines in the current cache way adopt a one-to-one correspondence mode to establish the mapping relation, then the same steps are used for selecting a part of disk address sets from the rest of disk address sets and the cache lines in the current cache way to establish the one-to-one correspondence mapping relation, and the operation is repeated in this way until all disk address sets and the cache lines in the current cache way establish the one-to-one correspondence mapping relation through multiple rounds of operation.

For example, as shown in fig. 3, assuming that the cache size of the disk array card is 64 bytes, the cache line size is 8 bytes, and two paths are divided altogether, each path includes 4 cache lines (for example only, but not limited to this, it may also be divided into 4 paths, 6 paths, 8 paths, etc.), assuming that all disk address sets cover 0x00 to 0x58, one disk address set includes 8 disk addresses, for example, 0x00 to 0x07, and then 0x00 to 0x48 are categorized as 10 disk address sets. Therefore, after the 4 cache lines of the first cache way and the 4 disk address sets establish a one-to-one mapping relationship, the 4 cache lines of the current cache way and the new 4 disk address sets (and the first 4 disk address sets are not repeated) establish a one-to-one mapping relationship, and finally two of the remaining 2 disk address sets and the 4 cache lines establish a one-to-one mapping relationship. The second cache way and the first cache way adopt the identical steps to create the mapping relation between each cache line and each disk address set, in the current specific application embodiment, one disk address set can respectively correspond to 2 cache lines in two ways and not only correspond to one cache line (if the coverage range of the current disk address set is expanded to 0x00 to 0x88 or higher, the mapping principle is the same, and the specific mapping steps are not repeated), the newly proposed mapping method is called "point-to-group mapping", namely, one disk address set can respectively correspond to one cache line in each cache way, and all the cache lines corresponding to the same disk address set are called the same "cache group".

Still taking the above two cache ways as an example, if an external program attempts to sequentially access disk addresses 0x00, 0x40, and 0x80, because data at 0x00 may be loaded into the first cache way, or into the second cache way, data at 0x40 may be loaded into the first cache way, or into the second cache way. Therefore, there may be a scenario in which data of 0x00 address is loaded into the first cache way and data of 0x40 address is loaded into the second cache way, so that the problem of bumping of the point-to-point mapping cache is avoided to a certain extent, and when the number of cache ways is increased, the effect of reducing cache bump is better.

Therefore, under the condition that the cache size is fixed, the point-to-group cache has better effect than the direct-mapped cache under the worst performance improvement condition, and the frequency of cache jolt is reduced.

Therefore, through the technical scheme provided by the embodiment of the invention, one disk address set can correspond to a plurality of cache lines, but not only one cache line, the data of one disk address set can be cached in any cache line with which a mapping relation is established, when a user needs to read the data, the disk array card controller can sequentially judge whether each cache line with which the mapping relation is established with a target address has corresponding cache data according to the target address of the data to be read, and only one cache line stores the data, the read data cannot be judged to be missing, so that the number of times of missing can be obviously reduced, the occurrence frequency of cache bump problems is obviously reduced, and the cache performance of the disk array is improved.

In some optional embodiments, the step S102 includes:

step a1, generating a disk address set sequence according to the addressing sequence of each disk address set;

step a2, sequencing cache lines in a current cache way to obtain a cache line sequence;

step a3, aligning one ends of the cache line sequence and the disk address set sequence;

and a4, starting from one aligned end of the disk address set sequence, taking the number of cache lines in the cache line sequence as the width of the sliding window, sliding the sliding window by taking the number of the cache lines as the sliding step length of the sliding window, selecting disk address sets with the same number as the width of the sliding window from the disk address set sequence before each sliding, and mapping each selected disk address set into each cache line according to a one-to-one corresponding position relation until all disk address sets in the disk address set sequence are mapped.

Specifically, in order to further improve the efficiency and accuracy of mapping relation creation, in the embodiment of the invention, firstly, disk address sets are arranged according to the addressing sequence of each disk address set to generate a disk address set sequence, and cache lines in a current cache way are also sequenced to obtain a cache line sequence; then, as shown in fig. 4, one end of the cache line sequence and one end of the disk address set sequence are aligned, each cache line in the form of the cache line sequence is used as a sliding window, and the number of the cache lines in the cache line is used as a sliding step length, and the two aligned ends of the two sequences slide. When the sliding window slides to the tail of the disk address set sequence, the corresponding mapping relation between all the disk address sets and the cache lines in each cache way can be established, the effect of the established mapping relation is as shown in fig. 5, the efficiency of the creation of the mapping relation is obviously improved, and the complexity of the creation of the mapping relation is reduced.

In the embodiment of the present invention, the method for configuring the cache of the disk array card provided in the embodiment of the present invention further includes the following steps:

step b1, setting numbers for cache lines in each cache way according to the same numbering rule;

step b2, setting offset bits, index bits and flag bits for the disk addresses in the disk address set, wherein the mapping relation established between the disk address set and the cache line is represented by the association relation between the index bits of each disk address and the cache line number;

when the data of the target disk address is read, the offset bit is used for determining the read data byte position in the cache line, the index bit is used for matching with the number of the cache line to determine the read cache line position, and the flag bit is used for comparing with the flag bit information stored in the cache line to verify that the data cached in the cache line is the data of the target disk address.

Specifically, in the embodiment of the present invention, offset bits, index bits, and flag bits are set for disk addresses in the disk address set, and cache lines in each cache way are numbered according to the same numbering rule, for example, the cache line numbers are 1, 2, 3, 4, …, and the like. In the embodiment of the invention, the numbers set for the cache lines and the index bits of the disk addresses are numbers with association relations, for example, a plurality of bits in the addresses are selected as the index bits, and the bits in the addresses can represent the numbers through a 2-system, so that the numbers are represented by the index bits of the 2-system, and the numbers represented by the index bits are respectively given to each cache line in each cache line as the numbers, thereby realizing the association relations between the cache line numbers and the disk address index bits. Assuming that the disk address is 011011000101, a part of bits such as "101" may be selected as index bits, and the numeral denoted by 101 is "5" to denote the cache line number.

Similarly, the present embodiment is based on the principle that the number of bits in the address may represent the number by 2, and further provided with an offset bit and a flag bit, as shown in fig. 6, where the offset bit is used to determine the location of the read data byte in the cache line, and the flag bit is used to compare with the flag bit information stored in the cache line, so as to verify that the data cached in the cache line is the data in the target disk address. Therefore, through the technical scheme provided by the embodiment of the invention, when data is read, the disk array card controller can accurately position which cache lines and the target disk address have a mapping relation according to the index bit of the target disk address, then determine which cache line cache data is the real corresponding data in the current disk address according to the flag bit, and then determine which byte data is specifically read by the read request according to the offset bit, so that the flexibility and accuracy of data reading are obviously improved.

Specifically, in the related art, the capacity of the disk array card of some commonly used disk array cards is 64 bytes, so when the disk array card with the capacity is adopted, each cache line needs a flag bit to occupy a certain space although the capacity of the cache line can be large or small, and if the space of the cache line is too small, the cache space of data is wasted because a large number of flag bits are saved. For example: the flag bit is also a part of the cache of the disk array card, and the original capacity of one cache line is 8 bytes, so that 8 bytes correspond to one flag bit, 8 flag bits are needed to be placed in the cache, a lot of space is occupied, if the capacity of one cache line is 1 byte, 1 byte corresponds to one flag bit, and 64 flag bits are needed, which generates huge waste for the cache of the disk array card. If the capacity of the cache line is defined to be too large, only fewer cache lines are used for each disk address, so that the cache data can be updated too quickly, and the secondary reading of the data is not facilitated.

In some optional embodiments, for a scenario in which the capacity of the disk array card is 64 bytes and the capacity of the cache line is 8 bytes, the step S101 includes:

and c1, dividing the cache of the disk array card into 2 cache lines, wherein each cache line comprises 4 cache lines.

Based on step c1, step b2 comprises:

step b21, starting from the lowest bit of each disk address, setting the first bit to the third bit as offset bits, setting the fourth bit to the fifth bit as index bits, and setting the remaining bit of each disk address as flag bits.

Specifically, as shown in fig. 7, when the access amount of the user to each disk address is relatively balanced, for example, the access amount of each disk address is not too large or too small, the embodiment of the invention adopts 2 cache ways, and each cache way includes 4 cache lines. By the aid of the dividing mode, data in the cache can be stored for a longer time, the corresponding disk addresses of the cache line are not too much, the data in the cache line cannot be covered too fast, and a user can read the cache data secondarily conveniently.

In addition, according to the technical means provided by the embodiment of the invention, when the disk array card cache is divided into 2 cache ways, and each cache way comprises 4 cache lines, only two index bits are needed, so that the index bits can traverse the numbers of all the cache lines in one cache way, the aim of accurate matching is achieved, more address bits are prevented from being wasted as index bits, more adaptation scenes of the zone bits are improved, and the method is suitable for different data of different types. Therefore, according to the scheme provided by the embodiment of the invention, from the lowest bit of each disk address, the first bit to the third bit of each disk address are set as offset bits, the fourth bit to the fifth bit are set as index bits, and the rest bit of each disk address is set as a flag bit, so that the effect of accurately searching the cache data can be realized.

For example: assuming that one byte of data is read from the address 0x0654, when the data is read, if a cache line is found according to the index bit ("10" in fig. 7) in the disk address, the flag information stored in the current cache line is fetched from the flag bit area of the cache line, and the flag bit area corresponds to the cache data area one by one, and the cache data area is used for storing the cache data that needs to be read and used actually. Each cache line holds only one flag bit information, the flag bit in the disk address being the bit width of the disk address divided by the index bit and the remainder of the offset bit (the flag bit being the shaded portion in fig. 7). And comparing the flag bit information with the flag bit in the disk address, wherein if the flag bit information is equal to the flag bit in the disk address, the cache hit is indicated, and if the flag bit information is not equal to the flag bit in the disk address, the cache miss is indicated. In fig. 7, assuming that the flag bit of the disk address is 0x84, the cache line storing the 0x84 flag information is a cache hit, and the cache line storing the 0x32 flag information is a cache miss.

In addition, if the related art scheme is adopted to avoid branching the disk array cache, the effect diagram of dividing the cache line into 8 bytes and searching data from each cache line based on the setting method of the index bit, the offset bit and the flag bit can refer to fig. 8, and the lowest 3 bits (bit 0-bit 2 in fig. 8) of the address are used to represent the offset bit, so as to address a certain byte in 8 bytes. Similarly, to cover 8 lines of cache lines, 3 bits in the disk address are required to be associated with the number of each cache line (e.g., bits 3-5 in FIG. 8, so that a line of cache lines is looked up by bits 3-5, this part of the address is referred to as the index bit).

It is not difficult to find that for the disk array cache without dividing the cache way, more bits are needed for representing the index bits (3 bits are greater than 2 bits) for the corresponding disk addresses, compared with the scheme for dividing the cache way in the embodiment of the invention, one address bit is wasted as the index bit, and the adaptation scene of different types of data is reduced.

and c2, dividing the cache of the disk array card into 8 cache lines, wherein each cache line comprises 1 cache line.

Based on step c2, step b2 comprises:

step b22, starting from the lowest bit of each disk address, setting the first bit to the third bit as offset bits, setting the index bit as null, and setting the remaining bit of each disk address as flag bit.

Specifically, as shown in fig. 9, according to the technical means provided by the embodiment of the present invention, when the user accesses a small part of disk addresses in a larger amount, and other disk addresses are rarely accessed, a partition manner that 8 cache ways each include 1 cache line is adopted. By the scheme, each cache line and each disk address set can be established with a mapping relation, and the disk addresses in any disk address set can store data in any cache line. Therefore, the frequently accessed disk addresses have larger occupation rights to the cache line, so that data in the frequently accessed disk addresses can be read out more quickly, redundant occupation of the less accessed disk addresses to the cache line is reduced, and secondary reading of the data by a user is facilitated. In addition, the division mode does not need index bits, so that more bits are prevented from being wasted as index bits, more adaptation scenes of the flag bits are improved, and the method is suitable for different data of different types.

In some alternative embodiments, the cache line further includes a status flag to indicate whether the data in the cache line has been altered, and a change flag to indicate whether the data in the cache line is valid data.

Specifically, as shown in fig. 10, a status flag and a change flag are added at the beginning and the end of each cache line respectively, the status flag indicates whether the data in the cache line is valid, so that misreading of the data by the disk array controller is avoided, and the change flag indicates whether the data in the cache line is changed, so that the problem that the data is tampered maliciously and is not found is avoided.

Based on the disk array card configured in the foregoing embodiment, the embodiment further provides a method for reading a cache of a disk array card, and fig. 11 is a flowchart of a method for reading a cache of a disk array card according to an embodiment of the present invention, where the flowchart includes the following steps:

step S1101, receiving a data reading request, and responding to the data reading request to obtain a target disk address of the data to be read;

step S1102, determining at least one entry target cache line which establishes a mapping relation with a target disk address;

in step S1103, the data corresponding to the target disk address is read from at least one target cache line.

Specifically, in this embodiment, if an external program tries to sequentially access the target disk address, because the data of the target disk address may be loaded into a certain cache line of any cache way, the disk array card controller may sequentially determine, according to the target disk address of the data to be read, whether each target cache line that establishes a mapping relationship with the target disk address has corresponding cache data, and if only one of the cache lines stores the corresponding data, it will not determine that the read data is missing, so that the number of times of the missing can be significantly reduced, thereby significantly reducing the occurrence frequency of cache bump problems, and improving the cache performance of the disk array. The specific principle can refer to the related description of the foregoing embodiment of the disk array card cache configuration method, which is not repeated herein.

In an alternative embodiment, step S1102 includes:

step d1, extracting a target index bit from a target disk address;

step d2, matching the target index bit with the cache line number in each cache way to obtain a target cache line number with an association relation with the target index bit;

And d3, determining a target cache line marked by the target cache line number in each cache way.

In an alternative embodiment, step S1103 includes:

step d4, extracting a target zone bit from the target disk address;

step d5, comparing the target zone bit with zone bit information stored in each target cache line in sequence;

and d6, when the bit zone information in the current target cache line is consistent with the target bit zone comparison, reading the data corresponding to the target disk address from the current target cache line.

In an alternative embodiment, step d6 includes:

step d7, extracting a target offset bit from the target disk address;

step d8, starting from the lowest bit of the cache data area in the current target cache line, searching to the high bit according to the target offset bit, and obtaining the target data byte position;

step d9, reading the corresponding data from the target data byte position.

Specifically, according to the technical means provided by the embodiment of the invention, when data is read, the disk array card controller can accurately position which cache lines and the current disk address have a mapping relation according to the index bit, so that the target cache line is determined, and the accuracy of cache line searching is ensured. And then determining which cache data in the cache line is the real corresponding data in the current disk address according to the target flag bit, and then counting from the lowest bit of the cache data area in the current target cache line to the high bit according to the target offset bit, so as to determine which byte of data is specifically read by the read request, thereby obviously improving the flexibility and accuracy of data reading. The principle of data reading in the steps d1 to d9 may refer to the related description of the foregoing embodiment of the disk array card cache configuration method, which is not repeated herein.

In some optional embodiments, step S1103 described above further includes:

and e1, when the zone bit information in each target cache line is inconsistent with the target zone bit comparison, reading corresponding data from the position of the target disk address in the redundant array of independent disks, and putting the read data into one target cache line.

Step e1 includes:

step e11, after reading the corresponding data from the position of the target disk address in the redundant array of independent disks, acquiring a data writing sequence, wherein the data writing sequence is used for representing a preset sequence of alternately writing the cache data into each target cache line;

step e12, determining the target cache line to which the cache data should be written at this time from all target cache lines according to the bit sequence of the target cache line to which the cache data is written last time in the data writing sequence;

and e13, placing the read data into a target cache line which should be written with the cache data.

Specifically, in the embodiment of the invention, when the disk array controller finds that the data corresponding to the target disk address is not cached in each target cache line corresponding to the target disk address, the disk array controller needs to read the corresponding data from the corresponding disk address and store the corresponding data in one target cache line with a mapping relation, so that the next reading of the data in the cache is facilitated to a certain extent, and the quick reading of the data can be realized.

In addition, in order to avoid that the read data is covered too fast, a strategy of alternately writing is adopted when each cache line stores the data, so that the data writing sequence is pre-deployed in each cache line and is used for indicating a preset sequence of alternately writing the cache data into each target cache line. Based on this, in this embodiment, according to the bit sequence of the target cache line of the last time of writing the cache data in the data writing sequence, the target cache line of the cache data to be written at this time is determined from all the target cache lines, and then the data to be cached at this time is written into the target cache line of the cache data to be written at this time. Only after each cache line is written once, new data is written in a mode that the new data covers old data of each cache line, so that the problem of cache jolt is further reduced.

In other alternative embodiments, step e1 above includes:

and f1, after reading corresponding data from the position of the target disk address in the redundant array of independent disks, judging a data storage process corresponding to the target disk address according to the disk address set where the target disk address is located, wherein the data storage process comprises a first process and a second process, the first process is used for managing the disk address set with the even number of the head address, and the second process is used for managing the disk address set with the odd number of the head address.

And f2, acquiring a data writing sequence, wherein the data writing sequence is used for representing a preset sequence of alternately writing the cache data into each target cache line.

And f3, determining the target cache line which should be written with the cache data at this time from all target cache lines according to the bit sequence of the target cache line which is written with the cache data at last time in the data writing sequence.

And f4, putting the read data into a target cache line which should be written with the cache data through the first process or the second process.

Specifically, in the embodiment of the present invention, in order to avoid that the data read at this time is covered too fast, a policy of alternately writing is adopted when each cache line stores the data, so that each cache line is pre-deployed with a data writing sequence, and the data writing sequence is used for indicating a preset sequence of alternately writing the cache data into each target cache line. Based on this, in this embodiment, according to the bit sequence of the target cache line of the last time of writing the cache data in the data writing sequence, the target cache line of the cache data to be written at this time is determined from all the target cache lines, and then the data to be cached at this time is written into the target cache line of the cache data to be written at this time. Only after each cache line is written once, new data is written in a mode that the new data covers old data of each cache line, so that the problem of cache jolt is further reduced.

The embodiment also provides a device for configuring cache of a disk array card, which is used for implementing the foregoing embodiments and preferred embodiments, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

The embodiment provides a disk array card cache configuration device, as shown in fig. 12, where the device includes:

The buffer circuit dividing module 1201 is configured to divide the disk array card buffer into a plurality of buffer circuits, where each buffer circuit is divided into the same number of buffer lines;

the cache way mapping module 1202 is configured to establish a mapping relationship for each cache way and each disk address set, where a mapping relationship is established between a current cache way and each disk address set through multiple rounds of establishment tasks, the current cache way is a cache way currently being established with each disk address set, in each round of establishment tasks, a disk address set that is not repeated is allocated to each cache line in the current cache way in sequence, and the disk address sets allocated between the rounds of establishment tasks are not repeated until all disk address sets are allocated to the current cache way.

In some optional embodiments, the cache way mapping module 1202 includes:

the address ordering unit is used for generating a disk address set sequence according to the addressing sequence of each disk address set;

the cache line sequencing unit is used for sequencing the cache lines in the current cache way to obtain a cache line sequence;

an alignment unit, configured to align one end of the cache line sequence and one end of the disk address set sequence;

the mapping unit is used for selecting the same number of disk address sets from one aligned end of the disk address set sequence according to the number of cache lines in the cache line sequence, and mapping each selected disk address set into each cache line according to a one-to-one corresponding position relation;

And the sliding unit is used for sliding the cache line sequence to the other end which is not aligned according to the number of the cache lines in the cache line sequence, returning to the step of selecting the same number of disk address sets, and mapping each selected disk address set into each cache line according to a one-to-one corresponding position relation until all disk address sets in the disk address set sequence are mapped.

In some optional implementations, this embodiment provides a disk array card cache configuration apparatus, further including:

a numbering unit, configured to set numbers for cache lines in each cache way according to the same numbering rule;

the characteristic bit setting unit is used for setting offset bits, index bits and flag bits for the disk addresses in the disk address sets, wherein the corresponding relation established between the disk address sets and the cache lines is represented by the association relation between the index bits of the disk addresses and the cache line numbers; when the data of the target disk address is read, the offset bit is used for determining the position of the read data byte in the cache line, the index bit is used for matching with the serial number of the cache line to determine the position of the read cache line, and the flag bit is used for comparing with the flag bit information stored in the cache line to verify that the data cached in the cache line is the data of the target disk address.

The embodiment also provides a device for reading the cache of the disk array card, which is used for realizing the above embodiment and the preferred implementation, and the description is omitted herein. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

The embodiment provides a disk array card cache reading device, as shown in fig. 13, the device includes:

a target disk address module 1301, configured to receive a data read request, and obtain a target disk address of data to be read in response to the data read request;

a target cache line matching module 1302, configured to determine at least one target cache line that has a mapping relationship with the target disk address;

the data reading module 1303 is configured to read data corresponding to the target disk address from at least one target cache line.

In some alternative embodiments, the target cache line matching module 1302 includes:

an index bit extraction unit for extracting a target index bit from a target disk address;

The index bit matching unit is used for matching the target index bit with the cache line number in each cache way to obtain a target cache line number with an association relation with the target index bit;

and the target cache line locating unit is used for determining a target cache line marked by the target cache line number in each cache way.

In some alternative embodiments, the data reading module 1303 includes:

the flag bit extraction unit is used for extracting a target flag bit from a target disk address;

the zone bit matching unit is used for comparing the target zone bit with zone bit information stored in each target cache line in sequence;

and the data extraction unit is used for reading the data corresponding to the target disk address from the current target cache line when the zone bit information in the current target cache line is consistent with the target zone bit comparison.

In some optional embodiments, the data extraction unit includes:

a bias bit extraction unit for extracting a target bias bit from a target disk address;

the offset matching unit is used for counting from the lowest bit of the cache data area in the current target cache line to the high bit according to the target offset;

and the data extraction subunit is used for reading the corresponding data according to the data byte position represented by the statistical result.

In some alternative embodiments, the data reading module 1303 further includes:

and the cache data storage unit is used for reading corresponding data from the position of the target disk address in the redundant array of independent disks and placing the read data into one target cache line when the zone bit information in each target cache line is inconsistent with the target zone bit comparison.

In some alternative embodiments, the cache data storing unit includes:

the sequence acquisition unit is used for acquiring a data writing sequence, wherein the data writing sequence is used for representing a preset sequence for alternately writing the cache data into each target cache line;

the sequence determining unit is used for determining the target cache line which should be written with the cache data at this time from all target cache lines according to the bit sequence of the target cache line which is written with the cache data at the last time in the data writing sequence;

and the cache data storage subunit is used for placing the read data into a target cache line which should be written with the cache data.

Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.

The disk array card cache configuration apparatus and the disk array card cache reading apparatus in this embodiment are presented in the form of functional units, where the units refer to ASIC (Application Specific Integrated Circuit ) circuits, processors and memories that execute one or more software or firmware programs, and/or other devices that can provide the above functions.

Referring to fig. 14, fig. 14 is a schematic structural diagram of a disk array card according to an alternative embodiment of the present invention. The disk array card includes: the system comprises a disk array card controller, a disk array card cache, a disk group, a monitoring module, a processor, a network interface and a firmware unit, wherein the processor is in communication connection with an external host, the firmware unit is in communication connection with the processor, the processor is in communication connection with the disk array card controller, the disk array card controller is in communication connection with the disk array card cache, the disk group and the monitoring module respectively, computer instructions are stored in the disk array card controller, and the method provided by the embodiment of the method is executed by executing the computer instructions.

In the embodiment of the present invention, in fig. 15, the host system is connected to the storage system through a Wide Area Network (WAN), a regional network, a wireless WIFI connection, a Storage Area Network (SAN), a Local Area Network (LAN), and the like, where the host system may be a printer, a notebook computer, a peripheral device, a workstation, a server, and the like, and the storage resources in the storage system are shared among the plurality of host systems through an optical fiber cable or a limited network, a wireless network, and the like. The network may include a wired network or a plurality of wireless networks, one network may be connected to other external networks through a switch, a storage system is formed by a plurality of disk array cards, and a plurality of storage systems may be connected to each other through a fibre channel over ethernet (FCoE), ethernet, iSCSI, fibre channel, etc. to form a large storage environment. It should be noted that the number and types of switches, host systems, servers, networks, and storage systems are not limited to the devices shown in fig. 15. For example, the disk array card shown in FIG. 15 is made up of three disk groups, including RAID0, RAID5, and RAID6. In practical use, the storage capacity of the disk array card is very large, and normally hundreds of disks form tens or hundreds of disk groups with different levels. The disk array card in the embodiment of the invention comprises a monitoring module, a processor, a network interface and a firmware unit besides a disk array card cache, a disk array card controller and a disk group.

Firmware units include drivers, disk array card kernels and file systems, etc., which can provide access to files and logical unit numbers LUNs and management of these functions. A driver and processor in the firmware unit execute some program instructions for handling host I/O requests.

The processor is a processor for communicating I/O with the host, and interacts with the host, the difference being that the disk array controller is used solely for processing the read-write logic of the disk array, the processor and the disk array controller do not interfere with each other. The network interface is used for the disk array card to access the network, and the stripe management hardware module is used for managing the positions and the number of stripes in the disk group, for example, stripe 0-stripe 9 in fig. 15, and the stripe units are represented. The engine accelerating hardware module, also called as a hardware accelerator, is a special accelerating chip/module which is used for replacing a CPU to complete complex and time-consuming high-power operation, and the process does not need or only needs a small amount of processors to participate. The monitoring module is used for monitoring abnormal problems of the disk array card.

The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.

Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.

Claims

1. The method for configuring the cache of the disk array card is characterized by comprising the following steps:

dividing the cache of the disk array card into a plurality of cache lines, wherein each cache line is divided into the same number of cache lines;

establishing a mapping relation between a current cache way and each disk address set through multiple rounds of establishment tasks, wherein the current cache way is the cache way which is currently establishing the mapping relation with each disk address set, in each round of establishment tasks, the disk address sets which are sequentially allocated to each cache line in the current cache way are not repeated, and the disk address sets which are allocated among the rounds of establishment tasks are not repeated;

and taking the next cache way as the current cache way, and repeatedly executing the step of establishing the mapping relation between the current cache way and each disk address set through multiple rounds of establishment tasks until each cache way and each disk address set establish the mapping relation so as to complete the cache configuration of the disk array card.

2. The method of claim 1, wherein establishing a mapping relationship for the current cache way and each set of disk addresses through multiple rounds of set-up tasks comprises:

generating a disk address set sequence according to the addressing sequence of each disk address set;

sequencing the cache lines in the current cache way to obtain a cache line sequence;

aligning one end of the cache line sequence and one end of the disk address set sequence;

and starting from one aligned end of the disk address set sequence, taking the number of cache lines in the cache line sequence as the width of a sliding window, sliding the sliding window by taking the number of the cache lines as the sliding step length of the sliding window, selecting disk address sets with the same number as the width of the sliding window from the disk address set sequence before each sliding, and mapping each selected disk address set into each cache line according to a one-to-one corresponding position relation until all disk address sets in the disk address set sequence are mapped.

3. The method of claim 1, wherein cache lines in each cache way are provided with corresponding numbers according to the same number rule, and disk addresses in each disk address set are provided with offset bits, index bits and flag bits, wherein a mapping relation established between the disk address sets and the cache lines is represented by an association relation between the index bits of the disk addresses and the cache line numbers;

When the data of the target disk address is read, the offset bit is used for determining the read data byte position in the cache line, the index bit is used for being matched with the serial number of the cache line to determine the read cache line position, and the flag bit is used for being compared with the flag bit information stored in the cache line to verify that the data cached in the cache line is the data of the target disk address.

4. The method of claim 3, wherein dividing the cache line into a plurality of cache ways when the capacity of the disk array card cache is 64 bytes, each cache way being divided into the same number of cache lines, comprises:

and dividing the cache of the disk array card into 2 cache lines, wherein each cache line comprises 4 cache lines.

5. The method of claim 4, wherein the offset bit, index bit, flag bit are set for the disk address by:

starting from the lowest bit of each disk address, setting the first bit to the third bit as the offset bit, setting the fourth bit to the fifth bit as the index bit, and setting the remaining bit of each disk address as the flag bit.

6. The method of claim 3, wherein dividing the cache line into a plurality of cache ways when the capacity of the disk array card cache is 64 bytes, each cache way being divided into the same number of cache lines, comprises:

and dividing the disk array card cache into 8 cache ways, wherein each cache way comprises 1 cache line.

7. The method of claim 6, wherein the offset bit, index bit, flag bit are set for the disk address by:

starting from the lowest bit of each disk address, setting the first bit to the third bit as the offset bit, setting the index bit to be null, and setting the remaining bit of each disk address as the flag bit.

8. The method of claim 1 or 7, wherein the cache line includes a status flag and a change flag, the change flag being used to indicate whether data in the cache line has been changed, the status flag being used to indicate whether data in the cache line is valid data.

9. The method for reading the cache of the disk array card is characterized by being applied to the disk array card configured by the disk array card cache configuration method according to any one of claims 1-8, and the method comprises the following steps:

Receiving a data reading request, and responding to the data reading request to acquire a target disk address of data to be read;

determining at least one entry target cache line establishing a mapping relation with the target disk address;

and reading data corresponding to the target disk address from at least one target cache line.

10. The method of claim 9, wherein said determining at least one target cache line that has a mapping relationship with the target disk address comprises:

extracting a target index bit from the target disk address;

matching the target index bit with the cache line number in each cache way to obtain a target cache line number with an association relation with the target index bit;

the target cache line marked by the target cache line number is determined in each cache way.

11. The method of claim 10, wherein the reading the data corresponding to the target disk address from at least one of the target cache lines comprises:

extracting a target zone bit from the target disk address;

comparing the target zone bit with zone bit information stored in each target cache line in sequence;

And when the bit zone information in the current target cache line is consistent with the target bit zone comparison, reading the data corresponding to the target disk address from the current target cache line.

12. The method of claim 11, wherein reading data corresponding to the target disk address from a current target cache line when tag information in the current target cache line is consistent with the target tag comparison, comprises:

extracting a target offset bit from the target disk address;

starting from the lowest bit of a cache data area in the current target cache line, searching to the high bit according to the target offset bit, and acquiring a target data byte position;

and reading corresponding data from the target data byte position.

13. The method of claim 11, further comprising, when the tag information in each of the target cache lines is inconsistent with the target tag alignment:

and reading corresponding data from the position of the target disk address in the redundant array of independent disks, and placing the read data into a target cache line.

14. The method of claim 13, wherein reading the corresponding data from the location of the target disk address in the redundant array of independent disks and placing the read data into a target cache line comprises:

After corresponding data is read from the position of the target disk address in the redundant array of independent disks, a data writing sequence is obtained, wherein the data writing sequence is used for representing a preset sequence of alternately writing cache data into each target cache line;

determining the target cache line which should be written with the cache data at this time from all the target cache lines according to the bit sequence of the target cache line which is written with the cache data at the last time in the data writing sequence;

and placing the read data into the target cache line which should be written with the cache data at the time.

15. The method of claim 13, wherein reading the corresponding data from the location of the target disk address in the redundant array of independent disks and placing the read data into a target cache line comprises:

after corresponding data is read from the position of the target disk address in the redundant array of independent disks, judging a data storage process corresponding to the target disk address according to a disk address set where the target disk address is located, wherein the data storage process comprises a first process and a second process, the first process is used for managing the disk address set with the even number of the head address, and the second process is used for managing the disk address set with the odd number of the head address;

Acquiring a data writing sequence, wherein the data writing sequence is used for representing a preset sequence of alternately writing cache data into each target cache line;

and the read data is put into the target cache line which should be written with the cache data through the first process or the second process.

16. A disk array card cache configuration apparatus, the apparatus comprising:

the cache way dividing module is used for dividing the cache of the disk array card into a plurality of cache ways, and each cache way is divided with cache lines with the same quantity;

the cache way mapping module is used for establishing a mapping relation for each cache way and each disk address set, wherein the mapping relation is established for the current cache way and each disk address set through a plurality of rounds of establishment tasks, the current cache way is the cache way which is currently establishing the mapping relation with each disk address set, in each round of establishment tasks, a disk address set which is not repeated is sequentially allocated for each cache line in the current cache way, and the disk address sets allocated among the rounds of establishment tasks are not repeated until all the disk address sets are allocated to the current cache way.

17. A disk array card cache reading device, which is applied to a disk array card configured by the disk array card cache configuration method according to any one of claims 1 to 8, the device comprising:

the target disk address module is used for receiving a data reading request and responding to the data reading request to acquire a target disk address of data to be read;

the target cache line matching module is used for determining at least one target cache line which establishes a mapping relation with the target disk address;

and the data reading module is used for reading the data corresponding to the target disk address from at least one target cache line.

18. A disk array card for performing the method of any one of claims 1 to 15.

19. The disk array card of claim 18, comprising: the method of any one of claims 1 to 15 is carried out by a disk array card controller, a disk array card cache, a disk group, a monitoring module, a processor, a network interface and a firmware unit, wherein the processor is in communication connection with an external host, the firmware unit is in communication connection with the processor, the processor is in communication connection with the disk array card controller, the disk array card controller is in communication connection with the disk array card cache, the disk group and the monitoring module respectively, and computer instructions are stored in the disk array card controller and executed by executing the computer instructions.

20. A computer readable storage medium having stored thereon computer instructions for causing a computer to perform the method of any one of claims 1 to 15.