CN117149067A - Chip storage method and chip storage system - Google Patents
Chip storage method and chip storage system Download PDFInfo
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- CN117149067A CN117149067A CN202311056961.XA CN202311056961A CN117149067A CN 117149067 A CN117149067 A CN 117149067A CN 202311056961 A CN202311056961 A CN 202311056961A CN 117149067 A CN117149067 A CN 117149067A
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 230000002035 prolonged effect Effects 0.000 abstract description 4
- 238000013500 data storage Methods 0.000 abstract description 2
- 238000007726 management method Methods 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/0644—Management of space entities, e.g. partitions, extents, pools
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
Abstract
The invention discloses a chip storage method and a chip storage system, wherein the chip storage method comprises the following steps: receiving a data writing request, wherein the data writing request comprises a storage area number and data content corresponding to a storage sequence; the number of digits of the stored sequence is N; sequentially distributing empty storage areas from the first sequence table to data contents, and recording the corresponding relation between the corresponding first serial numbers and the storage area numbers to form recorded data; the number of digits of the first sequence table is M, and M is more than N; updating the second sequence table according to the newly allocated storage area and the released storage area; the number of digits in the second sequence table is M; and judging whether all the empty storage areas of the first sequence list are allocated, if so, assigning all the values of the second sequence list to the first sequence list. According to the invention, the storage sequences, the first sequence table and the second sequence table are utilized to reasonably manage the storage areas in the chip, so that the rapid damage of the first storage areas in the chip caused by orderly writing data and erasing data in the traditional data storage method can be effectively avoided, and the service life of the storage chip can be prolonged.
Description
Technical Field
The present invention relates to the field of chip memory technologies, and in particular, to a chip memory method and a chip memory system.
Background
Memory chips are important data storage devices whose lifetime is related to the security of the stored data, and thus, the reliability of the memory chips is an important consideration for users. In the prior art, a read-write management mechanism for a memory chip is generally set to be simpler, namely, the memory chip is sequentially stored, data is sequentially erased when a memory space is recovered, and the data is sequentially written again when the data is written next time, so that the management mode is easy to cause that the erasing times of a former part of memory area in the chip are large, and the erasing times of a latter part of memory area are small, so that the memory area can be damaged rapidly, the service life of the chip is seriously influenced, and the read-write management of the chip is necessary to improve the service life of the chip.
Disclosure of Invention
The invention aims to: in order to overcome the defects in the prior art, the invention provides a chip storage method and a chip storage system which can reasonably allocate the storage space inside a chip so as to prolong the service life of the chip.
The technical scheme is as follows: to achieve the above object, the chip storage method of the present invention includes:
receiving a data writing request, wherein the data writing request comprises a storage area number and data content corresponding to a storage sequence; the number of digits of the storage sequence is N;
sequentially distributing empty storage areas from the first sequence table to the data content, and recording the corresponding relation between the corresponding first serial number and the storage area number to form recorded data; the number of digits of the first sequence table is M, and M is more than N;
updating the second sequence table according to the newly allocated storage area and the released storage area; the number of digits of the second sequence table is M;
and judging whether all the empty storage areas of the first sequence list are allocated, if so, giving all the values of the second sequence list to the first sequence list.
Further, each storage area number of the first sequence table is 0 or 1, wherein a digit corresponding to the allocated storage area is 1, and a digit corresponding to the unallocated storage area is 0;
the sequentially allocating the empty storage areas from the first sequence table to the data content, and recording the corresponding relation between the corresponding first serial number and the storage area number to form record data comprises the following steps:
allocating a storage area corresponding to a digit with a value of 0 in the first sequence table to the data content, and allocating the digit to a position 1;
and recording the corresponding relation between the first serial number corresponding to the digit and the storage area code.
Further, each storage area number of the second sequence table is 0 or 1;
and updating the second sequence table according to the newly allocated storage area and the released storage area, wherein the updating comprises the following steps:
synchronously setting 1 the digits corresponding to the positions in the second sequence table while updating the digits in the first sequence table;
judging whether the storage area numbers in the storage sequence meet preset conditions, if so, entering the next step; the preset conditions are as follows: the original storage area code has corresponding storage data and is covered by new data content;
obtaining a first serial number corresponding to the storage area code by inquiring record data;
and searching a corresponding digit in the second sequence table according to the first sequence number, and setting the digit at 0.
Further, after the allocating the empty storage areas to the data contents sequentially from the first sequence table, the method further includes:
and recording the first serial number corresponding to the allocated empty storage area at a position corresponding to the storage area code in the storage sequence.
A chip memory system, comprising:
the receiving module receives a data writing request, wherein the data writing request comprises a storage area number and data content corresponding to a storage sequence; the number of digits of the storage sequence is N;
the first processing module sequentially allocates empty storage areas to the data content from the first sequence table and records the corresponding relation between the corresponding first serial numbers and the storage area numbers to form record data; the number of digits of the first sequence table is M, and M is more than N;
the second processing module updates a second sequence table according to the newly allocated storage area and the released storage area; the number of digits of the second sequence table is M;
and the third processing module is used for judging whether all the empty storage areas of the first sequence list are allocated, and if so, giving all the values of the second sequence list to the first sequence list.
The beneficial effects are that: in the chip storage method and the chip storage system, the write-in request received by the system is requested according to the storage area code of the storage sequence, and the system allocates the storage area according to the first sequence table and correspondingly stores the storage area, because M is larger than N, the storage chip always has a spare storage area, the second sequence table updates data according to the released storage area in real time, and when the condition is met, the data of the second sequence table is copied to the first sequence table to cover the data of the first sequence table, and the information of the spare storage area can be shared to the first sequence table in time, so that the storage method can continuously run. By the method, all the storage areas can be written with data and recovered in turn, and the first storage areas in the chip are prevented from being damaged rapidly due to the fact that the data are written in sequence and erased each time, so that the service life of the storage chip can be prolonged.
Drawings
FIG. 1 is a flow chart of a chip storage method;
fig. 2 is a schematic diagram of the structure of a chip memory system.
Detailed Description
The invention will be further described with reference to the accompanying drawings.
The chip storage method is used for managing data writing into a storage chip, and divides the internal storage space of the storage chip into a plurality of storage areas, as shown in fig. 1, and comprises the following steps S101-S104:
step S101, receiving a data writing request, wherein the data writing request comprises a storage area number and data content corresponding to a storage sequence; the number of digits of the storage sequence is N;
step S102, sequentially allocating empty storage areas to the data content from a first sequence table, and recording the corresponding relation between the corresponding first serial number and the storage area number to form record data; the number of digits of the first sequence table is M, and M is more than N;
step S103, updating the second sequence table according to the newly allocated storage area and the released storage area; the number of digits of the second sequence table is M;
step S104, judging whether all the empty storage areas of the first sequence list are allocated, if yes, assigning all the values of the second sequence list to the first sequence list.
In the above steps, the writing request received by the system is requested according to the storage area code of the storage sequence, and the system allocates the storage area according to the first sequence table and stores the storage area correspondingly, because M is larger than N, the storage chip always has a spare storage area, the second sequence table updates data according to the released storage area in real time, and when the condition is met, the data of the second sequence table is copied to the first sequence table to cover the data, and the information of the spare storage area can be shared to the first sequence table in good time, so that the storage method can run continuously. By the method, all the storage areas can be written with data and recovered in turn, and the first storage areas in the chip are prevented from being damaged rapidly due to the fact that the data are written in sequence and erased each time, so that the service life of the storage chip can be prolonged.
Preferably, each storage area number of the first sequence table is 0 or 1, wherein a digit corresponding to the allocated storage area is 1, and a digit corresponding to the unallocated storage area is 0;
in the step S102, allocating empty storage areas to the data content in sequence from the first sequence table, and recording the corresponding relationship between the corresponding first serial number and the storage area number to form record data includes the following steps S201-S202:
step S201, a storage area corresponding to a digit with a value of 0 in the first sequence table is allocated to the data content, and the digit is 1;
step S202, recording the corresponding relation between the first serial number corresponding to the digit and the storage area code.
Preferably, each storage area number of the second sequence table is 0 or 1;
the updating the second sequence table according to the newly allocated storage area and the released storage area in the above step S103 includes the following steps S301-S302:
step S301, synchronously setting 1 the digits corresponding to the positions in the second sequence table while updating the digits in the first sequence table;
step S302, judging whether a storage area code in the storage sequence accords with a preset condition, if so, entering the next step; the preset conditions are as follows: the original storage area code has corresponding storage data and is covered by new data content;
step S303, obtaining a first serial number corresponding to the storage area code by inquiring record data;
step S304, searching the corresponding digit in the second sequence table according to the first sequence number, and setting the digit at 0.
Through the above steps S301-S304, the memory areas can be released in time, so that the available memory areas are maintained at the set number all the time.
Preferably, the allocating empty memory areas sequentially from the first sequence table to the data content in step S102 further includes:
and recording the first serial number corresponding to the allocated empty storage area at a position corresponding to the storage area code in the storage sequence.
In this example, the number of memory areas is 8, and the memory sequence includes 4 memory area numbers, that is, the memory chip has 4 external memory areas (that is, the memory chip is considered to have 4 memory areas when the external system requests to store), and in fact, has 8 actual memory areas, that is, the numbers of digits included in the first sequence table and the second sequence table are both 8. For the sake of illustration, the number of memory areas in the memory chip is substantially greater than 8, and the number of digits in the memory sequence is smaller than that in the first sequence table.
In the initial state, all digits of the first sequence table and the second sequence table are 0, and all actual storage areas do not store data.
If the first four writing requests respectively request to write data into the external storage areas A1, A2, A3 and A4 of the storage sequence, the corresponding data are as follows:
when the subsequent writing of data is performed, if the storage area code selected by the 5 th writing request is A2, the system actually allocates the data content corresponding to the writing request to be stored in the actual storage area corresponding to the first serial number B5, and then, since the data corresponding to the original A2 is actually stored in the actual storage area of B2, the data of the current A2 is replaced, and the data of the B2 actual storage area is abandoned, the data of the C2 position corresponding to B2 in the second sequence table is set to 0, so as to obtain the following tables:
the storage area numbers selected by the following 6 th, 7 th and 8 th writing requests are A3, A1 and A4 respectively, and the following tables are obtained by analogy according to the rules:
at this time, all the empty storage areas corresponding to the first sequence table are allocated, an assignment program is started, and the values of the second sequence table are assigned to the first sequence table to obtain the following tables:
if the storage area number selected by the 9 th write request is A3, the following tables are obtained:
as can be seen from the above process, after all the actual storage areas are written with data, a fixed number of storage areas are always in a recycling state, so that the cyclic operation of the method can be realized. By analogy, the reasonable allocation and recovery of the storage areas can be realized, and the first storage areas in the chip are prevented from being damaged rapidly due to the fact that data are written in sequence and data are erased each time, so that the service life of the storage chip can be prolonged.
The present invention also provides a chip memory system, as shown in fig. 2, which includes:
a receiving module 401, which receives a data writing request, where the data writing request includes a storage area code and data content corresponding to a storage sequence; the number of digits of the storage sequence is N;
the first processing module 402 sequentially allocates empty storage areas to the data content from the first sequence table, and records the corresponding relation between the corresponding first serial number and the storage area number to form record data; the number of digits of the first sequence table is M, and M is more than N;
a second processing module 403 for updating the second sequence table according to the newly allocated memory area and the released memory area; the number of digits of the second sequence table is M;
and a third processing module 404, configured to determine whether all empty storage areas of the first sequence table are allocated, and if yes, assign all values of the second sequence table to the first sequence table.
The details of other embodiments of implementing the above-mentioned chip storage method based on the chip storage system are described in the previous embodiments, and reference may be made to the corresponding details in the previous embodiments, which are not described herein.
The foregoing is only a preferred embodiment of the invention, it being noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the invention.
Claims (5)
1. A method of chip storage, the method comprising:
receiving a data writing request, wherein the data writing request comprises a storage area number and data content corresponding to a storage sequence; the number of digits of the storage sequence is N;
sequentially distributing empty storage areas from the first sequence table to the data content, and recording the corresponding relation between the corresponding first serial number and the storage area number to form recorded data; the number of digits of the first sequence table is M, and M is more than N;
updating the second sequence table according to the newly allocated storage area and the released storage area; the number of digits of the second sequence table is M;
and judging whether all the empty storage areas of the first sequence list are allocated, if so, giving all the values of the second sequence list to the first sequence list.
2. The chip storage method according to claim 1, wherein each storage area number of the first sequence table is 0 or 1, wherein a digit corresponding to an allocated storage area is 1, and a digit corresponding to an unallocated storage area is 0;
the sequentially allocating the empty storage areas from the first sequence table to the data content, and recording the corresponding relation between the corresponding first serial number and the storage area number to form record data comprises the following steps:
allocating a storage area corresponding to a digit with a value of 0 in the first sequence table to the data content, and allocating the digit to a position 1;
and recording the corresponding relation between the first serial number corresponding to the digit and the storage area code.
3. The chip storage method according to claim 2, wherein each storage area number of the second sequence table is 0 or 1;
and updating the second sequence table according to the newly allocated storage area and the released storage area, wherein the updating comprises the following steps:
synchronously setting 1 the digits corresponding to the positions in the second sequence table while updating the digits in the first sequence table;
judging whether the storage area numbers in the storage sequence meet preset conditions, if so, entering the next step; the preset conditions are as follows: the original storage area code has corresponding storage data and is covered by new data content;
obtaining a first serial number corresponding to the storage area code by inquiring record data;
and searching a corresponding digit in the second sequence table according to the first sequence number, and setting the digit at 0.
4. The chip storage method according to claim 1, wherein after sequentially allocating empty memory areas from the first sequence table to the data contents, further comprising:
and recording the first serial number corresponding to the allocated empty storage area at a position corresponding to the storage area code in the storage sequence.
5. A chip memory system, comprising:
a receiving module (401) for receiving a data writing request, wherein the data writing request comprises a storage area number and data content corresponding to a storage sequence; the number of digits of the storage sequence is N;
the first processing module (402) sequentially allocates empty storage areas to the data content from the first sequence table, and records the corresponding relation between the corresponding first serial numbers and the storage area numbers to form record data; the number of digits of the first sequence table is M, and M is more than N;
a second processing module (403) for updating the second sequence table based on the newly allocated memory area and the released memory area; the number of digits of the second sequence table is M;
and a third processing module (404) for judging whether all the empty storage areas of the first sequence list are allocated, and if so, assigning all the values of the second sequence list to the first sequence list.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311056961.XA CN117149067A (en) | 2023-08-22 | 2023-08-22 | Chip storage method and chip storage system |
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| CN202311056961.XA CN117149067A (en) | 2023-08-22 | 2023-08-22 | Chip storage method and chip storage system |
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