CN117148682A - Layout splitting method, system, equipment and storage medium - Google Patents
Layout splitting method, system, equipment and storage medium Download PDFInfo
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- CN117148682A CN117148682A CN202210571163.XA CN202210571163A CN117148682A CN 117148682 A CN117148682 A CN 117148682A CN 202210571163 A CN202210571163 A CN 202210571163A CN 117148682 A CN117148682 A CN 117148682A
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- 238000000206 photolithography Methods 0.000 description 8
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70475—Stitching, i.e. connecting image fields to produce a device field, the field occupied by a device such as a memory chip, processor chip, CCD, flat panel display
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
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Abstract
A layout splitting method, a layout splitting system, a layout splitting device and a layout splitting storage medium, wherein the layout splitting method comprises the following steps: obtaining a mask layout to be split, wherein a plurality of figures are arranged in the mask layout; splitting the mask layout into a plurality of sub mask layouts according to a layout splitting limiting rule, so that a plurality of graphs are distributed on different sub mask layouts to obtain a pre-splitting result; checking layout splitting limit rules for the plurality of sub-mask layouts to judge whether all the patterns in the sub-mask layouts meet the layout splitting limit rules; if all the patterns on the sub mask layout meet the layout splitting limit rule, taking the pre-splitting result as a final splitting result; if the graph on the sub mask layout does not meet the layout splitting limit rule, carrying out local splitting treatment on the local area of the sub mask layout which does not meet the layout splitting limit rule so as to update the pre-splitting result, and returning to execute the layout splitting limit rule check. The efficiency and accuracy of layout splitting are improved.
Description
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a layout splitting method, a layout splitting system, layout splitting equipment and a layout splitting storage medium.
Background
With the continuous development of technology, higher requirements are put on the performance and the integration level of integrated circuits, and the development, the setting and the manufacturing of integrated circuits are also rapid driving forces. In accordance with moore's law, challenges are presented to the design and fabrication process of integrated circuits. Due to the limitations of lithography (new light sources, lithography lenses, photoresists), the minimum feature size that can be achieved with a single layout has reached its limit. Following moore's law, MP (Multi-Patterning) technology is the most practical lithography process in the long term in the future in order to meet the demands of smaller feature sizes and ever-increasing performance of chips.
With the continuous increase and the increasing complexity of the design, the ultra-large-scale integrated circuit chip layout has higher and higher requirements on the resolution speed and accuracy of the EDA tool to finish the layout.
Disclosure of Invention
The problem solved by the embodiment of the invention is to provide a layout splitting method, which is beneficial to further improving the efficiency and accuracy of layout splitting.
In order to solve the above problems, an embodiment of the present invention provides a layout splitting method, including: obtaining a mask layout to be split, wherein a plurality of graphs are arranged in the mask layout; splitting the mask layout into a plurality of sub mask layouts according to layout splitting limiting rules, so that the plurality of figures are distributed on different sub mask layouts to obtain a pre-splitting result; checking layout splitting limit rules for a plurality of sub-mask layouts to judge whether all graphs in the sub-mask layouts meet the layout splitting limit rules; if all the patterns on the sub mask layout meet the layout splitting limiting rule, the pre-splitting result is used as a final splitting result; if the graph on the sub mask layout does not meet the layout splitting limit rule, carrying out local splitting treatment on a local area of the sub mask layout which does not meet the layout splitting limit rule so as to update the pre-splitting result, and returning to execute the layout splitting limit rule check, wherein the local splitting treatment is suitable for enabling the graph in the sub mask layout which does not meet the layout splitting limit rule to be distributed on different sub mask layouts.
Correspondingly, the embodiment of the invention also provides a layout splitting system, which comprises the following steps: the device comprises an acquisition module, a splitting module and a splitting module, wherein the acquisition module is used for acquiring a mask layout to be split, and a plurality of graphs are arranged in the mask layout; the splitting module is used for splitting the mask layout into a plurality of sub mask layouts according to layout splitting limiting rules, so that the plurality of graphs are distributed on different sub mask layouts to obtain a pre-splitting result; the checking module is used for checking the layout splitting limit rules of the plurality of sub-mask layouts so as to judge whether the figures in the sub-mask layouts all meet the layout splitting limit rules; the processing module is used for processing whether the patterns in the sub mask layout meet the layout splitting limit rule or not, and if the patterns on the sub mask layout meet the layout splitting limit rule, the pre-splitting result is used as a final splitting result; if the graph on the sub mask layout does not meet the layout splitting limit rule, carrying out local splitting treatment on a local area of the sub mask layout which does not meet the layout splitting limit rule so as to update the pre-splitting result, and returning to execute the layout splitting limit rule check, wherein the local splitting treatment is suitable for enabling the graph in the sub mask layout which does not meet the layout splitting limit rule to be distributed on different sub mask layouts.
Correspondingly, the embodiment of the invention also provides equipment, which comprises at least one memory and at least one processor, wherein the memory stores one or more computer instructions, and the one or more computer instructions are executed by the processor to realize the layout splitting method provided by the embodiment of the invention
Correspondingly, the embodiment of the invention also provides a storage medium which stores one or more computer instructions for realizing the layout splitting method provided by the embodiment of the invention.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a splitting method of a layout, which splits a mask layout into a plurality of sub mask layouts according to a layout splitting limit rule, so that the plurality of figures are distributed on different sub mask layouts to obtain a pre-splitting result; checking layout splitting limit rules for a plurality of sub-mask layouts to judge whether all graphs in the sub-mask layouts meet the layout splitting limit rules; and if the graph on the sub mask layout does not meet the layout splitting limit rule, carrying out local splitting treatment on the local area of the sub mask layout which does not meet the layout splitting limit rule so as to update the pre-splitting result. According to the method, the local splitting processing is carried out on the local area of the sub mask layout which does not meet the layout splitting limiting rule, so that the data processing amount is reduced, and the efficiency and the accuracy of layout splitting are improved under the condition that a plurality of graphs distributed on different sub mask layouts meet the layout splitting limiting rule.
Drawings
FIG. 1 is a flow chart of one embodiment of a method of splitting a layout of the present invention;
FIGS. 2 to 3 are schematic diagrams corresponding to steps in an embodiment of a splitting method of a layout of the present invention;
FIG. 4 is a functional block diagram of one embodiment of a split system of the layout of the present invention;
fig. 5 is a hardware configuration diagram of an embodiment of the apparatus provided by the present invention.
Detailed Description
The background technology shows that the efficiency and accuracy of the current layout splitting are required to be improved.
In order to solve the technical problems, the embodiment of the invention provides a layout splitting method. Referring to FIG. 1, a flow chart of one embodiment of a method of splitting a layout of the present invention is shown.
In this embodiment, the layout splitting method includes the following basic steps:
step S1: obtaining a mask layout to be split, wherein a plurality of graphs are arranged in the mask layout;
step S2: splitting the mask layout into a plurality of sub mask layouts according to layout splitting limiting rules, so that the plurality of figures are distributed on different sub mask layouts to obtain a pre-splitting result;
step S3: checking layout splitting limit rules for a plurality of sub-mask layouts to judge whether all graphs in the sub-mask layouts meet the layout splitting limit rules;
step S4: if all the patterns on the sub mask layout meet the layout splitting limiting rule, the pre-splitting result is used as a final splitting result;
step S5: if the graph on the sub mask layout does not meet the layout splitting limit rule, carrying out local splitting treatment on a local area of the sub mask layout which does not meet the layout splitting limit rule so as to update the pre-splitting result, and returning to execute the layout splitting limit rule check, wherein the local splitting treatment is suitable for enabling the graph in the sub mask layout which does not meet the layout splitting limit rule to be distributed on different sub mask layouts.
The embodiment of the invention provides a splitting method of a layout, which splits a mask layout into a plurality of sub mask layouts according to a layout splitting limit rule, so that the plurality of figures are distributed on different sub mask layouts to obtain a pre-splitting result; checking layout splitting limit rules for a plurality of sub-mask layouts to judge whether all graphs in the sub-mask layouts meet the layout splitting limit rules; and if the graph on the sub mask layout does not meet the layout splitting limit rule, carrying out local splitting treatment on the local area of the sub mask layout which does not meet the layout splitting limit rule so as to update the pre-splitting result. According to the method, the local splitting processing is carried out on the local area of the sub mask layout which does not meet the layout splitting limiting rule, so that the data processing amount is reduced, and the efficiency and the accuracy of layout splitting are improved under the condition that a plurality of graphs distributed on different sub mask layouts meet the layout splitting limiting rule.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with fig. 2 to 3 are described in detail below.
Referring to fig. 2, step S1 is performed: a mask layout 120 to be split is obtained, wherein a plurality of patterns 121 are arranged in the mask layout 120.
The mask layout 120 to be split provides a process basis for performing a layout splitting step subsequently.
In this embodiment, the step of obtaining the mask layout 120 to be split includes: providing an original layout, wherein the original layout is formed by multiple layers of initial layouts; and taking a layer of initial layout to be split in the original layout as a mask layout 120 to be split.
In this embodiment, the pattern 121 is used to make a mask, so that a photolithography process is performed by using the mask to form a corresponding target structure on the wafer.
Referring to fig. 3, step S2 is performed: according to the layout splitting restriction rule, the mask layout 120 is split into a plurality of sub-mask layouts 110, and the plurality of graphics 121 are distributed on different sub-mask layouts 110, so as to obtain a pre-splitting result.
Compared with the scheme of performing a photolithography process by using the mask layout 120, in the embodiment, the mask layout 120 is split into a plurality of sub-mask layouts 110, and in the subsequent semiconductor structure forming process, the plurality of sub-mask layouts 110 are used for performing a plurality of photolithography processes, so that the process window in the photolithography process is increased, and the accuracy of transferring the pattern 121 in the photolithography process is improved.
In this embodiment, according to the requirement of the process window in the photolithography process, the layout splitting restriction rule includes the minimum spacing requirement of the adjacent patterns 121 on the same layout.
In other embodiments, the layout splitting restriction rule may also be a spacing between the completely opposite patterns.
In this embodiment, the step of splitting the mask layout 120 into a plurality of sub-mask layouts 110 according to layout splitting constraint rules includes: according to the layout splitting limit rule, any pair of graphs 121 which do not meet the layout splitting limit rule in the mask layout 120 is obtained as a relation pair; determining the number of the sub mask layout 110; based on the number of sub-mask layouts 110 and the relation pair, the mask layout 120 is split into a plurality of sub-mask layouts 110, so that the patterns 121 in the same relation pair are located in different sub-mask layouts 110.
Before splitting the mask layout 120 into a plurality of sub-mask layouts 110, any pair of graphs 121 in the mask layout 120 which do not meet the layout splitting restriction rule is obtained as a relation pair according to the layout splitting restriction rule, that is, any pair of graphs 121 in the mask layout 120 which do not meet the layout splitting restriction rule is found out in advance to form a relation pair, and in the process of splitting the mask layout 120 into a plurality of sub-mask layouts 110, the running time of a splitting step can be reduced, and the layout splitting efficiency is improved.
With continued reference to fig. 3, step S3 is performed: and checking the layout splitting limit rules of the plurality of sub-mask layouts 110 to judge whether the patterns 121 in the sub-mask layouts 110 all meet the layout splitting limit rules.
In this embodiment, by checking the layout splitting restriction rule of the plurality of sub-mask layouts 110, the graph 121 in the sub-mask layout 110 that does not satisfy the layout splitting restriction rule is obtained, which is favorable for performing the subsequent local splitting processing on the graph 121 in the sub-mask layout 110 that does not satisfy the layout splitting restriction rule, and correspondingly, by performing the local splitting processing on the graph 121 in the sub-mask layout 110 that does not satisfy the layout splitting restriction rule, the probability that the graph 121 in the plurality of sub-mask layouts 110 does not satisfy the layout splitting restriction rule is also reduced.
With continued reference to fig. 3, step S4 is performed: and if all the graphs 121 on the sub-mask layout 110 meet the layout splitting limit rule, taking the pre-splitting result as a final splitting result.
Specifically, since the patterns 121 on the sub-mask layout 110 all satisfy the layout splitting restriction rule, the patterns 121 in the plurality of sub-mask layouts 110 are taken as the final splitting result.
With continued reference to fig. 3, step S5 is performed: if the pattern 121 on the sub-mask layout 110 does not meet the layout splitting restriction rule, performing local splitting processing on the local area 101 of the sub-mask layout 110 which does not meet the layout splitting restriction rule to update the pre-splitting result, and returning to perform the layout splitting restriction rule check, wherein the local splitting processing is adapted to enable the pattern 121 in the sub-mask layout 110 which does not meet the layout splitting restriction rule to be distributed on different sub-mask layouts 110.
It should be noted that, in this embodiment, the local area 101 of the sub-mask layout 110 that does not satisfy the layout splitting restriction rule is subjected to the local splitting processing, so as to reduce the data processing amount, and further improve the efficiency and accuracy of layout splitting under the condition that the multiple patterns 121 distributed on different sub-mask layouts 110 all satisfy the layout splitting restriction rule.
It should be further noted that, after the local splitting processing step, the patterns 121 that do not satisfy the layout splitting restriction rule are distributed on different sub-mask layouts 110, where the sub-mask layouts 110 are obtained from the pre-splitting result.
In this embodiment, the local splitting process includes: selecting the graph 121 which does not meet the layout splitting limit rule from the sub-mask layout 110 which does not meet the layout splitting limit rule as a conflict graph 102; determining a local area 101 based on the conflict pattern 102, the conflict pattern 102 being located in the local area 101; and splitting the graph 121 in the local area 101 according to a layout splitting limit rule, so that the graph 121 in the local area 101 is distributed on different sub-mask layouts 110.
It should be noted that, by determining the local area 101 through the conflict graph 102, in the step of performing local splitting processing, only splitting processing is performed on the graph 121 in the local area 101, so that the running time of the local splitting processing step is reduced, and meanwhile, the layout splitting efficiency is also improved.
In this embodiment, the step of determining the local area 101 based on the conflict graph 102 includes: in the sub-mask layout 110 which does not meet the layout splitting limit rule, respectively generating a plurality of sub-regions by taking the conflict graph 102 as a center; the sub-regions separated from each other are regarded as local regions 101.
In other embodiments, the step of determining the local area 101 based on the conflict graph 102 may further include generating a plurality of sub-areas in the sub-mask layout 110 that does not satisfy the layout splitting restriction rule, with the conflict graph 102 as a center, and integrating the sub-areas that overlap each other to synthesize the local area 101.
By integrating the mutually overlapped subareas to synthesize the local area 101, the frequency of carrying out local splitting treatment on the mutually overlapped subareas is reduced, so that the efficiency of layout splitting is improved.
The shape of the local area 101 includes one or more of square, rectangular, and circular. As an example, the shape of the local area 101 is square.
Specifically, the square is commonly used in the process of dividing the layout by an EDA tool, which is beneficial to improving the efficiency and accuracy of dividing the layout.
The side length D1 of the local area 101 should not be too large or too small. If the side length D1 of the local area 101 is too large, that is, the number of the graphics 121 in the local area 101 is too large, correspondingly, in the step of performing local splitting processing on the graphics 121 in the local area 101, the running time of layout splitting is increased, and the efficiency of layout splitting is reduced; if the side length D1 of the local area 101 is too small, it may be easy to cause that the local area 101 cannot completely enclose the conflict pattern 102, and the probability of occurrence of the conflict pattern 102 in the sub-mask layout 110 is increased. For this purpose, in the present embodiment, the side length D1 of the local area 101 is 3 micrometers to 5 micrometers.
In this embodiment, after determining the local area 101 based on the conflict graph 102, before splitting the graph 121 in the local area 101, the method further includes: an extension region 100 is determined based on the local region 101, the local region 101 is located inside the extension region 100, and a region where the local region 101 and the extension region 100 do not overlap is used as a buffer region 103, and the buffer region 103 surrounds the local region 101.
Specifically, the extension area 100 is determined by the local area 101, the local area 101 is located inside the extension area 100, that is, the pattern 121 of the local area 101 is separated from the pattern 121 outside the extension area 100 by the extension area 100, and in the step of performing the local splitting process on the pattern 121 in the local area 101, the probability of generating a new collision pattern 102 between the pattern 121 in the local area 101 and the pattern 121 outside the extension area 100 is reduced.
In this embodiment, the step of splitting the graph 121 in the local area 101 according to the layout splitting restriction rule includes: splitting the pattern 121 in the extension area 100, and after splitting, making the pattern 121 in the buffer area 103 still be located in the sub-mask layout 110 corresponding to the pre-splitting result.
In the process of splitting the pattern 121 in the extension area 100, the pattern 121 in the buffer area 103 is still located in the sub-mask layout 110 corresponding to the pre-splitting result, that is, the buffer area 103 plays a role of constraint, so that the probability that the pattern 121 in the buffer area 103 and the pattern 121 in the local area 101 generate a new conflict pattern 102 in the step of local splitting is reduced.
In this embodiment, the shapes of the extension area 100 and the local area 101 are square, and the distances D2 of the opposite sides of the extension area 100 and the local area 101 are equal, that is, when the distances D2 of the opposite sides of the extension area 100 and the local area 101 meet the requirement of layout splitting, the distances D2 of the opposite sides of the extension area 100 and the local area 101 are equal, so that the number of patterns in the buffer area meets the requirement of layout splitting, and in the step of splitting the patterns 121 in the extension area 100, the running time of layout splitting is reduced, and the efficiency of layout splitting is improved.
The distance D2 between the opposite sides of the extension region 100 and the local region 101 should not be too large or too small. If the distance D2 between the opposite sides of the extension area 100 and the local area 101 is too large, the patterns 121 in the extension area 100 are easy to be too much, and accordingly, in the step of splitting the patterns 121 in the extension area 100, the running time of layout splitting is increased, and the efficiency of layout splitting is reduced; if the distance D2 between the opposite sides of the extension area 100 and the local area 101 is too small, the number of patterns in the buffer area 103 is too small, and accordingly, the constraint effect of the buffer area 103 is reduced during the process of performing the local splitting process on the patterns 121 in the local area 101, so that the probability of generating new collision patterns 102 in the step of the local splitting process is increased. For this purpose, in the present embodiment, the distance D2 between the opposite sides of the extension region 100 and the local region 101 is 1 to 2 micrometers.
In this embodiment, after the local splitting process is completed, the pre-splitting result is updated, and the layout splitting restriction rule check is executed in a return manner, so as to determine whether the effect of the local splitting process meets the requirement.
Correspondingly, the local splitting treatment and the layout splitting restriction rule check are circularly carried out until the graphics in each sub mask layout meet the layout splitting restriction rule.
Correspondingly, the invention also provides a layout splitting system. FIG. 4 is a functional block diagram of one embodiment of a split system of the layout of the present invention.
In this embodiment, the layout splitting system 300 includes: an obtaining module 301, configured to obtain a mask layout to be split, where the mask layout has a plurality of graphics; a splitting module 302, configured to split the mask layout into a plurality of sub-mask layouts according to a layout splitting constraint rule, so that the plurality of graphics are distributed on different sub-mask layouts to obtain a pre-splitting result; a checking module 303, configured to perform layout splitting restriction rule checking on a plurality of the sub-mask layouts, so as to determine whether all the graphs in the sub-mask layouts meet the layout splitting restriction rule; the processing module 304 is configured to process whether all the graphics in the sub-mask layout meet a layout splitting restriction rule, and if all the graphics on the sub-mask layout meet the layout splitting restriction rule, take the pre-splitting result as a final splitting result; if the graph on the sub mask layout does not meet the layout splitting limit rule, carrying out local splitting treatment on a local area of the sub mask layout which does not meet the layout splitting limit rule so as to update the pre-splitting result, and returning to execute the layout splitting limit rule check, wherein the local splitting treatment is suitable for enabling the graph in the sub mask layout which does not meet the layout splitting limit rule to be distributed on different sub mask layouts.
The obtaining module 301 is configured to obtain a mask layout to be split.
The mask layout to be split provides a basis for the subsequent layout splitting step.
In this embodiment, the step of obtaining the mask layout to be split includes: providing an original layout, wherein the original layout is formed by multiple layers of initial layouts; and taking a layer of initial layout to be split in the original layout as a mask layout to be split.
In this embodiment, the pattern is used to make a mask, so that a photolithography process is performed by using the mask to form a corresponding target structure on the wafer.
Compared with the scheme of performing one lithography process by using the mask layout, in the embodiment, the mask layout is split into a plurality of sub-mask layouts by the splitting module 302, and in the subsequent formation process of the semiconductor structure, the plurality of sub-mask layouts are used for performing multiple lithography processes, so that the process window in the lithography process is increased, and the accuracy of graph transfer in the lithography process is improved.
In this embodiment, according to the requirement of the process window in the photolithography process, the layout splitting restriction rule includes the minimum spacing requirement of the adjacent patterns on the same layout.
In other embodiments, the layout splitting restriction rule may also be a spacing between the completely opposite patterns.
In this embodiment, the step of splitting the mask layout into a plurality of sub-mask layouts according to a layout splitting constraint rule includes: according to the layout splitting limit rule, any pair of graphs which do not meet the layout splitting limit rule in the mask layout is obtained and used as a relation pair; determining the number of the sub mask layout; based on the number of the sub mask layouts and the relation pairs, splitting the mask layout into a plurality of sub mask layouts, and enabling the graphics in the same relation pair to be located in different sub mask layouts.
Before splitting the mask layout into a plurality of sub-mask layouts, any pair of graphs which do not meet the layout splitting limit rule in the mask layout is obtained as a relation pair according to the layout splitting limit rule, namely, any pair of graph composition relation pairs which do not meet the layout splitting limit rule in the mask layout are found in advance, and in the process of splitting the mask layout into a plurality of sub-mask layouts, the running time of splitting steps can be reduced, and the layout splitting efficiency is improved.
The checking module 303 performs layout splitting restriction rule checking on a plurality of sub-mask layouts to obtain graphs which do not meet the layout splitting restriction rule in the sub-mask layouts, which is favorable for performing local splitting processing on the graphs which do not meet the layout splitting restriction rule in the sub-mask layouts, and correspondingly, performs local splitting processing on the graphs which do not meet the layout splitting restriction rule in the sub-mask layouts, thereby reducing the probability of the graphs which do not meet the layout splitting restriction rule in the sub-mask layouts.
The processing module 304 is configured to process whether all the graphics in the sub-mask layout meet a layout splitting restriction rule, and if all the graphics on the sub-mask layout meet the layout splitting restriction rule, the pre-splitting result is used as a final splitting result; and if the graph on the sub mask layout does not meet the layout splitting limit rule, carrying out local splitting treatment on the local area of the sub mask layout which does not meet the layout splitting limit rule.
According to the method, the local splitting processing is carried out on the local area of the sub-mask layout which does not meet the layout splitting limiting rule, so that the data processing amount is reduced, and the layout splitting efficiency is improved under the condition that a plurality of graphs distributed on different sub-mask layouts meet the layout splitting limiting rule.
In this embodiment, the local splitting process includes: selecting the graph which does not meet the layout splitting limit rule from the sub mask layout which does not meet the layout splitting limit rule as a conflict graph; determining a local area based on the conflict pattern, the conflict pattern being located in the local area; and splitting the graphics in the local area according to a layout splitting limit rule, so that the graphics in the local area are distributed on different sub-mask layouts.
In the step of carrying out local splitting processing, only the graphics in the local area are required to be split, so that the running time of the local splitting processing step is reduced, and the layout splitting efficiency is improved.
In this embodiment, the step of determining the local area based on the conflict graph includes: in the sub mask layout which does not meet the layout splitting limit rule, respectively generating a plurality of sub areas by taking the conflict graph as a center; and taking the mutually separated sub-areas as local areas.
In other embodiments, the step of determining the local area based on the conflict graph may further include generating a plurality of sub-areas with the conflict graph as a center in the sub-mask layout that does not satisfy the layout splitting restriction rule, and integrating the sub-areas that overlap each other to synthesize the local area.
By integrating the mutually overlapped subareas to synthesize the local area 101, the frequency of carrying out local splitting treatment on the mutually overlapped subareas is reduced, so that the efficiency of layout splitting is improved.
In this embodiment, the shape of the local area includes a square. Specifically, the square is commonly used in the process of dividing the layout by an EDA tool, which is beneficial to improving the efficiency and accuracy of dividing the layout.
In other embodiments, the shape of the partial region may further include one or both of a rectangle and a circle.
The side length of the local area should not be too large or too small. If the side length of the local area is too large, namely the number of the graphics in the local area is too large, correspondingly, in the step of carrying out local splitting treatment on the graphics in the local area, the running time of layout splitting is increased, and the efficiency of layout splitting is reduced; if the side length of the local area is too small, the local area can be easily caused to not completely enclose the conflict patterns, and the probability of occurrence of the conflict patterns in the sub-mask layout is increased. For this purpose, in this embodiment, the local area has a side length of 3 to 5 microns.
In this embodiment, after determining the local area based on the conflict pattern, before splitting the pattern in the local area, the method further includes: and determining an extension area based on the local area, wherein the local area is positioned inside the extension area, and the area where the local area and the extension area are not overlapped is used as a buffer area, and the buffer area surrounds the local area.
Specifically, the extension area is determined through the local area, the local area is located inside the extension area, namely, the pattern of the local area is separated from the pattern outside the extension area through the extension area, and in the step of carrying out local splitting processing on the pattern in the local area, the probability of generating a new conflict pattern between the pattern in the local area and the pattern outside the extension area is reduced.
In this embodiment, the step of splitting the graphics in the local area according to the layout splitting restriction rule includes: and splitting the graphics in the extension area, and after splitting, enabling the graphics in the buffer area to still be positioned in the sub-mask layout corresponding to the pre-splitting result.
In the process of splitting the graphics in the extension area, the graphics in the buffer area are still located in the sub-mask layout corresponding to the pre-splitting result, that is, the buffer area plays a role in constraint, so that the probability of generating new conflict graphics in the step of local splitting processing between the graphics in the buffer area and the graphics in the local area is reduced.
In this embodiment, the shapes of the extension area and the local area are square, and the distances between the opposite sides of the extension area and the local area are equal, that is, when the distances between the opposite sides of the extension area and the local area meet the requirement of layout splitting, the number of the graphics in the buffer area meets the requirement of layout splitting by setting the distances between the opposite sides of the extension area and the local area to be equal, and in the step of splitting the graphics in the extension area, the running time of layout splitting is reduced, and the efficiency of layout splitting is improved.
The distance between the opposite sides of the extended region and the local region should not be too large or too small. If the distance between the opposite sides of the extension area and the local area is too large, the patterns in the extension area are easy to be too many, and correspondingly, in the step of splitting the patterns in the extension area, the running time of layout splitting is increased, and the efficiency of layout splitting is reduced; if the distance between the opposite sides of the extension area and the local area is too small, the number of patterns in the buffer area is easy to be too small, accordingly, in the process of carrying out local splitting processing on the patterns in the local area, the constraint effect of the buffer area is reduced, and the probability of generating new conflict patterns in the step of local splitting processing is increased. For this purpose, in this embodiment, the distance between the opposite sides of the extended region and the local region is 1 to 2 microns.
In this embodiment, after the local splitting process is completed, the pre-splitting result is updated, and the layout splitting restriction rule check is executed in a return manner, so as to determine whether the effect of the local splitting process meets the requirement.
Correspondingly, the local splitting treatment and the layout splitting restriction rule check are circularly carried out until the graphics in each sub mask layout meet the layout splitting restriction rule.
The embodiment of the invention also provides equipment which can realize the layout splitting method provided by the embodiment of the invention through the layout splitting method in the form of a loader. An optional hardware structure of the terminal device provided in the embodiment of the present invention may be shown in fig. 5, and includes: at least one processor 01, at least one communication interface 02, at least one memory 03 and at least one communication bus 04.
In the present embodiment, the number of the processor 01, the communication interface 02, the memory 03, and the communication bus 04 is at least one, and the processor 01, the communication interface 02, and the memory 03 perform communication with each other through the communication bus 04. The communication interface 02 may be an interface of a communication module for performing network communication, such as an interface of a GSM module. The processor 01 may be a central processing unit CPU, or a specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits configured to implement embodiments of the present invention. The memory 03 may comprise a high-speed RAM memory or may further comprise a non-volatile memory (NVM), such as at least one magnetic disk memory. The memory 03 stores one or more computer instructions, and the one or more computer instructions are executed by the processor 01 to implement the layout splitting method provided by the embodiment of the present invention.
The embodiment of the invention also provides a storage medium which stores one or more computer instructions for realizing the layout splitting method provided by the embodiment of the invention.
Embodiments of the invention may be implemented by various means, such as hardware, firmware, software or combinations thereof. In a hardware configuration, the method according to the exemplary embodiments of the present invention may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, etc. In a firmware or software configuration, embodiments of the present invention may be implemented in the form of modules, procedures, functions, and so on. The software codes may be stored in memory units and executed by processors. The memory unit may be located inside or outside the processor and may send and receive data to and from the processor via various known means.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (13)
1. The layout splitting method is characterized by comprising the following steps of:
obtaining a mask layout to be split, wherein a plurality of graphs are arranged in the mask layout;
splitting the mask layout into a plurality of sub mask layouts according to layout splitting limiting rules, so that the plurality of figures are distributed on different sub mask layouts to obtain a pre-splitting result;
checking layout splitting limit rules for a plurality of sub-mask layouts to judge whether all graphs in the sub-mask layouts meet the layout splitting limit rules;
if all the patterns on the sub mask layout meet the layout splitting limiting rule, the pre-splitting result is used as a final splitting result;
if the graph on the sub mask layout does not meet the layout splitting limit rule, carrying out local splitting treatment on a local area of the sub mask layout which does not meet the layout splitting limit rule so as to update the pre-splitting result, and returning to execute the layout splitting limit rule check, wherein the local splitting treatment is suitable for enabling the graph in the sub mask layout which does not meet the layout splitting limit rule to be distributed on different sub mask layouts.
2. The splitting method of a layout according to claim 1, wherein the local splitting process comprises:
selecting the graph which does not meet the layout splitting limit rule from the sub mask layout which does not meet the layout splitting limit rule as a conflict graph;
determining a local area based on the conflict pattern, the conflict pattern being located in the local area;
and splitting the graphics in the local area according to a layout splitting limit rule, so that the graphics in the local area are distributed on different sub-mask layouts.
3. The method of splitting a layout according to claim 2, wherein the step of determining a local area based on the conflicting patterns comprises: in the sub mask layout which does not meet the layout splitting limit rule, respectively generating a plurality of sub areas by taking the conflict graph as a center;
and integrating the mutually separated subareas as local areas, and/or integrating the mutually overlapped subareas to synthesize the local areas.
4. The method of splitting a layout according to claim 2, wherein the shape of the local area comprises one or more of square, rectangle and circle.
5. The method for splitting a layout according to claim 4, wherein the shape of the local area is square, and the side length of the local area is 3 micrometers to 5 micrometers.
6. The splitting method of a layout according to any of claims 2 to 5, wherein after determining a local area based on the conflicting patterns, before splitting the patterns in the local area, the splitting method further comprises: determining an extension area based on the local area, wherein the local area is positioned inside the extension area, and a region where the local area and the extension area are not overlapped is used as a buffer area, and the buffer area surrounds the local area;
the step of splitting the graphics in the local area according to the layout splitting limit rule comprises the following steps: and splitting the graphics in the extension area, and after splitting, enabling the graphics in the buffer area to still be positioned in the sub-mask layout corresponding to the pre-splitting result.
7. The method for splitting a layout according to claim 6, wherein the shapes of the extension area and the local area are square, and the distances between opposite sides of the extension area and the local area are equal.
8. The method of splitting a layout according to claim 7, wherein the distance between opposite sides of the extended region and the local region is 1 micron to 2 microns.
9. The method of splitting a layout according to claim 1, wherein the step of splitting the mask layout into a plurality of sub-mask layouts according to a layout splitting restriction rule comprises: according to the layout splitting limit rule, any pair of graphs which do not meet the layout splitting limit rule in the mask layout is obtained and used as a relation pair;
determining the number of the sub mask layout;
based on the number of the sub mask layouts and the relation pairs, splitting the mask layout into a plurality of sub mask layouts, and enabling the graphics in the same relation pair to be located in different sub mask layouts.
10. The method of splitting a layout according to claim 1, wherein the layout splitting restriction rule includes a minimum pitch requirement of adjacent patterns on the same layout.
11. A layout splitting system, comprising:
the device comprises an acquisition module, a splitting module and a splitting module, wherein the acquisition module is used for acquiring a mask layout to be split, and a plurality of graphs are arranged in the mask layout;
the splitting module is used for splitting the mask layout into a plurality of sub mask layouts according to layout splitting limiting rules, so that the plurality of graphs are distributed on different sub mask layouts to obtain a pre-splitting result;
the checking module is used for checking the layout splitting limit rules of the plurality of sub-mask layouts so as to judge whether the figures in the sub-mask layouts all meet the layout splitting limit rules;
the processing module is used for processing whether the patterns in the sub mask layout meet the layout splitting limit rule or not, and if the patterns on the sub mask layout meet the layout splitting limit rule, the pre-splitting result is used as a final splitting result; if the graph on the sub mask layout does not meet the layout splitting limit rule, carrying out local splitting treatment on a local area of the sub mask layout which does not meet the layout splitting limit rule so as to update the pre-splitting result, and returning to execute the layout splitting limit rule check, wherein the local splitting treatment is suitable for enabling the graph in the sub mask layout which does not meet the layout splitting limit rule to be distributed on different sub mask layouts.
12. An apparatus comprising at least one memory and at least one processor, the memory storing one or more computer instructions, wherein the one or more computer instructions are executable by the processor to implement the method of splitting a layout as claimed in any one of claims 1 to 10.
13. A storage medium storing one or more computer instructions for implementing a method of splitting a layout according to any of claims 1-10.
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| CN202210571163.XA CN117148682A (en) | 2022-05-24 | 2022-05-24 | Layout splitting method, system, equipment and storage medium |
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| CN202210571163.XA CN117148682A (en) | 2022-05-24 | 2022-05-24 | Layout splitting method, system, equipment and storage medium |
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| CN117148682A true CN117148682A (en) | 2023-12-01 |
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| CN202210571163.XA Pending CN117148682A (en) | 2022-05-24 | 2022-05-24 | Layout splitting method, system, equipment and storage medium |
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