CN117148298B - A rapid testing system for multi-state amplitude and phase characteristics of transceiver channels - Google Patents

Abstract

The invention discloses a receiving and transmitting channel multi-state amplitude-phase characteristic rapid test system. The system comprises a main control computer, a state setting and testing synchronization device, a network router, a vector network analyzer and a testing cable, wherein the testing cable comprises a vector network analyzer testing cable, a state data cable, a state setting pulse cable and a testing synchronization pulse cable. The system of the invention can save a great amount of handshake waiting time, data storage and processing time and improve test efficiency.

Description

A rapid testing system for multi-state amplitude and phase characteristics of transceiver channels

Technical field

The invention belongs to the technical field of radar system testing, and specifically relates to a system for rapid testing of multi-state amplitude and phase characteristics of phased array antenna T/R transceiver channels, rapid testing of multi-state amplitude and phase characteristics of transceiver feed networks and calibration channels.

Background technique

Phased array antennas are currently the main antenna system used in many radar and satellite applications. The phased array antenna consists of many fixed antenna units, which are coherently fed through these units, and use variable phase and delay control on each unit to scan the beam to a given angle in space; at the same time, in order to shape the pattern , need to adopt amplitude control. The above phase shift, delay and amplitude control are realized by controlling the numerically controlled phase shifter, numerically controlled delay line and numerically controlled attenuator in the T/R component. After the T/R component is produced, it is necessary to test the amplitude and phase characteristics of all control states in the transmitting and receiving states of the T/R component, or after the T/R forms a feed network, it is necessary to test the transmitting and receiving paths of the feed network. The amplitude and phase characteristics of all control states are thus obtained, and the amplitude and phase base state performance and all combined state performance of the T/R component, antenna feed network transceiver channel and its calibration channel are obtained, which facilitates antenna designers to conduct pattern synthesis.

A vector network analyzer is usually used to test the amplitude and phase characteristics of the channel. Before the formal test, the test channel is first calibrated and the calibration data is saved. The vector network analyzer excitation signal power, frequency, number of test points and triggering mode settings are completed. Special test auxiliary equipment is controlled by Test the T/R channel power-on operation and set the T/R status, including transmit/receive control code, phase shift/attenuation/delay control code, vector network analyzer to test the channel amplitude and phase characteristics, save the test data, and change T in sequence /R state, complete channel amplitude and phase characteristic testing in all states. In order to improve test efficiency, computer program-controlled automatic testing is generally used. The control computer communicates with the vector network analyzer and test auxiliary equipment through a LAN or other instrument bus. The control computer sends status setting instructions to the test auxiliary equipment, and the test auxiliary equipment sets the channel under test. Working status and reply to the ready message, control the computer to control the vector network analyzer to complete a test, save the test data, and test the amplitude and phase characteristics of different states in sequence. The time required to complete the phase shift/attenuation/delay combined state amplitude and phase characteristic test of a T/R channel mainly depends on the total number of states that need to be tested.

The problem of low efficiency of existing test methods and devices when testing the amplitude and phase characteristics of a small number of transceiver channels is not very prominent. As applications put forward higher precision technical requirements for antenna directivity, pointing accuracy, pattern shape, etc. , the number of control bits for the phase shifter, delay and attenuator increases accordingly, and the number of states increases exponentially as a power of 2. When the phase shifter and attenuator are controlled with 6 bits, and the delay is controlled with 3 bits, the receiving channel has a total of 15 bits of control bits. , 32768 states; the transmit channel does not perform amplitude attenuation, has 9bits control bits, and 512 states. It is estimated that it takes 0.5 seconds to complete a state test. It takes 4-5 hours to test 32768 states of the receiving channel and 5 minutes to test 512 states of the transmitting channel. Therefore, if we consider the number of test channels required, the existing test method, which takes several hours to test each receiving channel, cannot be applied to actual engineering projects.

Analyzing existing testing methods, the reasons for low testing efficiency are as follows:

Low synchronization efficiency: The tested T/R transceiver channel status setting and startup vector network analyzer measurement are synchronized through network communication handshake. As the number of required test states increases, network communication overhead causes low test synchronization efficiency.

Data storage efficiency is low: After the instrument completes a test, the test data is calibrated and saved to a disk file. The calibration process takes time, and saving the file requires additional time overhead of interacting with the operating system. When the number of test states is large, each The time spent on data calibration processing and data storage after each test has been accumulated and greatly increased, reducing test efficiency.

Contents of the invention

Therefore, the present invention improves the above shortcomings in the following three aspects.

Optimize the settings of instrument test parameters, including the number of test points, measurement receiver bandwidth, etc., to shorten the time required for a single test while ensuring test accuracy. The shortest measured time is used as the basis for generating synchronization pulses in the status settings and test synchronization devices. Minimum time interval.

Utilizing the external trigger synchronization and Groups trigger functions of the vector network analyzer, the state setting and test synchronization device controls the device under test to change its state and simultaneously generates a pulse to trigger the vector network analyzer for a test. At the same time, the vector network analyzer triggers the test. The number of times is counted. When the count reaches the set Groups Counts, that is, the number of states, it enters the Sweep Hold state to achieve fast scanning. The main control computer ends the test task by querying when the Sweep status is Hold. This process does not require frequent handshakes and queries between the main control and the synchronization device, which improves test efficiency.

Offline data calibration. During the test process, the vector network analyzer stores the collected raw data into FIFO at high speed. After completing all state tests, the data in the FIFO is saved to a disk file. The post-processing software uniformly completes the raw test data for all channels. calibration. The number of time-consuming disk accesses during the test process is reduced to one, which greatly improves test efficiency.

The invention solves the problems of low synchronization efficiency and low efficiency of saving test data. The time to complete a 201 frequency point test is 15 ms, and the time to complete a 16384-state test of a receiving channel is shortened to 4-5 minutes, meeting the needs of engineering applications.

Therefore, the present invention proposes a rapid testing system for multi-state amplitude and phase characteristics of transceiver channels. The system includes a main control computer, a state setting and test synchronization device, a network router, a vector network analyzer, and a test cable. The test cable includes a vector network test cable, status data setting cable and status setting pulse cable and test sync pulse cable.

In the technical solution of the present invention, 1. The state setting and test synchronization device generates the state control signal and synchronous test pulse of the device under test. When testing multiple states, the state setting and measurement are synchronized through the synchronous test pulse, and the vector network analyzer measurement trigger mode is set. It is an external trigger, the measurement scan is in Groups mode, and the number of Groups is the number of states under test. When the test count reaches the number of states, the test stops and multiple state tests for one channel are completed; 2. Optimize the instrument settings and measure what is needed to complete a state test. The shortest time is used as the synchronization period of the test synchronization pulse. In this example, each state test takes 15ms to complete; 3. High-speed data storage. After the vector network analyzer completes a test, the original test data is directly saved to the FIFO. After completing all state tests, Save the original test data in the FIFO to a disk file; 4. Offline calibration, compile calibration processing and analysis software to perform calibration processing and other analysis on the multi-state test data, and obtain the base state amplitude and phase characteristic data of the transceiver channel and the amplitude and phase characteristics of each combined state data.

The invention has the following beneficial technical effects:

1. The synchronization pulse generated by the hardware is more efficient than the handshake synchronization through network communication. It takes about 15ms to complete one test, saving a lot of handshake waiting time;

2. Use FIFO to save the original test data. After all state tests are completed, the data is saved to a disk file. Compared with saving the test data to the disk each time, it saves a lot of time required for calibration processing and saving;

3. Complete calibration offline, eliminating the time required for data calibration processing for each test, and improving the test efficiency of the vector network analyzer.

Description of drawings

Figure 1 Block diagram of the rapid testing system for multi-state amplitude and phase characteristics of the transceiver channel;

Figure 2 Main control test flow chart;

Figure 3 Work flow chart of status setting and testing synchronization device;

Figure 4 Test timing diagram.

Detailed ways

In order to explain the technical solutions of the embodiments of the present invention more clearly, the drawings required to be used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and therefore do not It should be regarded as a limitation of the scope. For those of ordinary skill in the art, other relevant drawings can be obtained based on these drawings without exerting creative efforts.

The rapid testing system for multi-state amplitude and phase characteristics of the transceiver channel of the present invention includes: using the state setting and test synchronization device to set the working state of the transceiver channel under test, simultaneously sending out the test synchronization pulse, inputting it into the external trigger input port of the vector network analyzer, and starting The vector network analyzer starts testing; the cycle of the test synchronization pulse is set to the shortest test time of a single test state obtained by optimizing the parameters of the vector network analyzer; after the test starts, the state setting and test synchronization device sequentially change the working state of the tested transceiver channel and send out The test synchronization signal triggers the test and stores each test data in the high-speed FIFO; the vector network analyzer Groups Counts is set to the total number of states. When the total number of states counter reaches the total number of states required to be tested, the Sweep state of the vector network analyzer becomes Hold, stop the test; when the main control program of the main control computer queries that the vector network analyzer is in the Hold state, save the data in the FIFO to the disk file, and the test task ends. Data calibration software performs channel calibration and analysis on raw test data.

As shown in Figure 1, the rapid test system for multi-state amplitude and phase characteristics of transceiver channels includes a main control computer, status setting and test synchronization device, network router, vector network analyzer, and test cables. The test cables include Yanet test cable 1, Yanet test cable 2, status data setting cable, status setting pulse cable and test synchronization pulse cable. Among them, the main control computer, status setting and test synchronization device and vector network analyzer form a local area network. The main control computer is responsible for setting the test parameters of the vector network analyzer. The main parameters set by the vector network analyzer include: trigger mode external trigger, Groups mode, Groups counts are the total number of tests, IF bandwidth is 30kHz, and the number of test points is 201 (the number of test points can be set according to the test frequency interval requirements in the application). Execute the test process, start the state setting and test synchronization device and start working; when the total state counter is full, the vector network analyzer enters the Hold state, and the main control computer reads the FIFO data and saves it on the disk. The calibration software can be installed on any computer, read in the original test data, and obtain the amplitude and phase characteristic data of the calibration receiving channel after amplitude and phase calibration.

The main control test process is shown in Figure 2. The flow chart includes two branches: receiving channel testing and transmitting channel testing. Rapid testing using the method and system of the present invention includes the following steps:

Step 1: Vector network analyzer initialization;

Step 2: Set parameters such as excitation power, frequency, number of points, etc. on the vector network analyzer, perform calibration of the receiving/transmitting channel, and save the calibration data;

Step 3: In the receive channel status test branch, the vector network analyzer is configured in FIFO and Groups mode; in the transmit channel status test branch, the vector network analyzer is configured in pulse test mode;

Step 4: Configure the vector network analyzer for transceiver channel status test to external trigger mode;

Step 5: The main control computer shakes hands with the status setting and test synchronization device, and sends the test status number to the status setting and test synchronization device after success;

Step 6: Receive channel status test branch, set the vector network analyzer Groups counts to the number of states to be tested, wait for the state setting and test synchronization device to send and receive test synchronization pulses to start the vector network analyzer test, after completing the test of a state, the test data Written into the FIFO of the vector network analyzer, the test process is controlled by the state setting and test synchronization device until all state tests are completed; the transmit channel state test branch, the state setting and test synchronization device sends the test state number and transmits the test synchronization pulse, vector After the network analyzer receives the transmission test synchronization pulse and completes a state test, the test data is saved in the memory of the vector network analyzer. The main control computer sends this state test completion message to the state setting and test synchronization device. The state setting and test synchronization After receiving the test completion message, the device determines whether all transmission status tests have been completed. If not, it sets the next status and sends a transmission test synchronization pulse until all status tests are completed;

Step 7: In the receiving channel status test branch, the main control program queries the Sweep mode of the vector network analyzer. When it is Hold, the test ends; in the transmit channel status test branch, the status setting and test synchronization device completes all status tests and sends a test end message. ;

Step 8: In the receiving channel status test branch, read the vector network analyzer FIFO data and save the file to the disk; in the transmit channel status test branch, save the memory data to the disk file;

Step 9: In the receiving channel status test branch, use the calibration data obtained in step 2 to perform channel amplitude and phase calibration on the original data; in the transmit channel status test branch, complete the calibration during the vector network analyzer test;

Step 10: The vector network analyzer is reset and the test ends.

Figure 3 is a work flow chart of the status setting and test synchronization device. The flow chart is divided into a receiving channel test process and a receiving channel test process. The method of the present invention is used to set the working state of the device under test while sending out a test synchronization pulse and starting the vector. Network analyzer testing.

Step 1: Status setting and test synchronization device initialization;

Step 2: Wait to shake hands with the main control computer and receive the test status number;

Step 3: The receiving channel status test branch generates a status setting pulse, sends the status control data in the cache to the receiving channel under test, and synchronously generates a test synchronization pulse to the vector network analyzer; the transmit channel status test branch sets the transmit test status At the same time, it outputs the launch test synchronization pulse and notifies the main control computer to start testing;

Step 4: Receive the channel status test branch, judge whether the test count is full of the test status number, and end sending pulses when it is full; transmit the channel status test branch, judge whether the test count is full of the test status number, and stop sending pulses when it is full;

Step 5: If it is not full, receive the channel status test branch, set the pulse and test synchronization pulse delay for the test status according to the optimal test time of the vector network analyzer, set the next status, and send the next test synchronization pulse until the test End; launch channel status test branch, query the main control computer to send this test completion message, and set the next launch test status until the end of the test;

Step 6: The test ends, the status setting and test synchronization device are reset.

Figure 4 is a test sequence diagram, in which the status transmission clock, status data, status transmission enable, status setting pulse, reception control level and emission control pulse are the interface timing between the status setting and test synchronization device and the device under test, which are used to set the device under test. In the working state of the test piece, when the receiving control level is high, the channel under test is controlled to be in the receiving state; the receiving test synchronization pulse is completely synchronized with the status setting pulse, which is used to trigger the vector network analyzer to complete a receiving state test; receiving test The shortest period of the synchronization pulse and the state setting pulse is the shortest time required for the vector network analyzer to complete a single state amplitude and phase test. . The control pulse is emitted to control the transceiver conversion of the channel under test. When the level is low, it is in the transmitting state; the test synchronization pulse is emitted in synchronization with the emission control pulse, which is used to trigger the vector network analyzer to complete a transmission state test.

The status setting and test synchronization device proposed by the present invention can be an independent ground inspection equipment, or a board card inserted in the main control computer; it can form an automatic test system with the main control computer and the vector network analyzer, and the main The test can be completed under computer control, or you can manually complete the settings of the vector network analyzer, start the device, and the vector network analyzer is triggered by the synchronization pulse to complete multiple state tests.

The method and device proposed by the present invention can be used in any situation where high-efficiency testing of multiple states is required, such as testing the gain of different MGCs in the receiving channel, product performance testing on the T/R production line, etc., especially when it is necessary to test relevant indicators during temperature tests.

It is easy for those skilled in the art to understand that the above descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements, etc., made within the spirit and principles of the present invention, All should be included in the protection scope of the present invention.

Claims (4)

1. The system is characterized by comprising a main control computer, a state setting and testing synchronization device, a network router, a vector network analyzer and a testing cable, wherein the testing cable comprises a vector network testing cable, a state data setting cable, a state setting pulse cable and a testing synchronization pulse cable; the state setting and testing synchronization device generates a state control signal and a synchronous test pulse of a tested piece, the state setting and the measurement are synchronized through the synchronous test pulse during a plurality of state tests, a vector network analyzer is set to be triggered outside in a measurement triggering mode, the measurement scanning is in a Groups mode, the number of Groups is the number of the tested states, and when the test count is full of the number of the states, the test is stopped, so that a plurality of state tests of one channel are completed; measuring the shortest time required for completing one-time state test as the synchronization period of the test synchronization pulse; the method comprises the steps of storing high-speed data, directly storing original test data into a FIFO after a vector network analyzer completes one-time test, and storing the original test data in the FIFO into a disk file after all state tests are completed; calibration processing analysis software is compiled to perform calibration processing and other analysis on the multi-state test data, so as to obtain the base state amplitude-phase characteristic data and the combined state amplitude-phase characteristic data of the receiving and transmitting channels;

the system for rapidly testing the multi-state amplitude-phase characteristics of the receiving and transmitting channels adopts a testing method which comprises the following steps:

step 1: initializing a vector network analyzer;

step 2: setting excitation power, frequency and point parameters by a vector network analyzer, calibrating a receiving/transmitting channel, and storing calibration data;

step 3: receiving a channel state test branch, wherein the vector network analyzer is configured into a FIFO (first in first out) mode and a Groups mode; transmitting a channel state test branch, wherein the vector network analyzer is configured into a pulse test mode;

step 4: the receiving and transmitting channel state test vector network analyzer is configured to be in an external trigger mode;

step 5: the main control computer handshakes with the state setting and testing synchronization device, and after success, the main control computer sends the number of testing states to the state setting and testing synchronization device;

step 6: receiving channel state test branches, setting a group count of a vector network analyzer as a state number to be tested, waiting for a state setting and test synchronization device to send and receive a test synchronization pulse to start the test of the vector network analyzer, writing test data into a FIFO of the vector network analyzer after the test of one state is completed, and controlling the test process by the state setting and test synchronization device until all state tests are completed; the state setting and testing synchronization device sends a test state number and a transmission test synchronization pulse, after the vector network analyzer receives the transmission test synchronization pulse, test data are stored in a memory of the vector network analyzer after one-time state test is completed, the main control computer sends a state test completion message to the state setting and testing synchronization device, the state setting and testing synchronization device judges whether all transmission state tests are completed after receiving the test completion message, and if not, the state setting and testing synchronization device sets the next state and sends the transmission test synchronization pulse until all the state tests are completed;

step 7: in the receiving channel state test branch, the main control program inquires a Sweep mode of the vector network analyzer, and when the mode is Hold, the test is finished; transmitting a channel state test branch, and transmitting a test ending message after the state setting and testing synchronization device completes all state tests;

step 8: in a receiving channel state test branch, reading FIFO data of a vector network analyzer and storing files to a disk; transmitting a channel state test branch, and storing memory data to a disk file;

step 9: in the receiving channel state test branch, channel amplitude and phase calibration is carried out on the original data by using the calibration data obtained in the step 2; in the transmitting channel state test branch, the calibration is completed when the vector network analyzer tests;

step 10: and resetting the vector network analyzer, and ending the test.

2. The system of claim 1, wherein the host computer, the state setting and testing synchronization device and the vector network analyzer form a local area network, and the host computer is responsible for setting the test parameters of the vector network analyzer.

3. The system of claim 1, wherein the parameters of the vector network analyzer comprise: the triggering mode is external triggering, the mode is a Groups mode, the Groups counts are the total number of tests, the IF bandwidth is 30kHz, and the number of test points is set according to the test frequency point requirement.

4. The system of claim 1, wherein the status setting and testing synchronization device is a stand alone device or a board card is plugged into the host computer.