CN117134877B - Clock recovery method and device - Google Patents
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Abstract
Embodiments of the present disclosure provide a clock recovery method and apparatus, wherein the clock recovery method includes detecting validity of received data in real time, and resetting first and second clock recovery modules if the data is determined to be invalid; pre-equalizing the effective data; calculating a first timing error by using the pre-equalized data in a first clock recovery module, and performing clock recovery on the first timing error through a first loop filter; determining whether the first clock recovery module is locked, and when the first clock recovery module is determined to be locked, calculating a second timing error at the second clock recovery module and performing clock recovery through the second loop filter; the first and second clock recovery modules are reset if the first clock recovery module remains unlocked after a first predetermined time. The clock recovery method disclosed by the invention ensures the rapid convergence and robustness of the clock recovery algorithm, and can cope with the requirement of repeated plugging of the optical module of the data center and the requirement of protection switching or switching service.
Description
Technical Field
The present disclosure relates to the field of communications technologies, and in particular, to a method and apparatus for clock recovery.
Background
With the advent of massive Data applications such as 5G, high-definition video, big Data, chat GPT, etc., the network bandwidth of a Data Center (DC) serving as a Data bearer is continuously upgraded and evolved, and the industrial energy value of the network bandwidth is gradually highlighted. In high-speed data center applications, electrical or optical connections are required through high-speed serial de-serializer (SerDes) and optical Digital Signal Processing (DSP) chips. For example, in a SerDes system based on DSP architecture, on the receiving side, the best sampling clock needs to be recovered from the received data, and the recovered clock quality is the basis for stable operation of the system.
The main side of the current mainstream optical module adopts high-speed SerDes to access service data along with the continuous improvement of the network speed no matter the optical module for long-distance backbone network transmission or the optical module for short-distance access network/data center transmission. Because the clocks of the transmitting end and the receiving end have frequency deviation and clock jitter, the system needs to recover the sampling clock from the data at the receiving end at the first time, thereby ensuring the normal chain establishment of the subsequent optical modules. Due to the convenience of operation and maintenance and lower power consumption, the application duty ratio of pluggable optical modules in a network is higher and higher. The optical module used for the high-speed data center needs to quickly build a link when accessing service signals, particularly when repeatedly plugging the optical module and the link protection switching. However, in practical applications, when the optical module is plugged into or plugged out of or switched to switch services, the problem that the link establishment time is overtime or the link cannot be established often occurs, which seriously affects the deployment of the optical module.
Disclosure of Invention
To ensure rapid recovery of clocks from data in a SerDes system, embodiments of the present disclosure provide a clock recovery method and apparatus.
According to a first aspect, embodiments of the present disclosure provide a clock recovery method, including detecting validity of received data in real time, and resetting a first clock recovery module and a second clock recovery module if it is determined that the data is invalid; pre-equalizing the effective data; calculating a first timing error by using the pre-equalized data in a first clock recovery module, and performing clock recovery on the first timing error through a first loop filter; determining whether the first clock recovery module is locked, calculating a second timing error at the second clock recovery module when the first clock recovery module is determined to be locked, and performing clock recovery on the second timing error through a second loop filter, wherein the proportion and integral factor of the second loop filter are smaller than those of the first loop filter; the first and second clock recovery modules are reset if the first clock recovery module remains unlocked after a first predetermined time.
The method firstly judges the validity of the data, avoids the interference signal or the non-data signal (such as white noise) from entering the subsequent clock recovery process, ensures the normal operation of the subsequent clock recovery process, and reduces the complexity of the pre-equalization step.
Optionally, according to an embodiment of the first aspect of the disclosure, the detecting the validity of the received data in real time comprises one or both of the following steps: detecting the amplitude or the power of the received data in real time, carrying out infinite impulse response filtering on the amplitude or the power, and setting a first indication signal to be effective when the amplitude or the power after filtering is not lower than a first threshold value; detecting the symbol jump of the received data in real time, and setting a second indication signal to be effective when the jump frequency in a second preset time is not lower than a second threshold value.
Optionally, according to an embodiment of the first aspect of the disclosure, detecting the validity of the received data in real time includes detecting an amplitude or a power of the received data in real time, and performing infinite impulse response filtering on the amplitude or the power, and setting the first indication signal to be valid when the amplitude or the power after the filtering is not lower than a first threshold; detecting symbol jump of received data in real time, and setting a second indication signal to be effective when the jump frequency in a second preset time is not lower than a second threshold value; detecting in real time a data status signal received from an upstream device of the data link, setting the third indication signal to be valid when no abnormal data status signal is received, and setting the third indication signal to be invalid when at least one abnormal data status signal is received; and when the first indication signal, the second indication signal and the third indication signal are valid, judging that the received data are valid.
In the process of judging the validity of the clock recovery module data, whether the received data is interference data can be judged by judging the amplitude, the power, the symbol jump frequency and the like of the data. In addition, whether the data is valid, for example, whether an optical LOSs of signal (LOS) signal is received or not can be further determined by determining whether the data status exception signal sent by the previous stage module of the clock recovery module is received or not.
Optionally, according to an embodiment of the first aspect of the disclosure, the pre-equalizing the valid data includes pre-equalizing using a filter with tap coefficients not higher than third order.
Optionally, according to an embodiment of the first aspect of the disclosure, determining whether the first clock recovery module is locked includes determining that the clock recovery module is locked when an absolute value of an integrated loop accumulated value of the first loop filter is not below a third threshold, and otherwise determining that the clock recovery module is not locked. Optionally, the resetting the clock recovery module includes resetting respective integrated loop accumulated values of the first loop filter and the second loop filter. Optionally, the first clock recovery module and the second clock recovery module employ different timing error algorithms.
Optionally, according to an embodiment of the first aspect of the disclosure, the first clock recovery module includes a loop filter of second order or more, and the second clock recovery module includes a loop filter of second order or more.
According to an embodiment of a second aspect of the present disclosure, there is provided a clock recovery method including: detecting the validity of the received data in real time, and resetting at least a second clock recovery module if the data is determined to be invalid; pre-equalizing the effective data; calculating a first timing error by using the pre-equalized data in a first clock recovery module, and performing clock recovery on the first timing error through a first loop filter; determining whether the clock data recovered by the first clock recovery module is valid, if so, calculating a second timing error at the second clock recovery module, and performing clock recovery on the second timing error through a second loop filter, wherein the scale factor of the second loop filter is smaller than that of the first loop filter; and resetting at least the second clock recovery module if the clock data recovered by the first clock recovery module is invalid.
Optionally, according to an embodiment of the second aspect of the disclosure, determining whether the clock data recovered by the first clock recovery module is valid includes determining whether the error signal converges according to an error signal transmitted by the equalizer and/or determining whether decoding is successful according to a decoding status transmitted by the decoder.
Optionally, according to an embodiment of the second aspect of the disclosure, resetting at least the second clock recovery module includes resetting an integrated loop accumulated value of the second loop filter.
Optionally, according to an embodiment of the second aspect of the disclosure, the first clock recovery module includes a first order loop filter, and the second clock recovery module includes a loop filter of two or more orders.
According to an embodiment of a third aspect of the present disclosure, there is provided a clock recovery apparatus including a detection module that detects validity of received data in real time, and if it is determined that the data is invalid, sends information of the data invalidation to a reset module; a pre-equalization module that receives the valid data from the detection module and performs pre-equalization processing on the valid data; a first clock recovery module including a first loop filter that receives the pre-equalized data from the pre-equalization module to calculate a first timing error, the first loop filter performing clock recovery using the first timing error; a clock recovery state determination module that determines whether a clock recovery state of the first clock recovery module is valid; a second clock recovery module including a second loop filter that receives data from the pre-equalization module to calculate a second timing error when the clock recovery state determination module determines that the clock recovery state of the first clock recovery module is valid, the second loop filter using the second timing error for clock recovery, the second loop filter having a ratio and/or an integral factor that is less than the ratio and/or the integral factor of the first loop filter; and the reset module is connected with the detection module and the clock recovery state judgment module and is used for resetting at least the second clock recovery module.
Optionally, according to the third aspect of the disclosure, the detecting the validity of the received data in real time includes detecting the amplitude or the power of the received data in real time, and performing infinite impulse response filtering on the amplitude or the power, and setting the first indication signal to be valid when the amplitude or the power after the filtering is not lower than a first threshold; or detecting the amplitude or the power of the received data in real time, carrying out infinite impulse response filtering on the amplitude or the power, setting a first indication signal to be effective when the amplitude or the power after filtering is not lower than a first threshold value, and detecting the symbol jump of the received data in real time, and setting a second indication signal to be effective when the jump frequency in a second preset time is not lower than a second threshold value; or detecting the amplitude or power of the received data in real time, and performing infinite impulse response filtering on the amplitude or power, setting the first indication signal to be active when the amplitude or power after filtering is not lower than a first threshold value, and detecting the symbol transitions of the received data in real time, setting the second indication signal to be active when the number of transitions within a second predetermined time is not lower than a second threshold value, and detecting the data status signal received from an upstream device of the data link in real time, setting the third indication signal to be active when no abnormal data status signal is received, and setting the third indication signal to be inactive when at least one abnormal data status signal is received.
Optionally, according to the second aspect of the disclosure, when the first loop filter is a loop filter of second order or more, the clock recovery state determining module determining whether the clock recovery state of the first clock recovery module is valid includes determining whether the first clock recovery module is locked, if the first clock recovery module is locked, the clock recovery state of the first clock recovery module is valid, if a first predetermined time passes, the first clock recovery module is not yet locked, and a request for the reset of the first and second clock recovery modules is issued to the reset module.
Optionally, according to the second aspect of the disclosure, when the first loop filter is a first order loop filter, the clock recovery state determining module determines whether the clock recovery state of the first clock recovery module is valid, including determining whether the error signal converges according to the error signal sent by the equalizer and/or determining whether decoding is successful according to the decoding state sent by the decoder, and if the clock recovery state of the first clock recovery module is invalid, issuing a request for resetting at least the second clock recovery module to the resetting module.
Optionally, according to a second aspect of the disclosure, the first clock recovery module includes a first timing error detection module, a first loop filter, and a first digitally controlled oscillator, and the second clock recovery module includes a second timing error detection module, a second loop filter, and a second digitally controlled oscillator, wherein the first timing error detection module and the second timing error detection module use different timing error detection algorithms.
Not all of the advantages described above need be achieved at the same time in practicing any one of the devices of the present disclosure. Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the disclosure. The objects and advantages of the disclosed embodiments may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.
FIG. 1 is a schematic flow diagram of an overall method for clock recovery according to one embodiment of the present disclosure;
FIG. 2 is a schematic flow chart of a method of determining whether clock recovered data is valid according to one embodiment of the present disclosure;
FIG. 3 is a schematic flow chart diagram of a method of clock recovery by a first clock recovery module according to one embodiment of the disclosure;
FIG. 4 is a schematic flow chart diagram of a method of determining whether a first clock recovery module is locked according to one embodiment of the present disclosure;
FIG. 5 is a schematic flow chart diagram of a method of clock recovery by a second clock recovery module according to one embodiment of the disclosure;
FIG. 6 is a schematic flow chart diagram of an overall method for clock recovery according to another embodiment of the present disclosure;
FIG. 7 is a schematic flow chart diagram of a method of determining whether clock recovered data is valid in accordance with another embodiment of the present disclosure;
FIG. 8 is a schematic flow chart diagram of a method of determining whether clock data recovered by a first clock recovery module is valid according to another embodiment of the present disclosure;
FIG. 9 is a schematic diagram of a clock recovery apparatus according to an embodiment of the disclosure;
fig. 10A and 10B are schematic structural diagrams of a first clock recovery module and a second clock recovery module, respectively, according to an embodiment of the present disclosure.
Fig. 11 is a schematic block diagram of an optical/electrical communication system.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. Various embodiments may be combined with one another to form further embodiments not shown in the following description. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.
Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like in the description and in the claims, are not used for any order, quantity, or importance, but are used for distinguishing between different elements. Likewise, the terms "a" or "an" and the like do not necessarily denote a limitation of quantity. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
Fig. 11 shows a schematic block diagram of an optical/electrical communication system. Because the clocks of the transmitting end and the receiving end have frequency deviation and clock jitter, a clock recovery device is required to recover the sampling clock from the data received by the receiving end so as to ensure the stable operation of the system and obtain a correct decoding result. The clock recovery method in this disclosure may be used for clock recovery devices using electrically or optically connected Serdes systems.
Referring to fig. 1, an embodiment of the present disclosure provides a schematic flow chart of an overall method for clock recovery. First, the validity of the data for clock recovery is detected in real time in step 10, and when the data is judged to be valid, the data is subjected to pre-equalization processing in step 30. If the data is invalid, the first and second clock recovery modules will be reset at step 20.
FIG. 2 illustrates an exemplary method of determining whether data is valid. As shown in fig. 2, in step 101, the amplitude or power of the data for clock recovery is detected in real time, the amplitude or power of the data is filtered using an infinite impulse response filter, and when the output value after the filtering is not lower than a first threshold value, the first indication signal is set to be valid, and if the output value is lower than the first threshold value, the first indication signal is set to be invalid. Here, filtering the amplitude or power may improve the accuracy of the detection. Alternatively, the infinite impulse response filter may be a first-order or a multi-order infinite impulse response filter.
In step 102, symbol transitions of the data for clock recovery are detected in real time, and if the number of transitions is not below a second threshold for a predetermined detection time, the second indicator signal is set to be active, and if it is below the second threshold, the second indicator signal is set to be inactive. In this way, abnormal data such as white noise can be prevented from entering the first clock recovery module. Optionally, the threshold range in which the first indicator signal and the second indicator signal are valid may not include the first and/or second threshold points.
In step 103, the data status signal of the upstream module (or the upstream module, such as the optical module) of the clock recovery device is detected in real time, and if no abnormal data status signal is received, the third indication signal is set to be valid, and if at least one abnormal data status signal is received, the third indication signal is set to be invalid. The data status signal herein refers to a signal sent from an upstream device of the data link regarding whether data transmission is normal, for example, an optical LOSs of signal (LOS) signal received from an optical module, or an indication signal indicating that data generated by an upstream electrical device is abnormal or invalid, to indicate whether the received data is abnormal.
When the first indication signal, the second indication signal, and the third indication signal are all valid, the data for clock recovery is determined to be valid, otherwise the data for clock recovery is determined to be invalid (step 104). Alternatively, only steps 101 or 102 may be performed, or only steps 101 and 102 may be performed to obtain the corresponding indication signal. For example, when the Serdes interface is electrically connected to the DSP chip, only step 101 may be performed; if the first indication signal is valid, it is determined that the data for clock recovery is valid. When the Serdes interface and the DSP chip are used in an optical transmission scenario, steps 101 and 102 may be performed, and when the first and second indication signals are both valid, the data is determined to be valid.
When the data is judged to be valid, the data is pre-equalized, i.e. step 30 is entered, and when the data is judged to be invalid, step 20 of resetting the first and second clock recovery modules is entered. Through the detection step, interference or abnormal data can be eliminated, and the clock recovery efficiency is improved.
Referring back to fig. 1, at step 20, the first and second clock recovery modules are reset, which may include resetting the circuits having memory functions in the first and second clock recovery modules to an initial state, such as resetting the integrated loop accumulation values of the loop filters in the first and second clock recovery modules, or resetting some other values (e.g., the proportional values of the loop filters) or all values in the clock recovery modules to initial values. When the input signal changes, an interference signal can possibly appear, the interference signal can be prevented from entering the integrating loop by resetting the loop filter, the clock recovery time is too long, and the problem that the stable operation of the system is influenced due to the fact that clock recovery cannot be normally carried out is avoided.
In step 30, low complexity pre-equalization processing is performed on the valid data. Specifically, in the present disclosure, the low-complexity pre-equalization processing refers to pre-equalization processing performed by using a filter with fewer tap coefficients, and for example, three-order and less filters may be used. In one embodiment, a simplified symbol normal modulo algorithm (herein "simplified symbol normal modulo algorithm" may refer to, for example, reducing the amount of data involved in the normal modulo algorithm in the algorithm, e.g., a sample amount that is half or more less than that of a normal modulo algorithm may be used) as the low complexity adaptive filtering algorithm. Since the validity of the data is judged before the pre-equalization process, a low-complexity filter can be adopted in the pre-equalization process to realize the effect of eliminating the inter-symbol crosstalk in the link, and a high-complexity filter is not needed.
In step 40, timing error detection and loop filtering are performed using a first clock recovery module, and clock recovery is performed quickly. Specifically, referring to fig. 3, after the data enters the first clock recovery module, timing error detection is performed on the pre-equalized data (step 401). In step 402, the detected timing error is filtered by a first loop filter of a first clock recovery module. Loop filters of second order or more may be employed and the proportional and integral factors may be chosen to be large for fast clock recovery.
The "larger value" and the "smaller value" herein may be determined according to parameters such as the operating frequency of the clock recovery module in the system, loop delay, and the like. For example, the acceptable loop bandwidth for the system is BW, where B min ≤BW≤B max . When the loop bandwidths are respectively at B min And B max Respectively calculating the scale factors of the second-order loop filter as P min And P max The integral factors are respectively I min And I max . Thus, it can be considered that the scale factor P min And (3) withThe value in between is a "smaller value"; but->To P max The value between the two is 'larger', and the integration factors are the same. Determination of larger and smaller valuesThe manner may not be limited thereto and one skilled in the art may select according to the system requirements.
Referring back to fig. 1, in step 50, it is determined in real time whether the first clock recovery module enters a locked state. Specifically, as shown in fig. 4, the third threshold may be compared to the absolute value of the integration loop accumulated value (step 501), and when the absolute value of the integration loop accumulated value is less than the third threshold (or, alternatively, less than or equal to the third threshold), the clock recovery module is determined to enter the locked state (502) and step 60 is entered, otherwise, it is determined to be in the unlocked state. If the lock is not yet locked after the predetermined time of operation (step 503), then return to step 20 to reset the first clock recovery module and the second clock recovery module.
After the first clock recovery module is locked, timing error detection and loop filtering processing is performed at the second clock recovery module, step 60. Specifically, referring to fig. 5, timing error detection is performed on the data after pre-equalization (step 601). The detected timing error is then processed by a second loop filter of a second clock recovery module, step 602. Loop filters of second order or more may be employed herein. The proportional and integral factors of the second loop filter may be smaller than the proportional and integral factors of the first loop filter. Alternatively, the proportional and integral factors of the second loop filter may be chosen to be small (for "small" see description of the first loop filter above) for stable clock recovery.
Fig. 6 shows a schematic flow chart of an overall method for clock recovery of another embodiment. The main differences between this method and the method shown in fig. 1 are steps 20A, 40A and 50A.
Step 10A is similar to step 10 shown in fig. 1 in that the validity of the data for clock recovery is detected in real time, and when the data is judged to be valid, the data is subjected to pre-equalization processing in step 30A. If the data is invalid, at least a second clock recovery module will be reset at step 20A.
A specific example of step 10A is shown in fig. 7. The detection steps shown in fig. 7 are the same as those shown in fig. 2, and the specific details of steps 101A-104A can be found in the above description of steps 101-104, and are not repeated here. Also, only the step 101A or 102A may be performed, or only the steps 101A and 102A may be performed to obtain the corresponding indication signal. When only step 101A is performed, if the first indication signal is valid, it is determined that the data for clock recovery is valid. When only steps 101A and 102A are performed, if both the first and second indication signals are valid, the data is judged to be valid.
When the data is judged to be valid, the data is pre-equalized, i.e., step 30A is entered, and when the data is judged to be invalid, step 20A of resetting at least the second clock recovery module is entered. Through the detection step, interference or abnormal data can be eliminated, and the clock recovery efficiency is improved.
At step 20A, at least the second clock recovery module is reset, which may include resetting a circuit having a memory function in the second clock recovery module to an initial state, such as resetting an integrated loop accumulated value of a loop filter in the second clock recovery module, or resetting other values (e.g., a proportional value of the loop filter) or all values in the second clock recovery module to an initial value. In addition, the scaling value or other circuitry of the loop filter of the first clock recovery module may be reset.
Step 30A is identical to step 30 shown in fig. 1, and reference is made to the description of step 30 above for specific purposes.
In step 40A, timing error detection and loop filtering are performed using a first clock recovery module, and clock recovery is performed quickly. Specifically, after the data enters the first clock recovery module, timing error detection is performed on the pre-equalized data, and the detected timing error is filtered by the first loop filter of the first clock recovery module. A first order loop filter may be used where the scale factor selects a larger value for fast clock recovery.
In step 50A, it is determined whether the clock recovered by the first clock recovery module is valid based on the signal sent by the device downstream of the clock recovery apparatus, for example, the signal sent by the equalizer or decoder shown in fig. 11 may be received. More specifically, FIG. 8 shows a schematic flow chart of a method of determining whether clock data recovered by a first clock recovery module is valid. In step 501A, an error signal of the equalizer is received in real time, a convergence indicating signal of the equalizer is set according to a comparison result of the error signal and the fourth threshold value, and/or a signal whether to be successfully decoded is obtained from the decoder as a decoding indicating signal. In this step, one indication signal may be selected from the equalizer and the decoder to set, or the two indication signals may be used as a basis for determining whether the clock data recovered by the first clock recovery module is valid. When the error signal of the equalizer is not higher (or lower) than the fourth threshold value, the convergence indicating signal is set to be effective to indicate that the error signal of the equalizer is converged, otherwise, the convergence indicating signal is set to be ineffective to indicate that the error signal is not converged. The indication signal is not limited to the above two types, and other suitable signals may be selected according to the processing condition of the downstream device.
In step 502A, it is determined whether the clock data recovered by the first clock recovery module is valid according to the indication signal obtained in step 501A. When only one of the convergence indicating signal of the equalizer and the indicating signal whether the decoding is successful is obtained in step 501A, if the obtained indicating signal is invalid, the clock data recovered by the first clock recovery module is invalid. When two or more of the above indication signals are obtained in step 501A, the clock data recovered by the first clock recovery module is valid when the indication signals are valid.
Referring back to fig. 6, when the clock data recovered by the first clock recovery module is invalid, the reset operation may be performed by returning to step 20A.
When the clock data recovered by the first clock recovery module is valid, step 60A is performed. Step 60A is the same as step 60, and the second clock recovery module performs timing error detection on the pre-equalized data, and then processes the detected timing error by the second loop filter of the second clock recovery module. Loop filters of second order or more may be employed herein. The scale factor of the second clock recovery module is smaller than the scale factor of the first clock recovery module. Alternatively, the proportional and integral factors of the second clock module may select smaller values (for "smaller values" see description of the first loop filter above) for stable clock recovery.
Fig. 9 shows a schematic structural diagram of a clock recovery apparatus according to an embodiment of the present disclosure, which includes a detection module 71, a pre-equalization module 72, a first clock recovery module 73, a clock recovery state determination module 74, a second clock recovery module 75, and a reset module 76, and the order of operations of the respective modules is shown by arrows in the figure.
The detection module 71 detects validity of the received data in real time, and if the data is judged to be invalid, sends information of the data being invalid to the reset module 76. Specifically, the detection module 71 may perform one or more of steps 101-103 as shown in FIG. 2 (or steps 101A-103A as described in FIG. 7). The detection module 71 may include an infinite impulse response filter, which may be a first order or a multi-order infinite impulse response filter, as desired. The details of steps 101-103 (or steps 101A-103A) may be found in the corresponding descriptions above, and will not be described here again. The detection module 71 may determine whether the data is valid according to the first indication signal, the first and second indication signals, or the first, second and third indication signals obtained by the detection. For example, if the detection module 71 performs step 101 (or step 101A) alone, when the first indication signal is valid, it is determined that the data is valid. If the detection module 71 performs steps 101 and 102 (or steps 101A and 102A), it determines that the data is valid when both the first indication signal and the second indication signal are valid. If the detection module 71 performs steps 101, 102, 103 (or steps 101A, 102A, 103A), it may be determined that the data is valid when all three indication signals are valid.
The reset module 76 receives signals of the detection module 71 and the clock recovery state determination module 74 to perform a reset operation. The reset module 76 may selectively reset the first clock recovery module and the second clock recovery module. According to the clock recovery method as described in fig. 1, the reset module 76 may reset the memory-function circuits of the first and second clock recovery modules to an initial state, or may reset some other values (e.g., the proportional values of the loop filter) or all values in the first and second clock recovery modules to initial values. For example, the reset module 76 resets the accumulated values of the integrated loops of the first and second loop filters, as described above with respect to step 20.
Alternatively, according to the clock recovery method as shown in fig. 6, the reset module may reset the circuit with memory function of the second clock recovery module to the initial state, or may reset some other value (for example, the proportional value of the loop filter) or all values in the second clock recovery module to the initial value. For example, the reset module 76 resets the accumulated value of the integration loop of at least the second loop filter. In addition, the reset module may also reset the scaling value or other circuitry of the loop filter of the first clock recovery module. See in particular the description of step 20A above.
The pre-equalization module 72 receives valid data from the detection module 71 and performs pre-equalization processing on the valid data. The tap coefficients of the filter of the pre-equalization module 72 may be no higher than third order and may employ a low complexity adaptive filtering algorithm, such as a simplified symbol normal modulo algorithm. The pre-equalization module 72 may perform step 30 shown in fig. 1 or step 30A shown in fig. 6.
The first clock recovery module 73 may include a first timing error detection module 901, a first loop filter 902, and a first digitally controlled oscillator 903. The first timing error detection module 901 performs timing error detection on the pre-equalized data, and may use a suitable algorithm for timing error detection, for example, MM algorithm (Mueller-Muller algorithm), bang-Bang algorithm, gardner algorithm, or the like.
The timing error after detection is input to the first loop filter 902. The first loop filter 902 may select a loop filter of first order or more. When the first loop filter 902 is a first order loop filter, its scaling factor selects a larger value for fast time recovery. When the first loop filter 902 is a loop filter of second order or more, its proportional and integral factors select larger values for fast clock recovery. As described above, the larger and smaller values may be determined according to parameters such as the operating frequency of the clock recovery module, the loop delay, etc. in the system.
The clock recovery state determination module 74 determines the clock recovery state of the first clock recovery module. When the loop filters included in the first clock recovery module are different, different indication signals may be used to determine the clock recovery state of the first clock recovery module.
When the first clock recovery module includes a loop filter of two or more orders, the clock recovery state determination module 74 may determine whether the clock recovery state is normal by detecting in real time whether the first clock recovery module 73 enters the locked state (see the explanation of step 50 shown in fig. 1 and fig. 4). More specifically, when the absolute value of the integrated loop accumulated value of the first loop filter is smaller than the third threshold (or alternatively, not smaller than the third threshold), the first clock recovery module is judged to enter the locked state, and at this time, the clock recovery state is set to be valid, and a signal determined to enter the locked state may also be used as an indication signal that the clock recovery state is valid; otherwise, judging the unlocking state. If the clock recovery state is invalid after a predetermined time, the unlock signal at this time may be used as an indication signal of the clock recovery state, and the unlock signal may be sent to the reset module, so that the reset module resets the first and second clock recovery modules.
When the loop filter included in the first clock recovery module is a first order loop filter, the clock recovery status determination module 74 may determine whether the clock data recovered by the first clock recovery module is valid by detecting a signal transmitted by a downstream device, for example, it may perform steps 501A and 502A shown in fig. 8, which may be described in detail with reference to steps 501A and 502A above. When the clock data recovered by the first clock recovery module is valid, the clock recovery state judging module sets the clock recovery state to be valid. An indication signal indicating whether the clock data is valid may be used as an indication signal of the clock recovery state.
The second clock recovery module 75 is similar in structure to the first clock recovery module 73 and includes a second timing error detection module 911, a second loop filter 912, and a second digital oscillator 913. The pre-equalized data is timing error detected by the second timing error detection module 911, and a suitable algorithm may be used for timing error detection, such as an MM algorithm (Mueller-Muller algorithm), a Bang-Bang algorithm, a Gardner algorithm, or the like. In one embodiment, the second timing error detection module may select a different timing error algorithm than the first timing error detection module, e.g., the first timing error detection module selects the Bang-Bang algorithm and the second timing error detection module selects the MM algorithm. Different algorithms and circuits may be employed at different stages according to the characteristics of the different algorithms. For example, since the initial stage of clock recovery pursues performance and rapid convergence, a Bang-Bang algorithm may be employed; after the clock recovery circuit works stably, a MM algorithm with simpler circuit can be adopted, so that the power consumption of the circuit is reduced.
The timing error after detection is input to the second loop filter 912. The second loop filter 912 may select a loop filter of second order or more. At this time, the proportional and integral factors of the loop filter may be selected to be smaller than those of the first loop filter, alternatively, smaller values of the proportional and integral factors may be selected, respectively, for stable clock recovery, and clock adjustment information is output to the subsequent module to obtain a recovered clock.
In this embodiment, the first loop filter and the second loop filter may be implemented using DLPF (digital low pass filter). When the first loop filter and the second loop filter adopt loop filters of the same structure, the first loop filter and the second loop filter may share the same hardware circuit. The various modules illustrated above may be implemented by hardware circuitry.
In practical tests, the comparison result of the clock recovery device of the present disclosure with the conventional scheme is as follows:
TABLE 1
As can be seen from the comparison result in table 1, compared with the conventional scheme, the clock recovery scheme of the present disclosure can cope with the need of repeated plugging of the optical module of the data center and the need of protection switching or switching service, and in the application of the frequently plugged optical module, the rapid convergence and robustness of the clock recovery algorithm are ensured. When the high-speed SerDes accesses service data, the clock is ensured to be recovered from the data center at the first time, so that the normal link establishment of the optical module is ensured.
The method can reduce the complexity of a clock recovery scheme by carrying out detection, pre-equalization and other processes on the data, obtains faster tracking speed, and is particularly suitable for the application of high-speed data center optical modules, such as single wave 50G and 100G and higher-speed optical modules and SerDes application.
The foregoing is merely exemplary embodiments of the present disclosure and is not intended to limit the scope of the disclosure, which is defined by the appended claims.
Claims (20)
1. A method of clock recovery comprising:
detecting the validity of the received data in real time, and resetting the first clock recovery module and the second clock recovery module if the data is determined to be invalid;
pre-equalizing the effective data;
calculating a first timing error by using the pre-equalized data in a first clock recovery module, and performing clock recovery on the first timing error through a first loop filter;
determining whether the first clock recovery module is locked, calculating a second timing error at the second clock recovery module when the first clock recovery module is determined to be locked, and performing clock recovery on the second timing error through a second loop filter, wherein the proportion and integral factor of the second loop filter are smaller than those of the first loop filter;
And resetting the first clock recovery module and the second clock recovery module if the first clock recovery module is not locked after the first preset time.
2. The clock recovery method of claim 1, wherein the detecting the validity of the received data in real time comprises one or both of:
detecting the amplitude or the power of the received data in real time, carrying out infinite impulse response filtering on the amplitude or the power, and setting a first indication signal to be effective when the amplitude or the power after filtering is not lower than a first threshold value;
detecting the symbol jump of the received data in real time, and setting a second indication signal to be effective when the jump frequency in a second preset time is not lower than a second threshold value.
3. The method of clock recovery as recited in claim 1, wherein said detecting the validity of the received data in real time comprises:
detecting the amplitude or the power of the received data in real time, carrying out infinite impulse response filtering on the amplitude or the power, and setting a first indication signal to be effective when the amplitude or the power after filtering is not lower than a first threshold value;
detecting symbol jump of received data in real time, and setting a second indication signal to be effective when the jump frequency in a second preset time is not lower than a second threshold value;
Detecting in real time a data status signal received from an upstream device of the data link, setting the third indication signal to be valid when no abnormal data status signal is received, and setting the third indication signal to be invalid when at least one abnormal data status signal is received;
and when the first indication signal, the second indication signal and the third indication signal are all valid, determining that the received data is valid.
4. The method of clock recovery as recited in claim 1, wherein said pre-equalizing the valid data comprises pre-equalizing using a filter having tap coefficients not higher than three steps.
5. The clock recovery method of claim 1, wherein determining whether the first clock recovery module is locked comprises determining that the clock recovery module is locked when an absolute value of an integrated loop accumulated value of the first loop filter is not less than a third threshold, and otherwise determining that the clock recovery module is unlocked.
6. A clock recovery method as claimed in claim 3, wherein the data state signal comprises an optical loss of signal.
7. The method of clock recovery as recited in claim 1, wherein resetting the first clock recovery module and the second clock recovery module comprises resetting respective integrated loop accumulated values of the first loop filter and the second loop filter.
8. The clock recovery method of claim 1, wherein the first clock recovery module and the second clock recovery module employ different timing error algorithms.
9. A method of clock recovery comprising:
detecting the validity of the received data in real time, and resetting at least a second clock recovery module if the data is determined to be invalid;
pre-equalizing the effective data;
calculating a first timing error by using the pre-equalized data in a first clock recovery module, and performing clock recovery on the first timing error through a first loop filter;
determining whether the clock data recovered by the first clock recovery module is valid, if so, calculating a second timing error at the second clock recovery module, and performing clock recovery on the second timing error through a second loop filter, wherein the scale factor of the second loop filter is smaller than that of the first loop filter;
and resetting at least the second clock recovery module if the clock data recovered by the first clock recovery module is invalid.
10. The clock recovery method of claim 9, wherein the detecting the validity of the received data in real time comprises one or both of:
Detecting the amplitude or the power of the received data in real time, carrying out infinite impulse response filtering on the amplitude or the power, and setting a first indication signal to be effective when the amplitude or the power after filtering is not lower than a first threshold value;
detecting the symbol jump of the received data in real time, and setting a second indication signal to be effective when the jump frequency in a second preset time is not lower than a second threshold value.
11. The method of clock recovery as recited in claim 9, wherein said detecting the validity of the received data in real time comprises:
detecting the amplitude or the power of the received data in real time, carrying out infinite impulse response filtering on the amplitude or the power, and setting a first indication signal to be effective when the amplitude or the power after filtering is not lower than a first threshold value;
detecting symbol jump of received data in real time, and setting a second indication signal to be effective when the jump frequency in a second preset time is not lower than a second threshold value;
detecting in real time a data status signal received from an upstream device of the data link, setting the third indication signal to be valid when no abnormal data status signal is received, and setting the third indication signal to be invalid when at least one abnormal data status signal is received;
And when the first indication signal, the second indication signal and the third indication signal are all valid, determining that the received data is valid.
12. The clock recovery method of claim 9, wherein determining whether the clock data recovered by the first clock recovery module is valid comprises determining whether the error signal converges based on an error signal transmitted by an equalizer and/or determining whether decoding is successful based on a decoding status transmitted by a decoder.
13. The method of clock recovery as recited in claim 9, wherein said pre-equalizing the valid data comprises pre-equalizing using a filter having tap coefficients not higher than three steps.
14. The method of clock recovery as recited in claim 9 wherein said resetting at least a second clock recovery module comprises resetting an integrated loop accumulation value of a second loop filter.
15. The clock recovery method of claim 9, wherein the first clock recovery module comprises a first order loop filter and the second clock recovery module comprises a second order or more loop filter.
16. A clock recovery apparatus, comprising:
the detection module is used for actually detecting the validity of the received data, and if the data is determined to be invalid, the information of the data invalidation is sent to the reset module;
A pre-equalization module that receives the valid data from the detection module and performs pre-equalization processing on the valid data;
a first clock recovery module including a first loop filter that receives the pre-equalized data from the pre-equalization module to calculate a first timing error, the first loop filter performing clock recovery using the first timing error;
a clock recovery state determination module that determines whether a clock recovery state of the first clock recovery module is valid;
a second clock recovery module including a second loop filter that receives data from the pre-equalization module to calculate a second timing error when the clock recovery state determination module determines that the clock recovery state of the first clock recovery module is valid, the second loop filter using the second timing error for clock recovery, the second loop filter having a ratio and/or an integral factor that is less than the ratio and/or the integral factor of the first loop filter;
and the reset module is connected with the detection module and the clock recovery state judgment module and is used for resetting at least the second clock recovery module.
17. The clock recovery apparatus of claim 16, wherein the detecting module detects validity of the received data in real time comprises:
Detecting the amplitude or the power of the received data in real time, carrying out infinite impulse response filtering on the amplitude or the power, and setting a first indication signal to be effective when the amplitude or the power after filtering is not lower than a first threshold value; or alternatively
Detecting the amplitude or the power of the received data in real time, carrying out infinite impulse response filtering on the amplitude or the power, setting a first indication signal to be effective when the amplitude or the power after filtering is not lower than a first threshold value, and detecting the symbol jump of the received data in real time, and setting a second indication signal to be effective when the jump frequency in a second preset time is not lower than a second threshold value; or alternatively
Detecting the amplitude or power of the received data in real time and performing infinite impulse response filtering on the amplitude or power, setting the first indication signal to be active when the amplitude or power after filtering is not lower than a first threshold value, and detecting the sign jump of the received data in real time, setting the second indication signal to be active when the number of jumps within a second predetermined time is not lower than a second threshold value, and detecting the data status signal received from an upstream device of the data link in real time, setting the third indication signal to be active when no abnormal data status signal is received, and setting the third indication signal to be inactive when at least one abnormal data status signal is received.
18. The clock recovery apparatus of claim 16, wherein the clock recovery status determination module determining whether the clock recovery status of the first clock recovery module is valid when the first loop filter is a loop filter of two or more orders comprises determining whether the first clock recovery module is locked, if the first clock recovery module is locked, the clock recovery status of the first clock recovery module is valid, and if a first predetermined time has elapsed, the first clock recovery module is not yet locked, issuing a request to the reset module for a reset of the first and second clock recovery modules.
19. The clock recovery apparatus of claim 16, wherein the clock recovery state determination module determines whether the clock recovery state of the first clock recovery module is valid when the first loop filter is a first order loop filter, comprises determining whether an error signal converges based on an error signal transmitted by an equalizer and/or determining whether decoding is successful based on a decoding state transmitted by a decoder, and if the clock recovery state of the first clock recovery module is invalid, issuing a request to the reset module for resetting at least a second clock recovery module.
20. The clock recovery apparatus of claim 16, wherein the first clock recovery module comprises a first timing error detection module, a first loop filter, and a first digitally controlled oscillator, and the second clock recovery module comprises a second timing error detection module, a second loop filter, and a second digitally controlled oscillator, wherein the first timing error detection module and the second timing error detection module use different timing error detection algorithms.
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| CN101854497A (en) * | 2010-05-07 | 2010-10-06 | 深圳国微技术有限公司 | Digital television receiver and timing recovery method thereof |
| CN116668245A (en) * | 2023-06-19 | 2023-08-29 | 北京信息科技大学 | DSP device, receiving end and system combining clock recovery and blind equalization |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101854497A (en) * | 2010-05-07 | 2010-10-06 | 深圳国微技术有限公司 | Digital television receiver and timing recovery method thereof |
| CN116668245A (en) * | 2023-06-19 | 2023-08-29 | 北京信息科技大学 | DSP device, receiving end and system combining clock recovery and blind equalization |
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