CN117134771A - Digital-to-analog conversion device and method with signal correction mechanism - Google Patents

Abstract

The disclosure relates to a digital-to-analog conversion device with signal correction mechanism and a method thereof. A digital-to-analog conversion device with signal correction mechanism is provided. The digital-to-analog conversion circuit includes a conversion circuit for generating an output analog signal and an echo cancellation analog signal. The echo transmitting circuit downsamples the echo path to generate an echo signal. The echo correction circuit includes odd and even correction circuits, which are mapped by a codeword deviation table and processed by response coefficients according to odd and even input portions of an input digital signal to generate odd and even correction portions of an echo cancellation correction signal. The correction parameter operation circuit generates an offset according to an error signal of the echo signal relative to the echo cancellation correction signal and the path information related to the echo correction circuit. The echo correction circuit converges the response coefficient according to the error signal and the pseudo noise transmission path information, and updates the codeword deviation table according to the offset.

Description

Digital-to-analog conversion device and method with signal correction mechanism

Technical Field

The present invention relates to digital-to-analog conversion, and more particularly, to a digital-to-analog conversion apparatus and method with signal correction mechanism.

Background

Digital-to-analog conversion devices are important elements for converting signals from digital to analog form. The digital-to-analog conversion device can multiply corresponding conversion gain values according to different digital codes so as to generate analog signals with different sizes.

However, in the digital-to-analog conversion device, errors are often caused by the offset of the internal current source, and echo is caused by the mismatch between the signal itself and the signal in the transmission path, so that various correction techniques are required for correcting the input/output signal by the digital-to-analog conversion device to achieve the best conversion result.

Disclosure of Invention

In view of the foregoing, it is an objective of the present invention to provide a digital-to-analog conversion apparatus and method with a signal correction mechanism, so as to improve the prior art.

The invention includes a digital-to-analog conversion device with signal correction mechanism, comprising: the device comprises a digital-to-analog conversion circuit, an echo transmission circuit, an echo correction circuit and a correction parameter operation circuit. The digital-to-analog conversion circuit comprises a plurality of conversion circuits operating at a first frequency to convert according to a signal feed-in associated with an input digital signal having an input codeword, to generate an output analog signal and an echo cancellation analog signal, the echo cancellation analog signal outputting at least an echo cancellation of the output analog signal on an echo path. The echo transmitting circuit performs signal processing on the echo path to perform downsampling to generate an echo signal with a second frequency, wherein the second frequency is half of the first frequency. The echo correction circuit comprises an odd correction circuit and an even correction circuit which are operated at a second frequency and correspond to the conversion circuit for generating the echo cancellation analog signal, and the odd correction part and the even correction part of the echo cancellation correction signal are respectively generated by mapping by a complex code word deviation table and processing by a complex group of response coefficients according to signal feeds related to the odd input part and the even input part of the input digital signal. The correction parameter operation circuit is operated at a second frequency and used for generating complex offset according to an error signal of the echo signal relative to the echo cancellation correction signal and path information related to the echo correction circuit, wherein the echo correction circuit converges a response coefficient according to the error signal and pseudo noise transmission path information from the digital-to-analog conversion circuit to the echo transmission circuit, and updates a codeword deviation table according to the offset.

The invention further provides a digital-to-analog conversion method with a signal correction mechanism, which is applied to a digital-to-analog conversion device and comprises the following steps: the digital-to-analog conversion circuit converts according to a signal feed-in related to an input digital signal with an input codeword to generate an output analog signal and an echo cancellation analog signal, and the echo cancellation analog signal outputs at least echo cancellation to the output analog signal on an echo path, wherein the digital-to-analog conversion circuit comprises a complex conversion circuit operating at a first frequency; the echo transmitting circuit processes the signal of the echo path to generate an echo signal with a second frequency, wherein the second frequency is half of the first frequency; the echo correction circuit is used for respectively carrying out mapping by a complex code word deviation table and processing by a complex group of response coefficients according to signals related to an odd input part and an even input part of an input digital signal so as to generate an odd correction part and an even correction part of an echo cancellation correction signal, wherein the echo correction circuit comprises an odd correction circuit and an even correction circuit which are operated at a second frequency and correspond to a conversion circuit used for generating an echo cancellation analog signal; generating a plurality of offsets by the correction parameter operation circuit according to an error signal of the echo signal relative to the echo cancellation correction signal and path information related to the echo correction circuit, wherein the correction parameter operation circuit operates at a second frequency; and the echo correction circuit converges the response coefficient according to the error signal and the pseudo noise transmission path information from the digital-to-analog conversion circuit to the echo transmission circuit, and updates the codeword deviation table according to the offset.

The features, implementation and functions of the present invention are described in detail below with reference to the preferred embodiments shown in the drawings.

Drawings

FIG. 1 is a block diagram of a digital-to-analog conversion device with signal correction mechanism according to an embodiment of the present invention;

FIG. 2 is a more detailed block diagram of the signal input circuit according to one embodiment of the present invention;

FIG. 3 is a more detailed block diagram of the digital-to-analog conversion circuit according to one embodiment of the present invention;

FIG. 4 is a more detailed block diagram of an echo correction circuit according to an embodiment of the present invention;

FIG. 5 is a block diagram of a digital-to-analog conversion device according to another embodiment of the invention; and

FIG. 6 is a flow chart of a digital-to-analog conversion method with signal correction mechanism according to an embodiment of the invention.

Detailed Description

One objective of the present invention is to provide a digital-to-analog converter with signal correction mechanism, which can make the internal circuit operate at a second frequency half of the first frequency to correct according to the echo signal by down-sampling when generating the output analog signal with the first frequency and the echo cancellation analog signal.

Please refer to fig. 1. FIG. 1 is a block diagram of a digital-to-analog conversion apparatus 100 with signal correction mechanism according to an embodiment of the present invention. The digital-to-analog conversion apparatus 100 includes: the signal input circuit 110, the digital-to-analog conversion circuit 120, the echo transmitting circuit 130, the echo correcting circuit 140 and the correction parameter calculating circuit 150.

The signal input circuit 110 feeds signals into the digital-to-analog conversion circuit 120. The digital-to-analog conversion circuit 120 includes a complex conversion circuit operating at a first frequency, such as, but not limited to, 800 megahertz (MHz). The digital-to-analog conversion circuit 120 performs digital-to-analog conversion according to a signal feed-in related to an input digital signal IS having an input codeword, and generates an output analog signal OD and an echo cancellation analog signal. The echo cancellation analog signal performs at least echo cancellation on the output analog signal OD on the echo path EP.

The operations of the signal input circuit 110 and the digital-to-analog conversion circuit 120 will be described with reference to fig. 2 and 3.

FIG. 2 shows a more detailed block diagram of the signal input circuit 110 in accordance with one embodiment of the present invention. The signal input circuit 110 includes: an odd feed circuit 200, an even feed circuit 210, an odd pseudo noise generation circuit 220, and an even pseudo noise generation circuit 230.

FIG. 3 shows a more detailed block diagram of the digital-to-analog conversion circuit 120 in accordance with one embodiment of the present invention. The complex conversion circuits in the digital-to-analog conversion circuit 120 include an output conversion circuit 300, an output echo cancellation conversion circuit 310, and a pseudo noise conversion circuit 320.

The odd-numbered feed-in circuit 200 captures and outputs an odd-numbered input part ISO of the input digital signal IS. The even feed circuit 210 captures and outputs an even input portion ISE of the input digital signal IS. Therefore, when the input digital signal IS has the first frequency, the odd input portion ISO and the even input portion ISE have the second frequency, respectively, and the value of the second frequency IS approximately half of the first frequency. For the numerical example above, when the first frequency is 800 mhz, the second frequency is 400 mhz.

In one embodiment, the odd feed circuit 200 and the even feed circuit 210 receive the input digital signal IS from a signal source SS, such as a Transmitter (TX) in the communication system, as shown in fig. 1. Also, the odd feed circuit 200 and the even feed circuit 210 may be implemented by a filter circuit to filter and output the odd input portion ISO and the even input portion ISE, respectively.

The output conversion circuit 300 receives the odd input portion ISO and the even input portion ISE for conversion to generate an output analog signal OD. The output echo cancellation converting circuit 310 also receives the odd input portion ISO and the even input portion ISE, and converts them to generate an output echo cancellation analog signal OEC of the echo cancellation analog signals. The output analog signal OD is a signal actually transmitted to the outside. However, the output analog signal OD may leak out to, for example, but not limited to, a receiving circuit (RX, not shown) through the echo path EP shown in fig. 1. Thus, the output echo cancellation analog signal OEC performs echo cancellation on the output analog signal OD that is leaked onto the echo path EP.

The odd pseudo noise generating circuit 220 generates an odd pseudo noise digital signal INO which is fed to the digital-to-analog converting circuit 120. The even pseudo noise generating circuit 230 generates an even pseudo noise digital signal INE to be fed to the digital-to-analog converting circuit 120. In one embodiment, the odd and even pseudo noise digital signals INO and INE may be random 0, 1 signals of analog noise.

The pseudo noise converting circuit 320 receives the odd pseudo noise digital signal INO and the even pseudo noise digital signal INE for converting to generate the pseudo noise analog signal ON to the echo path EP. The generation of the odd and even pseudo-noise digital signals INO and INE and the feedback of the pseudo-noise analog signal ON can be used to measure the response of the digital-to-analog conversion circuit 120 to the echo path EP.

In one embodiment, the digital-to-analog conversion circuit 120 further includes a superimposing circuit 330 for superimposing the analog signals and transmitting the superimposed analog signals to the echo path EP of fig. 1, so as to perform echo cancellation on the output analog signal OD leaked to the echo path EP.

The echo transmitting circuit 130 of fig. 1 performs signal processing on the echo path EP to down-sample the echo signal ES having the second frequency which is half of the first frequency. The signal processing includes, for example, but not limited to, echo response processing and analog-to-digital conversion by down-sampling to generate the echo signal ES.

Each of the aforementioned digital-to-analog conversion circuits 120 includes a plurality of current sources (not shown) respectively, and generates analog signals according to the control of the corresponding signal feeds. The current sources may include thermometer and binary controlled current sources, each having a current offset value that causes a static mismatch error to the output analog signal.

The echo correction circuit 140 eliminates the static mismatch error of each conversion circuit. The echo correction circuit 140 generates an odd correction portion and an even correction portion of the echo cancellation correction signal by mapping from a complex codeword deviation table and processing from a complex set of response coefficients according to signal feeds associated with the odd input portion ISO and the even input portion ISE of the input digital signal IS, respectively, through an odd correction circuit and an even correction circuit included to operate at the second frequency and corresponding to the conversion circuit for generating the echo cancellation analog signal.

The echo correction circuit 140 further processes an odd pseudo noise correction signal ECNO and an even pseudo noise correction signal ECNE respectively according to the odd pseudo noise digital signal INO and the even pseudo noise digital signal INE by a set of odd pseudo noise response parameters CCNO and a set of even pseudo noise response parameters CCNE (as shown in FIG. 4).

Fig. 4 is a more detailed block diagram of the echo correction circuit 140 according to an embodiment of the present invention. The echo correction circuit 140 includes an odd output echo cancellation correction circuit 400, an even output echo cancellation correction circuit 410, an odd pseudo noise correction circuit 420, and an even pseudo noise correction circuit 430.

The odd output echo cancellation correction circuit 400 includes: the first mapping circuit 440A and the first response circuit 440B. The first mapping circuit 440A receives the odd input part ISO of the input digital signal IS and maps according to the first codeword deviation table TB1 to generate a first mapping signal DS1. The first response circuit 440B receives the first mapping signal DS1 and processes it according to a set of first response coefficients CC1 to generate an odd output echo cancellation correction signal ECS1.

The even output echo cancellation correction circuit 410 includes: the second mapping circuit 450A and the second response circuit 450B. The second mapping circuit 450A receives the even input portion ISE of the input digital signal IS and maps according to the second codeword deviation table TB2 to generate a second mapping signal DS2. The second response circuit 450B receives the second mapping signal DS2 and processes it according to a set of second response coefficients CC2 to generate an even output echo cancellation correction signal ECS2.

In the mapping circuit, each codeword deviation table includes a one-to-one correspondence between complex codewords and complex codeword deviation values. The input codeword is one of the codewords of the first codeword deviation table TB1 and the second codeword deviation table TB2. In the initial state, the deviation values corresponding to all codewords are preset to 0.

The odd pseudo noise correction circuit 420 receives the odd pseudo noise digital signal INO and processes the odd pseudo noise digital signal INO according to the odd pseudo noise response coefficient CCNO to generate the odd pseudo noise correction signal ECNO. The even pseudo noise correction circuit 430 receives the even pseudo noise digital signal INE and processes the even pseudo noise digital signal INE according to the even pseudo noise response coefficient CCNE to generate an even pseudo noise correction signal ECNE.

In one embodiment, the digital-to-analog conversion apparatus 100 of FIG. 1 further includes an error calculation circuit 160 for calculating an error signal DIS of the echo signal ES relative to the correction signals (i.e., ECS 1-ECS 2 and ECNO, ECNE).

In one embodiment, the digital-to-analog conversion apparatus 100 of fig. 1 further includes a residual echo cancellation circuit 170 for further canceling the residual echo. The residual echo cancellation circuit 170 includes: the echo cancellation circuit 190 and the echo response circuit 180.

The residual echo response circuit 180 receives the input digital signal IS and processes it according to a set of residual echo response coefficients CCR to generate a residual echo cancellation signal ECR. The cancellation circuit 190 subtracts the residual echo cancellation signal ECR and the error signal DIS to produce a final error signal FDIS. Wherein the residual echo response circuit 180 converges according to the final error signal FDIS.

The correction parameter operation circuit 150 generates a plurality of offsets according to the error signal DIS of the echo signal ES relative to the correction signals (i.e. ECS 1-ECS 2 and ECNO, ECNE) and the path information related to the echo correction circuit 140. In one embodiment, the correction parameter operation circuit 150 generates the offset according to the final error signal FDIS processed by the residual echo cancellation circuit 170.

In one embodiment, the path information is the path delays DL 1-DL 2 of the response circuits (the first response circuit 440B and the second response circuit 450B) to the correction parameter computing circuit 150, respectively. Since the processing of these circuits requires time, the correction parameter operation circuit 150 needs to trace back the calculated offset to the correct input codeword according to the path delays DL1 to DL2.

In one embodiment, the correction parameter operation circuit 150 receives the first and second response coefficients CC 1-CC 2 of the first and second response circuits 440B-450B, and multiplies the response coefficients by the value of the final error signal FDIS, and then accumulates the multiplied response coefficients to generate the corresponding inverted error value. The correction parameter calculation circuit 150 further sets the respective inversion error values to the first to second offsets DA1 to DA2 corresponding to the first to second mapping circuits 440A to 450A based on the path delays DL1 to DL2.

It should be noted that the above-mentioned offset generation method is only an example. In other embodiments, the correction parameter operation circuit 150 may generate the offset according to other methods.

The echo correction circuit 140 can train according to the final error signal FDIS and the pseudo noise transmission path information from the digital-to-analog conversion circuit 120 to the echo transmitting circuit 130, so that each set of response coefficients is converged to achieve the purpose of correcting the digital-to-analog conversion circuit 120. The pseudo noise transmission path information can be obtained by feeding the odd pseudo noise digital signal INO, the even pseudo noise digital signal INE and transmitting the pseudo noise analog signal ON.

To avoid the subject of the training from being pulled, the digital-to-analog conversion device 100 performs the training in different stages.

In the first training phase, the output conversion circuit 300 and the pseudo noise conversion circuit 320 are enabled to enable the odd pseudo noise correction circuit 420 and the even pseudo noise correction circuit 430 to converge the odd pseudo noise response coefficient CCNO and the even pseudo noise response coefficient CCNE according to the echo signal ES, so that the first response circuit 440B and the second response circuit 450B set the converged odd pseudo noise response coefficient CCNO and even pseudo noise response coefficient CCNE as the first response coefficient CC1 and the second response coefficient CC2 respectively.

In the second training phase, the output echo cancellation conversion circuit 310 is further enabled to update the first codeword deviation table TB1 and the second codeword deviation table TB2 according to the first offset DA1 and the second offset DA2 related to the odd output echo cancellation correction circuit 400 and the even output echo cancellation correction circuit 410.

In one embodiment, the output echo cancellation conversion circuit 310 includes a plurality of permutations of the bias values of the current sources corresponding to different input codewords, so that there is a mapping relationship between the bias values of the current sources and the offsets of the input codewords. The correction parameter operation circuit 150 may divide the offsets corresponding to different input codewords into plural groups according to the operation states of the current sources in the second training stage, and set each current source as the target current source to further set the corresponding current offset value operation formula. The current deviation value operation formula is the subtraction operation result of two groups so that the current deviation values of the current sources except the target current source are mutually offset.

The correction parameter operation circuit 150 substitutes the offset into the current offset operation formula corresponding to each current source to calculate the current offset of the target current source, and further converts the current offset of the current source into a complex codeword offset, so as to update the corresponding first and second codeword offset tables TB1 to TB2.

In one embodiment, the correction parameter operation circuit 150 may set the current bias values of two of the current sources to 0 as the anchor point to perform calculation, so as to avoid interaction on the system.

In the above manner, the correction parameter computing circuit 150 can update the first and second codeword deviation tables TB1 to TB2 of the first and second mapping circuits 440A to 450A.

In an embodiment, the output echo cancellation conversion circuit 310 may further include a control circuit (not shown) for generating an on sequence according to the current bias values corresponding to the current sources, and further for enabling the thermometer controlled current sources to be turned on according to the on sequence according to the input codeword by means of thermometer code control, so that the linearity of the on sequence of the current sources is greater than a predetermined value. The setting of the opening sequence may be implemented in different manners, which will not be described herein.

When the output analog signal OD is transmitted, the passing transformer will generate bounce or external impedance mismatch, and will also generate echo to the echo path EP, which cannot be completely eliminated by the output echo cancellation analog signal OEC. Therefore, in some embodiments, the digital-to-analog conversion apparatus 100 may further include a circuit for canceling the echo caused by the mismatch.

Please refer to fig. 1 to fig. 4. The above-described circuit related to mismatch echo cancellation is shown in fig. 1-4 in dashed blocks.

As shown in fig. 2, in some embodiments, the signal input circuit 110 further includes an odd filter circuit 240 and an even filter circuit 250, which respectively extract and filter the odd input portion ISO and the even input portion ISE of the input digital signal IS, and output the odd filter signal FSO and the even filter signal FSE to the digital-to-analog conversion circuit 120.

Further, the signal input circuit 110 may optionally further include a limiting circuit 260 configured to limit the maximum and minimum values of the odd-numbered filter signal FSO and the even-numbered filter signal FSE to a predetermined maximum value and a predetermined minimum value, respectively, and then transmit the maximum and minimum values to the digital-to-analog conversion circuit 120.

For example, when the common signal values of the odd-numbered filtered signal FSO and the even-numbered filtered signal FSE are between-6 and +6, the extreme values of-7 and +7 are not always present, which easily causes the related correction circuit to generate extreme value errors (peak error) in the subsequent correction process. Therefore, the limiting circuit 260 limits the extremum of-7 and +7 to the predetermined minimum and maximum values of-6 and +6, thereby avoiding the occurrence of extremum errors.

As shown in fig. 3, the digital-to-analog conversion circuit 120 further includes a non-matched echo cancellation conversion circuit 340 for receiving the odd filtered signal FSO and converting the even filtered signal FSE to generate a non-matched echo cancellation analog signal MEC.

As shown in fig. 4, the echo correction circuit 140 further includes an odd-numbered mismatch echo cancellation correction circuit 460 and an even-numbered mismatch echo cancellation correction circuit 470.

The odd-numbered mismatch echo cancellation correction circuit 460 includes: the third mapping circuit 480A and the third response circuit 480B. The third mapping circuit 480A receives the odd filtered signal FSO and maps according to the third codeword deviation table TB3 to generate a third mapped signal DS3. The third response circuit 480B receives the third mapping signal DS3 and processes the third mapping signal DS3 according to a set of third response coefficients CC3 to generate an odd-numbered mismatch echo cancellation correction signal ECS3.

The odd mismatch echo cancellation correction circuit 470 includes: fourth mapping circuit 490A and fourth response circuit 490B. The fourth mapping circuit 490A receives the even filtered signal FSE and maps according to the fourth codeword deviation table TB4 to generate a fourth mapped signal DS4. The fourth response circuit 490B receives the fourth mapping signal DS4 and processes it according to a set of fourth response coefficients CC4 to generate an even-number mismatch echo cancellation correction signal ECS4.

Similarly, each codeword deviation table also includes a one-to-one correspondence between complex codewords and complex codeword deviation values. And will not be described in detail herein.

The error calculation circuit 160 further calculates the error signal DIS with respect to the correction signal, the odd-numbered mismatch echo cancellation correction signal ECS3 and the even-numbered mismatch echo cancellation correction signal ECS4.

The correction parameter operation circuit 150 generates an offset according to the final error signal FDIS and the path information related to the odd-numbered mismatch echo cancellation correction circuit 460 and the even-numbered mismatch echo cancellation correction circuit 470, i.e., the path delays DL 3-DL 4 (shown in FIG. 5 below), so as to trace back the correct input codeword. The correction parameter operation circuit 150 receives the third to fourth response coefficients CC3 to CC4 of the third to fourth response circuits 480B to 490B, and multiplies the one-dimensional inversion of the response coefficients by the value of the final error signal FDIS, and then accumulates the one-dimensional inversion of the response coefficients to generate corresponding inversion error values. The correction parameter calculation circuit 150 further sets the respective inversion error values to the third to fourth offsets DA3 to DA4 corresponding to the third to fourth mapping circuits 480A to 490A based on the path delays DL3 to DL 4.

It should be noted that the above-mentioned offset generation method is only an example. In other embodiments, the correction parameter operation circuit 150 may generate the offset according to other methods.

The first training phase after adding the mismatched echo cancellation related circuit is substantially the same as described above, but the third response circuit 480B and the fourth response circuit 490B also set the converged odd pseudo noise response coefficient CCNO and even pseudo noise response coefficient CCNE to the third response coefficient CC3 and the fourth response coefficient CC4, respectively.

In the second training phase after adding the mismatched echo cancellation related circuit, the mismatched echo cancellation converting circuit 340 will also enable outputting the mismatched echo cancellation analog signal MEC to update the third to fourth codeword deviation tables TB3 to TB4 according to the third to fourth offsets DA3 to DA4 respectively related thereto. In one embodiment, the third to fourth codeword deviation tables TB3 to TB4 can be updated directly according to the feeding of the third to fourth offsets DA3 to DA4 without any anchor point. However, the present invention is not limited thereto.

Please refer to fig. 5. Fig. 5 shows a block diagram of a digital-to-analog conversion apparatus 500 according to another embodiment of the invention. The digital-to-analog conversion device 500 of fig. 5 is identical to the digital-to-analog conversion device 100 of fig. 1 in many points, and therefore, the description of the identical elements is omitted.

In the present embodiment, the digital-to-analog conversion apparatus 500 of fig. 5 includes a correlation circuit for performing the unmatched echo cancellation, and is configured with a mechanism for updating the odd filter coefficient FXO and the even filter coefficient FXE in the odd filter circuit 240 and the even filter circuit 250 of fig. 2.

In more detail, the echo transmitting circuit 130 of fig. 5 may be provided with two down-sampling circuits (not shown) for generating the odd echo signal ESO and the even echo signal ESE each having the second frequency. The odd echo signal ESO has an odd sign and the even echo signal ESE has an even sign. In fig. 5, the error signal DIS generated by the operation with the echo cancellation correction signal is shown as an odd echo signal ESO. However, in other embodiments, an even echo ESE signal may be selected to generate the error signal DIS in conjunction with the echo cancellation correction signal.

Also, the digital-to-analog conversion device 500 may further include an update circuit 510. The update circuit 510 includes an odd response circuit 520, an even response circuit 530, and a cross-over circuit 540.

The odd response circuit 520 and the even response circuit 530 respectively capture the odd input part ISO and the even input part ISE of the input digital signal IS to respond, and output as an odd response signal RSO and an even response signal RSE.

The interactive operation circuit 540 receives the odd response signal RSO, the even response signal RSE, the odd echo signal ESO, and the even echo signal ESE. The interaction circuit 540 further performs interaction according to the odd-numbered response signal RSO, the even-numbered response signal RSE, the odd-numbered sign of the odd-numbered echo signal ESO, and the even-numbered sign of the even-numbered echo signal ESE. Wherein the odd and even signs may represent positive and negative signs, respectively, +1 and-1. The odd sign is respectively operated with the odd response signal RSO and the even response signal RSE, and the even sign is also respectively operated with the odd response signal RSO and the even response signal RSE. Such an interaction will generate an interaction result MOR with a first frequency, so that the odd filter circuit 240 and the even filter circuit 250 update the odd filter coefficient FXO and the even filter coefficient FXE accordingly.

Therefore, the digital-to-analog conversion apparatus 100 of the present invention generates the output analog signal and the echo cancellation analog signal at the first frequency, and corrects the second frequency, which is a half of the first frequency, by down-sampling the second frequency, so that the internal circuit can operate at the first frequency according to the echo signal.

Please refer to fig. 6. FIG. 6 is a flow chart of a digital-to-analog conversion method 600 with signal correction mechanism according to an embodiment of the invention.

In addition to the above-mentioned devices, the present invention further discloses a digital-to-analog conversion method 600, which is applied to, for example, but not limited to, the digital-to-analog conversion device 100 of fig. 1. One embodiment of a digital-to-analog conversion method 600 is shown in FIG. 6, and includes the following steps.

In step S610: the digital-to-analog conversion circuit 120 converts according to a signal feed related to an input digital signal IS having an input codeword, and generates an output analog signal OD and an echo cancellation analog signal, which at least performs echo cancellation on the output analog signal OD on an echo path, wherein the digital-to-analog conversion circuit 120 comprises a complex conversion circuit operating at a first frequency.

In step S620: the echo path EP is signal-processed by the echo transmitting circuit 130 to down-sample the echo signal ES having a second frequency, which is half of the first frequency.

In step S630: the echo correction circuit 140 IS fed with signals related to the odd input part ISO and the even input part ISE of the input digital signal IS, mapped by a complex codeword deviation table and processed by a complex set of response coefficients to generate an odd correction part and an even correction part of the echo cancellation correction signal, respectively, wherein the echo correction circuit comprises an odd correction circuit and an even correction circuit which operate at a second frequency and correspond to a conversion circuit for generating an echo cancellation analog signal.

In step S640: the correction parameter operation circuit 150 generates a plurality of offsets according to the error signal DIS of the echo cancellation correction signal and the echo signal ES, and the path information related to the echo correction circuit 140, wherein the correction parameter operation circuit 150 operates at the second frequency.

In step S650: the echo correction circuit 140 converges the response coefficient according to the error signal DIS and the pseudo noise transmission path information from the digital-to-analog conversion circuit 120 to the echo transmitting circuit 130, and updates the codeword deviation table according to the offset.

It should be noted that the above embodiment is only an example. In other embodiments, those skilled in the art will appreciate that modifications may be made without departing from the spirit of the invention.

In summary, the digital-to-analog conversion apparatus and method with signal correction mechanism of the present invention can make the internal circuit operate at the second frequency half of the first frequency to correct according to the echo signal by down-sampling when generating the output analog signal and the echo cancellation analog signal at the first frequency.

Although the embodiments of the present disclosure have been described above, these embodiments are not limited thereto, and those skilled in the art can make various changes to the technical features of the present disclosure according to the explicit or implicit disclosure of the present disclosure, where the various changes may be within the scope of protection sought herein, in other words, the scope of protection of the present disclosure shall be defined by the claims of the present disclosure.

[ symbolic description ]

100 digital-to-analog conversion device

110 signal input circuit

120 digital-to-analog conversion circuit

130 echo transmitting circuit

140 echo correction circuit

150 correction parameter operation circuit

160 error calculation circuit

170 residual echo cancellation circuit

180 residual echo response circuit

190 cancel circuit

200 odd number feed-in circuit

210 even feed-in circuit

220 odd pseudo noise generating circuit

230 even pseudo noise generating circuit

240 odd filter circuit

250 even filter circuit

260 limiting circuit

300 output conversion circuit

310 output echo cancellation conversion circuit

320 pseudo noise converting circuit

330 superposition circuit

340 mismatch echo cancellation conversion circuit

400 odd output echo cancellation correction circuit

410 even output echo cancellation correction circuit

420 odd pseudo noise correction circuit

430 even pseudo noise correction circuit

440A first mapping circuit

440B first response circuit

450A second mapping circuit

450B second response circuit

460 odd number mismatch echo cancellation correction circuit

470 even number mismatch echo cancellation correction circuit

480A third mapping circuit

480B third response circuit

490A fourth mapping circuit

490B fourth response circuit

500 digital-to-analog conversion device

510 update circuit

520 odd response circuit

530 even response circuit

540 interaction operation circuit

600 digital-to-analog conversion method

S610-S650 steps

CC1 first response coefficient

CC2 second response coefficient

CC3 third response coefficient

CC4 fourth response coefficient

CCNE: even pseudo noise response parameter

Odd pseudo noise response parameter of CCNO

CCR: residual echo response coefficient

DA1 first offset

DA2 second offset

DA3 third offset

DA4 fourth offset

DIS error signal

DL 1-DL 4 path delay

DS1 first mapping signal

DS2, the second mapping signal

DS3, third mapping signal

DS4 fourth mapping signal

ECS1 odd output echo cancellation correction signal

ECS2 even output echo cancellation correction signal

ECS3 odd number mismatch echo cancellation correction signal

ECS4 even number mismatch echo cancellation correction signal

ECNE: even pseudo noise correction signal

ECNO: odd pseudo noise correction signal

ECR residual echo cancellation signal

EP echo path

ES echo signal

ESE: even echo signal

ESO odd echo signal

FDIS final error signal

FSE even filtered signal

FSO odd-numbered filter signal

FXE even filter coefficients

FXO odd filter coefficients

INO odd pseudo noise digital signal

INE even pseudo noise digital signal

IS: input digital signal

ISE even input section

ISO odd input part

MEC, mismatch echo cancellation analog signal

MOR, interactive operation result

OD: output analog signal

OEC for outputting echo cancellation analog signal

Pseudo noise analog signal

RSE: even response signal

RSO odd response signal

SS signal source

TB1 first codeword deviation table

TB2 second codeword deviation table

TB3 third codeword deviation table

TB4 fourth codeword deviation table

Claims (10)

1. A digital-to-analog conversion device with signal correction mechanism includes:

a digital-to-analog conversion circuit including a plurality of conversion circuits operating at a first frequency for converting according to a signal feed associated with an input digital signal having an input codeword to generate an output analog signal and an echo cancellation analog signal, the echo cancellation analog signal performing at least an output echo cancellation on the output analog signal on an echo path;

an echo transmitting circuit for processing the echo path to down sample to generate an echo signal with a second frequency, wherein the second frequency is half of the first frequency;

an echo correction circuit including an odd correction circuit and an even correction circuit operating at the second frequency and corresponding to the conversion circuits for generating the echo cancellation analog signal, the odd correction circuit and the even correction circuit being respectively mapped by a complex codeword deviation table and processed by a complex set of response coefficients according to signal feeds associated with an odd input portion and an even input portion of the input digital signal to generate an echo cancellation correction signal; and

and the correction parameter operation circuit is operated at the second frequency and generates a plurality of offsets according to an error signal of the echo signal relative to the echo cancellation correction signal and path information related to the echo correction circuit, wherein the echo correction circuit converges the plurality of response coefficients according to the error signal and pseudo-noise transmission path information from the digital-to-analog conversion circuit to the echo transmission circuit, and updates the plurality of code word deviation tables according to the offsets.

2. The digital-to-analog conversion apparatus of claim 1, further comprising a signal input circuit configured to feed signals into the digital-to-analog conversion circuit, comprising:

an odd-numbered feed-in circuit for picking up the odd-numbered input part of the input digital signal for output;

an even feed-in circuit for picking up the even input part of the input digital signal for output;

an odd pseudo noise generating circuit for generating an odd pseudo noise digital signal and feeding it into the digital-to-analog converting circuit; and

an even pseudo noise generating circuit generates an even pseudo noise digital signal to be fed into the digital-to-analog converting circuit.

3. The digital-to-analog conversion apparatus of claim 2, wherein the digital-to-analog conversion circuit comprises:

an output conversion circuit for receiving the odd input part and the even input part of the input digital signal and converting the odd input part and the even input part to generate the output analog signal;

an output echo cancellation converting circuit for receiving the odd-numbered input part and the even-numbered input part of the input digital signal and converting the odd-numbered input part to generate an output echo cancellation analog signal in the echo cancellation analog signal to the echo path; and

a pseudo noise converting circuit receives the odd pseudo noise digital signal and the even pseudo noise digital signal for conversion to generate a pseudo noise analog signal to the echo path.

4. The digital-to-analog conversion apparatus of claim 3, wherein the echo correction circuit comprises:

an odd output echo cancellation correction circuit comprising:

a first mapping circuit for receiving the odd input part of the input digital signal and mapping the odd input part according to a first codeword deviation table in the codeword deviation tables to generate a first mapping signal; and

a first response circuit for receiving the first mapping signal and processing the first mapping signal according to a first response coefficient of the plurality of response coefficients to generate an odd number output echo cancellation correction signal of the echo cancellation correction signals;

an even output echo cancellation correction circuit comprising:

a second mapping circuit for receiving the even number input part of the input digital signal and mapping the even number input part according to a second codeword deviation table in the codeword deviation tables to generate a second mapping signal; and

a second response circuit for receiving the second mapping signal and processing the second mapping signal according to a second response coefficient of the plurality of response coefficients to generate an even number of the echo cancellation correction signals and outputting the echo cancellation correction signals;

an odd pseudo noise correction circuit for receiving the odd pseudo noise digital signal and processing the odd pseudo noise digital signal according to a group of odd pseudo noise response coefficients to generate an odd pseudo noise correction signal; and

an even pseudo noise correction circuit receives the even pseudo noise digital signal and processes the even pseudo noise digital signal according to a set of even pseudo noise response coefficients to generate an even pseudo noise correction signal.

5. The digital-to-analog conversion apparatus of claim 4, wherein in a first training phase, the output conversion circuit and the pseudo noise conversion circuit are enabled to make the odd pseudo noise correction circuit and the even pseudo noise correction circuit converge the set of odd pseudo noise response coefficients and the set of even pseudo noise response coefficients according to the echo signal, so that the first response circuit and the second response circuit set the converged set of odd pseudo noise response coefficients and the set of even pseudo noise response coefficients as the set of first response coefficients and the set of second response coefficients, respectively; and

in a second training phase, the output echo cancellation conversion circuit is further enabled to update the first codeword deviation table and the second codeword deviation table according to a first offset and a second offset of the offsets related to the odd output echo cancellation correction circuit and the even output echo cancellation correction circuit.

6. The digital-to-analog conversion apparatus according to claim 4, wherein the signal input circuit further comprises an odd filter circuit and an even filter circuit for respectively capturing the odd input portion and the even input portion of the input digital signal for filtering and outputting as an odd filter signal and an even filter signal to the digital-to-analog conversion circuit;

the digital-to-analog conversion circuit further comprises a non-matched echo cancellation conversion circuit for receiving the odd-numbered filter signal and the even-numbered filter signal and converting the odd-numbered filter signal to generate a non-matched echo cancellation analog signal of the echo cancellation analog signals to the echo path;

the echo correction circuit further comprises:

an odd-numbered mismatch echo cancellation correction circuit comprising:

a third mapping circuit for receiving the odd-numbered filter signal and mapping the odd-numbered filter signal according to a third codeword deviation table in the codeword deviation tables to generate a third mapping signal; and

a third response circuit for receiving the third mapping signal and processing the third mapping signal according to a third response coefficient of the plurality of response coefficients to generate an odd number mismatch echo cancellation correction signal of the echo cancellation correction signals;

an even-numbered mismatch echo cancellation correction circuit comprising:

a fourth mapping circuit for receiving the even-numbered filter signal and mapping the even-numbered filter signal according to a fourth codeword deviation table of the codeword deviation tables to generate a fourth mapping signal; and

a fourth response circuit for receiving the fourth mapping signal and processing the fourth mapping signal according to a fourth response coefficient of the plurality of response coefficients to generate an even number mismatch echo cancellation correction signal of the echo cancellation correction signals;

the third response circuit and the fourth response circuit respectively set the converged set of odd pseudo noise response coefficients and the set of even pseudo noise response coefficients as the set of third response coefficients and the set of fourth response coefficients, and the mismatch echo cancellation conversion circuit is further enabled in a second training phase to update the third codeword deviation table and the fourth codeword deviation table according to a third offset and a fourth offset related to the odd mismatch echo cancellation correction circuit and the even mismatch echo cancellation correction circuit among the offsets.

7. The digital-to-analog conversion apparatus of claim 6, wherein the echo transmitting circuit downsamples to generate an odd echo signal and an even echo signal having an odd sign for the second frequency, the even echo signal having an even sign, the digital-to-analog conversion apparatus further comprising an update circuit comprising:

an odd response circuit for picking up the odd input part of the input digital signal to respond and outputting an odd response signal;

an even response circuit for capturing the even input part of the input digital signal to respond and outputting as an even response signal; and

an interactive operation circuit updates a set of odd filter parameters of the odd filter circuit and a set of even filter parameters of the even filter circuit according to an interactive operation result among the odd response signal, the even response signal, the odd sign and the even sign.

8. The digital-to-analog conversion apparatus according to claim 6, wherein the signal input circuit further comprises a limiting circuit configured to limit a maximum value and a minimum value of the odd-numbered filtered signal and the even-numbered filtered signal to a predetermined maximum value and a predetermined minimum value, respectively, and then to transmit the maximum value and the minimum value to the digital-to-analog conversion circuit.

9. The digital-to-analog conversion apparatus of claim 1, further comprising a residual echo cancellation circuit comprising:

the residual echo response circuit receives the input digital signal and processes the input digital signal according to a group of residual echo response coefficients to generate a residual echo cancellation signal; and

a cancellation circuit for subtracting the residual echo cancellation signal from the error signal to generate a final error signal;

the residual echo response circuit converges according to the final error signal, and the correction parameter operation circuit generates the offsets according to the final error signal and the path information related to the echo correction circuit.

10. A digital-to-analog conversion method with signal correction mechanism is applied to a digital-to-analog conversion device, comprising:

converting by a digital-to-analog conversion circuit according to a signal feed-in related to an input digital signal having an input codeword, generating an output analog signal and an echo cancellation analog signal, the echo cancellation analog signal performing at least one output echo cancellation on the output analog signal on an echo path, wherein the digital-to-analog conversion circuit comprises a plurality of conversion circuits operating at a first frequency;

the echo path is processed by an echo transmitting circuit to generate an echo signal with a second frequency, wherein the second frequency is half of the first frequency;

an echo correction circuit is used for generating an odd correction part and an even correction part of an echo cancellation correction signal according to the signal feed related to an odd input part and an even input part of the input digital signal and mapping by a complex code word deviation table and processing by a complex group of response coefficients, wherein the echo correction circuit comprises an odd correction circuit and an even correction circuit which are operated at the second frequency and correspond to the conversion circuits used for generating the echo cancellation analog signal;

generating a plurality of offsets by a correction parameter operation circuit according to an error signal of the echo signal relative to the echo cancellation correction signal and path information related to the echo correction circuit, wherein the correction parameter operation circuit operates at the second frequency; and

the echo correction circuit converges the plurality of groups of response coefficients according to the error signal and pseudo noise transmission path information from the digital-to-analog conversion circuit to the echo transmission circuit, and updates the plurality of groups of code word deviation tables according to the offsets.