CN117133781A - Image sensor structure and forming method thereof - Google Patents

Abstract

The application provides an image sensor structure and a forming method thereof. A semiconductor structure is disclosed. The semiconductor structure includes a plurality of pixels and adjacent pixels separated by deep trench isolation structures. In an embodiment, a method of forming a semiconductor structure includes: epitaxially growing a p-type semiconductor layer on the substrate; epitaxially growing an n-type semiconductor layer over the p-type semiconductor layer; forming a p-type well in the n-type semiconductor layer after epitaxial growth of the n-type semiconductor layer; forming an n-type doped region in the n-type semiconductor layer, the n-type doped region being surrounded by the p-type well; forming a first trench extending through the n-type semiconductor layer and the p-type semiconductor layer and surrounding the p-type well; and forming a first isolation structure in the first trench.

Description

Image sensor structure and forming method thereof

Technical Field

The present disclosure relates to the field of semiconductor technology, and more particularly, to an image sensor structure and a method of forming the same.

Background

The semiconductor Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in IC materials and design have resulted in multi-generation ICs, where each generation has smaller and more complex circuitry than the previous generation. During the development of ICs, the functional density (i.e., the number of interconnected devices per chip area) generally increases, while the geometry (i.e., the smallest component (or line) that can be created using a manufacturing process) decreases. This shrinking process generally provides benefits by improving production efficiency and reducing associated costs. This shrinking also increases the complexity of processing and manufacturing ICs.

Techniques for fabricating image sensors are also continually advancing, such as Complementary Metal Oxide Semiconductor (CMOS) image sensor technology. The demand for higher resolution and lower power consumption has driven the trend toward further miniaturization and integration of image sensors. The corresponding pixels in the image sensor are thus scaled down. Such a shrinking process generally provides benefits by improving production efficiency and reducing associated costs. This reduction also increases the complexity of processing and manufacturing. For example, as the size of pixels continues to decrease, optical crosstalk and interference between pixels may occur more frequently. Furthermore, as the size of pixels continues to decrease, controlling the accuracy of the implantation process used to form the various doped regions in the pixels becomes a challenge. While existing CMOS image sensors generally have served their intended purpose, they have not been satisfactory in all respects.

Disclosure of Invention

According to an aspect of the present application, there is provided a method comprising: epitaxially growing a p-type semiconductor layer on the substrate; epitaxially growing an n-type semiconductor layer over the p-type semiconductor layer; forming a p-type well in the n-type semiconductor layer after epitaxial growth of the n-type semiconductor layer; forming an n-type doped region in the n-type semiconductor layer, the n-type doped region being surrounded by the p-type well; forming a first trench extending through the n-type semiconductor layer and the p-type semiconductor layer and surrounding the p-type well; and forming a first isolation structure in the first trench.

According to another aspect of the application, there is provided a method comprising: forming an n-type semiconductor layer of a photodiode over a top surface of a substrate; forming a p-well in an n-type semiconductor layer of the photodiode; forming a floating diffusion region in an n-type semiconductor layer of the photodiode and adjacent to the p-well; forming an isolation structure extending through the p-well and the n-type semiconductor layer of the photodiode; and forming a gate structure extending through the floating diffusion region and into the n-type semiconductor layer of the photodiode, wherein the gate structure is disposed between the p-well and the floating diffusion region, wherein the gate structure surrounds the floating diffusion region in a top view.

According to yet another aspect of the present application, there is provided a semiconductor structure comprising: a first semiconductor layer including a first type dopant; a first doped region formed in the first semiconductor layer and including a first type dopant; a gate structure extending into the first semiconductor layer and adjacent to the first doped region, wherein, in a top view, the gate structure surrounds the first doped region; a second doped region formed in the first semiconductor layer and spaced apart from the first doped region by the gate structure, wherein the second doped region includes a second type dopant having a doping polarity opposite to a doping polarity of the first type dopant; and an isolation structure extending through the first semiconductor layer and adjacent to the second doped region.

Drawings

The disclosure may be best understood from the following detailed description when read with the accompanying drawing figures. Note that the various features are not drawn to scale and are for illustrative purposes only, in accordance with industry standard practices. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates a flow chart of an exemplary method for fabricating a semiconductor structure in accordance with various embodiments of the present disclosure.

Fig. 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 and 15 illustrate partial cross-sectional views of a workpiece during various stages of manufacture in the method of fig. 1 in accordance with aspects of the present disclosure.

FIG. 16 illustrates a partial cross-sectional view of an alternative embodiment of the workpiece shown in FIG. 8 in accordance with aspects of the present disclosure.

Fig. 17 illustrates a partial top view of a semiconductor structure in accordance with aspects of the present disclosure.

Fig. 18 illustrates a partial top view of an alternative semiconductor structure in accordance with aspects of the present disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the application. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed beyond the scope of the depicted.

Furthermore, in the present disclosure below, the formation of a feature over, connection of a feature to, and/or coupling of a feature to another feature may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed between the features so that the features may not be in direct contact. Furthermore, spatially relative terms, such as "lower," "upper," "horizontal," "vertical," "above," "below," "upper," "lower," "top," "bottom," and the like, as well as derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.), are intended to facilitate the relationship of one feature to another in the present disclosure. Spatially relative terms are intended to encompass different orientations of the device in which the features are included.

Furthermore, when a number or range of numbers is described using "about," "approximately," etc., the term is intended to cover numbers within a reasonable range that accounts for inherent variations in the manufacturing process as understood by one of ordinary skill in the art. For example, the number or range of numbers encompasses a reasonable range including the number, e.g., within +/-10% of the number, based on known manufacturing tolerances associated with manufacturing features having characteristics associated with the number. For example, a material layer having a thickness of "about 5nm" may range in size from 4.25nm to 5.75nm, with the manufacturing tolerances associated with depositing the material layer known to those of ordinary skill in the art as +/-15%. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

The image sensor may include an array of pixels arranged in two dimensions. Each pixel includes a photodiode and a plurality of transistors (e.g., transfer gate transistors (transfer gate transistor)) formed in a pixel region. Typically, the photodiode includes an n-type region with a graded doping profile to increase charge transfer from the photodiode to the floating diffusion region of the pixel. According to the graded doping profile, the dopant concentration of the upper portion of the n-type region closer to the gate structure of the pass gate transistor is higher than the dopant concentration of the lower portion of the n-type region of the photodiode farther from the gate structure. In some prior art techniques, forming the n-type region of the photodiode in a small pixel includes: a thick photoresist layer is formed over the p-type substrate, the thick photoresist layer is patterned to form a patterned thick photoresist layer, and an ion implantation process is performed while using the patterned thick photoresist layer as an implantation mask. However, for devices with small pixel pitch, the patterned thick photoresist layer may collapse due to its high aspect ratio (i.e., its thickness to width ratio), resulting in undesirable implantation results and reduced performance of the pixel. Furthermore, deep Trench Isolation (DTI) structures have been chosen as a promising approach for isolating adjacent pixels of CMOS image sensors. In the fabrication process of the image sensor, surface defects (e.g., dangling bonds) may be formed in regions of the semiconductor substrate near the sidewalls of the DTI structure. Such surface defects may generate electric charges even without any incident light. If left untreated, surface defects may produce dark currents, resulting in white pixels. It is desirable to improve passivation along the entire sidewall of the DTI structure to reduce surface defects.

The present disclosure relates generally to image sensors. More particularly, some embodiments relate to CMOS image sensors having a DTI structure defining an array of pixel regions for pixels in which components of the pixel reside. In an embodiment, the n-type region of the photodiode is formed by less of a maskless epitaxial growth process and is doped in situ, rather than using a photolithographic process that requires high resolution. Thus, the manufacturing cost can be advantageously reduced. In some embodiments, the DTI structure is a hybrid structure including a dielectric liner extending along sidewall surfaces of the conductive material layer. By applying an appropriate bias voltage to the conductive material layer, carrier accumulation can be formed near the sidewalls of the DTI structure to reduce surface defects. In some embodiments, the gate structure of the transfer gate transistor may be a vertical gate structure surrounding the floating diffusion region of the pixel, providing better control over charge transfer.

Aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, fig. 1 is a flowchart illustrating a method 100 of forming a semiconductor structure in accordance with an embodiment of the present disclosure. The method 100 is described below in connection with fig. 2-18, where fig. 2-16 are partial cross-sectional views of a workpiece 200 at various stages of fabrication in the method of fig. 1, and fig. 17-18 illustrate exemplary partial top views of a semiconductor structure. The method 100 is merely an example and is not intended to limit the present disclosure to what is explicitly described therein. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of the methods. For simplicity reasons, not all steps are described in detail herein. Because the workpiece 200 will be manufactured into the semiconductor structure 200 or the image sensor 200 after the manufacturing process is finished, the workpiece 200 may be referred to as the semiconductor structure 200 or the image sensor 200 depending on the context. The method 100 may be used to form stacked silicon CMOS image sensors, non-stacked image sensors, and other suitable structures. For the avoidance of doubt, X, Y and Z directions in the drawings are perpendicular to each other and are used consistently. In this disclosure, like reference numerals refer to like features unless otherwise specified.

Referring to fig. 1-2, the method 100 includes a block 102 in which a p-type semiconductor layer 204 is epitaxially formed over a front side surface of a substrate 202. A workpiece 200 is provided. The workpiece 200 includes a plurality of pixel regions (e.g., pixel region 1000 for forming pixels) and a plurality of isolation regions (e.g., isolation region 2000) for forming isolation structures (e.g., deep trench isolation structures). After the fabrication process in method 100 is completed, an isolation structure (e.g., DTI structure 220a shown in fig. 8) formed in isolation region 2000 isolates two adjacent pixel regions 1000. The isolation region 2000 may be disposed at an edge of each pixel region 1000 such that each pixel region 1000 may be defined as an enclosed space surrounded by walls of an isolation structure (e.g., DTI structure 220a shown in fig. 8) to be formed, as seen in a top view.

The workpiece 200 includes a substrate 202. In an embodiment, substrate 202 is a bulk silicon substrate (i.e., comprising bulk single crystal silicon). In various embodiments, the substrate 202 may include other semiconductor materials, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, siGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP, gaInAsP, or a combination thereof. In some alternative embodiments, the substrate 202 may comprise a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate, and include a carrier, an insulator on the carrier, and a semiconductor layer on the insulator. In an embodiment, the substrate 202 comprises undoped silicon. The substrate 202 includes a first surface 202a and a second surface 202b facing each other. In the embodiment shown in fig. 2, the first surface 202a is a top or front side surface of the substrate 202, and the second surface 202b is a bottom or back side surface of the substrate 202.

Still referring to fig. 2, a first semiconductor layer 204 is formed on the first surface 202a of the substrate 202. In this embodiment, an epitaxial growth process is performed to epitaxially grow the first semiconductor layer 204. The first semiconductor layer 204 may be formed using a process such as Vapor Phase Epitaxy (VPE), ultra high vacuum chemical vapor deposition (UHV-CVD), low pressure vapor deposition (LPCVD), and/or Plasma Enhanced Chemical Vapor Deposition (PECVD), molecular Beam Epitaxy (MBE), or other suitable epitaxial processes, or combinations thereof. The epitaxial growth process allows the first semiconductor layer 204 to grow from the first surface 202a of the substrate. In this embodiment, the first semiconductor layer 204 is a p-type semiconductor layer, and may be referred to as a p-type epitaxial layer 204. The p-type epitaxial layer 204 is doped in situ with dopant(s). For example, the p-type epitaxial layer 204 may include boron doped silicon. Forming the p-type semiconductor layer 204 may advantageously prevent or reduce electrons in the n-type semiconductor layer 206 (shown in fig. 2) from moving to the bottom surface of the photodiode. In some embodiments, the thickness of the p-type semiconductor layer 204 may be between a few nanometers and hundreds of nanometers.

Still referring to fig. 1-2, the method 100 includes block 104 in which a second semiconductor layer 206 is epitaxially formed on the first semiconductor layer 204. The doping polarity of the second semiconductor layer 206 is opposite to the doping polarity of the first semiconductor layer 204. In embodiments in which the first semiconductor layer 204 is a p-type semiconductor layer, the second semiconductor layer 206 is an n-type semiconductor layer. The second semiconductor layer 206 may be referred to as an n-type semiconductor layer in this embodiment. An epitaxial growth process is performed to epitaxially grow the n-type semiconductor layer 206. The n-type semiconductor layer 206 may be formed using a process such as Vapor Phase Epitaxy (VPE), ultra high vacuum chemical vapor deposition (UHV-CVD), low pressure vapor deposition (LPCVD), and/or Plasma Enhanced Chemical Vapor Deposition (PECVD), molecular Beam Epitaxy (MBE), or other suitable epitaxial process, or a combination thereof. The epitaxial growth process allows the n-type semiconductor layer 206 to grow from the top surface of the p-type semiconductor layer 204. The n-type semiconductor layer 206 may also be referred to as an n-type epitaxial layer 206. The n-type semiconductor layer 206 is doped in-situ with dopant(s). For example, n-type semiconductor layer 206 may include phosphorus doped silicon. In an embodiment, the n-type semiconductor layer 206 is a charge collecting portion of a photodiode. A PN junction may be formed near the top surface of the p-type semiconductor layer 204 to prevent or reduce electrons in the n-type semiconductor layer 206 from moving to the bottom surface of the n-type semiconductor layer 206. In various embodiments, the dopant concentration of the n-type semiconductor layer 206 is non-uniform along the Z-direction. In an embodiment, the dopant concentration of the n-type semiconductor layer 206 is continuously graded from its bottom surface to its top surface to increase the efficiency of the photodiode. For example, the dopant concentration of the upper portion of the n-type semiconductor layer 206 is greater than the dopant concentration of the lower portion of the n-type semiconductor layer 206. Since the n-type semiconductor layer 206 is epitaxially formed and the dopant concentration may be adjusted along the epitaxial growth process, an implantation process (e.g., ion implantation) for forming an n-type doped region in the p-type substrate may be omitted. Accordingly, manufacturing costs associated with the formation of the n-type region of the photodiode may be advantageous, and a manufacturing process for forming a device having a small pixel pitch may be simplified.

Referring to fig. 1 and 3, the method 100 includes a block 106 in which a doped well 208 is formed in the second semiconductor layer 206 and in the pixel region 1000. The doping polarity of the doping well 208 is opposite to the doping polarity of the second semiconductor layer 206. In embodiments in which the second semiconductor layer 206 is an n-type semiconductor layer, the doped well 208 is a p-type well 208. The p-type well 208 may be referred to as a p-well 208. After epitaxially forming the n-type semiconductor layer 206, a photoresist layer (not shown) may be formed over the n-type semiconductor layer 206, exposed to a radiation source using a photomask, and then developed to form a patterned photoresist layer. A doping process may be performed to form a p-type well 208 in the n-type semiconductor layer 206 while using the patterned photoresist layer as an implantation mask. Forming the p-type well 208 in the n-type semiconductor layer 206 may prevent or reduce electrons in the n-type semiconductor layer 206 from moving to the top surface of the photodiode. In this embodiment, the doping process may include an ion implantation process, and may be performed by implanting an appropriate p-type dopant (e.g., boron). The thickness of the p-type well 208 may be between a few nanometers and a few hundred nanometers. In an embodiment, the p-type well 208 may comprise a ring shape in top view. In the cross-sectional view of the workpiece 200 depicted in fig. 3, two portions of the p-type well 208 are shown. After the p-type well 208 is formed, the patterned photoresist layer may be selectively removed.

Referring to fig. 1 and 4, the method 100 includes a block 108 in which a doped region 210 is formed in the second semiconductor layer 206 and in the pixel region 1000. The doping polarity of the doped region 210 is the same as the doping polarity of the second semiconductor layer 206. In embodiments in which the second semiconductor layer 206 is an n-type semiconductor layer, the doped region 210 is an n-type doped region 210. The n-type doped region 210 may also be referred to as a floating diffusion region 210. In this embodiment, after forming the p-type well 208, another patterned photoresist layer (not shown) may be formed over the n-type semiconductor layer 206. A doping process (e.g., an ion implantation process) may be performed to form n-type doped regions 210 in the n-type semiconductor layer 206 while using the patterned photoresist layer as an implantation mask. The doping process may include an ion implantation process and may be performed by implanting an appropriate n-type dopant (e.g., phosphorus, arsenic). The dopant concentration of the n-type doped region 210 may be greater than the dopant concentration of the p-type well 208. In an embodiment, n-type doped region 210 may be a heavily doped region and p-type well 208 may be a lightly doped region. The depth of the n-type doped region 210 may be less than the depth of the p-type well 208. In an embodiment, in a top view, the p-type well 208 surrounds the n-type doped region 210.

Referring to fig. 1 and 5, the method 100 includes a block 110 in which a first etching process is performed to form a first trench 212, the first trench 212 extending through the n-type semiconductor layer 206 and the p-type semiconductor layer 204 and into the substrate 202. The first trench 212 surrounds the p-type well 208. In an embodiment, the shape of the first groove 212 comprises a ring shape in top view. In the cross-sectional view of the workpiece 200 depicted in fig. 5, two portions of the first trench 212 are shown. In some embodiments, forming the first trench 212 includes forming a patterned masking film (e.g., a photoresist layer or a hard mask layer) (not shown) over the workpiece 200. The patterned masking film may include an opening that exposes portions of the p-type well 208 and the n-type semiconductor layer 206 in the isolation region 2000. In some embodiments, the patterned masking film may include silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, other suitable materials, or combinations thereof, and may be formed by Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), other suitable methods, or combinations thereof. A first etching process is performed to form the first trench 212 in the isolation region 2000 while using the patterned masking film as an etching mask. In this embodiment, the first trench 212 extends through the p-type well 208, the n-type semiconductor layer 206, the p-type semiconductor layer 204, and into the substrate 202. That is, the first trench 212 exposes the substrate 202. The first etching process may be a dry etching process, a wet etching process, or a combination thereof, that implements a suitable etchant. The first trench 212 may include tapered sidewalls as shown in fig. 5 or 15, or have substantially vertical sidewalls as shown in fig. 14. After forming the first trench 212, the patterned masking film may be selectively removed.

Referring to fig. 1 and 6, the method 100 includes a block 112 in which a second etching process is performed to form a second trench 214 disposed between the p-type well 208 and the n-type doped region 210. In some embodiments, forming the second trench 214 includes forming a patterned masking film (e.g., a photoresist layer or a hard mask layer) (not shown) over the workpiece 200. The patterned masking film may include openings that expose portions of the p-type well 208 and the n-type doped region 210. In some embodiments, the patterned masking film may include silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, other suitable materials, or combinations thereof, and may be formed by Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), other suitable methods, or combinations thereof. While using the patterned masking film as an etching mask, a second etching process is then performed to form the second trenches 214 in the pixel region 1000. After forming the second trenches 214, the patterned masking film may be selectively removed. The second etching process and the first etching process may be performed with the same etchant(s). As shown in fig. 6, the second trench 214 isolates the p-type well 208 from the n-type doped region 210. For example, the p-type well 208 and the n-type doped region 210 are exposed in the second trench 214. In an embodiment, in a top view, the second trench 214 comprises a ring shape and surrounds the n-type doped region 210. In the present embodiment, the depth D2 of the second trench 214 is greater than the depth D1 of the n-type doped region 210, so that the gate structure formed in the second trench 214 may provide better control of charge transfer. In an embodiment, the depth D2 of the second trench 214 is less than the depth D3 of the first trench 212. In some alternative embodiments, the second trenches 214 may be formed prior to forming the first trenches 212.

Referring to fig. 1 and 7, the method 100 includes a block 114 in which a dielectric liner 216 is conformally formed over the workpiece 200 and the first trench 212 and the second trench 214. In some embodiments, dielectric liner 216 may comprise a low-k dielectric material (e.g., silicon oxide), a high-k dielectric material (e.g., silicon nitride, aluminum oxide, tantalum oxide, hafnium oxide, titanium oxide, zirconium oxide, silicon oxynitride), a combination thereof, or other suitable material(s) having a dielectric constant greater than silicon oxide, which is approximately 3.9 a dielectric constant. In the embodiment shown in fig. 7, the dielectric liner 216 is conformally formed over the workpiece 200 by a deposition process, such as Atomic Layer Deposition (ALD), chemical Vapor Deposition (CVD), thermal oxidation, or other suitable method. The term "conformal" may be used herein to facilitate the description of layers having a substantially uniform thickness in various regions. The deposited thickness of the dielectric liner 216 may be between about 5nm and about 50 nm. In some embodiments, the dielectric liner 216 may be a multi-layer structure. For example, forming the dielectric liner 216 may include conformally forming a first liner layer and conformally depositing a second liner layer over the first liner layer. After depositing the dielectric liner 216, a planarization process (e.g., chemical mechanical polishing) may be performed to remove excess portions of the dielectric liner 216 formed outside the first trench 212 and the second trench 214.

Referring to fig. 1 and 8-9, the method 100 includes a block 116 in which a layer 218 of conductive material is formed over the workpiece 200 and in the first trench 212 and the second trench 214. A layer 218 of conductive material is deposited over the workpiece 200 to substantially fill the first trench 212 and the second trench 214. In some embodiments, the conductive material layer 218 may include doped polysilicon, titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), or tantalum carbide (TaC), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metallic materials, or combinations thereof. In various embodiments, the conductive material layer 218 may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable process. In some embodiments, the composition of the conductive material layer 218 may be selected to increase the reflectivity of the deep trench isolation (DIT) structures 220a (shown in fig. 8) to be formed and to reduce light penetration.

After depositing the conductive material layer 218, a planarization process (e.g., chemical mechanical polishing) may be performed to remove excess portions of the conductive material layer 218. The planarization process also defines the structure of the Deep Trench Isolation (DTI) structure 220a formed in the first trench 212 and the structure of the vertical gate structure 220b formed in the second trench 214. The deep trench isolation structure 220a follows the shape of the first trench 212 and is formed in the isolation region 2000 to isolate or reduce electrical and optical crosstalk between two adjacent pixels. The vertical gate structure 220b follows the shape of the second trench 214 and is formed in the pixel region 1000. In various embodiments, a pixel may include a transfer transistor. The gate structure of the pass transistor may be referred to as a pass gate. In this embodiment, the vertical gate structure 220b is the transfer gate of the transfer gate transistor. The depth D2 (shown in fig. 6) of the vertical gate structure 220b is less than the depth D3 (shown in fig. 6) of the deep trench isolation structure 220a. In the present embodiment, the depth D2 of the vertical gate structure 220b is greater than the depth D1 of the floating diffusion region 210. In top view, the deep trench isolation structures 220a surround the pixel region 1000, and the vertical gate structures 220b surround the floating diffusion region 210. After forming the deep trench isolation structures 220a and the vertical gate structures 220b, other components or features (not explicitly shown) of the pixel may be formed in the pixel region 1000.

The n-type semiconductor layer 206 of the photodiode is a potential well for storing photoelectrons when the workpiece 200 is in operation. A bias voltage VDTI (shown in fig. 9) may be applied to the conductive material layer 218 of the deep trench isolation structure 220a to generate carrier accumulation near the sidewalls of the deep trench isolation structure 220a using field effect. In an embodiment in which the second semiconductor layer 206 is an n-type semiconductor layer 206, it is desirable to form hole accumulation. Providing hole accumulation will repel photoelectrons in the n-type semiconductor layer 206, so that the photoelectrons can be away from the interface between the n-type semiconductor layer 206 and the deep trench isolation structure 220a. In an embodiment, the bias voltage VDTI may be configured to be negatively biased such that electrons stored in the n-type semiconductor layer 206 are repelled away from the deep trench isolation structures 220a. A bias voltage VTX may be applied to the vertical gate structure 220b and a bias voltage VFD may be applied to the floating diffusion region 210. Whether electrons in the n-type semiconductor layer 206 can move to the floating diffusion region 210 is controlled by the bias voltage VTX and the bias voltage VFD. More specifically, when the transfer gate transistor is turned off, the bias voltage VTX may be configured to be negatively biased to pull up the surrounding potential energy, and electrons stored in the n-type semiconductor layer 206 may not reach the floating diffusion region 210 even when the bias voltage VFD is positively biased. When the transfer gate transistor is turned on, the bias voltage VTX may be configured to be forward biased to pull down the surrounding potential, and electrons in the n-type semiconductor layer 206 may move up and into the floating diffusion region 210 when the bias voltage VFD is forward biased.

In some embodiments, after forming features in the pixel region 1000, further processing may be performed to form the interconnect structure 222 over the first surface 202a of the substrate 202. In some embodiments, the interconnect structure 222 may include a plurality of inter-layer dielectric (ILD) layers and a plurality of metal lines or contact vias (e.g., gate vias) in each ILD layer. The metal lines and contact vias in each ILD layer may be formed of a metal, such as aluminum, tungsten, ruthenium, or copper. Since the interconnect structure 222 is formed over the front side of the workpiece 200, the interconnect structure 222 may also be referred to as a front side interconnect structure 222. The bias voltages VDTI, VTX, and/or VFD may be applied to the deep trench isolation structures 220a, the vertical gate structures 220b, and the floating diffusion regions 210, respectively, through metal lines and contact vias in the interconnect structures.

Referring to fig. 1 and 10-12, the method 100 includes a block 118 in which the workpiece 200 is flipped and a planarization process is performed on a backside surface (e.g., the second surface 202 b) of the workpiece 200. Referring to fig. 10, another substrate 224 is bonded or attached to the interconnect structure 222. In some embodiments, the substrate 224 may be bonded to the workpiece 200 by fusion bonding, by using an adhesive layer, or by other bonding methods. In some cases, the substrate 224 may be a carrier substrate and may include a semiconductor material (e.g., silicon), sapphire, glass, a polymeric material, or other suitable material. In some embodiments, substrate 224 may comprise an Application Specific Integrated Circuit (ASIC). The workpiece 200 is then flipped over as shown in fig. 11, with the substrate 202 on top and disposed over the interconnect structure 222. Referring to fig. 12, the workpiece 200 is thinned, planarized, recessed, etched, and/or polished from the second surface 202b until the conductive material layer 218 in the DTI structure 220a is exposed. In this embodiment, the substrate 202 may be partially removed. After the thinning process, DTI structure 220a extends completely through p-type semiconductor layer 204 and n-type semiconductor layer 206, and may be referred to as a Full DTI (FDTI) structure 220a. Accordingly, the pixels formed in the pixel region 1000 are electrically and optically isolated from the pixels in the adjacent pixel region 1000 by the FDTI structure 220a.

Referring to fig. 1 and 13, method 100 includes block 120 in which further processing is performed. Such further processing may include forming grid 226, color filters 228, and microlenses 230. Other suitable processes may be further performed to complete the fabrication of the semiconductor structure 200, which semiconductor structure 200 is in embodiments a backside illuminated image sensor.

In the above-described embodiment, the first trench 212 for forming the DTI structure 220a therein is formed from the front side surface of the n-type semiconductor layer 206 and includes tapered sidewalls. In some alternative embodiments, as shown in fig. 14, the first trench 212, and thus the DTI structure 220a formed therein, may have substantially vertical sidewalls. The profile of the first trench 212 may be adjusted by adjusting the etch parameters. In an alternative embodiment, as shown in fig. 15, the first trench 212 may be formed from a backside surface of the n-type semiconductor layer 206 and include tapered sidewalls. For example, the first trench 212 and the deep trench isolation structure 222a may be formed after the workpiece 200 is flipped.

In the above-described embodiments, the p-type well 208 may be annular in shape and surround the floating diffusion region 210 in a top view. In some other embodiments, for example, as shown in fig. 16, when the workpiece 200 includes a vertical gate structure that spans a larger width in the X-direction, another p-type well 208' may be formed between two portions of the vertical gate structure 220b and under the floating diffusion region 210. In some embodiments, the p-well 208' and the p-well 208 may be formed simultaneously by performing a blanket ion implantation process. Thus, the dopant concentration of the p-type well 208' is the same as the dopant concentration of the p-type well 208. In some other embodiments, the p-type well 208' may be formed after formation of the p-type well 208. For example, as described with reference to fig. 3, a first ion implantation mask may be provided and a first ion implantation process may be performed to form the p-type well 208. After the p-type well 208 is formed, the first ion implantation mask may be removed. Then, a second ion implantation mask may be provided, and a second ion implantation process may be performed to form a p-type well 208' surrounded by the p-type well 208. The dopant concentration of the p-type well 208' may be different from the dopant concentration of the p-type well 208. The floating diffusion region 210 may be formed after the p-type well 208' is formed. Operations of blocks 110-120 of method 100 may be performed to complete fabrication of workpiece 200.

Fig. 17 depicts a partial top view of semiconductor structure 200. In some embodiments, the workpiece 200 shown in fig. 15 may be a cross-sectional view of the semiconductor structure 200 taken along line A-A' shown in fig. 17. As shown in fig. 17, the gate structure 220b surrounds the floating diffusion region 210, the photodiode 232 surrounds the gate structure 220b, and the deep trench isolation structure 220a surrounds the photodiode 232 and isolates the photodiode 232 from adjacent photodiodes 232. The top view of the floating diffusion region 210 and the top view of the gate structure 220b may include square, rectangular, rounded square, or rounded rectangle.

Semiconductor structure 200 further includes a plurality of contacts formed over deep trench isolation structures 220a, photodiode 232, and gate structure 220 b. Bias voltages VDTI, VTX, and/or VFD may be applied to the deep trench isolation structures 220a, the vertical gate structures 220b, and the floating diffusion regions 210, respectively, through contacts. The semiconductor structure 200 further includes a drive transistor 236 adjacent to the deep trench isolation structure 220a. The drive transistor 236 may act as a source follower and may be configured to amplify the charge stored in the floating diffusion region 210 to effect charge-voltage conversion. The semiconductor structure 200 further includes a reset transistor 238. Although not shown, the source/drain terminal of the reset transistor 238 may be electrically connected to the floating diffusion region 210, and the gate terminal of the reset transistor 238 may be configured to receive a reset signal such that the reset transistor 238 may be turned on and off to reset the floating diffusion region 210 to a predetermined voltage (e.g., a voltage at or near the power supply voltage VDD) in response to the reset signal. The semiconductor structure 200 also includes a select transistor 240 (e.g., a row select transistor for selecting a row of pixels to operate). Although not shown, the source/drain terminal of the selection transistor 240 may be electrically connected to the source/drain terminal of the driving transistor 236, and the gate terminal of the selection transistor 240 is configured to receive a unit pixel selection signal such that the selection transistor 240 provides an output signal of the driving transistor 236 in response to the unit pixel selection signal. Semiconductor structure 200 may include additional features.

In the above-described embodiment described with reference to fig. 17, the top view of the floating diffusion region 210 and the top view of the gate structure 220b each include rounded rectangles. Other shapes are also possible. For example, as shown in fig. 18, a top view of the floating diffusion region 210 and a top view of the gate structure 220b each include hexagons.

Although not intended to be limiting, one or more embodiments of the present disclosure provide a number of benefits to image sensors and imaging systems. For example, by forming a DTI structure, a pixel can be electrically and optically isolated from its neighboring pixels. Optical crosstalk can be advantageously reduced or even substantially eliminated. By applying a negative bias voltage to the DTI structure, holes can accumulate at the sidewall surfaces of the DTI structure such that passivation is increased, thereby reducing dark current and white pixels without affecting other aspects of the device. In addition, the n-type region in the photodiode of the smaller pixel is formed by a maskless epitaxial growth process, instead of using a photolithography process requiring high resolution, the manufacturing cost can be advantageously reduced. Furthermore, the disclosed methods can be easily integrated into existing semiconductor manufacturing processes.

The present disclosure provides many different embodiments. Semiconductor structures and methods of making the same are disclosed herein. In one exemplary aspect, the present disclosure is directed to a method. The method comprises the following steps: epitaxially growing a p-type semiconductor layer on the substrate, epitaxially growing an n-type semiconductor layer over the p-type semiconductor layer, forming a p-type well in the n-type semiconductor layer after epitaxial growth of the n-type semiconductor layer, forming an n-type doped region in the n-type semiconductor layer, the n-type doped region being surrounded by the p-type well, forming a first trench extending through the n-type semiconductor layer and the p-type semiconductor layer and surrounding the p-type well, and forming a first isolation structure in the first trench.

In some embodiments, the method may further include forming a second trench to separate the p-type well and the n-type doped region, and forming a second isolation structure in the second trench. In some embodiments, the depth of the second trench may be greater than the depth of the n-type doped region. In some embodiments, the second isolation structure surrounds the n-doped region in a top view. In some embodiments, the forming of the first isolation structure may include conformally depositing a dielectric liner over the substrate, depositing a layer of conductive material over the dielectric liner, and performing a planarization process on the dielectric liner and the layer of conductive material to expose a top surface of the n-type semiconductor layer. In some embodiments, the layer of conductive material may include doped polysilicon, tungsten, titanium, or aluminum. In some embodiments, the dopant concentration of the upper portion of the n-type semiconductor layer may be different from the dopant concentration of the lower portion of the n-type semiconductor layer. In some embodiments, the method may further include forming a p-type doped region in the n-type semiconductor layer after forming the p-type well in the n-type semiconductor layer, wherein the p-type doped region is disposed directly below the n-type doped region.

In another exemplary aspect, the present disclosure is directed to a method. The method comprises the following steps: forming an n-type semiconductor layer of the photodiode over a top surface of the substrate, forming a p-well in the n-type semiconductor layer of the photodiode, forming a floating diffusion region in the n-type semiconductor layer of the photodiode and adjacent to the p-well, forming an isolation structure extending through the p-well and the n-type semiconductor layer of the photodiode, and forming a gate structure extending through the floating diffusion region and into the n-type semiconductor layer of the photodiode, wherein the gate structure is disposed between the p-well and the floating diffusion region, wherein in a top view the gate structure surrounds the floating diffusion region.

In some embodiments, the method may further include epitaxially forming a p-type semiconductor layer on the top surface of the substrate, wherein the n-type semiconductor layer of the photodiode is spaced apart from the substrate by the p-type semiconductor layer. In some embodiments, forming the n-type semiconductor layer may include epitaxially forming an in-situ doped n-type semiconductor layer over a top surface of the substrate, wherein a dopant concentration of an upper portion of the n-type semiconductor layer is different than a dopant concentration of a lower portion of the n-type semiconductor layer. In some embodiments, the forming of the isolation structure may include performing a first etching process to form a first trench extending through the p-well and the n-type semiconductor layer of the photodiode, conformally depositing a dielectric liner over the substrate and the first trench, depositing a layer of conductive material over the dielectric liner and in the first trench, and performing a planarization process on the dielectric liner and the layer of conductive material to expose a top surface of the n-type semiconductor layer. In some embodiments, the method may further include performing a planarization process on a bottom surface of the substrate to expose the conductive material layer, the bottom surface of the substrate being opposite to a top surface of the substrate, and forming a color filter under the photodiode. In some embodiments, the forming of the gate structure may further include performing a second etching process to form a second trench separating the p-well and the floating diffusion region, wherein the conformal deposition of the dielectric liner further partially fills the second trench, and the deposition of the layer of conductive material further fills a remaining portion of the second trench. In some embodiments, the bottom surface of the gate structure may be lower than the floating diffusion region. In some embodiments, the dopant concentration of the floating diffusion region may be greater than the dopant concentration of the p-well.

In another exemplary aspect, the present disclosure is directed to a semiconductor structure. The semiconductor structure includes: a first semiconductor layer including a first type dopant; a first doped region formed in the first semiconductor layer and including a first type dopant; a gate structure extending into the first semiconductor layer and adjacent to the first doped region, wherein in a top view the gate structure surrounds the first doped region; a second doped region formed in the first semiconductor layer and spaced apart from the first doped region by the gate structure, wherein the second doped region includes a second type dopant having a doping polarity opposite to a doping polarity of the first type dopant; and an isolation structure extending through the first semiconductor layer and adjacent to the second doped region.

In some embodiments, the semiconductor structure may further include: and a third semiconductor layer disposed below the first semiconductor layer and including a second type dopant, wherein the isolation structure further extends through the third semiconductor layer. In some embodiments, the isolation structure may further comprise: a conductive layer; and a dielectric layer extending along sidewall surfaces of the conductive layer. In some embodiments, the depth of the isolation structure may be greater than the depth of the gate structure, and the depth of the gate structure may be greater than the depth of the first doped region.

The foregoing disclosure outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A method, comprising:

epitaxially growing a p-type semiconductor layer on the substrate;

epitaxially growing an n-type semiconductor layer over the p-type semiconductor layer;

forming a p-type well in the n-type semiconductor layer after epitaxial growth of the n-type semiconductor layer;

forming an n-type doped region in the n-type semiconductor layer, the n-type doped region being surrounded by the p-type well;

forming a first trench extending through the n-type semiconductor layer and the p-type semiconductor layer and surrounding the p-type well; and

a first isolation structure is formed in the first trench.

2. The method of claim 1, further comprising;

forming a second trench to separate the p-type well and the n-type doped region; and

and forming a second isolation structure in the second groove.

3. The method of claim 2 wherein a depth of the second trench is greater than a depth of the n-type doped region.

4. The method of claim 2, wherein the second isolation structure surrounds the n-doped region in a top view.

5. The method of claim 1, wherein the forming of the first isolation structure comprises:

conformally depositing a dielectric liner over the substrate;

depositing a layer of conductive material over the dielectric liner; and

a planarization process is performed on the dielectric liner and the conductive material layer to expose a top surface of the n-type semiconductor layer.

6. The method of claim 5, wherein the layer of conductive material comprises doped polysilicon, tungsten, titanium, or aluminum.

7. The method of claim 1, wherein a dopant concentration of an upper portion of the n-type semiconductor layer is different from a dopant concentration of a lower portion of the n-type semiconductor layer.

8. The method of claim 1, further comprising:

after the p-type well is formed in the n-type semiconductor layer, a p-type doped region is formed in the n-type semiconductor layer, wherein the p-type doped region is disposed directly below the n-type doped region.

9. A method, comprising:

forming an n-type semiconductor layer of a photodiode over a top surface of a substrate;

forming a p-well in an n-type semiconductor layer of the photodiode;

forming a floating diffusion region in an n-type semiconductor layer of the photodiode and adjacent to the p-well;

forming an isolation structure extending through the p-well and the n-type semiconductor layer of the photodiode; and

forming a gate structure extending through the floating diffusion region and into an n-type semiconductor layer of the photodiode, wherein the gate structure is disposed between the p-well and the floating diffusion region,

wherein, in a top view, the gate structure surrounds the floating diffusion region.

10. A semiconductor structure, comprising:

a first semiconductor layer including a first type dopant;

a first doped region formed in the first semiconductor layer and including the first type dopant;

a gate structure extending into the first semiconductor layer and adjacent to the first doped region, wherein, in a top view, the gate structure surrounds the first doped region;

a second doped region formed in the first semiconductor layer and spaced apart from the first doped region by the gate structure, wherein the second doped region includes a second type dopant having a doping polarity opposite to a doping polarity of the first type dopant; and

an isolation structure extends through the first semiconductor layer and is adjacent to the second doped region.