CN117133752A

CN117133752A - Three-dimensional memory, preparation method thereof and memory system

Info

Publication number: CN117133752A
Application number: CN202210537683.9A
Authority: CN
Inventors: 王迪; 谢景涛; 周文犀; 夏志良; 霍宗亮
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-05-16
Filing date: 2022-05-16
Publication date: 2023-11-28

Abstract

The embodiment of the application provides a three-dimensional memory, a preparation method thereof and a memory system. The stacked structure defines, in a plane perpendicular to the stacking direction, a first region including a first dielectric layer and a gate layer stacked one on another, and a second region including a first dielectric layer and a second dielectric layer stacked one on another. The plurality of contact structures are located in the second region and are respectively connected with the plurality of gate layers located at different stack heights in a first direction parallel to the plane. The portion of the gate layer outside the second region in the first direction is a connection region, and the connection region in each gate layer has a plurality of different sizes in the first direction. By adjusting the size of the connection region of the gate layer in the first direction, the gate layers at different stacking heights can be electrically communicated with the corresponding contact structures, and the reliability of the three-dimensional memory is improved.

Description

Three-dimensional memory, preparation method thereof and memory system

Technical Field

The present application relates to the field of semiconductor design and fabrication, and more particularly, to a structure of a three-dimensional memory, a method of manufacturing the three-dimensional memory, and a memory system.

Background

With the rising and developing fields of artificial intelligence, big data, internet of things, mobile communication, mobile equipment and cloud storage, the requirement on the storage density of a memory such as a three-dimensional memory is also higher and higher, however, the storage density of the memory is further increased more and more difficult due to factors such as technology, equipment and materials.

In addition, as the number of stacked layers in the memory increases and the storage density per unit area increases, the process steps in the fabrication of the three-dimensional memory become complicated and lengthy. Therefore, how to simplify the manufacturing process of the three-dimensional memory while considering the reliability and the overall performance of the three-dimensional memory is a problem to be solved at present.

Disclosure of Invention

Embodiments of the present application provide a three-dimensional memory, a method of manufacturing the same, and a memory system that can at least partially solve the above-mentioned problems, or other problems, existing in the related art.

In one aspect, the application provides a three-dimensional memory comprising: a stacked structure defining a first region and a second region in a plane perpendicular to a stacking direction, wherein the first region includes a first dielectric layer and a gate layer stacked on each other, and the second region includes the first dielectric layer and the second dielectric layer stacked on each other; and a plurality of contact structures located in the second region and respectively connected with a plurality of gate layers located at different stack heights in a first direction, the first direction being parallel to the plane, wherein a portion of the gate layer located outside the second region in the first direction is a connection region, and the connection region in each gate layer has a plurality of different dimensions in the first direction.

In one embodiment, the contact structure includes a first contact structure connected with the gate layer at a first stack height and a second contact structure connected with the gate layer at a second stack height, the first stack height being smaller than the second stack height, wherein a length of a first portion of the first contact structure extending in the stacking direction is greater than a length of a first portion of the second contact structure extending in the stacking direction; and a length of the first portion of the first contact structure in the first direction at the first stack height is less than a length of the first portion of the second contact structure in the first direction at the second stack height.

In one embodiment, the connection region of each gate layer includes a plurality of partitions respectively corresponding to different contact structures, wherein a size of a first partition corresponding to a first portion of the first contact structure is larger than a size of a second partition corresponding to a first portion of the second contact structure in the first direction.

In one embodiment, the memory further comprises: a gate line spacing structure passing through the first region in the stacking direction and extending in a second direction, wherein the second direction is parallel to the plane and perpendicular to the first direction; and a dummy channel structure extending in the first region along the stacking direction and located between the gate line spacing structure and the contact structure, wherein a plurality of the dummy channel structures have different sizes from each other in the first direction.

In one embodiment, the dummy channel structure corresponding to the first contact structure has a smaller dimension in the first direction than the dummy channel structure corresponding to the second contact structure.

In one embodiment, the dummy channel structure corresponding to the first contact structure has a smaller area of the orthographic projection than the dummy channel structure corresponding to the second contact structure.

In one embodiment, the dimension D1 of the virtual channel structure in the first direction satisfies: d1 is less than or equal to 120nm and less than or equal to 150nm.

In one embodiment, the memory further comprises: a gate line spacing structure passing through the first region in the stacking direction and extending in a second direction, wherein the second direction is parallel to the plane and perpendicular to the first direction; and a dummy channel structure extending in the stacking direction between the gate line spacing structure and the contact structure, wherein a plurality of adjacent dummy channel structures have different pitches in the second direction.

In one embodiment, a pitch between adjacent dummy channel structures corresponding to the deeper contact structures in the second direction is greater than a pitch between adjacent dummy channel structures corresponding to the shallower contact structures in the second direction.

In one embodiment, the spacing L1 satisfies: l1 is more than or equal to 30nm.

In one embodiment, the dimension of the orthographic projection of the virtual channel structure in the plane in at least one direction is greater than or equal to the dimension in the other direction.

In one embodiment, the orthographic projection of the virtual channel structure has a circular or elliptical profile.

In one embodiment, the angle α between the orthographic projection of the virtual channel structure in the plane and the orthographic projection of the gate line clearance structure in the plane satisfies: alpha is less than 60 degrees.

Another aspect of the present application provides a storage system comprising: a controller; and the memory provided in any one of the aspects of the present application, the controller being coupled to the memory and configured to control the memory to store data.

In yet another aspect, the present application provides a method for preparing a three-dimensional memory, the method comprising: alternately stacking the first dielectric layer and the second dielectric layer to form a stacked structure; removing part of the second dielectric layer to form a gap, and filling the gap with a conductive material to form a gate layer; and forming a plurality of contact structures which extend along a stacking direction and are respectively connected with a plurality of gate layers positioned at different stacking heights in a first direction perpendicular to the stacking direction, wherein a region where the rest of the second dielectric layer is positioned is set as a second region, a portion of the gate layer positioned outside the second region in the first direction is a connection region, and the connection region in each gate layer has a plurality of different sizes in the first direction.

In one embodiment, the method further comprises: forming dummy channel structures extending in the stacking direction in the stacking structure before forming the void, wherein the dummy channel structures have different sizes from each other in the first direction, or adjacent dummy channel structures have different pitches in a second direction, or the dummy channel structures have different sizes from each other in the first direction, and adjacent dummy channel structures have different pitches in the second direction, wherein the second direction, the stacking direction, and the first direction are perpendicular to each other; and removing a portion of the second dielectric layer surrounding the virtual channel structure during the forming of the void.

In one embodiment, forming the contact structure includes: forming a plurality of contact holes, wherein the contact holes respectively extend to second dielectric layers at different stacking heights along the stacking direction, the contact holes comprise a first contact hole and a second contact hole, the length of the first contact hole along the stacking direction is larger than that of the second contact hole along the stacking direction, and the bottom aperture of the first contact hole is smaller than that of the second contact hole; forming a barrier layer on the side wall of the contact hole; removing a part of the second dielectric layer in contact with the bottom of the contact hole through the contact hole to form a first opening, wherein the first opening exposes a gate layer with the same stacking height as the removed second dielectric layer; and filling conductive material at least in the surface of the barrier layer and the first opening to form a conductive contact layer.

In one embodiment, a dimension of the dummy channel structure corresponding to the first contact hole in the first direction is set smaller than a dimension of the dummy channel structure corresponding to the second contact hole in the first direction.

In one embodiment, forming a virtual channel structure extending in the stacking direction in the stacking structure includes: an area of orthographic projection of a virtual channel structure corresponding to the first contact hole in a plane perpendicular to the stacking direction is set smaller than an area of orthographic projection of a virtual channel structure corresponding to the second contact hole in the plane.

In one embodiment, forming a virtual channel structure extending in the stacking direction in the stacking structure includes: and setting the interval between adjacent virtual channel structures corresponding to the first contact holes in the second direction to be larger than the interval between adjacent virtual channel structures corresponding to the second contact holes in the second direction.

In one embodiment, forming a virtual channel structure extending in the stacking direction in the stacking structure includes: an orthographic projection of the virtual channel structure in a plane perpendicular to the stacking direction is set such that a dimension in at least one direction is greater than or equal to a dimension in the other direction.

In one embodiment, the method further comprises: forming a gate line gap passing through the stacked structure in the stacking direction and extending in the second direction; removing a portion of the second dielectric layer via the gate line gap to form the void; and setting an angle α between an orthographic projection of the virtual channel structure in a plane perpendicular to the stacking direction and an orthographic projection of the gate line clearance in the plane to be: alpha is less than 60 degrees.

According to the three-dimensional memory, the preparation method and the storage system thereof provided by at least one embodiment of the application, no step and word line contact on the step are required to be formed in the three-dimensional memory, and the electrical communication between the gate layers at different stacking heights and external circuits can be realized through the contact structures arranged in the second region of the three-dimensional memory.

In addition, in at least one embodiment of the present application, the connection region of the gate layer may be formed by removing a portion of the second dielectric layer of the first region in the stacked structure, for example, a portion of the second dielectric layer surrounding the dummy channel structure, forming a void, and filling the void with a conductive material. In the process of forming the connection region, the dimension of the space (or gap) for forming the connection region of the gate layer in the first direction can be adjusted by adjusting the characteristic dimension of the virtual channel structure, for example, at least one of the dimension of the virtual channel structure in the first direction, the orthographic projection area of the virtual channel structure in the plane of the first direction and the distance between the virtual channel structures, so that the dimension of the connection region corresponding to the contact structures in each gate layer in the first direction is different, and the gate layers at different stacking heights can be in good electrical communication with the corresponding contact structures, thereby improving the reliability of the three-dimensional memory.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the following drawings. In the drawings:

FIG. 1 is a schematic perspective view of a portion of a three-dimensional memory according to one embodiment of the application;

FIG. 2A is a schematic cross-sectional view of the three-dimensional memory shown in FIG. 1 taken along line A-A';

FIG. 2B is a schematic cross-sectional view of the three-dimensional memory shown in FIG. 1 taken along line B-B';

FIG. 3A is a schematic partial cross-sectional view of a three-dimensional memory according to one embodiment of the application;

FIG. 3B is a schematic partial cross-sectional view of a three-dimensional memory according to another embodiment of the application;

FIG. 3C is a schematic partial cross-sectional view of a three-dimensional memory according to yet another embodiment of the application;

FIG. 4 is an enlarged cross-sectional schematic view of the contact structure of FIG. 2B, according to one embodiment of the present application;

FIG. 5 is a schematic view of a first portion according to one embodiment of the application;

FIG. 6 is a partial top schematic view of a three-dimensional memory according to one embodiment of the application;

FIGS. 7-9 are partial top schematic views of a three-dimensional memory according to one embodiment of the application;

FIG. 10 is a schematic view of a partition of a laminate structure according to one embodiment of the application;

FIG. 11 is a schematic view of a partition of a laminate structure according to another embodiment of the present application;

fig. 12 to 15 are schematic front projection views of a dummy channel structure and a gate line spacing structure in a plane perpendicular to a stacking direction, respectively, according to an embodiment of the present application;

FIG. 16 is a flow chart of a method of fabricating a three-dimensional memory according to one embodiment of the application;

17A-17M are process diagrams of a method of fabricating a three-dimensional memory according to one embodiment of the application, respectively; and

FIG. 18 is a schematic diagram of a storage system architecture according to one embodiment of the application.

Detailed description of the preferred embodiments

The present application will be described in detail below with reference to the attached drawings, and the exemplary embodiments mentioned herein are only for explaining the present application, not for limiting the scope of the present application. Like reference numerals refer to like elements throughout the specification.

In the drawings, the thickness, size, and shape of the components have been slightly adjusted for convenience of description. The figures are merely examples and are not drawn to scale. As used herein, the terms "about," "approximately," and similar terms are used to represent approximations, rather than degrees of expression, and are intended to illustrate inherent deviations in measured or calculated values that will be appreciated by one of ordinary skill in the art.

It is also to be understood that the expression "and/or" includes any and all combinations of one or more of the associated listed items. The terms "comprising," "including," "having," and/or "having" are intended to be inclusive and non-exclusive of the elements, features, and/or components that are described, but do not preclude the presence or addition of one or more other elements, features, components, and/or groups thereof. Furthermore, when a statement such as "at least one of the following" appears after a list of features listed, it modifies the entire list of features rather than just modifying the individual elements in the list. When describing embodiments of the present application, use of "may" means "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

In addition, when the terms "connected," "overlying" and/or "formed on …" are used in the present application, it may mean that the corresponding components are in direct contact or indirect contact, unless expressly defined otherwise or able to be deduced from the context.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. Furthermore, unless explicitly stated otherwise in the present disclosure, words defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.

In addition, the embodiments of the present application and the features of the embodiments may be combined with each other without collision. Furthermore, unless explicitly defined or contradicted by context, the particular steps in the methods described herein need not be limited to the order described, but may be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Fig. 1 is a schematic perspective partial view of a three-dimensional memory 1000 according to one embodiment of the application. Fig. 2A is a schematic cross-sectional view of the three-dimensional memory 1000 shown in fig. 1 taken along line A-A'. Fig. 2B is a schematic cross-sectional view of the three-dimensional memory 1000 shown in fig. 1 taken along line B-B'.

As shown in fig. 1, the three-dimensional memory 1000 includes: a stacked structure 200 and a plurality of contact structures 700. The stacked structure 200 defines a first region 01 and a second region 02 in a plane perpendicular to a stacking direction (z-direction), the plane being provided with a first direction (x-direction) and a second direction (y-direction) perpendicular to each other, wherein the first region 01 includes a first dielectric layer 210 and a gate layer 230 stacked on each other, the gate layer 230 being a control gate of each memory cell; the second region 02 includes a first dielectric layer 210 and a second dielectric layer 220 stacked on each other. A plurality of contact structures 700 are located in the second region 02 and are respectively connected with a plurality of gate layers 230 located at different stack heights in a first direction, and the gate layers 230 achieve electrical communication with external circuitry through their corresponding contact structures 700. A portion of each gate layer 230 located outside the second region 02 in the first direction is formed as a connection region 230-1. The connection region 230-1 of each gate layer 230 has a plurality of different sizes in the first direction. In addition, in fig. 1, in order to facilitate the observation of the connection between the contact structure 700 and the corresponding gate layer 230, the first dielectric layers 210 and the second dielectric layers 220 that the contact structure 700 passes through in the stacking direction are omitted, and the gate layer 230 has the same stacking height as the second dielectric layers 220 that are omitted.

Conventional three-dimensional memories typically include a stacked structure formed by alternating stacks of gate layers and dielectric layers, wherein word line contacts located in a stepped region in the stacked structure allow electrical communication of the gate layers with external circuitry.

However, as the number of stacked layers increases, the formation of word line contacts in the step region requires multiple steps such as photolithography and etching to form a stepped profile, which greatly increases the manufacturing cost of the three-dimensional memory; meanwhile, the larger the number of steps is, the larger the area of the step area to be formed is, and the integration level of the three-dimensional memory is not improved. In addition, the more the number of stacked layers, the more the warpage degree of the wafer is increased, the more difficult the alignment of the step surface in the step area is when the word line contact is formed, resulting in the degradation of the reliability or the low yield of the electrical test of the three-dimensional memory, and finally affecting the reliability and the overall performance of the three-dimensional memory.

The three-dimensional memory provided by the embodiment of the application has the advantages that steps and word line contacts positioned on the steps are not required to be formed in the three-dimensional memory, and the electrical communication between the gate layers positioned at different stacking heights and an external circuit can be realized through the contact structure arranged in the second region of the three-dimensional memory, so that the preparation process is simplified, the generation cost is reduced, the area required by a device is reduced, and the storage density, the reliability and the overall performance of the unit area of the three-dimensional memory are improved.

In addition, the contact structure generally includes a contact hole having a predetermined depth in the stacking direction formed through processes such as photolithography and etching so as to form a connection with the gate layers at different stack heights. However, with the improvement of the integration level of the three-dimensional memory and the increase of the stacking layer number, the depth of the contact hole connected with the gate layer at the lower stacking height is increased, and the gate layer is easily broken down in the process of forming the contact hole, so that short circuits between different gate layers are caused. The laminated structure in the three-dimensional memory provided by the embodiment of the application comprises the first area and the second area, wherein the second area is an insulating dielectric material laminated layer formed by mutually stacking the first dielectric layer and the second dielectric layer, and the contact structure is arranged in the insulating dielectric material laminated layer, so that the contact structure is electrically communicated with the corresponding grid electrode layer, and short circuit between different grid electrode layers can be prevented.

Specifically, referring to fig. 1 to 2B, the first region 01 of the stacked structure 200 may include a first dielectric layer 210 and a gate layer 230 stacked in a stacking direction. The gate layer 230 may include a conductive material, such as any one or combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide. The first dielectric layer 210 may be used as an isolation stack layer including, but not limited to, a layer of insulating dielectric material such as a silicon oxide layer. The second region 02 of the stacked structure 200 may include a first dielectric layer 210 and a second dielectric layer 220 stacked in a stacking direction, the first dielectric layer 210 and the second dielectric layer 220 being two different insulating dielectric material layers, for example, the second dielectric layer 220 includes, but is not limited to, an insulating dielectric material layer such as a silicon nitride layer. In addition, the plurality of second dielectric layers 220 and the plurality of gate layers 230 may have the same stack height. The number of layers of the laminated structure 200 is not limited to the number of layers shown in the figure, and may be provided separately as needed, for example, 32 layers, 64 layers, 128 layers, and the like.

In addition, the stacked structure 200 may further include a cover layer 240, which is located at the highest stacking position of the stacked structure 200. Capping layer 240 includes, but is not limited to, a layer of insulating dielectric material such as a silicon oxide layer.

In addition, as the demand for three-dimensional memory storage increases, the number of memory stacks increases. The stacked structure 200 may include a plurality of sub-stacked structures formed using, for example, a dual stack technique or a multi-stack technique. The plurality of sub-stack structures may be sequentially stacked in a stacking direction to form the stack structure 200, wherein each sub-stack structure may include a plurality of first regions including a first dielectric layer and a gate layer stacked one on another and a second region including a first dielectric layer and a second dielectric layer stacked one on another. The number of layers of each sub-stack structure may be the same or different. The contents of the single stacked structure described hereinafter may be fully or partially applied to a stacked structure formed of a plurality of sub-stacked structures, and thus, related or similar contents thereof will not be described again.

Referring to fig. 1, in one embodiment of the present application, the three-dimensional memory 1000 may further include a gate line spacing structure 400. The gate line spacing structure 400 passes through the first region 01 in the stacking direction and extends in the second direction. It is understood that the connection region 230-1 of the gate layer 230 is a portion of the gate layer 230 located between the gate line spacing structure 400 and the contact structure 700 in the first direction.

Referring to fig. 1 and 2A, the first direction size of the connection region 230-1 at the line A-A 'is m2, and referring to fig. 1 and 2B, the first direction size of the connection region 230-1 at the line B-B' is m1, and the first direction size m2 of the connection region 230-1 of the gate layer 230 at the line A-A 'is not equal to the first direction size m1 thereof at the line B-B'. The line A-A 'of the connection region 230-1 may be understood as an intersection of a portion of the connection region 230-1 corresponding to any of the contact structures 700 and a section along the line A-A'; the line B-B 'of the connection region 230-1 may be understood as an intersection of a portion of the connection region 230-1 corresponding to the other contact structure 700 and a cross-section of the line B-B'. Furthermore, the cross-section along the line A-A ', line B-B' may be, for example, a cross-section through the center point of the contact structure 700 and extending in the first direction, based on the center point of the orthographic projection of the contact structure 700 in a plane perpendicular to the stacking direction.

Fig. 4 is an enlarged cross-sectional schematic view of the contact structure 700 of fig. 2B, in accordance with one embodiment of the present application. Fig. 5 is a schematic view of a first portion 701 according to one embodiment of the application. Fig. 6 is a partial top schematic view of a three-dimensional memory 1000 according to one embodiment of the application.

As shown in fig. 4, the contact structure 700 may include two portions connected to each other, a first portion 701 and a second portion 702, wherein the first portion 701 extends along a stacking direction, and the second portion 702 connects the gate layer 230 and the first portion 701 at a stacking height corresponding to the gate layer 230 of the contact structure 700. Specifically, the first portion 701 may include a contact hole 710, a barrier layer 720, and a conductive material located in the contact hole 710, and the contact hole 710 may be generally formed by a process such as photolithography and etching, and extend in a stacking direction by a predetermined depth, wherein the predetermined depth may be determined according to a stacking height of the corresponding gate layer 230. The second portion 702 includes a first opening 730 and a conductive material filled in the first opening 730, and the first opening 730 is located in a plane perpendicular to the stacking direction and connected with the corresponding gate layer 230 and the contact hole 710. The first portion 701 and the second portion 702 include a conductive contact layer 740 formed of a conductive material, and thus electrical communication between the gate layer 230 and an external circuit may be achieved through the contact structure 700.

Alternatively, the conductive material forming the conductive contact layer 740 may include any one or combination of a conductive metal material such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and a doped semiconductor material such as doped crystalline silicon or silicide, etc., which is not limited in this regard.

Further, in one embodiment of the present application, the conductive contact layer 740 may not be completely filled with the contact hole 710 formed with the barrier layer 720, for example, the first portion 701 may include the barrier layer 720, the conductive contact layer 740, and the dielectric filling layer 750 sequentially formed at the sidewall of the contact hole 710. Dielectric fill layer 750 may be, for example, a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride. By forming the dielectric fill layer in the first portion of the contact structure, the use of conductive materials may be reduced, achieving the effect of reducing the cost of manufacturing the three-dimensional memory and reducing the stress deformation of the stacked structure.

In forming the contact structure 700, it is often necessary to remove a portion of the second dielectric layer 220 in contact with the bottom of the contact hole 710 through the contact hole 710 that has been formed, thereby forming a first opening 730 capable of exposing the gate layer 230 having the same stack height as the removed second dielectric layer 220, and forming a connection with the gate layer 230 by filling the contact hole 710 and the first opening 730 with a conductive material.

However, as shown in fig. 4 to 5, the contact hole extends in the stacking direction, and the hole diameter of the bottom portion thereof tends to be smaller with the hole depth, and the deeper contact hole generally has a smaller hole diameter, limited by the conventional process. For example, it can be appreciated that the first contact hole 710-1 shown in the left diagram of fig. 5 is connected to the gate layer 230 at a first stack height (as shown in fig. 2B), and the second contact hole 710-2 shown in the right diagram of fig. 5 is connected to the gate layer 230 at a second stack height (as shown in fig. 2A), the first stack height being smaller than the second stack height. Thus, the first contact hole 710-1 has a relatively deep hole depth h1 and has a small bottom aperture d1; in contrast, the second contact hole 710-2 shown in the right-hand drawing of fig. 5 has a relatively shallow hole depth h2 and has a larger bottom hole diameter d2. Alternatively, it is also understood that the length h1 of the deeper, first contact structure first portion 701-1 is greater than the length h2 of the shallower, second contact structure first portion 701-2; further, a dimension d1 of the first portion 701-1 of the first contact structure in the first direction at the first stack height is smaller than a dimension d2 of the first portion 701-2 of the second contact structure in the first direction at the second stack height.

As shown in fig. 5 to 6, fig. 6 includes an orthographic projection view of the first portions 701 of the plurality of contact structures 700 having different hole depths in fig. 5 projected into a plane perpendicular to the stacking direction, and it can be found that as the contact holes of the contact structures become deeper, the distance between the contact structures and their corresponding gate layers becomes larger. For example, a first contact hole 710-1 (or first portion 701-1 of a deeper first contact structure understood as a first contact hole having a relatively deep hole depth h1 and a smaller bottom hole diameter d 1) is orthographically projected into a plane perpendicular to the stacking direction, the distance between the first portion 701-1 of the deeper contact hole and the gate layer 230 being s1; conversely, the second contact hole 710-2 (or first portion 701-2 of the second contact structure, which is understood to be shallower) having a relatively shallower hole depth h2 and a larger bottom aperture d2, is orthographically projected into a plane perpendicular to the stacking direction, the first portion 701-2 having a shallower contact hole being at a distance s2 from the gate layer 230, the distance s1 being significantly greater than the distance s2.

Referring to fig. 2A and 2B, a thinner barrier layer 250 is further formed on the surface of the gate layer 230, and the barrier layer 250 may be a high dielectric metal compound such as aluminum oxide. Thus, as shown in fig. 6, when the dimensions of the connection regions 230-1 of the gate layer 230 in the first direction are consistent, for example, the dimensions are m0, in order to ensure that the contact structure having the deeper contact hole can be connected to the corresponding gate layer, the dimension of the first opening 730 in the first direction needs to be determined according to the distance s1 between the deepest contact hole (for example, the first contact hole 710-1) and the corresponding gate layer 230, which often results in damage of the barrier layer 250 on the surface of the gate layer 230 corresponding to the shallower contact hole (for example, the second contact hole 710-2) due to over etching or the like, causing leakage of the gate layer 230, and further affecting the yield and reliability of the three-dimensional memory device 1000.

Therefore, in at least one embodiment of the present application, by adjusting the size of the connection region of the gate layer in the first direction, it is ensured that the gate layers located at different stack heights can form good electrical communication with their corresponding contact structures in the first direction, thereby improving the reliability and overall performance of the three-dimensional memory.

In particular, referring to fig. 2A through 5, in one embodiment of the present application, the contact structure 700 may include a first portion 701 extending in a stacking direction. A dimension d1 of the first portion 701-1 of the deeper first contact structure 700-1 in the first direction at the first stack height is smaller than a dimension d2 of the first portion 701-2 of the shallower second contact structure 700-2 in the first direction at the second stack height, wherein the first contact structure 700-1 is connected with the gate layer 230 at the first stack height; the second contact structure 700-2 is connected with the gate layer 230 at the second stack height.

Furthermore, as an option, the connection region 230-1 of each gate layer 230 may include a plurality of partitions, such as a first partition (such as the connection region 230-1 shown in fig. 2B) corresponding to the first portion 701-1 of the deeper first contact structure 700-1 and a second partition (such as the connection region 230-1 shown in fig. 2A) corresponding to the first portion 701-2 of the shallower second contact structure 700-2, wherein a dimension m1 of the first partition along the first direction is greater than a dimension m2 of the second partition along the first direction.

Fig. 7 is a partial top schematic view of a three-dimensional memory 1000 according to one embodiment of the application. Fig. 8 is a partial top view schematic of a three-dimensional memory 1000 according to one embodiment of the application. Fig. 9 is a partial top view schematic of a three-dimensional memory 1000 according to one embodiment of the application.

Referring to fig. 1, 7 through 8, in one embodiment of the present application, the three-dimensional memory 1000 may further include a virtual channel structure 600. The dummy channel structure 600 extends in the first region 01 in the stacking direction and is located between the gate line spacing structure 400 and the contact structure 700. The plurality of dummy channel structures 600 have different sizes from each other in the first direction. For example, the dummy channel structure 600 corresponding to the deeper first contact structure 700-1 has a smaller dimension D1 in the first direction than the dummy channel structure 600 corresponding to the shallower second contact structure 700-2.

Further, alternatively, the dummy channel structure 600 corresponding to the deeper first contact structure 700-1 has a smaller area of orthographic projection in a plane perpendicular to the stacking direction than the dummy channel structure 600 corresponding to the shallower second contact structure 700-2.

Specifically, a plurality of virtual channel structures 600 corresponding to each contact structure 700 may be defined using a center line passing through the center point of the contact structure 700 and extending in the first direction, based on the center point of the orthographic projection of the first portion 701 of the contact structure 700 in a plane perpendicular to the stacking direction. An equal number of N dummy channel structures 600 on both sides of the center line of each contact structure 700 may be taken as the dummy channel structures 600 corresponding to each contact structure 700, where N is a positive integer greater than or equal to 1.

As shown in fig. 8, taking an orthographic projection of the dummy channel structure 600 in a plane perpendicular to the stacking direction as an example of a circular profile, it is understood that the dimension D1 of the dummy channel structure 600 in the first direction is a diameter of the circular profile. The dimension D1 of the plurality of dummy channel structures 600 corresponding to the deeper first contact structures 700-1 in the first direction is smaller than the dimension D1 of the plurality of dummy channel structures 600 corresponding to the shallower second contact structures 700-2 in the first direction.

Alternatively, in one embodiment of the present application, the dimension D1 of the virtual channel structure 600 in the first direction satisfies: d1 is less than or equal to 120nm and less than or equal to 150nm.

Further, the area of orthographic projection of the plurality of dummy channel structures 600 corresponding to the deeper first contact structures 700-1 in a plane perpendicular to the stacking direction is smaller than the area of orthographic projection of the plurality of dummy channel structures 600 corresponding to the shallower second contact structures 700-2 in the plane.

Referring to fig. 1, 7 to 9, in one embodiment of the present application, a pitch L1 in the second direction between a plurality of adjacent dummy channel structures 600 may be different.

For example, as shown in fig. 9, a plurality of virtual channel structures 600 corresponding to each contact structure 700 may also be defined by a center line passing through the center point of the contact structure 700 and extending in the x-direction, based on the center point of the orthographic projection of the first portion 701 of the contact structure 700 in a plane perpendicular to the stacking direction. An equal number of N dummy channel structures 600 on both sides of the center line of each contact structure 700 may be taken as the dummy channel structures 600 corresponding to each contact structure 700, where N is a positive integer greater than or equal to 1.

The spacing L1 between adjacent dummy channel structures 600 in the second direction corresponding to the deeper first contact structures 700-1 may be greater than the spacing L1 between adjacent dummy channel structures 600 in the second direction corresponding to the shallower second contact structures 700-2. Alternatively, the pitch L1 may be set to be a pitch between center points of orthographic projections of adjacent virtual channel structures 600 in a plane perpendicular to the stacking direction in the second direction.

Alternatively, in one embodiment of the present application, the pitch L1 between adjacent virtual channel structures corresponding to the contact structures in the second direction satisfies: l1 is more than or equal to 30nm.

Further, the above embodiments may be combined, for example, the dimensions of the dummy channel structures in the first direction may be adjusted, and the distance between the dummy channel structures may be adjusted.

Referring to fig. 1, 2A and 2B, the dummy channel structure 600 extends in the first region 01 in the stacking direction and is located between the gate line spacing structure 400 and the contact structure 700, and thus it can be understood that the dummy channel structure 600 passes through the plurality of connection regions 230-1 in the stacking direction.

A stacked structure (not shown) may be formed by alternately stacking the first dielectric layer 210 and the second dielectric layer 220, and after the virtual channel structure 600 is formed, a void (not shown) may be formed by removing a portion of the second dielectric layer 220 in the stacked structure, and filling the void with a conductive material, forming the gate layer 230, wherein the connection region 230-1 may be formed by removing a portion of the second dielectric layer 220 surrounding the virtual channel structure 600.

Thus, by adjusting the feature size of the dummy channel structure 600, for example, at least one of the size of the dummy channel structure 600 in the first direction (x-direction), the orthographic projected area of the dummy channel structure in the plane of the first direction, and the distance between the dummy channel structures 600, the size of the contact surface of the second dielectric layer 220 surrounding the dummy channel structure 600 with the etchant may be changed, so that when the portion of the second dielectric layer 220 surrounding the dummy channel structure 600 is removed at a certain etching rate, the portion of the second dielectric layer 220 removed in the first direction is not equal in amount during the same time, thereby making the size of the void for forming the connection region 230-1 different in the first direction, and making the size of the connection region 230-1 formed in the above-mentioned void different in the first direction.

For example, the region of the second dielectric layer 220 where the dummy channel structure 600 corresponding to the deeper first contact structure 700-1 is located is a first partition (not shown), the region of the second dielectric layer 220 where the dummy channel structure 600 corresponding to the shallower second contact structure 700-2 is located is a second partition (not shown), and the first partition and the second partition of each second dielectric layer 220 may be understood as portions opposite to the first partition and the second partition of the connection region 230-1 formed later by setting the size of the dummy channel structure 600 in the first partition in the first direction smaller than the size of the dummy channel structure 600 in the second partition, or by setting the pitch between adjacent dummy channel structures 600 in the first partition in the second direction larger than the pitch between adjacent dummy channel structures 600 in the second partition, or by combining the above embodiments.

The size of the contact surface of the portion of the second dielectric layer 220 surrounding the virtual channel structure 600 in the first partition is relatively larger than that of the second partition, and thus when the portion of the second dielectric layer 220 surrounding the virtual channel structure 600 is removed at a certain etching rate, the second dielectric layer 220 removed in the first direction in the first partition of the second dielectric layer 220 is relatively more in the same time. Further, in the connection region 230-1 formed by removing the above-mentioned portions, the size of the first partition in the first direction is larger than the size of the second partition in the first direction.

In other words, the connection region of the gate layer may be formed by removing the local region in the second dielectric layer, and the distribution of the local region in the first direction in each second dielectric layer of the stacked structure may be adjusted by adjusting the feature size of the virtual channel structure in the local region, so as to adjust the size of the space (or void) for forming the connection region of the gate layer in the first direction, thereby making the sizes of the connection regions of the gate layer in the first direction different.

Fig. 10 is a schematic view of a partition of a stacked structure 200 according to one embodiment of the application. Fig. 11 is a schematic view of a partition of a stacked structure 200 according to another embodiment of the present application.

Specifically, as shown in fig. 1, 10 and 11, the stacked structure 200 may define a first region 01 and a second region 02 in a plane perpendicular to the stacking direction, wherein the first region 01 includes the gate layer 230, the second region 02 includes the second dielectric layer 220, and the gate layer 230 and the second dielectric layer 220 may have the same stacking height. However, it will be appreciated by those skilled in the art that the size or shape of both the first region including the gate layer and the second region including the second dielectric layer may be configured according to a different three-dimensional memory architecture without departing from the teachings of the present application.

Referring to fig. 7, 10 and 11, the first region 01 of the stacked structure 200 is mainly used to form the channel structure 300, and may include a gate layer 230, a gate line spacing structure 400 and a dummy channel structure 600. The second region 02 of the stacked structure 200 is a stack of insulating dielectric materials, and is primarily used to form the contact structure 700. In addition, the three-dimensional memory 1000 may further include a transition channel structure 500. The transition channel structure 500 may serve as a support to prevent structural bending of the gate layer 230 and improve structural stability of the three-dimensional memory 1000. The transition channel structure 500 may be located in the first region 01 or the second region 02, which is not limited in the present application.

In addition, the stacked structure 200 may further include a gate line gap 410, the gate line gap 410 may form the gate line gap structure 400, and the gate line gap 410 may be used to form the gate layer 230.

Specifically, the first dielectric layer 210 and the second dielectric layer 220 may be alternately stacked first to form a stacked structure (not shown), and then the channel structure 300, the transition channel structure 500, and the dummy channel structure 600 may be formed in the stacked structure, after which the gate line space 410 may be formed, and the gate line space 410 may be used as a path for providing an etchant, and a portion of the second dielectric layer 220 in the stacked structure may be removed by using a process such as wet etching to form a void (not shown), and the void may be filled with a conductive material to form the gate layer 230.

Thus, as described above, the gate layer may be obtained by removing a portion of the second dielectric layer, by adjusting the feature size of the virtual channel structure located in the region between the gate line gap and the contact structure, the distribution of the local region (such as the oval-shaped circled portion of the dotted line in fig. 10 and 11) of the virtual channel structure located in the second dielectric layer of the stacked structure in the first direction may be changed, and by removing the above local region of the second dielectric layer, the connection region of the gate layer may be formed, so that the feature size of the virtual channel structure in the above region may be adjusted to adjust the size of the space (or void) used to form the connection region of the gate layer in the first direction, thereby making the size of the connection region corresponding to the plurality of contact structures in the gate layer different in the first direction, and ensuring that the gate layers located at different stack heights can all form good electrical communication with their corresponding contact structures.

Fig. 12 to 15 are schematic orthographic views of the dummy channel structure 600 and the gate line spacing structure 400, respectively, in a plane perpendicular to the stacking direction according to an embodiment of the present application.

As shown in fig. 12 to 13, in one embodiment of the present application, the orthographic projection of the virtual channel structure 600 in a plane perpendicular to the stacking direction is not limited to a circular profile, but may be, for example, an elliptical profile, a fan-shaped profile, or the like, or other two-dimensional shape having directionality. For example, as an option, the dimension of the orthographic projection of the virtual channel structure 600 in a plane perpendicular to the stacking direction is greater than or equal to the dimension in at least one direction.

The virtual channel structure provided by at least one embodiment of the present application not only can be used for adjusting the space of the connection region forming the gate layer, so that the sizes of the connection regions corresponding to the plurality of contact structures in the gate layer in the first direction are different; but also can play a supporting role, prevent the grid layer from structural bending and improve the structural stability of the three-dimensional memory. Thus, to provide the above effect, the orthographic projection of the virtual channel structure in a plane perpendicular to the stacking direction may have a larger area. However, increasing the orthographic projected area of the virtual channel structure may result in shortening the shortest distance between the virtual channel structure and the contact structure, and in the process of preparing the three-dimensional memory, the contact structure and the virtual channel structure are easy to form connection, so that a leakage phenomenon occurs, thereby damaging the electrical characteristics and structural robustness of the finally formed three-dimensional memory.

Therefore, the orthographic projection of the virtual channel structure in the plane perpendicular to the stacking direction is set to be a two-dimensional shape with directivity, such as an elliptic contour, a sector contour and the like, so that the projection area of the virtual channel structure can be increased, and meanwhile, the shortest distance between the virtual channel structure and the contact structure is ensured not to be too small, thereby preventing the occurrence of the electric leakage phenomenon and improving the electrical characteristics and the structural robustness of the three-dimensional memory.

In addition, as shown in fig. 14 to 15, alternatively, in the case where the orthographic projection of the dummy channel structure 600 is a two-dimensional shape having directionality, the dummy channel structure 600 may have various arrangements in a plane perpendicular to the stacking direction according to different architectures of the three-dimensional memory, wherein an angle α between the orthographic projection of the dummy channel structure 600 in the plane perpendicular to the stacking direction and the orthographic projection of the gate line clearance structure 400 in the plane perpendicular to the stacking direction may satisfy: alpha is less than 60 degrees.

In addition, as shown in fig. 7, 10 and 11, the three-dimensional memory 1000 further includes a channel structure 300 extending in the first region 01 of the stacked structure 200. The channel structure 300 may include a channel hole (not shown) filled with a semiconductor layer and a composite dielectric layer, for example, a functional layer (not shown) and a channel layer (not shown) sequentially formed on an inner wall of the channel hole. In addition, the channel structure 300 may further include a channel filling dielectric layer (not shown) that may be filled in the remaining space of the channel hole after the functional layer and the channel layer have been formed.

The functional layer may include a blocking layer (not shown), a charge trapping layer (not shown), and a tunneling layer (not shown) disposed in this order inside the channel hole. Alternatively, the channel hole may have a cylindrical or pillar shape extending in the stacked structure 200 in the stacking direction. The functional layer may also have a cylindrical or pillar shape extending in the stacked structure 200, similar to the channel hole.

The channel layer may be located on the surface of the tunneling layer and can be used to transport desired charges (electrons or holes). The channel layer may also have a cylindrical or pillar shape extending in the stacked structure 200. The channel layer may be made of a semiconductor material such as polysilicon or monocrystalline silicon, and may have conductive impurities. For example, the channel layer may be an N-type doped or P-type doped polysilicon layer.

In addition, the three-dimensional memory 1000 further includes a local conductive contact structure connecting the channel layers, such as a channel plug (not shown) formed above the channel layers in the stacking direction, and a semiconductor conductive layer (not shown) or an epitaxial layer (not shown) formed below the channel layers. The local conductive contact structure is typically a bit line contact or a source line contact of a three-dimensional memory for enabling electrical communication of the channel structure with the bit line or the source line.

In addition, the channel structure 300, the transition channel structure 500, and the dummy channel structure 600 may have partially identical internal structures. For example, the functional layer, the channel layer, and the channel fill dielectric layer of the channel structure 300 may be formed while filling the transition channel hole of the transition channel structure 500 and the dummy channel hole of the dummy channel structure 600 with the functional layer, the channel layer, and the channel fill dielectric layer as well.

Further, as an option, based on the transition channel structure 500 and the dummy channel structure 600 not having a memory function, an insulating dielectric material layer such as a silicon oxide layer may be generally filled in the transition channel hole of the transition channel structure 500 and the dummy channel hole of the dummy channel structure 600.

Fig. 3A is a schematic partial cross-sectional view of a three-dimensional memory 1000 according to one embodiment of the application. Fig. 3B is a schematic partial cross-sectional view of a three-dimensional memory 1000 according to another embodiment of the application. Fig. 3C is a schematic partial cross-sectional view of a three-dimensional memory 1000 according to yet another embodiment of the application.

As shown in fig. 3A to 3C, the three-dimensional memory 1000 provided in at least one embodiment of the present application further includes a substrate 100', and the stacked structure 200 may be located on the substrate 100'. However, those skilled in the art will appreciate that the substrate 100' may include different layer structures depending on the three-dimensional memory architecture without departing from the teachings of the present application, which is not limited in this regard. For example, the substrate 100' may include a partial structure connected to the channel layer 330, which is used to form a circuit loop for conducting the operation of the memory cell.

Alternatively, as shown in fig. 3A, in one embodiment of the present application, the base 100' includes a first substrate semiconductor layer 110. The channel layer 330 may pass through the stacked structure 200 in the stacking direction and extend to the first substrate semiconductor layer 110, wherein the first substrate semiconductor layer 110 is connected with at least a bottom surface portion of the channel layer 330.

For example, the channel layer 330 may pass through the stack structure 200 in the stacking direction and extend into the first substrate semiconductor layer 110, wherein the first substrate semiconductor layer 110 may be connected to a bottom surface portion of the channel layer 330 and to a portion of a side surface portion of the channel layer 330, the portion of the side surface portion being a portion of the side surface portion of the channel layer 330 connected to the bottom surface portion.

The first substrate semiconductor layer 110 may be a highly doped semiconductor layer. For example, the first substrate semiconductor layer 110 may be doped with any suitable, e.g., N-type dopant (e.g., phosphorus (P), arsenic (Ar), or antimony (Sb)) to contribute free electrons and increase the conductivity of the intrinsic semiconductor.

In addition, in one embodiment of the present application, in order to achieve a good and stable electrical connection between the channel layer 330 and the first substrate semiconductor layer 110, to improve the electrical performance of the three-dimensional memory, the exposed channel layer 330 may be highly doped prior to the step of forming the first substrate semiconductor layer 110.

Specifically, the channel layer 330 may include at least two regions (e.g., the third region 333 and the fourth region 334) having different doping concentrations along the stacking direction, wherein the third region 333 is adjacent to the fourth region 334, the third region 333 is closer to the first substrate semiconductor layer 110 than the fourth region 334, and the doping concentration of the conductive impurity of the third region 333 is greater than the doping concentration of the conductive impurity of the fourth region 334. The above arrangement can increase the doping concentration of the conductive impurities in the portion of the channel layer 330 closer to the first substrate semiconductor layer 110, achieve good and stable electrical connection between the channel layer 330 and the first substrate semiconductor layer 110, and improve the electrical performance of the three-dimensional memory 1000.

In addition, the first substrate semiconductor layer 110 further includes a common source extraction point 111, which may be disposed opposite to the channel structure 300, for example, which is not limited in the present application.

Alternatively, as shown in fig. 3B, in one embodiment of the present application, the base 100' includes a second substrate semiconductor layer 130. The channel layer 330 may pass through the stack structure 200 in a stacking direction and extend through the second substrate semiconductor layer 130, wherein the second substrate semiconductor layer 130 may be connected with a side portion of the channel layer 330.

The second substrate semiconductor layer 130 may be a highly doped semiconductor layer. For example, the second substrate semiconductor layer 130 may be doped with any suitable, e.g., N-type dopant (e.g., phosphorus (P), arsenic (Ar), or antimony (Sb)) to contribute free electrons and increase the conductivity of the intrinsic semiconductor.

Alternatively, as shown in fig. 3C, in one embodiment of the present application, the three-dimensional memory may also include a substrate 100', and the channel structure 300 may include a channel hole 310, a functional layer 320, an epitaxial layer 120, and a channel layer 330. The channel hole 310 may penetrate at least the stacked structure 200 in the stacking direction. Epitaxial layer 120 is located at the bottom of channel hole 310. The functional layer 320 is located at a sidewall of the channel hole 310. Channel layer 330 is located on the surface of functional layer 320 and the surface of epitaxial layer 120 remote from substrate 100'.

Epitaxial layer 120 may be at least one of epitaxial silicon, silicon germanium, III-V compound materials, II-VI compound materials, organic semiconductor materials, and other suitable semiconductor materials.

According to the three-dimensional memory provided by at least one embodiment of the application, no step and word line contact on the step are required to be formed in the three-dimensional memory, and the contact structure arranged in the second region of the three-dimensional memory can realize the electric communication between the gate layers at different stacking heights and an external circuit, so that the preparation process is simplified, the generation cost is reduced, the area required by a device is reduced, and the storage density per unit area, the reliability and the overall performance of the three-dimensional memory are improved.

In addition, the laminated structure in the three-dimensional memory provided by the embodiment of the application comprises the first area and the second area, the second area is an insulating dielectric material laminated layer formed by mutually stacking the first dielectric layer and the second dielectric layer, and the contact structure is arranged in the second area, so that the contact structure is electrically communicated with the corresponding grid electrode layer, and short circuit between different grid electrode layers can be prevented.

In addition, according to at least one embodiment of the present application, by adjusting the size of the connection region in the gate layer in the first direction, it is ensured that the gate layers located at different stack heights can form good electrical communication with the corresponding contact structures, and the reliability of the three-dimensional memory is improved. In addition, in at least one embodiment of the present application, a gap is formed by removing a portion of the second dielectric layer in the stacked structure, and the gap is filled with a conductive material to form a gate layer, where the connection region may be formed by removing a region of the second dielectric layer where the virtual channel structure is located. Thus, by adjusting the feature size of the dummy channel structure, for example, at least one of the size of the dummy channel structure in the first direction, the orthographic projected area of the dummy channel structure in the plane in which the first direction is located, and the pitch between the dummy channel structures, the distribution of the region in which the dummy channel structure is located in each of the second dielectric layers in the stacked structure can be changed, and thus the size of the connection region formed by removing the region in the first direction can be changed.

In other words, the connection region of the gate layer may be formed by removing a portion of the second dielectric layer in the region where the virtual channel is located, so that the feature size of the virtual channel structure in the region may be adjusted to adjust the size of the space (or void) for forming the connection region of the gate layer in the first direction, so that the size of the connection region of the gate layer in the first direction is different.

Fig. 16 is a flow chart of a method 2000 of fabricating a three-dimensional memory according to one embodiment of the present application. Fig. 17A to 17M are process diagrams of a method 2000 for manufacturing a three-dimensional memory according to an embodiment of the present application, respectively.

As shown in fig. 16, the method 2000 for preparing the three-dimensional memory may include:

s1, alternately stacking the first dielectric layers and the second dielectric layers to form a stacked structure.

S2, removing part of the second dielectric layer to form a gap, and filling the gap with a conductive material to form a gate layer.

S3, forming a plurality of contact structures which extend along the stacking direction and are respectively connected with a plurality of gate layers positioned at different stacking heights in the first direction, wherein the area where the rest second dielectric layers are positioned is set as a second area, the part, positioned outside the second area, of the gate layers in the first direction is a connecting area, and the connecting area in each gate layer has a plurality of different sizes in the first direction.

The specific process of each step of the above-described preparation method 2000 in one embodiment of the present application will be described in detail below with reference to fig. 17A to 17M.

Step S1

Fig. 17A is a schematic cross-sectional view of a structure formed after forming a stacked structure 200' according to a fabrication method of one embodiment of the present application. Fig. 17B is a schematic cross-sectional view of the structure formed after forming channel structure 300, transition channel structure 500, and dummy channel structure 600 according to a method of fabrication in accordance with an embodiment of the present application.

As shown in fig. 17A to 17B, the step S1 of alternately stacking the first dielectric layer and the second dielectric layer to form a stacked structure may include, for example: providing an initial substrate 100; and forming a stacked structure 200' on the initial substrate 100; the channel structure 300, the transition channel structure 500, and the dummy channel structure 600 are formed in the stacked structure 200'.

Specifically, in one embodiment of the present application, the starting substrate 100 may be made of any suitable semiconductor material, such as a group iii-v compound, e.g., single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide. Further, the initial substrate 100 may be selected from single crystal silicon.

In one embodiment of the application, the initial substrate 100 may be, for example, a composite substrate for supporting device structures thereon. Multiple layers of different materials may be sequentially disposed by a thin film deposition process such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof to form the initial substrate 100.

The initial substrate 100 may include a substrate sacrificial layer for subsequent formation of a semiconductor connection layer (e.g., a second substrate semiconductor layer is formed at a subsequent step, etc.). The substrate sacrificial layer may comprise a single layer, multiple layers, or a suitable composite layer. For example, the substrate sacrificial layer may include any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Alternatively, the substrate sacrificial layer may be a high dielectric constant dielectric layer, and alternatively, the substrate sacrificial layer may include a dielectric layer, a sacrificial layer, and a dielectric layer disposed in sequence, where the dielectric layer may be a silicon nitride layer and the sacrificial layer may be a silicon oxide layer. Alternatively, the substrate sacrificial layer may comprise any one or more of a dielectric material, a semiconductor material, and a conductive material. For example, the sacrificial layer may be monocrystalline silicon or polycrystalline silicon, and in particular, in one embodiment of the present application, an exemplary material forming the sacrificial layer may be polycrystalline silicon.

A partial region of the initial substrate 100 may also form a well region formed by doping with N-type or P-type dopants via an ion implantation or diffusion process. The dopant may include any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb). In some embodiments of the present application, the well regions may be selected from the same dopant preparation, or may be selected from different dopant preparation, further, the doping concentration of the well regions may be the same or different, which is not limited in the present application.

After forming the initial substrate 100, the stacked structure 200' may be formed on the initial substrate 100 by one or more thin film deposition processes, which may include, but are not limited to, chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof, as the present application is not limited in this regard.

The stacked structure 200' may include a plurality of pairs of first dielectric layers 210 and second dielectric layers 220 alternately stacked with each other. For example, the stacked structure 200' may include 64 pairs, 128 pairs, or more than 128 pairs of first dielectric layers 210 and second dielectric layers 220.

In some embodiments, the first dielectric layer 210 and the second dielectric layer 220 may include a first dielectric material and a second dielectric material different from the first dielectric material, respectively. Exemplary materials for forming the first dielectric layer 210 and the second dielectric layer 220 may include silicon oxide and silicon nitride, respectively. The silicon oxide layer may be used as an isolation stack layer and the silicon nitride layer may be used as a sacrificial stack layer. Portions of the sacrificial stack layer may then be etched away and replaced with a conductor layer comprising a conductive material to form a gate layer of the three-dimensional memory.

In addition, the stacked structure 200' may further include a cover layer 240, which is located at the highest stacking position of the stacked structure 200. Capping layer 240 includes, but is not limited to, a layer of insulating dielectric material such as a silicon oxide layer.

The method of making the individual stacked structures is described above. In fact, as the demand for three-dimensional memory storage increases, the memory stack increases. In order to break through the limitation of the conventional process limit, a dual-stack technology or a multi-stack technology may be used to form a stack structure by sequentially stacking a plurality of sub-stack structures in the thickness direction of the stack structure, wherein each sub-stack structure may include a plurality of first dielectric layers and second dielectric layers alternately stacked. The number of layers per sub-stack may be the same or different. Since the matters and structures related to the preparation process of the single stacked structure described above may be fully or partially applied to the stacked structure formed by including a plurality of sub-stacked structures described herein, the matters related or similar thereto will not be described in detail. However, it will be appreciated by those skilled in the art that the subsequent fabrication process may be performed on the basis of a multi-stack structure or a single stack structure.

Referring to fig. 17B, after the stack structure 200 'is formed, a channel structure 300, a transition channel structure 500, and a dummy channel structure 600 may be formed in the stack structure 200'.

Forming the plurality of channel structures 300 extending in the stacking direction in the stack structure 200' may include: forming a channel hole 310; a functional layer 320 and a channel layer 330 are sequentially formed on the inner wall of the channel hole 310; and forming a channel plug (not shown) and a channel filling dielectric layer (not shown).

The channel structure 300 may include a channel hole 310 filled with a semiconductor layer and a composite dielectric layer. The functional layer 320 and the channel layer 330 may be formed on the inner wall of the channel hole 310 by a thin film deposition process such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof.

Specifically, the etching may be performed by, for example, a dry etching process or a combination of dry and wet etching processes; other fabrication processes may also be performed to form the channel holes 310, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, for example. The channel hole 310 may have a cylindrical or pillar shape extending in the stacking direction in the stacking structure 200'. Alternatively, the channel hole 310 may extend into the initial substrate 100.

The functional layer 320 may include a blocking layer (not shown) formed on an inner wall of the channel hole 310 to block charges from flowing out, a charge trapping layer (not shown) formed on a surface of the blocking layer to store charges during operation of the three-dimensional memory, and a tunneling layer (not shown) formed on a surface of the charge trapping layer.

In some embodiments, the functional layer 320 may include an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the functional layer 320 may have a structure other than an ONO configuration. The channel layer 330 may be formed on a surface of the tunneling layer and can be used to transport desired charges (electrons or holes).

However, it will be appreciated by those skilled in the art that the formation of functional layers on the sidewalls and bottom of the channel holes, or on the sidewalls of the channel holes, may be selected depending on the three-dimensional memory architecture without departing from the teachings of the present application, which is not limited in this regard.

For example, alternatively, according to one embodiment of the present application, the functional layer 320 may be formed on the sidewalls and bottom surface of the channel hole 310, and the channel layer 330 may be formed on the surface of the tunneling layer of the functional layer 320 through a thin film deposition process such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof.

Alternatively, according to an embodiment of the present application, an epitaxial layer (not shown) may be formed on the bottom surface of the channel hole 310, and a functional layer 320 may be formed on the sidewall of the channel hole 310 and the surface of the epitaxial layer, and after removing a portion of the functional layer 320 on the surface of the epitaxial layer, a channel layer 330 may be formed on the surface of the tunneling layer of the remaining functional layer 320 and the surface of the epitaxial layer by a thin film deposition process such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof.

In some embodiments, the channel layer 330 may be made of a semiconductor material, such as polysilicon or monocrystalline silicon, and may have conductive impurities. For example, the channel layer may be an N-doped or P-doped polysilicon layer. Similar to the channel hole 310, the channel layer 330 may also have a cylindrical or pillar shape extending in the stacking direction in the stack structure 200'. Alternatively, the channel layer 330 may also extend into the initial substrate 100.

In addition, the channel structure 300 further includes a channel plug formed at an end of the channel hole 310 remote from the starting substrate 100 (which may be understood as a top end of the channel structure 300). Specifically, the channel holes 310 may be filled with a channel filling dielectric layer after the functional layer 320 and the channel layer 330 are formed. The trench fill dielectric layer may comprise an oxide dielectric layer, such as silicon oxide or the like. Further, during the filling process, a plurality of insulating gaps may be formed in the trench filling dielectric layer by controlling the trench filling process to mitigate structural stress. A channel plug is then formed in the portion of the channel fill dielectric layer that is at the top of the channel hole 310. The material of the channel plug may be selected from the same material as that of the channel layer 330, such as N-type doped polysilicon or P-type doped polysilicon. The channel plug is connected to the channel layer 330.

After forming the channel structure 300, the transition channel structure 500 and the dummy channel structure 600 having a distance from the channel structure 300 in the first direction (x-direction) may be formed in the same manner as described above, and thus the description thereof will not be repeated.

Further, as an option, based on the transition channel structure 500 and the dummy channel structure 600 not having a memory function, only an insulating dielectric material layer such as a silicon oxide layer may be filled, typically in a transition channel hole (not shown) of the transition channel structure 500 and a dummy channel hole (not shown) of the dummy channel structure 600, by a thin film deposition process such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof. Likewise, a plurality of insulating gaps may also be formed in the insulating dielectric material layer by controlling the trench filling process to mitigate structural stress of the transition channel structure 500 and the dummy channel structure 600.

Referring to fig. 7, after forming the channel structure 300, the transition channel structure 500, and the dummy channel structure 600, the plurality of channel structures 300 may constitute a channel structure array, the plurality of transition channel structures 500 may constitute a transition channel structure array, and the plurality of dummy channel structures 600 may constitute a dummy channel structure array, each of which is arranged in a plurality of rows and columns in the first direction and the second direction (y direction). In addition, the channel structure array, the transition channel structure array, and the dummy channel structure array are spaced apart in the first direction.

In addition, as described above, the feature size of the dummy channel structure (or the dummy channel hole) can be adjusted, for example, at least one of the size of the dummy channel structure (or the dummy channel hole) in the first direction, the orthographic projection area of the dummy channel structure in the plane where the first direction is located, and the distance between the dummy channel structure (or the dummy channel hole) and each other, so as to change the distribution of the region where the dummy channel structure is located in the second dielectric layer of the stacked structure, and by removing the above region in the second dielectric layer, the feature size of the dummy channel structure in the region can be adjusted, so that when the second dielectric layer surrounding the dummy channel structure is removed at a certain etching rate, the portion of the second dielectric layer removed in the first direction is not equal in the same time, and then the size of the space (or the void) for forming the connection region of the gate layer in the first direction is adjusted, so that the size of the connection region corresponding to the plurality of contact structures in the gate layer in the first direction is different, and good electrical communication between the gate layer located at different stack heights and the corresponding contact structures can be ensured.

Specifically, in one embodiment of the present application, the subsequently formed contact structure may include a contact hole extending in the stacking direction in the stacking structure, and a position of the contact hole in the contact structure connected to each gate layer may be predetermined, for example, a position of orthographic projection of the deeper contact hole and the shallower contact hole in a plane perpendicular to the stacking direction. The front projections and the regions between the front projections are formed as projection regions, and the connection region of each gate layer opposite to the projection regions may be divided into a plurality of regions, where different regions correspond to different contact structures, such as a first region corresponding to a deeper contact hole and a second region corresponding to a shallower contact hole. The size of the first partition in the first direction may be set to be larger than the size of the second partition in the first direction. By adjusting the size of the connection region corresponding to the plurality of contact structures in the gate layer in the first direction, good electrical communication between the gate layers located at different stacking heights and the corresponding contact structures can be ensured.

Further, in one embodiment of the present application, by adjusting a feature size of the virtual channel structure, for example, at least one of a size of the virtual channel structure in the first direction, an orthographic projected area of the virtual channel structure in a plane where the first direction is located, and a distance between the virtual channel structures, a distribution of a local area where the virtual channel structure is located in the second dielectric layer in the first direction may be changed, so as to change a size of a contact surface between the local area and the etchant in the second dielectric layer, and therefore, by removing the second dielectric layer in the local area, a connection area of the gate layer may be formed, and adjusting a feature size of the virtual channel structure in the local area may adjust a size of a space (or a void) for forming the connection area of the gate layer in the first direction, so that a size of the connection area corresponding to the plurality of contact structures in the gate layer in the first direction is different.

For example, as shown in fig. 8, the dimension of the dummy channel structure corresponding to the deeper contact hole in the first direction may alternatively be set smaller than the dimension of the dummy channel structure corresponding to the shallower contact hole in the first direction. Further, after the position of the contact hole in the contact structure in the plane perpendicular to the stacking direction is determined in advance, the area of the orthographic projection of the dummy channel structure in the plane perpendicular to the stacking direction corresponding to the deeper contact hole may be set smaller than the area of the orthographic projection of the dummy channel structure in the plane perpendicular to the stacking direction corresponding to the shallower contact hole. Further, in one embodiment of the present application, the dimension D1 of the virtual channel structure 600 in the first direction satisfies: d1 is less than or equal to 120nm and less than or equal to 150nm.

Alternatively, as shown in fig. 9, after the positions of the contact holes in the contact structures in the plane perpendicular to the stacking direction are predetermined, the pitch between adjacent dummy channel structures corresponding to the deeper contact holes in the second direction may be set to be larger than the pitch between adjacent dummy channel structures corresponding to the shallower contact holes in the second direction. Further, in one embodiment of the present application, the pitch L1 between adjacent dummy channel structures 600 in the second direction corresponding to the contact structures (e.g., the first contact structure 700-1, the second contact structure 700-2) satisfies: l1 is more than or equal to 30nm.

Alternatively, in combination with the above selection scheme, the dimension of the dummy channel structures in the first direction and the spacing between the dummy channel structures are adjusted.

Furthermore, in one embodiment of the present application, the orthographic projection of the virtual channel structure in a plane perpendicular to the stacking direction may be set to a circular contour; or may be provided as an oval profile, a fan profile, etc., or may be provided as other two-dimensional shapes having directionality. For example, as an option, the dimension of the orthographic projection of the virtual channel structure in a plane perpendicular to the stacking direction in at least one direction is set to be greater than or equal to the dimension in the other direction.

By setting the orthographic projection of the virtual channel structure in a plane perpendicular to the stacking direction to a two-dimensional shape having directionality, the virtual channel structure can be made to have a larger projected area.

Thus, the virtual channel structure provided in at least one embodiment of the present application may be used to adjust the space of the connection region forming the gate layer so that the connection regions corresponding to the plurality of contact structures in the gate layer have different sizes in the first direction; but also can play a supporting role, prevent the grid layer from structural bending and improve the structural stability of the three-dimensional memory.

In addition, as another alternative, in the case that the orthographic projection of the virtual channel structure is a two-dimensional shape with directionality, the virtual channel structure can be arranged in a plane perpendicular to the stacking direction according to different architectures of the three-dimensional memory, wherein an included angle α between the orthographic projection of the virtual channel structure in the plane perpendicular to the stacking direction and the orthographic projection of the gate line spacing structure formed subsequently in the plane perpendicular to the stacking direction can be satisfied: alpha is less than 60 degrees.

Step S2

Fig. 17C is a schematic top view of a structure formed after forming the gate line gap 410 according to a method of manufacturing according to an embodiment of the present application. Fig. 17D is a schematic cross-sectional view of a structure formed after forming the gate line gap 410 according to a method of manufacturing according to an embodiment of the present application. Fig. 17E is a schematic cross-sectional view of a structure formed after forming a gate line space sacrificial layer 420 in a gate line space 410 according to a manufacturing method of an embodiment of the present application. Fig. 17F is a schematic top view of a structure formed after removing a portion of the gate line space sacrificial layer 420 according to a fabrication method of one embodiment of the present application. Fig. 17G is a schematic cross-sectional view of a structure formed after removing a portion of the gate line space sacrificial layer 420 and a portion of the second dielectric layer 220 according to a fabrication method of an embodiment of the present application. Fig. 17H is a schematic top view of a structure formed after removal of the remaining gate line space sacrificial layer 420' according to a fabrication method of one embodiment of the present application. Fig. 17I is a schematic cross-sectional view of a structure formed after continuing to remove a portion of the second dielectric layer 220 according to a method of fabrication in accordance with an embodiment of the present application. Fig. 17J is a schematic cross-sectional view of a structure formed after forming gate layer 230 according to a fabrication method of one embodiment of the present application. Fig. 17K is a schematic cross-sectional view of a structure formed after forming a gate line spacing structure 400 according to a method of manufacturing according to an embodiment of the present application.

As shown in fig. 17C to 17K, removing a portion of the second dielectric layer to form a void and filling the void with a conductive material to form a gate layer in step S2 may include, for example: forming a gate line space 410 passing through the stacked structure 200' in the stacking direction and extending in the second direction, wherein the gate line space 410 defines a first gap 410-1 and a second gap 410-2 in the second direction, the first gap 410-1 corresponding to the channel structure 300 and the transition channel structure 500; filling the gate line space 410 with a filling sacrificial layer 420; removing the portion of the filling sacrificial layer 420 located in the first gap 410-1; and removing a portion of the second dielectric layer 220 through the first gap 410-1 to form a first void 11; removing the remaining filled sacrificial layer 420' and removing a portion of the second dielectric layer 220 surrounding the virtual channel structure 600 via the second gap 410-2 to form a second void 12, the first void 11 and the second void 12 constituting a void (not shown); filling the voids with a conductive material to form gate layer 230; and forming a gate line spacing structure 400.

Specifically, as shown in fig. 17C and 17D, in one embodiment of the present application, the gate line slit 410 may be formed by, for example, a dry etching process or a combination of dry and wet etching processes. The gate line slit 410 passes through the stacked structure 200' in the stacking direction and extends in the second direction. Alternatively, the gate line slit 410 may pass through the stacked structure 200' in the stacking direction and extend into the initial substrate 100.

The gate line slit 410 may be used as a path for providing an etchant, and a portion of the second dielectric layer 220 in the stacked structure 200' may be removed by a process such as wet etching, thereby forming a gate layer.

Since the subsequently formed contact structure connected to the gate layer generally includes a contact hole having a predetermined depth in the stacking direction formed through processes such as photolithography and etching, so as to form a connection with the gate layer at different stack heights. In addition, with the improvement of the integration level of the three-dimensional memory and the increase of the stacking layer number, the depth of the contact hole connected with the gate layer at the lower stacking height is increased, and the gate layer is easily broken down in the process of forming the contact hole, so that short circuits between different gate layers are caused.

The laminated structure in the three-dimensional memory provided by the embodiment of the application comprises the first area and the second area, wherein the second area is an insulating dielectric material laminated layer formed by mutually stacking the first dielectric layer and the second dielectric layer, and the contact structure is arranged in the insulating dielectric material laminated layer, so that the contact structure is electrically communicated with the corresponding grid electrode layer, and short circuit between different grid electrode layers can be prevented. Therefore, in order to achieve the above-mentioned effects, the method for manufacturing the three-dimensional memory according to the embodiment of the present application only removes a portion of the second dielectric layer, and controls the shape and size of the finally formed gate layer by removing a portion of the second dielectric layer in a divided manner.

Specifically, as shown in fig. 17C, the gate line gap 410 may define a first gap 410-1 and a second gap 410-2 in the second direction, the first gap 410-1 corresponding to the channel structure 300 and the transition channel structure 500.

As shown in fig. 17D and 17E, the gate line space 410 may be filled with the filling sacrificial layer 420 by a thin film deposition process such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof. Since the filling sacrificial layer 420 needs to be sequentially removed in a subsequent step, for example, a carbon layer, a polysilicon layer, etc. may be used as the filling sacrificial layer 420, damage to the stacked structure 200' may be prevented in the subsequent removed process step, and the cost of manufacturing the three-dimensional memory may be reduced.

As shown in fig. 17E and 17F, the portion of the filling sacrificial layer 420 located in the first gap 410-1 may be removed by, for example, a dry etching process or a combination of dry and wet etching processes, exposing the first gap 410-1, and leaving the remaining filling sacrificial layer 420' located only in the second gap 410-2. By filling the remaining filling sacrificial layer 420' in the second gap 410-2, a partial removal of a portion of the second dielectric layer may be achieved.

After closing the second gap 410-2, the first gap 410-1 may be used as a path for providing an etchant, and a portion of the second dielectric layer 220 in the stacked structure 200' may be removed using a process such as wet etching, for example, to form the first gap 11, as shown in fig. 17F and 17G. Since the first gap 410-1 corresponds to the channel structure 300 and the transition channel structure 500, the first void 11 is formed between the plurality of channel structures 300 and between the plurality of transition channel structures 500.

As shown in fig. 17H and 17I, the remaining filling sacrificial layer 420' may be removed by, for example, a dry etching process or a combination of dry and wet etching processes, exposing the second gap 410-2. The second gap 410-2 may be used as a path for providing an etchant and a chemical precursor, and a process such as wet etching may be used to remove portions of the second dielectric layer 220 surrounding the virtual channel structure 600 to form the second void 12. Since the second void 12 surrounds the dummy channel structure 600, it may be used later to form a connection region corresponding to the plurality of contact structures in the gate layer. Furthermore, by setting the feature size, shape and distribution of the virtual channel structure 600 before, the distribution of the second dielectric layer in the region where the virtual channel structure is located is changed, and the second dielectric layer in the region is removed to form the connection region of the gate layer, so that the connection regions corresponding to the multiple contact structures in the gate layer have different sizes in the first direction, and good electrical communication between the gate layers at different stacking heights and the corresponding contact structures is ensured.

As shown in fig. 17G, 17I, and 17J, the first void 11 and the second void 12 constitute voids in which the gate layer 230 may be formed by a thin film deposition process such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof in some embodiments of the application. The gate layer 230 may include a conductive material, such as any one or combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide.

In addition, the method 1000 of fabricating a three-dimensional memory according to an embodiment of the present application further includes forming the dielectric layer 13 on the inner walls of the void and on the inner sidewalls of the gate line slit 410 using a thin film deposition process such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof, as an alternative dielectric layer 13 may be a high dielectric constant dielectric layer, before forming the gate layer 230. Further, a thin film deposition process such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof may also be employed to form the adhesion layer 14 between the first dielectric layer 210 and the gate layer 230 or between the dielectric layer and the gate layer 230, for example, the adhesion layer 14 may be, for example, a titanium nitride TiN layer.

In addition, as shown in fig. 17K, in some embodiments of the present application, after forming the gate layer 230, the gate line slit structure 400 may also be formed by filling the gate line slit 410. Specifically, a thin film deposition process such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof may be employed to fill the dielectric fill layer 420 in the gate line slits 410 to form the gate line slit structure 400. Dielectric fill layer 420 may be formed of dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride, or may be formed of semiconductor materials such as polysilicon, as the application is not limited in this regard.

Further, after forming the gate line slit structure 400 and the gate layer 230 in the stacked structure 200 '(as shown in fig. 17J), the stacked structure 200' is formed as the stacked structure 200.

Step S3

Fig. 17L is a schematic cross-sectional view of a structure formed after forming the shallower contact hole 710-1 according to a fabrication method according to an embodiment of the present application. Fig. 17M is a schematic cross-sectional view of a structure formed after forming the deeper contact hole 710-2 according to a fabrication method of an embodiment of the present application.

As shown in fig. 17L, 17M, and 1 to 4, step S3 forms a plurality of contact structures extending along the stacking direction and respectively connected to a plurality of gate layers located at different stacking heights in the first direction, wherein the area where the remaining second dielectric layer is located is set as a second area, the portion of the gate layer located outside the second area in the first direction is a connection area, and the connection area in each gate layer has a plurality of different dimensions in the first direction may include: forming a contact hole 710; forming a barrier layer 720 on sidewalls of the contact hole 710; removing a portion of the second dielectric layer 220 in contact with the bottom of the contact hole 710 through the contact hole 710 to form a first opening 730, and exposing the gate layer 230 having the same stack height as the removed portion of the second dielectric layer 220; and filling at least the surface of the barrier layer 720 and the first opening 730 with a conductive material to form a conductive contact layer 740, thereby forming the contact structure 700.

Specifically, as shown in fig. 4, 17L and 17M, a plurality of contact holes 710, such as shallower contact holes 710-1 and deeper contact holes 710-2, which extend in the stacking direction and have different depths, may be formed in the stacked structure 200 by, for example, a dry etching process or a combination of dry and wet etching processes. Each contact structure 700 (shown in fig. 1) is connected to a corresponding gate layer 230, and the stacked structure 200 further includes a second dielectric layer 220 having the same stack height as each gate layer 230, so that the contact holes 710 may alternatively extend in the stacking direction to the second dielectric layer 220 having the same stack height. In other words, the bottom of the contact hole 710 is in contact with the second dielectric layer 220 of the same stack height.

After forming the contact hole 710, an initial barrier layer (not shown) may be formed on the surface of the stacked structure 200 remote from the initial substrate 100, the sidewalls of the contact hole, and the surface of the second dielectric layer 220 of the same stack height as described above, using a thin film deposition process such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof. The initial barrier layer may be made of a dielectric material such as silicon oxide, silicon nitride, and silicon oxynitride, or may be made of a high-k dielectric material such as aluminum oxide, for example, without limitation to the present application.

After forming the initial barrier layer, a portion of the initial barrier layer on the surface of the second dielectric layer 220 at the same stack height may be removed to form the barrier layer 720. A portion of the second dielectric layer 220 in contact with the bottom of the contact hole 710 is removed through the contact hole 710 by, for example, a dry etching process or a combination of dry and wet etching processes under the protection of the barrier layer 720, thereby forming a first opening 730, the first opening 730 exposing the gate layer 230 having the same stack height as the removed portion of the second dielectric layer 220.

In addition, when the outer surface of the gate layer 230 is coated with the adhesive layer 14 and the dielectric layer 13 from inside to outside, after the first opening 730 is formed, the dielectric layer 13 and the adhesive layer 14 coated on the outer surface of the gate layer 230 to be exposed may be removed through the first opening 730, thereby exposing the gate layer 230, so that the conductive contact layer 740 to be filled later can be connected to the gate layer 230.

As shown in fig. 4, after forming the first opening 730, a thin film deposition process, such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof, may be used to fill at least the surface of the barrier layer 720 and the first opening 730 with an electrically conductive material to form an electrically conductive contact layer 740, thereby forming the contact structure 700.

Further, as shown in fig. 4, in one embodiment of the present application, the conductive contact layer 740 may not be completely filled with the contact hole 710 formed with the barrier layer 720, for example, the first portion 701 may include the barrier layer 720, the conductive contact layer 740, and the dielectric filling layer 750 sequentially formed at the sidewall of the contact hole 710. Dielectric fill layer 750 may be, for example, a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride. By forming the dielectric fill layer in the first portion of the contact structure, the use of conductive materials may be reduced, achieving the effect of reducing the cost of manufacturing the three-dimensional memory and reducing the stress deformation of the stacked structure.

As shown in fig. 4, the contact structure 700 may include two parts connected to each other, a first part 701 and a second part 702. The first portion 701 may include a contact hole 710, a barrier layer 720, and a conductive material located in the contact hole 710, and the contact hole 710 may generally extend a predetermined depth in a stacking direction, wherein the predetermined depth may be determined according to a stacking height of the corresponding gate layer 230. The second portion 702 includes a first opening 730 and a conductive material filled in the first opening 730, and the first opening 730 is located in a plane perpendicular to the stacking direction and connected with the corresponding gate layer 230 and the contact hole 710. The first portion 701 and the second portion 702 include a conductive contact layer 740 formed of a conductive material, and thus electrical communication between the gate layer 230 and an external circuit may be achieved through the contact structure 700.

Limited by the prior art, the contact hole extends along the stacking direction, and the aperture at the bottom of the contact hole tends to be smaller with the depth of the hole, and the deeper contact hole generally has smaller aperture. A contact hole having a relatively deep hole depth has a smaller bottom aperture; the contact hole having a relatively shallow hole depth has a larger bottom aperture. Thus, after the first portions of the plurality of contact structures having different hole depths are projected into a plane perpendicular to the stacking direction, as the contact holes of the contact structures become deeper, the distance between the contact structures and their corresponding gate layers also becomes larger.

When the sizes of the connection regions corresponding to the plurality of contact structures in the gate layer in the first direction are consistent, in order to ensure that the contact structure with the deeper contact hole can be connected with the corresponding gate layer, the size of the first opening in the first direction needs to be determined according to the distance between the deepest contact hole and the corresponding gate layer, which often causes damage to the gate layer corresponding to the shallower contact hole due to over etching and other conditions, and finally causes the reliability and overall performance of the formed three-dimensional memory to be reduced.

Therefore, in at least one embodiment of the present application, by adjusting the dimensions of the connection regions corresponding to the plurality of contact structures in the gate layer in the first direction, it is possible to ensure that the gate layers located at different stack heights can all form good electrical communication with their corresponding contact structures, and prevent the occurrence of shorting or the like between different gate layers, thereby improving the reliability and overall performance of the three-dimensional memory.

In addition, referring again to fig. 2A to 2B, fig. 3A to 3C, and fig. 17A, the method 2000 for fabricating a three-dimensional memory according to the present application further includes forming a partial structure connected to the channel layer, where the partial structure is used to form a circuit loop for conducting the operation of the memory cell.

Specifically, in combination with fig. 2A to 2B, 3A, and 17A, in one embodiment of the present application, forming a partial structure connected to a channel layer includes: removing the initial substrate 100 and exposing a portion of the functional layer 320 extending into the initial substrate 100; removing the exposed functional layer 320 to expose a portion of the channel layer 330 corresponding to the removed functional layer 320; the first substrate semiconductor layer 110 is formed, and the first substrate semiconductor layer 110 covers the exposed portion in the channel layer 330.

Further, after exposing a portion of the channel layer 330 corresponding to the removed functional layer 320, the exposed channel layer 330 may be doped, for example, N-type by a process such as ion implantation. The N-type doping may include any suitable dopant, such as N-type dopant (e.g., phosphorus (P), arsenic (Ar), or antimony (Sb)), to contribute free electrons and increase the conductivity of the intrinsic semiconductor. As shown in fig. 3A, after the exposed channel layer 330 is again highly doped, the channel layer 330 may include a third region 333 formed by a secondary doping process. The third region 333 is closer to the subsequently formed first substrate semiconductor layer 110 than other regions of the channel layer 330 adjacent thereto (e.g., the fourth region 334), and the doping concentration of the conductive impurity of the third region 333 is greater than that of the fourth region 334. The doping concentration of the conductive impurities in the part of the channel layer, which is closer to the first substrate semiconductor layer, is improved, so that good and stable electrical connection between the channel layer and the first substrate semiconductor layer can be realized, and the electrical performance of the three-dimensional memory is improved.

Alternatively, in combination with fig. 2A to 2B, 3B, and 17A, in one embodiment of the present application, forming a partial structure connected to a channel layer includes: removing a substrate sacrificial layer (not shown) in the initial substrate 100 to form a substrate void (not shown), and exposing a side portion of the functional layer 320 via the substrate void; removing a side portion of the exposed functional layer 320 to expose a portion of the channel layer 330 corresponding to the removed functional layer 320; and forming a second substrate semiconductor layer 130 in the initial substrate 100 extending through the exposed portion of the channel layer 330.

As yet another option, in conjunction with fig. 2A to 2B, 3C, and 17A, in one embodiment of the present application, forming a partial structure connected to a channel layer includes: forming an epitaxial layer 120 at the bottom of the channel hole 310; forming a functional layer 320 on an inner wall of the channel hole 310; and forming a channel layer 330 connected to the epitaxial layer 120 on the surface of the functional layer 320 and the surface of the epitaxial layer 120 remote from the initial substrate 100.

Fig. 18 is a schematic diagram of a memory system 30000 according to an embodiment of the application.

As shown in fig. 18, at least one embodiment of yet another aspect of the present application further provides a storage system 30000. The memory system 30000 may include a memory 20000 and a controller 32000. The memory 20000 may be the same as the memory described in any of the embodiments above, and will not be repeated in the present application. The memory 20000 may be a two-dimensional memory or a three-dimensional memory, and is described below as an example of the three-dimensional memory.

Alternatively, the three-dimensional memory may include at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

The memory system 30000 may include a three-dimensional memory 20000 and a controller 32000. The three-dimensional memory 20000 may be the same as the three-dimensional memory described in any of the embodiments above, and will not be repeated herein. The controller 32000 may control the three-dimensional memory 20000 through the channel CH, and the three-dimensional memory 20000 may perform operations based on the control of the controller 32000 in response to a request from the host 31000. The three-dimensional memory 20000 may receive a command CMD and an address ADDR from the controller 32000 through the channel CH and access an area selected from the memory cell array in response to the address. In other words, the three-dimensional memory 20000 may perform an internal operation corresponding to a command on an area selected by an address.

In some embodiments, the three-dimensional storage system may be implemented as a multimedia card such as universal flash memory storage (UFS) devices, solid State Drives (SSDs), MMC, eMMC, RS-MMC and micro MMC forms, secure digital cards in SD, mini SD and micro SD forms, personal Computer Memory Card International Association (PCMCIA) card type storage devices, peripheral Component Interconnect (PCI) type storage devices, PCI-express (PCI-E) type storage devices, compact Flash (CF) cards, smart media cards or memory sticks, and the like. The storage system provided by the application has the same beneficial effects as the three-dimensional storage because the three-dimensional storage provided by the application is arranged, and the description is omitted here.

Although exemplary methods and structures for preparing a three-dimensional memory are described herein, it is understood that one or more features may be omitted, substituted, or added to the structure of the three-dimensional memory. Furthermore, the illustrated materials of the layers are merely exemplary.

The above description is only illustrative of the preferred embodiments of the present application and of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the application is not limited to the selected combination of the above technical features, but also encompasses other technical solutions formed by any combination of the above technical features or their equivalents without departing from the technical concept. Such as the above-mentioned features and the technical features disclosed in the present application (but not limited to) having similar functions are replaced with each other.

Claims

1. A three-dimensional memory, comprising:

a stacked structure defining a first region and a second region in a plane perpendicular to a stacking direction, wherein the first region includes a first dielectric layer and a gate layer stacked on each other, and the second region includes the first dielectric layer and the second dielectric layer stacked on each other; and

A plurality of contact structures located in the second region and respectively connected with a plurality of the gate layers located at different stack heights in a first direction, the first direction being parallel to the plane,

the portion of the gate layer located outside the second region in the first direction is a connection region, and the connection region of each gate layer has a plurality of different sizes in the first direction.

2. The memory of claim 1, wherein,

the contact structure comprises a first contact structure connected with the gate layer at a first stack height and a second contact structure connected with the gate layer at a second stack height, the first stack height being smaller than the second stack height,

wherein the length of the first portion of the first contact structure extending in the stacking direction is greater than the length of the first portion of the second contact structure extending in the stacking direction; and

a length of the first portion of the first contact structure in the first direction at the first stack height is less than a length of the first portion of the second contact structure in the first direction at the second stack height.

3. The memory of claim 2, wherein,

the connection region of each gate layer includes a plurality of partitions respectively corresponding to different contact structures, wherein a size of a first partition corresponding to a first portion of the first contact structure is larger than a size of a second partition corresponding to a first portion of the second contact structure in the first direction.

4. The memory of claim 2, wherein,

a gate line spacing structure passing through the first region in the stacking direction and extending in a second direction, wherein the second direction is parallel to the plane and perpendicular to the first direction; and

a dummy channel structure extending in the first region along the stacking direction and located between the gate line spacing structure and the contact structure,

wherein a plurality of the dummy channel structures have different sizes from each other in the first direction.

5. The memory of claim 4, wherein,

the dummy channel structure corresponding to the first contact structure has a smaller dimension in the first direction than the dummy channel structure corresponding to the second contact structure.

6. The memory of claim 4, wherein a dimension D1 of the virtual channel structure in the first direction satisfies:

120nm≤D1≤150nm。

7. The memory of claim 2, wherein the memory further comprises:

wherein a plurality of adjacent dummy channel structures have different pitches in the second direction.

8. The memory of claim 7, wherein,

the spacing between adjacent dummy channel structures corresponding to the first contact structure in the second direction is greater than the spacing between adjacent dummy channel structures corresponding to the second contact structure in the second direction.

9. The memory of claim 7, wherein the spacing L1 satisfies:

L1≥30nm。

10. the memory according to any one of claim 4 to 9,

the dimension of the orthographic projection of the virtual channel structure in the plane is larger than or equal to the dimension in other directions.

11. The memory of claim 10, wherein,

The orthographic projection of the virtual channel structure has a circular profile or an elliptical profile.

12. The memory according to claim 4 or 7, wherein,

the angle alpha between the orthographic projection of the virtual channel structure in the plane and the orthographic projection of the grid line clearance structure in the plane is as follows: alpha is less than 60 degrees.

13. A storage system, comprising:

a controller; and

the memory of any one of claims 1 to 12, the controller coupled to the memory and configured to control the memory to store data.

14. A method of making a three-dimensional memory, the method comprising:

alternately stacking the first dielectric layer and the second dielectric layer to form a stacked structure;

removing part of the second dielectric layer to form a gap, and filling the gap with a conductive material to form a gate layer; and

forming a plurality of contact structures extending along a stacking direction and respectively connected with a plurality of gate layers at different stacking heights in a first direction perpendicular to the stacking direction,

the remaining area where the second dielectric layer is located is set as a second area, a portion, located outside the second area, of the gate layer in the first direction is a connection area, and the connection area in each gate layer has a plurality of different sizes in the first direction.

15. The method of claim 14, wherein the method further comprises:

forming dummy channel structures extending in the stacking direction in the stacking structure before forming the void, wherein the dummy channel structures have different sizes from each other in the first direction, or adjacent dummy channel structures have different pitches in a second direction, or the dummy channel structures have different sizes from each other in the first direction, and adjacent dummy channel structures have different pitches in the second direction, wherein the second direction, the stacking direction, and the first direction are perpendicular to each other; and

and removing the part of the second dielectric layer surrounding the virtual channel structure in the process of forming the gaps.

16. The method of claim 15, wherein forming the contact structure comprises:

forming a plurality of contact holes, wherein the contact holes respectively extend to second dielectric layers at different stacking heights along the stacking direction, the contact holes comprise a first contact hole and a second contact hole, the length of the first contact hole along the stacking direction is larger than that of the second contact hole along the stacking direction, and the bottom aperture of the first contact hole is smaller than that of the second contact hole;

Forming a barrier layer on the side wall of the contact hole;

removing a part of the second dielectric layer in contact with the bottom of the contact hole through the contact hole to form a first opening, wherein the first opening exposes a gate layer with the same stacking height as the removed second dielectric layer; and

and filling conductive materials at least in the surface of the barrier layer and the first opening to form a conductive contact layer.

17. The method of claim 16, wherein forming a virtual channel structure extending in the stacking structure along the stacking direction comprises:

and setting the dimension of the virtual channel structure corresponding to the first contact hole in the first direction to be smaller than the dimension of the virtual channel structure corresponding to the second contact hole in the first direction.

18. The method of claim 16, wherein forming a virtual channel structure extending in the stacking structure along the stacking direction comprises:

and setting the interval between adjacent virtual channel structures corresponding to the first contact holes in the second direction to be larger than the interval between adjacent virtual channel structures corresponding to the second contact holes in the second direction.

19. The method of claim 15, wherein forming a virtual channel structure extending in the stacking direction in the stacking structure comprises:

an orthographic projection of the virtual channel structure in a plane perpendicular to the stacking direction is set such that a dimension in at least one direction is greater than or equal to a dimension in the other direction.

20. The method of claim 15, wherein the method further comprises:

forming a gate line gap passing through the stacked structure in the stacking direction and extending in the second direction;

removing a portion of the second dielectric layer via the gate line gap to form the void; and

an angle alpha between an orthographic projection of the virtual channel structure in a plane perpendicular to the stacking direction and an orthographic projection of the gate line clearance in the plane is set as: alpha is less than 60 degrees.