CN117133524A

CN117133524A - On-chip inductor structure and manufacturing method thereof

Info

Publication number: CN117133524A
Application number: CN202311171260.0A
Authority: CN
Inventors: 朱秋昀; 杜茂华
Original assignee: Tongfu Microelectronics Co Ltd
Current assignee: Tongfu Microelectronics Co Ltd
Priority date: 2023-09-11
Filing date: 2023-09-11
Publication date: 2023-11-28

Abstract

An on-chip inductor structure and a manufacturing method thereof, wherein after a first magnetic layer is formed on the surface of a substrate, an inductor is formed on the surface of the first magnetic layer, and the inductor comprises a wire circuit; forming a first photosensitive coating covering the inductor; performing first exposure on the first photosensitive coating, wherein the first exposure is provided with a first window, and the width of the first window is larger than that of the inductor; forming a second photosensitive coating layer on the surface of the first photosensitive coating layer; performing second exposure on the second photosensitive coating, wherein a second window is formed in the second exposure, and the width of the second window is equal to that of the wire line; removing the first photosensitive coating and the second photosensitive coating which are not exposed around the inductor, and curing to form a patterned coating covering the inductor, wherein the side wall of the patterned coating is in a slowly descending arc shape and is provided with a buffer area, and the corner of the buffer area is in a concave angle; a second magnetic layer is formed on the patterned coating surface. The coverage rate and thickness uniformity of the second magnetic layer are improved.

Description

On-chip inductor structure and manufacturing method thereof

Technical Field

The application relates to the field of semiconductors, in particular to an on-chip inductor structure and a manufacturing method thereof.

Background

Inductors are the main components of microelectronic circuits such as switching regulators, radio Frequency (RF) circuits, and electromagnetic interference (electro magnetic interference, EMI) mitigation circuits. As microelectronic devices continue to move toward higher levels of integration and complexity, it becomes important to achieve high inductance within small-sized microelectronic devices. Thus the inductor must implement on-die or in-package (on-package) integration to achieve high performance circuits, but the performance of existing on-die inductor structures remains to be improved.

Disclosure of Invention

Some embodiments of the present application provide a method for manufacturing an on-chip inductor structure, including:

providing a substrate;

forming a first magnetic layer on a surface of the substrate;

forming an inductor on the surface of the first magnetic layer, wherein the inductor at least comprises one wire line;

forming a first photosensitive coating layer covering the inductor on the first magnetic layer, wherein a first bulge structure is arranged in the first photosensitive coating layer right above the wire line;

performing first exposure on the first photosensitive coating on the inductor, wherein the first exposure is provided with a first window, and the width of the first window is larger than that of the inductor;

after the first exposure is carried out, a second photosensitive coating is formed on the surface of the first photosensitive coating, and a convex second bulge structure is arranged in the second photosensitive coating right above the wire line;

performing second exposure on the second photosensitive coating right above the wire line, wherein a second window is formed in the second exposure, and the width of the second window is equal to that of the wire line;

removing the unexposed first photosensitive coating and the second photosensitive coating around the inductor, curing the remaining exposed first photosensitive coating and second photosensitive coating, forming a patterned coating covering the inductor on the first magnetic layer, wherein the patterned coating comprises the cured first photosensitive coating and the cured second photosensitive coating positioned on the surface of the cured first photosensitive coating, the patterned coating right above the wire line is provided with an upward bulge structure, the side walls of the cured second photosensitive coating and the cured first photosensitive coating around the inductor are in a slow descending arc shape, and a buffer area is formed at the junction of the side wall of the cured second photosensitive coating and the side wall of the cured first photosensitive coating, and the corner of the buffer area is in a concave angle;

a second magnetic layer is formed on the patterned coating surface.

In some embodiments, the material of the first and second photosensitive coatings is a negative photoresist.

In some embodiments, the material of the negative photoresist is a photosensitive polyimide polymer, a polybenzoxazole polymer or a benzocyclobutene polymer.

In some embodiments, the process of removing the unexposed first and second photosensitive coatings around the inductor includes a development process; the process of curing the remaining exposed first and second photosensitive coatings includes a heat treatment.

In some embodiments, the surface of the first photosensitive coating on both sides of the first bump structure is lower than the top surface of the first bump structure; the surfaces of the second photosensitive coating on two sides of the second bulge structure are lower than the top surfaces of the second bulge structure.

In some embodiments, the width of the cured second photosensitive coating is less than the width of the cured first photosensitive coating.

In some embodiments, the inductor is a spiral inductor or a linear inductor, and when the inductor is a spiral inductor, the wire line is one and spiral; when the inductor is a linear inductor, at least two wire lines are arranged, and at least two wire lines are parallel to each other.

In some embodiments, further comprising: forming a first dielectric layer on a surface of the first magnetic layer before forming an inductor on the surface of the first magnetic layer; a second dielectric layer is formed on the patterned coated surface prior to forming a second magnetic layer on the patterned coated surface.

In some embodiments, the first magnetic layer and the second magnetic layer are each a stacked structure in which magnetic thin film layers and spacers are alternately stacked.

There is also provided, in some embodiments of the application, an on-chip inductor structure comprising:

a substrate;

a first magnetic layer on a surface of the substrate;

an inductor on a surface of the first magnetic layer, the inductor including at least one wire line;

a patterned coating on the first magnetic layer and covering the inductor, wherein the patterned coating comprises a cured first photosensitive coating and a cured second photosensitive coating on the surface of the cured first photosensitive coating, the patterned coating right above the wire line is provided with an upward bulge structure, the side wall of the cured second photosensitive coating and the side wall of the cured first photosensitive coating around the inductor are in a slowly descending arc shape, and a buffer area is formed at the junction of the side wall of the cured second photosensitive coating and the side wall of the cured first photosensitive coating, and the corner of the buffer area is in a concave angle;

a second magnetic layer on the patterned coated surface.

In some embodiments, the material of the cured first photosensitive coating and the cured second photosensitive coating is a negative photoresist.

In some embodiments, further comprising: a first dielectric layer located between the inductor and the first magnetic layer; a second dielectric layer between the second magnetic layer and the patterned coating.

In some embodiments, the bulge structure comprises a first bulge structure in the cured first photosensitive coating and a second bulge structure in the cured second photosensitive coating.

The on-chip inductor structure and the manufacturing method thereof in the foregoing embodiments of the present application include a method for forming an inductor on a surface of a first magnetic layer after forming the first magnetic layer on the surface of a substrate, the inductor including at least one wire line; forming a first photosensitive coating layer covering the inductor on the first magnetic layer, wherein a first bulge structure is arranged in the first photosensitive coating layer right above the wire line; performing first exposure on the first photosensitive coating on the inductor, wherein the first exposure is provided with a first window, and the width of the first window is larger than that of the inductor; after the first exposure is carried out, a second photosensitive coating is formed on the surface of the first photosensitive coating, and a convex second bulge structure is arranged in the second photosensitive coating right above the wire line; performing second exposure on the second photosensitive coating right above the wire line, wherein a second window is formed in the second exposure, and the width of the second window is equal to that of the wire line; removing the unexposed first photosensitive coating and the second photosensitive coating around the inductor, curing the remaining exposed first photosensitive coating and second photosensitive coating, forming a patterned coating covering the inductor on the first magnetic layer, wherein the patterned coating comprises the cured first photosensitive coating and the cured second photosensitive coating positioned on the surface of the cured first photosensitive coating, the patterned coating right above the wire line is provided with an upward bulge structure, the side walls of the cured second photosensitive coating and the cured first photosensitive coating around the inductor are in a slow descending arc shape, and a buffer area is formed at the junction of the side wall of the cured second photosensitive coating and the side wall of the cured first photosensitive coating, and the corner of the buffer area is in a concave angle; a second magnetic layer is formed on the patterned coating surface. By combining the above specific steps, a patterned coating layer with a specific structure is formed (the patterned coating layer comprises a cured first photosensitive coating layer and a cured second photosensitive coating layer positioned on the surface of the cured first photosensitive coating layer), the patterned coating layer right above the wire line is provided with an upward bulge structure, the side wall of the cured second photosensitive coating layer around the inductor and the side wall of the cured first photosensitive coating layer form a slowly descending arc shape, and the junction of the side wall of the cured second photosensitive coating layer and the side wall of the cured first photosensitive coating layer forms a buffer zone, the corner of the buffer zone forms a concave angle), the patterned coating layer right above the wire line is provided with an upward bulge structure, the steepness of the patterned coating layer surface right above the wire line is reduced (the steepness is not excessively inclined or is excessively vertical), the side wall of the cured second photosensitive coating layer around the inductor and the side wall of the cured first photosensitive coating layer form a slowly descending arc shape, and the magnetic coverage is not excessively inclined or is excessively inclined at the junction of the side wall of the cured first photosensitive coating layer and the side wall of the cured first photosensitive coating layer forms a steep or excessively vertical), the magnetic coverage is further reduced (the steepness of the patterned coating layer right above the wire line is reduced) and the steepness of the patterned coating layer is excessively inclined or excessively vertical at the steep side wall, the second magnetic layer formed on the patterned coating surface is prevented from being too thin at a certain position, so that the position reaches the saturation magnetic flux density earlier than other positions, and the inductor is saturated, and the inductance of the inductor is affected.

Drawings

Fig. 1-14 are schematic diagrams illustrating a fabrication process of an on-chip inductor structure according to some embodiments of the present application.

Detailed Description

The following describes the embodiments of the present application in detail with reference to the drawings. In describing embodiments of the present application in detail, the schematic drawings are not necessarily to scale and are merely illustrative and should not be taken as limiting the scope of the application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

Some embodiments of the present application first provide a method for manufacturing an on-chip inductor structure, and the foregoing method is described in detail with reference to the accompanying drawings.

Referring to fig. 1, a substrate is provided.

In some embodiments, the base plate includes a semiconductor substrate 22 and an interlayer dielectric layer 24 on a surface of the semiconductor substrate 22.

In some specific embodiments, the material of the semiconductor substrate 22 may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); silicon On Insulator (SOI), germanium On Insulator (GOI); or may be other materials such as III-V compounds such as gallium arsenide. The semiconductor substrate 22 may also be implanted with certain dopant ions to alter electrical parameters according to design requirements. The semiconductor substrate 22 is further formed with a shallow trench isolation structure (not shown in the figure), where the shallow trench isolation structure is used for isolating adjacent active regions, and the material of the shallow trench isolation structure may be one or more of silicon oxide, silicon nitride, and silicon oxynitride. A semiconductor device is formed in and/or on the active region, the semiconductor device including one or more of a transistor, a resistor, a capacitor, and a diode.

In some embodiments, an interconnect structure 26 is also formed in the interlevel dielectric layer 24 (or in the dielectric layer 24 and on the dielectric layer 24). In a specific embodiment, the interconnect structure 26 includes a metal line, or includes a metal line and a conductive plug connected to the metal line.

In some embodiments, the interlayer dielectric layer 24 may be a single-layer or multi-layer stacked structure, and the corresponding interconnect structure 26 may be a single-layer or multi-layer stacked structure, where each of the interconnect structures is formed in and on the interlayer dielectric layer of the corresponding layer. The material of the interlayer dielectric layer 24 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, carbon, FSG (fluorine doped silicon dioxide), BSG (boron doped silicon dioxide), PSG (phosphorus doped silicon dioxide), BPSG (boron phosphorus doped silicon dioxide) or low dielectric constant (K is less than 2.5). The material of the interconnection structure 26 is one or more of Al, cu, ag, au, pt, ni, ti, tiN, taN, ta, taC, W and WN.

In some embodiments, the substrate further comprises: a passivation layer 26 formed on the surface of the interlayer dielectric layer 24; the method comprises the steps of carrying out a first treatment on the surface of the A first adhesive layer 28 formed on the surface of the passivation layer 26; an underlying dielectric layer 30 is formed on the surface of the first adhesion layer 28.

The material of the passivation layer 26 may be one or more of silicon nitride, silicon carbide, silicon oxide, or silicon oxynitride.

The first adhesive layer 28 serves to improve layer-to-layer adhesion. The first adhesion layer 28 may be a metal material or alloy of titanium, copper, tantalum, etc., or a combination of other metals, and the formation process of the first adhesion layer 28 includes Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), etc.

The underlayer dielectric layer 30 is used for electrical isolation between the subsequently formed first magnetic layer and the substrate. The bottom dielectric layer 30 may be one or more of silicon nitride, silicon carbide, silicon oxide, or silicon oxynitride, and the formation process of the bottom dielectric layer 30 includes Atomic Layer Deposition (ALD), chemical Vapor Deposition (CVD), or Plasma Enhanced Chemical Vapor Deposition (PECVD).

In one embodiment, referring to fig. 2, portions of the underlying dielectric layer 30 and the first adhesion layer 28 are etched away, with the remaining underlying dielectric layer 30 having a surface thereon that is subsequently used to form the first magnetic layer.

The etching to remove portions of the underlying dielectric layer 30 and the first adhesion layer 28 may employ Ion Beam Etching (IBE), reactive Ion Etching (RIE), reactive Ion Beam Etching (RIBE).

Referring to fig. 3 and 4, a first magnetic layer 32 is formed on the surface of the substrate.

In some embodiments, the first magnetic layer 32 is formed on the surface of the underlayer dielectric layer 30.

The first magnetic layer 32 and the second magnetic layer 50 (refer to fig. 14) formed later form a magnetic shell to encapsulate the inductor 40 (refer to fig. 14) formed later, and a continuous magnetic circuit is formed or magnetic coupling is generated between the first magnetic layer 32 and the second magnetic layer 50, so that a wire line in the inductor 40 between the first magnetic layer 32 and the second magnetic layer 50 acts, and the inductance of the inductor is increased.

In some embodiments, the forming of the first magnetic layer 32 includes: forming a first magnetic layer 32 (refer to fig. 3) on the surfaces of the underlayer dielectric layer 30 and the passivation layer 26; the first magnetic layer 32 is patterned, the first magnetic layer 32 outside the underlying dielectric layer 30 is removed, and the first magnetic layer 32 on the surface of the underlying dielectric layer 30 is retained.

The first magnetic layer 32 may have a single-layer structure or a multi-layer stacked structure composed of a magnetic material.

In some embodiments, when the first magnetic layer 32 is a multi-layer stacked structure, the first magnetic layer 32 is a stacked structure in which magnetic thin film layers and spacer layers are alternately stacked, and the material of the magnetic thin film layers is a nanocrystalline magnetic alloy or an amorphous magnetic alloy, which may be CoZrTa, coZrTaB, niFe, coP, feBN, coZrO, etc., formed by copper Physical Vapor Deposition (PVD) or the like. The material of the spacer layer may be silicon oxide, cobalt oxide, etc., and is formed by a deposition process such as Physical Vapor Deposition (PVD) or an oxidation process such as plasma oxidation and thermal oxidation. The thickness of the spacer layer is typically 5-10% of the thickness of the magnetic thin film layer.

In other embodiments, the first magnetic layer 32 is a multi-layer stacked structure, and the first magnetic layer 32 is a stacked structure in which magnetic thin film layers of different magnetic materials are alternately stacked, and in a specific embodiment, the first magnetic layer 32 is a stacked structure in which first magnetic thin film layers and second magnetic thin film layers are alternately stacked, and the materials of the first magnetic thin film layers and the second magnetic thin film layers are different magnetic materials.

In some embodiments, referring to fig. 5, a first dielectric layer 34 is formed on the surface of the first magnetic layer 32 (and the surface of the passivation layer 26).

The first dielectric layer 34 serves to electrically isolate the subsequently formed inductor from the first magnetic layer 32 and to increase the dielectric constant of the material between the first magnetic layer 32 and the subsequently formed second magnetic layer 50 (see fig. 14). The first dielectric layer 34 on the surface of the first magnetic layer 32 has a flat surface.

In some embodiments, the first dielectric layer 34 material may be a polymer, specifically Polyimide (PI), polybenzoxazole (PBO), or the like. In other embodiments, the first dielectric layer 34 may also be an inorganic dielectric material, and specifically may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride.

In some embodiments, referring to fig. 6, further comprising: a seed layer is formed on the surface of the first dielectric layer 34. The seed layer 36 serves as a seed layer and a conductive layer for subsequent use in forming the inductor using electroplating. The seed layer 36 is formed by Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), or the like. The material of the seed layer 36 may be copper, titanium, or other metals and alloys thereof, or a combination of metals.

Referring to fig. 7 and 8, an inductor 40 is formed on the surface of the first magnetic layer 32, and the inductor 40 includes at least one wire line 41.

In this embodiment, the inductor 40 is formed on the surface of the first dielectric layer 34 on the surface of the first magnetic layer 32. In other embodiments, the inductor 40 may be formed directly on the surface of the first magnetic layer 32.

In some embodiments, the inductor 40 is formed by a process comprising: forming a mask layer 38 (see fig. 7) over the seed layer 34, the mask layer 38 having an opening therein exposing a portion of the surface of the seed layer 34, the shape and location of the opening defining the shape and location of the inductor 40 formed; filling a conductive material in the opening by adopting an electroplating process to form an inductor 40, wherein the inductor 40 at least comprises a wire line 41, and the conductive material can be copper, titanium, nickel, gold and other metals and alloys thereof or a combination of a plurality of metals; the mask layer and the seed layer on both sides of the wire line are removed (refer to fig. 8).

The inductor 40 is a spiral inductor or a wire inductor, and in some embodiments, when the inductor 40 is a spiral inductor, the wire line is one and spiral; in other embodiments, when the inductor 40 is a linear inductor, at least two wire lines 41 are provided, at least two wire lines 41 are parallel to each other, and fig. 8 illustrates that two wire lines 41 in the inductor 40 are taken as an example.

Referring to fig. 9, a first photosensitive coating 42 covering the inductor 40 is formed on the first magnetic layer 32, and the first photosensitive coating 42 directly above the wire line 41 has a convex first bump structure 11 therein.

The first photosensitive coating 42 is subsequently used to form the lower portion of the patterned coating.

In some embodiments, the material of the first photosensitive coating 42 is a negative photoresist, and in particular embodiments, the material of the negative photoresist is a photosensitive polyimide Polymer (PI), a polybenzoxazole Polymer (PBO), or a benzocyclobutene polymer (BCB). The first photosensitive coating 42 may be subsequently patterned by an exposure and development process.

The process of forming the first photosensitive coating 42 includes a spin coating process, a spray coating process, physical Vapor Deposition (PVD), or Chemical Vapor Deposition (CVD).

The first photosensitive coating 42 includes a first bump structure 11 protruding above the wire line 41, the top corner of the first bump structure 11 is arc-shaped, the surface of the first photosensitive coating 42 on both sides of the first bump structure 11 is lower than the top surface of the first bump structure 11, the first bump structure 11 facilitates forming the second bump structure 12 (see fig. 11) in the second photosensitive coating 44 formed subsequently, and further, when the first photosensitive coating 42 and the second photosensitive coating 44 are exposed (specific first exposure and second exposure are performed to the first photosensitive coating 42 and the second photosensitive coating 44, respectively), the patterned coating is formed after development and curing (the patterned coating includes the cured first photosensitive coating and the cured second photosensitive coating on the cured first photosensitive coating surface), the first bump structure 11 is easily formed in the patterned coating directly above the wire line 41, the degree of inclination of the surface of the patterned coating directly above the wire line is reduced (see fig. 11), the corner is not formed, the corner is not inclined, the side wall is thus formed in a slow or a slow manner, the side wall is not inclined (the side wall is not inclined) and the side wall is not formed at a slow angle, the side wall is not inclined (the side wall is not inclined or the side wall is too steep), further, when the second magnetic layer 50 is formed on the patterned coating surface (refer to fig. 14), coverage rate and thickness uniformity of the second magnetic layer 50 are improved, so that the second magnetic layer 50 formed on the patterned coating surface is prevented from being too thin at a certain position, and reaches a saturation magnetic flux density earlier than at other positions, so that the inductor 38 is saturated, and inductance of the inductor 38 is affected.

Referring to fig. 10, a first exposure is performed on the first photosensitive coating 42 on the inductor 40, the first exposure having a first window 51, the first window 51 having a width greater than the width of the inductor 40.

The first photosensitive coating 42 is subjected to a first exposure by using a first photomask plate 54, where the first photomask plate includes a light-transmitting portion and an opaque portion, and exposure light passes through the light-transmitting portion of the first photomask plate 54 and is projected into the first photosensitive coating 42 through a corresponding optical component. The first window 51 at the time of the first exposure is the size of the dimension of the exposure light projected into the first photosensitive coating 42, or the first window 51 at the time of the first exposure is the feature size of the light-transmitting portion of the first photomask 54 multiplied by the optical component magnification. The width of the inductor 40 is the vertical distance between the outer sidewalls of the two wire lines 41 on the outermost side of the inductor.

The size of the first window 51 defines the size of the cross-linked hardened portion of the first photosensitive coating 42, i.e., the size of the lower portion of the subsequently patterned coating, and the width of the first window 51 is greater than the width of the inductor 40, i.e., the subsequently patterned coating is to cover at least the inductor 40.

Referring to fig. 11, after the first exposure, a second photosensitive coating 44 is formed on the surface of the first photosensitive coating 42, and the second photosensitive coating 44 directly above the wire line 41 has a convex second bump structure 12 therein.

The second photosensitive coating 442 is subsequently used to form an upper portion of the patterned coating.

In some embodiments, the material of the second photosensitive coating 44 is a negative photoresist, and in particular embodiments, the material of the negative photoresist is a photosensitive polyimide Polymer (PI), a polybenzoxazole Polymer (PBO), or a benzocyclobutene polymer (BCB). The second photosensitive coating 44 can be subsequently patterned by an exposure and development process.

The process of forming the second photosensitive coating 44 includes a spin coating process, a spray coating process, physical Vapor Deposition (PVD), or Chemical Vapor Deposition (CVD).

The second photosensitive coating 44 is formed to include a second bump structure 12 protruding directly above the wire line 41, the top corner of the second bump structure 12 is curved, the surface of the second photosensitive coating 44 on both sides of the second bump structure 12 is lower than the top surface of the second bump structure 12, so that the second photosensitive coating 44 is subjected to a specific second exposure, and the specific first exposed first photosensitive coating 42 and the specific first exposed second photosensitive coating 44 are subjected to development and curing to form a patterned coating (the patterned coating includes a cured first photosensitive coating and a cured second photosensitive coating on the cured first photosensitive coating surface), the patterned coating directly above the wire line 41 is easy to form a protruding bump structure, the steep (non-sloped or too-vertical) of the patterned coating surface directly above the wire line 41 is reduced, and the side walls of the patterned coating around the inductor 40 are easy to form a slow-down gradient, thus the gradient (non-sloped) of the first side wall and the corner of the patterned coating is further sloped (the non-sloped or too steep) of the magnetic buffer layer 50 is further, the gradient (the non-sloped or too-sloped side wall) of the patterned side wall is further) is reduced, and the gradient (the gradient of the magnetic layer is further) is not sloped (the gradient-sloped) is further) is formed at the side walls (the side walls 50 is further sloped and the side walls are not sloped, the second magnetic layer 50 formed on the patterned coating surface is prevented from being too thin at a location that reaches a saturation magnetic flux density earlier than at other locations, thereby saturating the inductor 38 and affecting the inductance of the inductor 38.

Referring to fig. 12, a second exposure is performed to the second photosensitive coating 44 directly above the wire line 41, the second exposure having a second window 52, the width of the second window 52 being equal to the width of the wire line 41.

A second photomask 56 is used when the second photosensitive coating 44 is subjected to the second exposure, the second photomask 56 includes a plurality of light-transmitting portions and a plurality of light-impermeable portions, and exposure light passes through the light-transmitting portions of the second photomask 56 when the second exposure is performed and then is projected into the second photosensitive coating 44 through corresponding optical components. The second window 52 at the second exposure is the size of the exposure light projected into the second photosensitive coating 44, or the second window 52 at the second exposure is the feature size of the light-transmitting portion of the second photomask 56 multiplied by the optical assembly magnification. The width of the wire line 41 is the vertical distance between two opposite outer sidewalls of the wire line 41.

The size of the second window 51 defines the size of the cross-linked hardened portion of the second photosensitive coating 42, i.e., the size of the upper portion of the subsequently patterned coating, and the width of the second window 52 is equal to or slightly greater than the width of the wire trace 41, thereby cross-linking hardening the second photosensitive coating 44 directly above and near the wire trace 41 so that the subsequently patterned coating has a convex bump structure, and the patterned coating sidewall has a slowly decreasing arc shape and has a buffer.

Referring to fig. 13, the first and second photo-sensitive coatings which are not exposed around the inductor 40 are removed, the remaining first and second photo-sensitive coatings 42 and 44 which are exposed are cured, a patterned coating covering the inductor 40 is formed on the first magnetic layer 32, the patterned coating includes the cured first photo-sensitive coating 42 and the cured second photo-sensitive coating 44 which is located on the surface of the cured first photo-sensitive coating 42, the patterned coating directly above the wire line 41 has the bulge structure 13 which bulges upward, the side walls of the cured second photo-sensitive coating 44 and the cured first photo-sensitive coating 42 around the inductor 40 are in a slowly descending arc shape, and a buffer area 45 is formed at the junction of the side wall of the cured second photo-sensitive coating 44 and the side wall of the cured first photo-sensitive coating 42, and the corner of the buffer area 45 is in a concave angle.

The patterned coating directly above the wire line 41 has an upward bulge structure 13 comprising a first bulge structure and a second bulge structure on the surface of the first bulge structure, wherein the first bulge structure is located in a first photosensitive coating 42 cured directly above the wire line 41, and the second bulge structure is located in a second photosensitive coating 44 cured directly above the wire line 41. The vertex angle of the bulge structure 13 is arc-shaped.

The width of the cured second photosensitive coating 44 is less than the width of the cured first photosensitive coating 42, the sidewalls of the cured second photosensitive coating 44 extend in a slowly descending arc to a buffer 45 at the interface with the sidewalls of the cured first photosensitive coating 42, and the sidewalls of the cured first photosensitive coating 42 extend from the slowly descending arc to the surface of the first magnetic layer 32.

Referring to fig. 14, a second magnetic layer 50 is formed on the surface of the patterned coating 40.

In some embodiments, the second magnetic layer 50 is formed directly on the surface of the patterned coating 40. In other embodiments, the second adhesion layer 46 and the second dielectric layer 48 on the surface of the second adhesion layer 46 are formed on the surface of the patterned coating 40 before the second magnetic layer 50 is formed.

In some embodiments, further comprising: a third dielectric layer 52 is formed on the surface of the second magnetic layer 50.

The materials and formation processes of the second adhesive layer 46 are the same as those of the first adhesive layer 28, and the materials and formation processes of the second dielectric layer 48 and the third dielectric layer 52 are the same as those of the underlying dielectric layer 30 and the first dielectric layer 34. The material and forming process of the second magnetic layer 50 are the same as those of the first magnetic layer 32.

The second magnetic layer 50 is formed to blanket over the first magnetic layer 32, and the second magnetic layer 50 has a length greater than the length of the first magnetic layer 32.

In the present application, when the second magnetic layer 50 is formed, since the patterned coating layer with a specific structure is formed by the organic combination of the above specific steps (the patterned coating layer includes the cured first photosensitive coating layer 42 and the cured second photosensitive coating layer 44 on the surface of the cured first photosensitive coating layer 42, the patterned coating layer directly above the wire line 41 has the bump structure that bulges upward, the sidewall of the cured second photosensitive coating layer 44 around the inductor 40 and the sidewall of the cured first photosensitive coating layer 42 form a slowly decreasing arc shape, and the junction between the sidewall of the cured second photosensitive coating layer 44 and the sidewall of the cured first photosensitive coating layer 42 forms a buffer area 45, the corner of the buffer area forms a concave angle), the patterned coating layer directly above the wire line 41 has the bump structure that reduces the steepness of the patterned coating surface directly above the wire line 41 (not too steeply inclining or too perpendicularly), the sidewall of the patterned coating layer around the inductor 40 and the sidewall of the cured second photosensitive coating layer 44 forms a slowly inclining or excessively inclining (not excessively inclining the side wall of the patterned coating layer) and the patterned coating layer at the corner of the buffer area (not excessively inclining or the corner of the cured second photosensitive coating layer) is formed at the junction between the sidewall of the cured second photosensitive coating layer and the patterned coating layer and the cured second photosensitive coating layer (not forming a sharply inclining or excessively inclining side wall of the patterned coating layer) (the buffer area is formed at the corner of the buffer area is not excessively inclining or the side of the patterned coating layer). The coverage rate and thickness uniformity of the second magnetic layer 50 are improved, and the thickness of the second magnetic layer 50 formed on the patterned coating surface at a certain position is prevented from being too thin, so that the position reaches the saturation magnetic flux density earlier than other positions, and the inductor 38 is saturated, and the inductance of the inductor 38 is affected.

Some embodiments of the present application also provide an on-chip inductor structure, referring to fig. 14 and 13 in combination, comprising:

a substrate;

a first magnetic layer 32 on a surface of the substrate;

an inductor 40 located on the surface of the first magnetic layer 32, the inductor 40 including at least one wire line 41;

a patterned coating layer on the first magnetic layer 32 and covering the inductor 40, wherein the patterned coating layer comprises a cured first photosensitive coating layer 42 and a cured second photosensitive coating layer 44 on the surface of the cured first photosensitive coating layer 42, the patterned coating layer right above the wire line 41 is provided with an upward bulge structure 13 (refer to fig. 13), the side wall of the cured second photosensitive coating layer 44 and the side wall of the cured first photosensitive coating layer 42 around the inductor 40 are in a slowly descending arc shape, and a buffer zone 45 is formed at the interface of the side wall of the cured second photosensitive coating layer 44 and the side wall of the cured first photosensitive coating layer 42, and the corner of the buffer zone 45 is in a concave angle;

a second magnetic layer 50 on the patterned coated surface.

In some embodiments, the material of the cured first photosensitive coating 42 and the cured second photosensitive coating 44 is a negative photoresist.

In some embodiments, the width of the cured second photosensitive coating 44 is less than the width of the cured first photosensitive coating 42.

In some embodiments, the inductor 40 is a spiral inductor or a linear inductor, and when the inductor is a spiral inductor, the wire line is one and spiral; when the inductor is a linear inductor, at least two wire lines are arranged, and at least two wire lines are parallel to each other.

In some embodiments, further comprising: a first dielectric layer 34 located between the inductor 40 and the first magnetic layer 32; a second dielectric layer 48 between the second magnetic layer 50 and the patterned coating.

In some embodiments, further comprising: a (second) adhesion layer 46 located between the second dielectric layer 48 and the patterned coating.

In some embodiments, the first magnetic layer 32 and the second magnetic layer 50 are stacked structures in which magnetic thin film layers and spacers are alternately stacked.

In some embodiments, the bulge structure 13 includes a first bulge structure in the cured first photosensitive coating 42 and a second bulge structure in the cured second photosensitive coating 44.

It should be noted that the terms "comprising" and "having" and variations thereof herein are intended to cover a non-exclusive inclusion. The terms "first," "second," and the like are used to distinguish similar objects and not necessarily to describe a particular order or sequence unless otherwise indicated by context, it should be understood that the data so used may be interchanged where appropriate. In addition, the embodiments of the present application and the features in the embodiments may be combined with each other without collision. In addition, in the above description, descriptions of well-known components and techniques are omitted so as to not unnecessarily obscure the present application. In the foregoing embodiments, each embodiment is mainly described for the differences from the other embodiments, and the same/similar parts between the embodiments need to be referred to (or referred to) each other.

Although the present application has been described in terms of the preferred embodiments, it is not intended to be limited to the embodiments, and any person skilled in the art can make any possible variations and modifications to the technical solution of the present application by using the methods and technical matters disclosed above without departing from the spirit and scope of the present application, so any simple modifications, equivalent variations and modifications to the embodiments described above according to the technical matters of the present application are within the scope of the technical matters of the present application.

Claims

1. A method of fabricating an on-chip inductor structure, comprising:

providing a substrate;

forming a first magnetic layer on a surface of the substrate;

forming an inductor on the surface of the first magnetic layer, wherein the inductor at least comprises one wire line; forming a first photosensitive coating layer covering the inductor on the first magnetic layer, wherein a first bulge structure is arranged in the first photosensitive coating layer right above the wire line;

a second magnetic layer is formed on the patterned coating surface.

2. The method of fabricating an on-chip inductor structure according to claim 1, wherein the material of the first photosensitive coating and the second photosensitive coating is a negative photoresist.

3. The method of fabricating an on-chip inductor structure according to claim 2, wherein the negative photoresist material is a photosensitive polyimide polymer, a polybenzoxazole polymer or a benzocyclobutene polymer.

4. The method of fabricating an on-chip inductor structure according to claim 1 or 2, wherein the process of removing the unexposed first and second photosensitive coatings around the inductor comprises a developing process; the process of curing the remaining exposed first and second photosensitive coatings includes a heat treatment.

5. The method of fabricating an on-chip inductor structure according to claim 1, wherein a surface of the first photosensitive coating on both sides of the first bump structure is lower than a top surface of the first bump structure; the surfaces of the second photosensitive coating on two sides of the second bulge structure are lower than the top surfaces of the second bulge structure.

6. The method of fabricating an on-chip inductor structure according to claim 1 or 5, wherein the width of the cured second photosensitive coating is smaller than the width of the cured first photosensitive coating.

7. The method of manufacturing an on-chip inductor structure according to claim 1, wherein the inductor is a spiral inductor or a linear inductor, and when the inductor is a spiral inductor, the wire line is one and spiral; when the inductor is a linear inductor, at least two wire lines are arranged, and at least two wire lines are parallel to each other.

8. The method of fabricating an on-chip inductor structure of claim 1, further comprising:

forming a first dielectric layer on a surface of the first magnetic layer before forming an inductor on the surface of the first magnetic layer; a second dielectric layer is formed on the patterned coated surface prior to forming a second magnetic layer on the patterned coated surface.

9. The method of manufacturing an on-chip inductor structure according to claim 1, wherein the first magnetic layer and the second magnetic layer are stacked structures in which magnetic thin film layers and spacer layers are alternately stacked.

10. An on-chip inductor structure, comprising:

a substrate;

a first magnetic layer on a surface of the substrate;

an inductor on a surface of the first magnetic layer, the inductor including at least one wire line; a patterned coating on the first magnetic layer and covering the inductor, wherein the patterned coating comprises a cured first photosensitive coating and a cured second photosensitive coating on the surface of the cured first photosensitive coating, the patterned coating right above the wire line is provided with an upward bulge structure, the side wall of the cured second photosensitive coating and the side wall of the cured first photosensitive coating around the inductor are in a slowly descending arc shape, and a buffer area is formed at the junction of the side wall of the cured second photosensitive coating and the side wall of the cured first photosensitive coating, and the corner of the buffer area is in a concave angle;

a second magnetic layer on the patterned coated surface.

11. The on-chip inductor structure of claim 10, wherein the material of the cured first photosensitive coating and the cured second photosensitive coating is a negative photoresist.

12. The on-chip inductor structure of claim 11, wherein the material of the negative photoresist is a photosensitive polyimide polymer, a polybenzoxazole polymer or a benzocyclobutene polymer.

13. The on-chip inductor structure of claim 10, wherein a width of the cured second photosensitive coating is less than a width of the cured first photosensitive coating.

14. The on-chip inductor structure of claim 10, wherein the inductor is a spiral inductor or a wire inductor, and the wire line is one and spiral when the inductor is a spiral inductor; when the inductor is a linear inductor, at least two wire lines are arranged, and at least two wire lines are parallel to each other.

15. The on-chip inductor structure of claim 10, further comprising: a first dielectric layer located between the inductor and the first magnetic layer; a second dielectric layer between the second magnetic layer and the patterned coating.

16. The on-chip inductor structure of claim 10, wherein the first magnetic layer and the second magnetic layer are each a stacked structure in which magnetic thin film layers and spacer layers are alternately stacked.

17. The on-chip inductor structure of claim 10, wherein the bump structure comprises a first bump structure in the cured first photosensitive coating and a second bump structure in the cured second photosensitive coating.