CN117132674A - Wafer map generation method and test equipment - Google Patents
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- CN117132674A CN117132674A CN202310974969.8A CN202310974969A CN117132674A CN 117132674 A CN117132674 A CN 117132674A CN 202310974969 A CN202310974969 A CN 202310974969A CN 117132674 A CN117132674 A CN 117132674A
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- 238000012360 testing method Methods 0.000 title claims abstract description 59
- 238000000034 method Methods 0.000 title claims abstract description 39
- 238000010586 diagram Methods 0.000 claims abstract description 22
- 238000012937 correction Methods 0.000 claims abstract description 12
- 238000005516 engineering process Methods 0.000 claims description 8
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- 238000009432 framing Methods 0.000 claims description 3
- 238000013507 mapping Methods 0.000 claims description 3
- 230000003287 optical effect Effects 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 230000008878 coupling Effects 0.000 description 7
- 238000010168 coupling process Methods 0.000 description 7
- 238000005859 coupling reaction Methods 0.000 description 7
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- 230000005693 optoelectronics Effects 0.000 description 2
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T11/00—2D [Two Dimensional] image generation
- G06T11/001—Texturing; Colouring; Generation of texture or colour
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T11/00—2D [Two Dimensional] image generation
- G06T11/40—Filling a planar surface by adding surface attributes, e.g. colour or texture
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/0002—Inspection of images, e.g. flaw detection
- G06T7/0004—Industrial image inspection
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/60—Analysis of geometric attributes
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/70—Determining position or orientation of objects or cameras
- G06T7/73—Determining position or orientation of objects or cameras using feature-based methods
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/30—Subject of image; Context of image processing
- G06T2207/30108—Industrial image inspection
- G06T2207/30148—Semiconductor; IC; Wafer
Abstract
The invention relates to a wafer map generation method and test equipment, which comprises the following steps: scanning and photographing the wafer on the wafer test table to obtain a complete scanning picture; deducing a wafer reasoning diagram of all complete chips according to the scanning picture; removing chips outside the wafer range in the wafer inference graph according to the wafer range to obtain an uncorrected wafer graph file; traversing all chips to be tested of the wafer on the wafer test table by using the uncorrected wafer map file, and correcting errors of the actual positions of each chip in the wafer map file to obtain a high-precision wafer map. The wafer is scanned and photographed to obtain a complete scanning picture, and then the wafer inference diagram of all complete chips can be inferred according to the scanning picture, and the wafer diagram with high precision can be obtained after the chips outside the wafer range are removed and error correction is carried out, so that the wafer diagram can be automatically generated without inputting and manually measuring the chips.
Description
Technical Field
The invention relates to the field of silicon photon and photoelectron integration, in particular to a wafer map generation method and test equipment.
Background
The wafer map records the distribution information of chips on the wafer, plays an important role in the semiconductor wafer testing process, and can be directly guided into a scanning machine under the condition of the existing wafer map. Without the wafer map, subsequent generation of the wafer map is required.
In the related art, the wafer map of the silicon optoelectronic chip is generally created by adopting a list input mode, so that the operation is complex, the length, width and relative position of each chip are required to be manually measured, the precision of the generated wafer map is not high, and the realization of end surface optical coupling of the silicon optoelectronic wafer is not facilitated.
Therefore, it is necessary to design a new wafer map generation method.
Disclosure of Invention
The embodiment of the invention provides a wafer map generation method and test equipment, which are used for solving the problems that the wafer map generated in the related technology is low in precision and is not beneficial to realizing end surface optical coupling of a silicon optical wafer.
In a first aspect, a method for generating a wafer map is provided, including the following steps: scanning and photographing the wafer on the wafer test table to obtain a complete scanning picture; deducing a wafer reasoning diagram of all complete chips according to the scanning picture; removing chips outside the wafer range in the wafer inference graph according to the wafer range to obtain an uncorrected wafer graph file; traversing all chips to be tested of the wafer on the wafer test table by using the uncorrected wafer map file, and correcting errors of the actual positions of each chip in the wafer map file to obtain a high-precision wafer map.
In some embodiments, traversing all the chips to be tested of the wafer on the wafer test table by using the uncorrected wafer map file, and performing error correction on the actual position of each chip in the wafer map file to obtain a high-precision wafer map, including:
loading an uncorrected wafer map file to a wafer test bench, establishing a mapping relation, and converting the relative position coordinates of each chip in the wafer map file into physical coordinates of each chip on the wafer test bench;
and controlling the wafer test bench to move to the converted physical coordinate position of each chip, calculating the deviation between the actual position of each chip and the physical coordinate position by using an image recognition algorithm, and correcting the relative position coordinates of each chip according to the deviation to obtain a high-precision wafer map.
In some embodiments, the reasoning about the wafer reasoning diagram of the complete chip according to the scan picture includes:
firstly selecting an exposure unit from the generated scanning pictures, then selecting chips to be tested in the exposure unit in a framing way, and calculating appearance attribute information of one exposure unit and the chips in the exposure unit by using a visual identification technology to serve as an exposure unit image template;
and deducing a wafer deducing graph which is a complete exposure unit and a chip by using the exposure unit image template.
In some embodiments, the reasoning about wafer reasoning about complete exposure units and chips using the exposure unit image template includes:
and (3) utilizing an exposure unit image template, combining image complementation and image recognition to deduce a wafer reasoning diagram of the complete exposure unit and the chip.
In some embodiments, the wafer inference graph, which is all the complete exposure unit and the chip, is inferred by using the exposure unit image template and combining image complement and image recognition, including:
using an exposure unit image template to complement all complete exposure units in a scanned picture through an image complement algorithm, wherein each exposure unit is provided with a complete chip;
selecting one chip as an origin, taking a row of chip arrangement as an X axis, and taking a column of chip arrangement as a Y axis to establish a rectangular coordinate system;
performing image recognition on the completed picture by using an exposure unit image template, and measuring the position information of each exposure unit and the position information of all chips in one exposure unit;
and (3) combining the position information of all chips in one exposure unit with the position information of all exposure units to obtain and store the position information of all chips in each exposure unit, thereby obtaining the wafer inference graph of all complete exposure units and chips.
In some embodiments, before the image recognition is performed on the completed picture by using the exposure unit image template, the method further includes: numbering all the exposure units according to a preset rule, and generating the numbers of all chips in each exposure unit by combining the numbers of the exposure units.
In some embodiments, the appearance attribute information includes edges of the exposure unit and contours, textures, and shapes of the exposure unit and the chip.
In some embodiments, the scanning and photographing the wafer on the wafer test bench to obtain a complete scan image includes:
according to the size of the wafer, the wafer is divided into a plurality of parts for scanning and photographing, and the plurality of parts of photos are combined into a complete scanning picture by utilizing an image splicing technology.
In some embodiments, after the scanning and photographing the wafer on the wafer test bench to obtain the complete scan picture, the method further includes:
selecting two feature points with the farthest distance on a reference diameter line of a wafer, and calculating an included angle between a connecting line of the two feature points and a horizontal reference line;
and rotating the scanned picture and the wafer according to the calculated included angle, so that the position of the wafer is aligned.
In a second aspect, there is provided a test apparatus comprising: the wafer test bench is used for placing a wafer; the wafer map generation device is used for scanning and photographing the wafer on the wafer test table to obtain a complete scanning picture; and deducing a wafer reasoning diagram of all the complete chips according to the scanning picture; the wafer map generating device is also used for removing chips outside the wafer range in the wafer inference map according to the range of the wafer to obtain an uncorrected wafer map file; traversing all chips to be tested of the wafer on the wafer test table by using the uncorrected wafer map file, and correcting errors of the actual positions of each chip in the wafer map file to obtain a high-precision wafer map.
The technical scheme provided by the invention has the beneficial effects that:
the embodiment of the invention provides a wafer map generation method and test equipment, wherein a wafer is scanned and photographed to obtain a complete scanning image comprising the wafer and chips, then a wafer reasoning image of all the complete chips can be deduced according to the scanning image, and a high-precision wafer map can be obtained after the chips outside the wafer range are removed and the actual position of each chip is subjected to error correction, so that the wafer map can be automatically generated without inputting and manually measuring the chips, and the high-precision wafer map is created without repeatedly adjusting parameters, and the errors caused by manual measurement can be reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a method for generating a wafer map according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a complete scanned image according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a frame-selected exposure unit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a chip selected by a frame according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a wafer inference diagram for a complete chip according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of an uncorrected wafer map file according to one embodiment of the present invention;
fig. 7 is a schematic structural diagram of a corrected wafer map according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The embodiment of the invention provides a wafer map generation method and test equipment, which can solve the problems that the wafer map generated in the related technology is low in precision and is unfavorable for realizing end-face optical coupling of a silicon optical wafer.
Referring to fig. 1, a method for generating a wafer map according to an embodiment of the present invention includes the following steps:
s1: and scanning and photographing the wafer on the wafer test table to obtain a complete scanning picture. The method can be used for scanning and photographing by utilizing a CCD (charge coupled device) to obtain a scanning picture, wherein the scanning picture comprises a complete wafer and all chips, and the method is used by being matched with a wafer test bench.
S2: and deducing a wafer reasoning diagram of all the complete chips according to the scanning picture. The whole chips are referred to herein as a whole structure, and the wafer inference graph includes not only the whole chips within the wafer range but also the fictional chips outside the wafer range and the chips on the wafer edge (a part of the chips are outside the wafer range), and the fictional chips are not actually present or cannot be used, and need to be removed in the final wafer map file, i.e. the subsequent step S3.
S3: and removing chips outside the wafer range in the wafer inference graph according to the wafer range to obtain an uncorrected wafer graph file (see FIG. 6). The wafer map file at this time contains all the complete chips within the wafer.
S4: traversing all chips to be tested of the wafer on the wafer test table by using the uncorrected wafer map file, and correcting errors of the actual positions of each chip in the wafer map file to obtain a high-precision wafer map.
In the embodiment of the invention, the wafer is scanned and photographed to obtain the complete scanning picture comprising the wafer and the chips, then the wafer inference picture of all the complete chips can be inferred according to the scanning picture, the fictive chips possibly exist at the moment, an uncorrected wafer picture file can be obtained after the fictive chips outside the wafer range are removed, then all the chips to be tested of the wafer on the wafer test table can be traversed by using the uncorrected wafer picture file, and error correction is carried out on the actual position of each chip in the wafer picture file, and finally the high-precision wafer picture is obtained, therefore, the wafer picture can be automatically generated without inputting and manually measuring the chips, the operation is simple and convenient, the parameter is not required to be repeatedly adjusted to create the high-precision wafer picture, and the error caused by manual measurement can be reduced.
Because the silicon optical chip needs to be coupled with an external light source, wherein the end face coupling needs to be performed by extending an optical probe into a scribing groove of the silicon optical wafer, the width of the scribing groove is only 50um-100um, the accuracy of the coupling position is required to be very high no matter the single optical probe or the optical probe array is adopted, and the error is required to reach the um level. Because of the introduction of artificial measurement errors and motor motion accumulated errors, the actual position of each chip needs to be adjusted repeatedly. This is difficult to achieve if the position is to be de-calibrated during the test, again because of the obstruction of the vision of the electrical and optical probes. The wafer map obtained by the wafer map generation method provided by the embodiment of the invention has higher progress, can be used for generating the wafer map of the silicon photoelectronic chip, and can be used for coupling test of the wafer end face of the silicon photoelectronic chip.
In some embodiments, in step S4, traversing all the chips to be tested of the wafer on the wafer test table by using the uncorrected wafer map file, and performing error correction on the actual position of each chip in the wafer map file to obtain a high-precision wafer map, which may include: loading an uncorrected wafer map file to a wafer test table, establishing a mapping relation, and converting the relative position coordinates of each chip in the wafer map file into physical coordinates of each chip on the wafer test table, wherein given the physical coordinates of a certain chip, the relative position coordinates of all the chips can be converted into the physical coordinates of the wafer test table; then, according to the physical coordinates of each chip obtained in the foregoing, the wafer test bench is controlled to move to the converted physical coordinate position of each chip, at this time, the chip may be in the middle of the lens of the wafer test bench, or may have a deviation (the deviation is generally small, generally is an image recognition deviation introduced by a low-magnification CCD or a deviation introduced by non-uniform thinning of the wafer, etc.), at this time, an image recognition algorithm (a template matching method or the like is adopted) may be used to calculate the deviation between the actual position and the physical coordinate position of each chip, and according to the deviation, the relative position coordinate correction is performed on each chip, and the corrected position information is written into a wafer map file, so as to obtain a high-precision wafer map (see fig. 7). And traversing each chip to realize wafer map correction. When the error correction is carried out, the embodiment can randomly traverse each chip to accurately correct the actual position of each chip, has high flexibility and lower cost, can realize correction and generation of a wafer map on the existing wafer test bench, and can reduce the dependence on an ultrahigh-precision motor of the wafer test bench. In the correction process, a high-resolution CCD may be switched to improve correction accuracy.
Further, in some embodiments, in step S1, the scanning and photographing the wafer on the wafer test bench to obtain a complete scan image may include: the wafer is placed on a wafer test bench (the wafer should be aligned as much as possible when the wafer is placed, the chips arranged in rows on the wafer are parallel to the horizontal axis in the horizontal plane as much as possible, and the chips arranged in columns on the wafer are parallel to the vertical axis in the horizontal plane as much as possible), the wafer is divided into a plurality of parts according to the size of the wafer to carry out scanning photographing (one part can be scanned at a time), and the plurality of parts of photos are combined into a complete scanning picture by utilizing an image splicing technology (see fig. 2). Common image stitching algorithms are position stitching and feature stitching.
In some optional embodiments, after the scanning and photographing the wafer on the wafer test bench, obtaining a complete scan picture may further include: selecting two feature points furthest apart from each other on a reference diameter line (the reference diameter line is a line which passes through the center of the wafer and is parallel to a certain row of chips) of the wafer, and calculating an included angle between a connecting line of the two feature points and a horizontal datum line (which can be a defined datum line); and rotating the scanned picture and the wafer according to the calculated included angle, so that the position of the wafer is aligned. After the alignment, the selected reference diameter line on the wafer is parallel or coincident with the horizontal reference line; the adjusted wafer and the scanned picture are beneficial to the determination and subsequent calculation of the position coordinates of the subsequent chips, and the measurement accuracy is improved.
Further, in some embodiments, referring to fig. 3 and 4, in step S2, the reasoning about the wafer reasoning diagram of the complete chip according to the scan picture may include: firstly selecting an exposure unit (shot) from the generated scanning picture, then selecting a chip (Die) to be tested in the exposure unit in a framing manner, and calculating appearance attribute information of one exposure unit and the chip in the exposure unit by using a visual identification technology to serve as an exposure unit image template; and deducing a wafer deducing graph which is a complete exposure unit and a chip by using the exposure unit image template. That is, all complete exposure units in the scanned picture are deduced by using one exposure unit, wherein a plurality of chips are arranged in each exposure unit, and the number of chips in each exposure unit is the same.
Referring to fig. 5, in some embodiments, the wafer inference graph, which is an entire exposure unit and chip, is inferred using the exposure unit image template, may include: and (3) utilizing an exposure unit image template, combining image complementation and image recognition to deduce a wafer reasoning diagram of the complete exposure unit and the chip. After the scanned picture is obtained, if the image recognition is directly carried out, incomplete exposure units cannot be recognized, so that all exposure units and chips can be recognized by carrying out image complementation and then image recognition on the scanned picture.
Preferably, the reasoning of the wafer reasoning graph of the complete exposure unit and the chip by using the exposure unit image template and combining image complementation and image recognition may include:
s21: the incomplete exposure units are complemented, namely, all the complete exposure units are complemented in a scanned picture by utilizing an exposure unit image template through an image complement algorithm, wherein each exposure unit is provided with a complete chip; because the wafer is formed by regularly arranging and combining a plurality of exposure units, the exposure unit image template extracted above is utilized to carry out complementation through an image complementation algorithm. The image complement is performed for three reasons, namely, for carrying out ID numbering on the chip, for better image recognition, for the fact that incomplete exposure unit images and incomplete chip images are difficult to recognize by using a visual algorithm, and for the convenience of establishing a rectangular coordinate system.
S22: one chip is selected as an origin, a row of the chip arrangement is taken as an X axis, and a column of the chip arrangement is taken as a Y axis to establish a rectangular coordinate system. The first chip in the upper left corner may be preferred as the origin, although other chips may be selected as the origin.
S23: and carrying out image recognition on the completed picture by using an exposure unit image template, and measuring the position information of each exposure unit and the position information of all chips in one exposure unit. The position information of the exposure unit comprises the number of the exposure unit and the relative position coordinates of the exposure unit in the wafer map; the location information of the chip includes the number of the chip, whether the chip is available (incomplete or not available outside the wafer range), the relative location coordinates of the chip in the wafer. The image recognition mainly adopts a feature matching method to compare two pictures to realize image matching.
S24: and (3) combining the position information of all chips in one exposure unit with the position information of all exposure units to obtain and store the position information of all chips in each exposure unit, thereby obtaining the wafer inference graph of all complete exposure units and chips. The relative position coordinates of all chips in one exposure unit are obtained only by obtaining the relative position coordinates of all chips in one exposure unit and combining the relative position coordinates of all exposure units, and the wafer inference graph obtained at the moment contains fictitious chips, and the fictitious chips are removed in a final wafer graph file.
In some optional embodiments, before the image recognition is performed on the completed picture by using the exposure unit image template, the method may further include: numbering all the exposure units according to a preset rule, and generating the numbers of all chips in each exposure unit by combining the numbers of the exposure units. The preset rule may be, for example, that the numbers from left to right and from top to bottom are increased to obtain the numbers of the exposure units, and then the numbers of the chips in the exposure units may be obtained by adopting the same rule. The exposure unit and the serial number of the chip are mainly used for carrying out ID marking on the chip, because the wafer map is mainly used for testing, the testing needs to correspond the chip and the data, and the ID information of each chip is also contained in the wafer map file.
Preferably, the appearance attribute information may include an edge of the exposure unit, and a contour, texture, and shape of the exposure unit and the chip.
The embodiment of the invention provides a method for generating a wafer map, wherein a wafer comprises more than one exposure unit, each exposure unit comprises more than one chip (Die), and each exposure unit comprises more than one chip. The wafer is composed of periodic exposure units and chips, and according to the size of the wafer, the sizes of the exposure units and the chips can be used for establishing a very accurate wafer map, but in actual engineering, the established wafer map is often inaccurate due to the reasons of dimension measurement errors, motor motion accumulation errors and the like, and particularly in the silicon-based photoelectron field, the accuracy of the wafer map needs to reach the um level due to the fact that end face coupling on a chip is required. The method is high in automation degree and convenient to operate, and a high-precision wafer map can be generated.
The embodiment of the invention also provides test equipment, which comprises: the wafer test bench is used for placing a wafer and can test the wafer; the wafer map generation device is used for scanning and photographing the wafer on the wafer test table to obtain a complete scanning picture; and deducing a wafer reasoning diagram of all the complete chips according to the scanning picture; the wafer map generating device is also used for removing chips outside the wafer range in the wafer inference map according to the range of the wafer to obtain an uncorrected wafer map file; traversing all chips to be tested of the wafer on the wafer test table by using the uncorrected wafer map file, and correcting errors of the actual positions of each chip in the wafer map file to obtain a high-precision wafer map.
The test device provided by the embodiment of the present invention can implement the method for generating the wafer map provided by any of the embodiments, which is not described herein.
In the description of the present invention, it should be noted that the azimuth or positional relationship indicated by the terms "upper", "lower", etc. are based on the azimuth or positional relationship shown in the drawings, and are merely for convenience of describing the present invention and simplifying the description, and are not indicative or implying that the apparatus or element in question must have a specific azimuth, be constructed and operated in a specific azimuth, and thus should not be construed as limiting the present invention. Unless specifically stated or limited otherwise, the terms "mounted," "connected," and "coupled" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
It should be noted that in the present invention, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. The wafer map generation method is characterized by comprising the following steps of:
scanning and photographing the wafer on the wafer test table to obtain a complete scanning picture;
deducing a wafer reasoning diagram of all complete chips according to the scanning picture;
removing chips outside the wafer range in the wafer inference graph according to the wafer range to obtain an uncorrected wafer graph file;
traversing all chips to be tested of the wafer on the wafer test table by using the uncorrected wafer map file, and correcting errors of the actual positions of each chip in the wafer map file to obtain a high-precision wafer map.
2. The method for generating a wafer map according to claim 1, wherein traversing all the chips to be tested of the wafer on the wafer test table by using the uncorrected wafer map file, and performing error correction on the actual position of each chip in the wafer map file to obtain a high-precision wafer map comprises:
loading an uncorrected wafer map file to a wafer test bench, establishing a mapping relation, and converting the relative position coordinates of each chip in the wafer map file into physical coordinates of each chip on the wafer test bench;
and controlling the wafer test bench to move to the converted physical coordinate position of each chip, calculating the deviation between the actual position of each chip and the physical coordinate position by using an image recognition algorithm, and correcting the relative position coordinates of each chip according to the deviation to obtain a high-precision wafer map.
3. The method of generating a wafer map according to claim 1, wherein the step of deducing a wafer map of all complete chips from the scanned image comprises:
firstly selecting an exposure unit from the generated scanning pictures, then selecting chips to be tested in the exposure unit in a framing way, and calculating appearance attribute information of one exposure unit and the chips in the exposure unit by using a visual identification technology to serve as an exposure unit image template;
and deducing a wafer deducing graph which is a complete exposure unit and a chip by using the exposure unit image template.
4. The method of claim 3, wherein the reasoning about wafer reasoning about complete exposure units and chips using the exposure unit image template comprises:
and (3) utilizing an exposure unit image template, combining image complementation and image recognition to deduce a wafer reasoning diagram of the complete exposure unit and the chip.
5. The method of claim 4, wherein the reasoning about wafer reasoning about complete exposure units and chips by using the exposure unit image template and combining image complementation and image recognition comprises:
using an exposure unit image template to complement all complete exposure units in a scanned picture through an image complement algorithm, wherein each exposure unit is provided with a complete chip;
selecting one chip as an origin, taking a row of chip arrangement as an X axis, and taking a column of chip arrangement as a Y axis to establish a rectangular coordinate system;
performing image recognition on the completed picture by using an exposure unit image template, and measuring the position information of each exposure unit and the position information of all chips in one exposure unit;
and (3) combining the position information of all chips in one exposure unit with the position information of all exposure units to obtain and store the position information of all chips in each exposure unit, thereby obtaining the wafer inference graph of all complete exposure units and chips.
6. The method of claim 5, further comprising, before performing image recognition on the completed picture using the exposure unit image template to measure the position information of each exposure unit and the position information of all chips in one of the exposure units:
numbering all the exposure units according to a preset rule, and generating the numbers of all chips in each exposure unit by combining the numbers of the exposure units.
7. The method for generating a wafer map according to claim 3, wherein:
the appearance attribute information includes the edges of the exposure unit, and the contours, textures, and shapes of the exposure unit and the chip.
8. The method of claim 1, wherein scanning the wafer on the wafer test table to obtain a complete scan image comprises:
according to the size of the wafer, the wafer is divided into a plurality of parts for scanning and photographing, and the plurality of parts of photos are combined into a complete scanning picture by utilizing an image splicing technology.
9. The method of claim 1, further comprising, after performing a scan photograph of the wafer on the wafer test table to obtain a complete scan photograph:
selecting two feature points with the farthest distance on a reference diameter line of a wafer, and calculating an included angle between a connecting line of the two feature points and a horizontal reference line;
and rotating the scanned picture and the wafer according to the calculated included angle, so that the position of the wafer is aligned.
10. A test apparatus, comprising:
the wafer test bench is used for placing a wafer;
the wafer map generation device is used for scanning and photographing the wafer on the wafer test table to obtain a complete scanning picture; and deducing a wafer reasoning diagram of all the complete chips according to the scanning picture;
the wafer map generating device is also used for removing chips outside the wafer range in the wafer inference map according to the range of the wafer to obtain an uncorrected wafer map file; traversing all chips to be tested of the wafer on the wafer test table by using the uncorrected wafer map file, and correcting errors of the actual positions of each chip in the wafer map file to obtain a high-precision wafer map.
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| CN202310974969.8A CN117132674A (en) | 2023-08-02 | 2023-08-02 | Wafer map generation method and test equipment |
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| CN202310974969.8A CN117132674A (en) | 2023-08-02 | 2023-08-02 | Wafer map generation method and test equipment |
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| CN117576092B (en) * | 2024-01-15 | 2024-03-29 | 成都瑞迪威科技有限公司 | Wafer component counting method based on image processing |
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