CN117129088A

CN117129088A - Chip temperature testing method and system

Info

Publication number: CN117129088A
Application number: CN202310994928.5A
Authority: CN
Inventors: 罗小凌; 黄爱华; 徐定向
Original assignee: Shanghai Gengen Information Technology Co ltd
Current assignee: Suzhou Akeydrive Information Technology Co ltd
Priority date: 2023-08-08
Filing date: 2023-08-08
Publication date: 2023-11-28
Anticipated expiration: 2043-08-08
Also published as: CN117129088B

Abstract

The present invention relates to the field of data mining technologies, and in particular, to a method and a system for testing chip temperature. The method comprises the following steps: acquiring and analyzing a chip test thermal imaging image set to acquire a chip test thermal imaging thermal energy image set; processing the thermal imaging thermal energy image set for chip test and constructing a model; acquiring and extracting temperature test chip data to obtain temperature test chip structure data, and calculating the temperature test chip structure data to obtain predicted temperature data of the temperature test chip; converting the data of the temperature test chip to obtain a thermal imaging image of the temperature test chip; analyzing the thermal imaging image of the temperature test chip to obtain a first temperature of the test chip; analyzing the thermal imaging image of the temperature test chip to obtain a second temperature of the test chip; and calculating the first temperature of the test chip and the second temperature of the test chip to obtain the temperature of the test chip. The invention tests the chip temperature based on deep learning.

Description

Chip temperature testing method and system

Technical Field

The present invention relates to the field of data mining technologies, and in particular, to a method and a system for testing chip temperature.

Background

The traditional chip temperature testing method is mostly based on a sensor and a physical model, uses an external sensor to measure the chip surface temperature, and estimates the temperature distribution inside the chip through the physical model. However, these methods have problems of measurement bias, complicated calibration, time delay, and the like, which limit the accuracy of temperature test.

Disclosure of Invention

Accordingly, the present invention is directed to a chip temperature testing method for solving at least one of the above-mentioned problems.

In order to achieve the above object, a chip temperature testing method includes the following steps:

step S1: acquiring a chip test thermal imaging image set by a thermal imaging technology, and performing thermal energy analysis on the chip thermal imaging image set so as to acquire the chip test thermal imaging thermal energy image set;

step S2: performing image enhancement processing on the chip test thermal imaging thermal energy image set so as to obtain an enhanced chip test thermal imaging thermal energy image set; constructing a chip thermal energy detection model for the enhanced chip test thermal imaging thermal energy image set based on the convolutional neural network;

step S3: acquiring temperature test chip data, extracting structural data of the temperature test chip data to obtain temperature test chip structural data, and calculating predicted temperature according to the temperature test chip structural data to obtain predicted temperature data of the temperature test chip;

Step S4: acquiring a thermal imaging image of the temperature test chip by using a thermal imaging technology; performing first temperature analysis on the thermal imaging image of the temperature test chip by using the chip thermal energy detection model, so as to obtain a first temperature of the test chip;

step S5: performing a second temperature analysis on the thermal imaging image of the temperature test chip based on the predicted temperature data of the temperature test chip, thereby obtaining a second temperature of the test chip;

step S6: and carrying out accurate temperature calculation on the first temperature of the test chip and the second temperature of the test chip, thereby obtaining the temperature of the test chip.

According to the invention, a chip test thermal imaging image set is obtained through a thermal imaging technology, and thermal energy analysis is carried out on the chip thermal imaging image set, so that a chip test thermal imaging thermal energy image set is obtained; a thermal imaging image set of the chip is acquired, providing information for testing the temperature distribution of the chip surface. The thermal energy characteristics of the test chip can be known through thermal energy analysis, and a basis is provided for subsequent temperature calculation and analysis. Performing image enhancement processing on the chip test thermal imaging thermal energy image set so as to obtain an enhanced chip test thermal imaging thermal energy image set; constructing a chip thermal energy detection model for the enhanced chip test thermal imaging thermal energy image set based on the convolutional neural network; the image enhancement processing can improve the image quality, reduce noise and interference in the image, and enable the subsequent temperature analysis to be more accurate. The thermal energy detection model constructed by the convolutional neural network can automatically learn and extract the thermal energy characteristics in the image, so that the thermal energy detection and analysis of the chip are realized. Acquiring temperature test chip data through a chip management cloud platform, extracting structural data of the temperature test chip data, thus acquiring temperature test chip structural data, and carrying out predicted temperature calculation according to the temperature test chip structural data, thus acquiring predicted temperature data of the temperature test chip; the acquisition of the structural data of the temperature test chip can provide related information such as the geometric shape, material parameters and the like of the chip, and provides a basis for subsequent temperature calculation and analysis. The temperature distribution inside the chip can be estimated by carrying out expected temperature calculation according to the structural data of the temperature test chip, and the reference data of the temperature test is provided. Acquiring a thermal imaging image of the temperature test chip by using a thermal imaging technology; performing first temperature analysis on the thermal imaging image of the temperature test chip by using the chip thermal energy detection model, so as to obtain a first temperature of the test chip; the temperature distribution condition of the chip can be intuitively presented by converting the chip data into a thermal imaging image by utilizing a thermal imaging technology. And analyzing the thermal imaging image by using the chip thermal energy detection model to extract thermal energy characteristics in the image and obtain a first temperature value of the test chip. Performing a second temperature analysis on the thermal imaging image of the temperature test chip based on the predicted temperature data of the temperature test chip, thereby obtaining a second temperature of the test chip; analysis of the thermographic image based on the predicted temperature data may further accurately estimate the temperature of the chip. And carrying out accurate temperature calculation on the first temperature of the test chip and the second temperature of the test chip, thereby obtaining the temperature of the test chip. By performing accurate temperature calculations on the first temperature and the second temperature, a more accurate test chip temperature may be obtained. The actual temperature value of the test chip can be obtained through accurate temperature calculation, and accurate measurement of the chip temperature is provided. This is important for chip reliability, performance evaluation, and thermal management.

Optionally, step S1 specifically includes:

step S11: acquiring a chip test thermal imaging image set by a thermal imaging technology;

step S12: image segmentation is carried out on the chip test thermal imaging image set by a region image segmentation method, so that the chip test thermal imaging region image set is obtained;

step S13: carrying out statistical analysis on the chip test thermal imaging region image set so as to obtain a high-frequency thermal energy region image set and a low-frequency thermal energy region image set;

step S14: carrying out potential thermal energy analysis on the chip test thermal imaging region image set so as to obtain a potential thermal energy region image set;

step S15: and carrying out time sequence combination on the potential thermal energy region image set, the high-frequency thermal energy region image set and the low-frequency thermal energy region image set, thereby obtaining the chip test thermal imaging thermal energy image set.

The invention obtains a chip test thermal imaging image set through a thermal imaging technology; the thermal imaging technology is a non-contact measurement method, and can acquire temperature information without disturbing the chip surface. This makes thermal imaging technology an ideal choice for assessing thermal characteristics of chips without the need for physical contacts or sensors. The thermographic image set provides an overall visual representation of the chip surface temperature. The thermal distribution condition and the hot spot position on the chip can be intuitively observed through the color coding or gray level image. Thermal imaging techniques are capable of capturing multidimensional temperature information of the chip surface. By acquiring the thermal imaging image set, the temperature distribution condition of different areas of the chip can be known, and a data basis is provided for further analysis. The region image segmentation method can separate the thermal energy region in the chip thermal imaging image set from the background. These thermal energy regions typically represent important features, hot spots, or problem areas on the chip. By accurate region extraction, a target region image set related to chip thermal energy can be obtained. Region image segmentation may remove the effects of background or irrelevant regions, thereby reducing or eliminating noise data. This helps to improve the accuracy of analysis and result accuracy for the thermal energy region of the chip. Through region image segmentation, a target region in the chip test thermal imaging region image set can be distinguished from a background, so that thermal energy features focused by researchers can be displayed and presented more intuitively. The frequency distribution condition of different heat energy areas can be obtained by testing the thermal imaging area image set through the statistical analysis chip. This helps to understand the overall distribution characteristics of the chip thermal energy, including the high frequency thermal energy region and the low frequency thermal energy region. Statistical analysis can help identify areas of thermal energy where problems or anomalies may exist. The high frequency thermal energy region may represent hot spots or concentrated thermal energy concentrations on the chip, while the low frequency thermal energy region may reflect other thermal energy characteristics. By identifying these suspicious regions, further troubleshooting and improvement measures can be performed. The latent thermal energy analysis may help focus on specific areas or locations in the thermal energy distribution image. This helps to determine the hot spot areas or important thermal energy characteristics that may be present, so that the thermal energy distribution of the chip is better understood. By latent thermal energy analysis, abnormal regions that do not coincide with the normal thermal energy distribution pattern can be detected and identified. These abnormal areas may indicate problems with the chip such as temperature non-uniformity, heat dissipation failure, or other thermal anomalies. By time sequence combination, thermal energy images at different time points can be fused together to form a thermal energy image set of time sequence. The time sequence analysis can reveal the thermal energy change and evolution condition of the chip at different times, and data support is provided for subsequent modeling.

Optionally, the potential thermal energy analysis in step S14 is specifically:

carrying out potential thermal energy region identification on the chip test thermal imaging region image set through a chip potential thermal energy region identification algorithm, so as to obtain a potential thermal energy region image set;

the functional formula of the chip potential heat energy region identification algorithm is specifically as follows:

wherein E is the energy value of the potential heat energy area of the chip, x is the horizontal axis coordinate of the specific pixel point, y is the vertical axis coordinate of the specific pixel point, n is the total number of the pixel points in the image set, i is the serial number of the pixel points in the image set, and x _i The horizontal axis coordinate, y, of the ith pixel point in the thermal imaging area image set for chip testing _i The vertical axis coordinates of the ith pixel point in the thermal imaging area image set are tested for the chip.

The invention constructs a functional formula of a chip potential thermal energy region identification algorithm, which is used for carrying out potential thermal energy region identification on a chip test thermal imaging region image set. The formula fully considers the horizontal axis coordinate x of a specific pixel point affecting the energy value E of the chip potential thermal energy region, the vertical axis coordinate y of the specific pixel point, the total number n of the pixel points in the image set, the pixel point serial number i in the image set and the horizontal axis coordinate x of the ith pixel point in the image set of the chip test thermal imaging region _i Vertical axis coordinate y of ith pixel point in chip test thermal imaging area image set _i A functional relationship is formed:

wherein the method comprises the steps ofMeaning that all pixels are used for averaging. />And->Respectively at the position x _i And y _i A second derivative value at the location. The second derivative is used to measure the curvature or abrupt change in the location. These derivative values reflect the rate of temperature change in the thermal image. sin (x) _i ) ² And cos (y) _i ) ² Respectively calculate the positions x _i And y _i Square values of sine and cosine functions at the point to take into account the effect of angle. />Calculating position x _i And y _i Square root of sum of squares of sine and cosine functions. This part of the calculation results in the length of the coordinate position. />Calculating the position x _i And y _i The sum of the absolute values of the second derivative. This part of the calculation is used to measure the curvature of the location. Combining the calculated results, and transforming by using natural logarithmic function>The intensity of the thermal energy zone at a particular location is shown. />And summing the intensity of the thermal energy area of each pixel point in the image set and dividing the intensity by the total number of the pixel points to obtain an average value. The summing part is used for integrating all imagesAnd obtaining the energy value of the element point to obtain the energy value of the potential heat energy area of the whole chip. The second derivative term and the curvature term in this formula take into account the change in spatial position and the degree of curvature of the curve. Thus, the change and the characteristics of the thermal energy area can be more accurately captured, and a finer thermal energy analysis result is provided. The sine and cosine function terms in the formula take into account the angle information of the coordinate position. This is particularly useful when analyzing thermal energy regions with periodic features, such as thermal energy flow patterns at the chip surface. The formula sums and averages all the pixels in the image set, and integrates the thermal energy area intensity of all the pixels. This may provide a more comprehensive thermal energy estimate taking into account the energy distribution throughout the region. The logarithmic function transformation in the formula takes the intensity of the thermal energy region into account in combination with the length and curvature of the location. This allows the energy estimate to be compared to other factors to evaluate the relative intensity of the thermal energy region to find a potential thermal energy region.

Optionally, step S2 specifically includes:

step S21: performing detail enhancement processing on the chip test thermal imaging thermal energy image set by a high-pass filtering method, so as to obtain a filter chip test thermal imaging thermal energy image set;

step S22: the visual effect of the thermal imaging thermal energy image set of the filter chip test is increased by the self-adaptive contrast enhancement technology, so that the thermal imaging thermal energy image set of the enhancement chip test is obtained;

and S23, constructing a chip thermal energy detection model for the thermal imaging thermal energy image set for the enhanced chip test based on a convolutional neural network algorithm.

The high-pass filtering method of the invention carries out detail enhancement processing on the thermal imaging thermal energy image set of the chip test, can extract high-frequency information in the image, and emphasizes details and edges of the image. This helps to highlight the thermal energy variation area on the chip and eliminates low frequency noise and background in the image. By the detail enhancement processing, a clearer and clearer image can be provided, and more accurate input is provided for a subsequent thermal energy detection model. The self-adaptive contrast enhancement technology can adjust the contrast of the image, so that the thermal energy change is more obvious, and the visual effect of thermal energy detection is improved. By increasing the local contrast, hot spots and abnormal areas on the chip can be displayed more clearly, so that the subsequent thermal energy detection model can identify and detect the areas better. . The construction of the chip thermal energy detection model based on the convolutional neural network algorithm is beneficial to realizing automatic thermal energy identification and anomaly detection. The convolutional neural network can effectively extract key information in the chip thermal energy image by learning image features and modes, and classifies and detects the key information. Therefore, hot spots, abnormal areas and other important features can be quickly and accurately identified, and powerful support is provided for chip testing and fault diagnosis.

Optionally, step S23 specifically includes:

performing time sequence extraction on the thermal imaging thermal energy image set of the enhanced chip test according to a preset time division ratio, so as to obtain convolution time sequence data;

carrying out local feature extraction on the thermal imaging thermal energy image set for testing the enhanced chip by using a convolution operation technology, so as to obtain convolution structure data;

constructing a space-time 3D convolutional neural network according to the convolutional time sequence data and the convolutional structure data;

and performing model training on the time-space 3D convolutional neural network by using the thermal imaging thermal energy image set tested by the enhanced chip, thereby obtaining a chip thermal energy detection model.

According to the invention, the time sequence extraction is carried out on the thermal imaging thermal energy image set for testing the enhanced chip according to the preset time division ratio, so that the image sequences can be organized according to the time sequence to form the convolution time sequence data. This helps to capture dynamic information and time dependencies in the image sequence to provide more comprehensive input data. And (3) carrying out local feature extraction on the thermal imaging thermal energy image set for testing the enhanced chip by using a convolution operation technology, and capturing local mode and structure information in the image by sliding a convolution kernel on the image and carrying out feature extraction. This helps to extract textures, edges and other important local features in the image in order to better represent the image content. And constructing a space-time 3D convolutional neural network according to the convolutional time sequence data and the convolutional structure data. The space-time 3D convolutional neural network combines the information of time and space dimensions, has stronger modeling capability, and can better capture the space-time relationship and dynamic characteristics in the image sequence. The network structure can process the time sequence change of the image sequence, so that the chip heat energy detection can be more effectively carried out. And performing model training on the time-space 3D convolutional neural network by using the thermal imaging thermal energy image set tested by the enhancement chip. Through training, the network can learn the characteristics and modes in the chip thermal energy image, and adjust network parameters through an optimization algorithm so as to achieve a more accurate thermal energy detection target. The purpose of model training is to enable the network to accurately identify and locate hot spots, abnormal areas, or other features of interest from the input image.

Optionally, step S3 specifically includes:

acquiring temperature test chip data, and extracting structural data of the temperature test chip data so as to acquire the structural data of the temperature test chip;

describing the temperature distribution situation of the temperature test chip structure data by a heat conduction technology, so as to obtain the chip temperature distribution situation;

constructing a chip heat conduction model according to the temperature test chip structure data and the chip temperature distribution condition;

and calculating the expected temperature of the temperature test chip structure data through the chip heat conduction model, so as to obtain the expected temperature data of the temperature test chip.

According to the invention, the temperature test chip data is obtained through the chip management cloud platform. Structural data, such as chip geometry, material properties, thermal conductivity, etc., are extracted from the temperature test chip data. This can transform the physical structure of the temperature test chip into a data form that can be analyzed and modeled later. Based on the theory of thermal conduction, the propagation and distribution of temperature in the chip structure can be described using thermal conduction techniques. The heat conduction equation in the heat conduction technology considers factors such as the geometric shape of the chip, the thermal conductivity of the material, the boundary condition and the like, and can obtain an analytical solution or a numerical solution of the temperature distribution by an analytical method or a numerical simulation method. The temperature profile description provides an understanding of the thermal behavior and thermal coupling phenomena of the chip. According to the structural data of the temperature test chip and the described temperature distribution condition, a heat conduction model of the chip can be constructed. The model can be used to simulate and calculate the internal temperature of the chip over time and the external conditions. Constructing an accurate heat conduction model is helpful for researching the heat coupling effect of the chip, optimizing the heat dissipation design of the chip and the like. Through the chip heat conduction model, the expected temperature calculation can be performed on the structural data of the temperature test chip. Thus, the expected temperature data of the temperature test chip under different working loads and environment conditions can be obtained. The acquisition of the expected temperature data can be used for evaluating the thermal performance of the chip, performing temperature management, heat dissipation design and the like. Meanwhile, the accuracy of the chip heat conduction model can be verified and improved by comparing with actual measurement data.

Optionally, step S4 specifically includes:

acquiring a thermal imaging image of the temperature test chip by using a thermal imaging technology;

carrying out thermal region separation on the thermal imaging image of the temperature test chip so as to obtain a thermal region image of the temperature test chip;

and carrying out temperature prediction on the thermal area image of the temperature test chip by using the chip thermal energy detection model, so as to obtain a first temperature of the test chip.

The thermal imaging technology can acquire the temperature distribution information of the object by measuring the infrared radiation of the object surface and convert the temperature distribution information into a thermal imaging image. The thermal imaging of the temperature test chip can intuitively display the thermal distribution condition inside the chip, help determine the hot spot position and the temperature gradient, and provide global visual information. Thermal region separation is the process of distinguishing thermal regions (e.g., hot spots) in a thermal imaging image from the surrounding environment. The thermal region in the temperature test chip image can be separated from background noise or other low temperature regions by image processing and segmentation algorithms on the thermal imaging image. This helps to more accurately identify and locate the temperature anomaly region. Through the chip thermal energy detection model, each pixel point in the thermal area image can be associated with a corresponding temperature value. Therefore, the image information of the thermal area of the temperature test chip can be converted into a specific temperature value, and the quantification of the chip temperature is realized. The chip thermal energy detection model is obtained by training and learning a large amount of thermal imaging image data, and has higher prediction accuracy. And the temperature of the thermal area image of the temperature test chip is predicted through the model, so that a relatively accurate temperature estimation result can be obtained.

Optionally, step S5 specifically includes:

extracting brightness characteristics of the thermal imaging image of the temperature test chip so as to obtain the characteristics of the temperature test chip;

correlating the characteristics of the temperature test chip with the expected temperature data of the temperature test chip, thereby obtaining a characteristic-temperature characteristic matrix;

constructing a second temperature estimation model for the characteristic-temperature characteristic matrix through a decision tree algorithm;

and performing second temperature estimation on the temperature test chip characteristics by using a second temperature estimation model, so as to obtain a second temperature of the test chip.

According to the invention, the brightness characteristic extraction is carried out on the thermal imaging image of the temperature test chip, so that the light intensity information in the image can be captured. These brightness features may reflect the heat distribution of the thermal area of the chip, thereby providing preliminary information about temperature changes. And correlating the brightness characteristics of the temperature test chip with corresponding temperature test data to establish a characteristic-temperature characteristic matrix. This matrix maps the relationship between the luminance characteristics and the actual temperature, providing a data basis for subsequent temperature estimation. A second temperature estimation model may be constructed by processing and analyzing the feature-temperature feature matrix using a decision tree algorithm. The decision tree algorithm can divide according to different values of the features, so that a mapping relation between the features and the temperature is established. This model may be used to predict a second temperature for the temperature test chip feature. And estimating the second temperature of the temperature test chip feature by using the established second temperature estimation model. Thus, the prediction result of the second temperature can be directly obtained by inputting the characteristic data of the temperature test chip. From this estimation result, the test chip second temperature can be obtained. Compared with the traditional physical sensor for real-time temperature measurement, the time for acquiring temperature data can be greatly shortened by utilizing the second temperature estimation model for temperature estimation.

Optionally, step S6 specifically includes:

acquiring chip temperature test environment data;

and calculating the temperature test chip structure data, the chip temperature test environment data, the first temperature of the test chip and the second temperature of the test chip through an accurate chip temperature calculation formula, so as to obtain the temperature of the test chip.

The accurate chip temperature calculation formula specifically comprises the following steps:

wherein T is _xp The temperature of the chip is t, the time for testing the temperature of the chip is F, the surface area of the chip is A, the thermal conductivity of the chip is I, the cycle number is d, the thickness of the chip is D, R is the radius of the chip, C is the specific heat capacity of the chip material, B is the ratio of the surface area to the volume of the chip, alpha is the first temperature of the tested chip, beta is the second temperature of the tested chip, P is the heat dissipation power of the chip by the external environment, Q is the internal heat generation power of the chip, and k is the correlation coefficient of the temperature and the time of the chip.

The invention constructs an accurate chip temperature calculation formula for calculating the temperature test chip structure data, the chip temperature test environment data, the first temperature of the test chip and the second temperature of the test chip. The formula fully considers influencing the chip temperature T _xp The temperature test method comprises the steps of (1) testing the temperature of a chip, namely, testing the first temperature alpha of the chip, testing the second temperature beta of the chip, radiating power P of the external environment on the chip, internal heating power Q of the chip and correlation coefficient k of the temperature and time of the chip, wherein the functional relation is formed by the chip surface area F, the thermal conductivity A of the chip, the cycle number l, the thickness d of the chip, the radius R of the chip, the specific heat capacity C of the chip material, the specific heat capacity B of the surface area and the volume of the chip:

Wherein the method comprises the steps ofAn exponential function and a limit sign are used in part. k represents the correlation coefficient of the chip temperature and time, and t represents the time of the chip temperature test environment. The exponential function represents the temperature trend over time, and the limit sign represents the ratio of chip surface area to thermal conductivity for an infinite number of cycles. />A sinusoidal function is used in part. d represents the thickness of the chip and R represents the radius of the chip. The sine function represents the effect of the structural features of the chip on temperature. />Proportional and logarithmic functions are used in part. C represents the specific heat capacity of the chip material, B represents the ratio of the surface area to the volume of the chip, and beta and alpha represent the second temperature and the first temperature of the test chip. The ratio represents the adjustment of the heat capacity of the material to the temperature, and the logarithmic function represents the correlation between the parameters. />Part represents the ratio of the heat dissipation power of the environment to the chip to the heat generation power inside the chip. P represents the heat dissipation power of the external environment to the chip, and Q represents the internal heating power of the chip. The formula takes into account a number of factors, such as time, thermal conductivity, surface area, thickness, material properties, etc. By incorporating these factors into the calculation, the temperature profile of the chip can be more fully assessed. The exponential function in the formula represents the correlation of temperature and time, and can help predict the change trend of the chip temperature along with time. This is beneficial in assessing thermal characteristics of the chip, designing heat dissipation schemes, etc. The sine function in the formula represents the effect of the structural features of the chip on temperature. By taking into account the thickness and radius of the chip The effect of the thermal profile and the structural parameters of the chip on the temperature can be described more accurately. The proportional and logarithmic functions in the formula can adjust the correlation between the parameters to better match the actual situation. This is beneficial in optimizing chip design, accurately estimating temperature, etc.

According to the invention, the chip temperature test environment data is obtained through the chip management cloud platform. By performing accurate temperature calculations on the temperature test chip configuration data, the chip temperature test environment data, the test chip first temperature, and the test chip second temperature, a more accurate test chip temperature may be obtained.

Optionally, the present invention further provides a chip temperature testing system, including:

the thermal energy analysis module is used for acquiring a chip test thermal imaging image set through a thermal imaging technology and carrying out thermal energy analysis on the chip thermal imaging image set so as to acquire the chip test thermal imaging thermal energy image set;

the model building module is used for carrying out image enhancement processing on the chip test thermal imaging thermal energy image set so as to obtain an enhanced chip test thermal imaging thermal energy image set; constructing a chip thermal energy detection model for the enhanced chip test thermal imaging thermal energy image set based on the convolutional neural network;

The predicted temperature calculation module is used for acquiring the temperature test chip data, extracting structural data of the temperature test chip data so as to acquire the temperature test chip structural data, and calculating the predicted temperature according to the temperature test chip structural data so as to acquire the predicted temperature data of the temperature test chip;

the first temperature analysis module is used for acquiring a thermal imaging image of the temperature test chip by utilizing a thermal imaging technology; performing first temperature analysis on the thermal imaging image of the temperature test chip by using the chip thermal energy detection model, so as to obtain a first temperature of the test chip;

the second temperature analysis module is used for carrying out second temperature analysis on the thermal imaging image of the temperature test chip based on the predicted temperature data of the temperature test chip so as to obtain a second temperature of the test chip;

and the accurate temperature calculation module is used for carrying out accurate temperature calculation on the first temperature of the test chip and the second temperature of the test chip so as to obtain the temperature of the test chip.

The chip temperature test system can realize any chip temperature test method, is used for combining the operation and signal transmission media among the modules to complete the chip temperature test method, and the internal modules of the system are mutually cooperated to realize the temperature test of the chip.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of a non-limiting implementation, made with reference to the accompanying drawings in which:

FIG. 1 is a schematic flow chart of the chip temperature test method according to the present invention;

FIG. 2 is a detailed step flow chart of step S1 of the present invention;

FIG. 3 is a detailed step flow chart of step S2 of the present invention;

the achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.

Detailed Description

The following is a clear and complete description of the technical method of the present patent in conjunction with the accompanying drawings, and it is evident that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, are intended to fall within the scope of the present invention.

Furthermore, the drawings are merely schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. The functional entities may be implemented in software or in one or more hardware modules or integrated circuits or in different networks and/or processor methods and/or microcontroller methods.

It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

In order to achieve the above objective, referring to fig. 1 to 3, the present invention provides a chip temperature testing method, which includes the following steps:

in the embodiment, the thermal imager is aligned to the chip group, so that the proper distance between the imager and the chip is ensured. Pressing a measurement button or trigger records a thermal imaging image, thereby obtaining a chip test thermal imaging image set. And carrying out statistical analysis and potential thermal energy analysis on the chip thermal imaging image set so as to obtain the chip test thermal imaging thermal energy image set.

in the embodiment, the detail enhancement processing is performed on the chip test thermal imaging thermal energy image set by a high-pass filtering method, so that the filter chip test thermal imaging thermal energy image set is obtained; the visual effect of the thermal imaging thermal energy image set of the filter chip test is increased by the self-adaptive contrast enhancement technology, so that the thermal imaging thermal energy image set of the enhancement chip test is obtained; performing time sequence extraction on the thermal imaging thermal energy image set of the enhanced chip test according to a preset time division ratio of 1 second, so as to obtain convolution time sequence data; carrying out local feature extraction on the thermal imaging thermal energy image set for testing the enhanced chip by using a convolution operation technology, so as to obtain convolution structure data; constructing a space-time 3D convolutional neural network according to the convolutional time sequence data and the convolutional structure data; and performing model training on the time-space 3D convolutional neural network by using the thermal imaging thermal energy image set tested by the enhanced chip, thereby obtaining a chip thermal energy detection model.

in this embodiment, temperature test chip data is obtained through a chip management cloud platform, and structural data extraction is performed on the temperature test chip data, so as to obtain temperature test chip structural data. Describing the temperature distribution situation of the temperature test chip structure data by a heat conduction technology, so as to obtain the chip temperature distribution situation; constructing a chip heat conduction model according to the temperature test chip structure data and the chip temperature distribution condition; and calculating the expected temperature of the temperature test chip structure data through the chip heat conduction model, so as to obtain the expected temperature data of the temperature test chip.

in the embodiment, a thermal imaging technology is utilized to obtain a thermal imaging image of a temperature test chip; carrying out thermal region separation on the thermal imaging image of the temperature test chip so as to obtain a thermal region image of the temperature test chip; and carrying out temperature prediction on the thermal area image of the temperature test chip by using the chip thermal energy detection model, so as to obtain a first temperature of the test chip.

in the embodiment, brightness characteristic extraction is carried out on the thermal imaging image of the temperature test chip, so that the characteristics of the temperature test chip are obtained; correlating the characteristics of the temperature test chip with the expected temperature data of the temperature test chip, thereby obtaining a characteristic-temperature characteristic matrix; constructing a second temperature estimation model for the characteristic-temperature characteristic matrix through a decision tree algorithm; and performing second temperature estimation on the temperature test chip characteristics by using a second temperature estimation model, so as to obtain a second temperature of the test chip.

In the embodiment, chip temperature test environment data are acquired through a chip management cloud platform; and calculating the temperature test chip structure data, the chip temperature test environment data, the first temperature of the test chip and the second temperature of the test chip through an accurate chip temperature calculation formula, so as to obtain the temperature of the test chip.

Optionally, step S1 specifically includes:

in the embodiment, the thermal imager is aligned to the chip group, so that the proper distance between the imager and the chip is ensured. Pressing a measurement button or trigger records a thermal imaging image, thereby obtaining a chip test thermal imaging image set.

in this embodiment, the appropriate cutting threshold is set according to the gray scale values of different areas in the image in the chip test thermal imaging image set. Thresholding can convert an image into a binary image, separating objects from the background. And selecting a watershed algorithm based on the cutting threshold value to cut the images in the chip test thermal imaging image set, so as to obtain the chip test thermal imaging region image set.

in this embodiment, statistical analysis is performed on the thermal imaging region image set for chip test by using a frequency analysis method, so as to obtain a high-frequency thermal energy region image set and a low-frequency thermal energy region image set.

in this embodiment, the chip test thermal imaging area image set is subjected to potential thermal energy area identification by using a chip potential thermal energy area identification algorithm, so as to obtain a potential thermal energy area image set.

In this embodiment, the latent thermal energy region image set, the high-frequency thermal energy region image set, and the low-frequency thermal energy region image set are combined according to a time sequence, so as to obtain the thermal imaging thermal energy image set for chip testing.

Optionally, the potential thermal energy analysis in step S14 is specifically:

in this embodiment, a chip potential thermal energy region recognition algorithm is constructed by testing relevant parameters of pixels, coordinate information and relevant parameters of a decision tree of a thermal imaging region image set through a chip. And carrying out potential thermal energy region identification on the chip test thermal imaging region image set through a chip potential thermal energy region identification algorithm, so as to obtain the potential thermal energy region image set.

wherein the method comprises the steps ofMeaning that all pixels are used for averaging. />And->Respectively at the position x _i And y _i A second derivative value at the location. The second derivative is used to measure the curvature or abrupt change in the location. These derivative values reflect the rate of temperature change in the thermal image. sin (x) _i ) ² And cos (y) _i ) ² Respectively calculate the positions x _i And y _i Square values of sine and cosine functions at the point to take into account the effect of angle. />Calculating position x _i And y _i Square root of sum of squares of sine and cosine functions. This part of the calculation results in the length of the coordinate position. />Calculating the position x _i And y _i The sum of the absolute values of the second derivative. This part of the calculation is used to measure the curvature of the location. Combining the calculated results, and transforming by using natural logarithmic function>The intensity of the thermal energy zone at a particular location is shown. />And summing the intensity of the thermal energy area of each pixel point in the image set and dividing the intensity by the total number of the pixel points to obtain an average value. The summation partThe method is used for integrating the energy values of all the pixel points to obtain the energy value of the potential heat energy area of the whole chip. The second derivative term and the curvature term in this formula take into account the change in spatial position and the degree of curvature of the curve. Thus, the change and the characteristics of the thermal energy area can be more accurately captured, and a finer thermal energy analysis result is provided. The sine and cosine function terms in the formula take into account the angle information of the coordinate position. This is particularly useful when analyzing thermal energy regions with periodic features, such as thermal energy flow patterns at the chip surface. The formula sums and averages all the pixels in the image set, and integrates the thermal energy area intensity of all the pixels. This may provide a more comprehensive thermal energy estimate taking into account the energy distribution throughout the region. The logarithmic function transformation in the formula takes the intensity of the thermal energy region into account in combination with the length and curvature of the location. This allows the energy estimate to be compared to other factors to evaluate the relative intensity of the thermal energy region to find a potential thermal energy region.

Optionally, step S2 specifically includes:

in the embodiment, the Laplace filtering method in the high-pass filtering method is used for highlighting the edges and details of the image for the chip test thermal imaging thermal energy image set, so that the filter chip test thermal imaging thermal energy image set is obtained.

in the embodiment, the self-adaptive contrast enhancement processing is performed on the thermal imaging thermal image set tested by the filter chip, and the brightness and the contrast in the image are adjusted to make the details of the image clearer, so that the thermal imaging thermal image set tested by the enhancement chip is obtained.

In the embodiment, time sequence extraction is performed on the thermal imaging thermal energy image set for testing the enhanced chip according to a preset time division ratio of 1 second, so that convolution time sequence data are obtained; carrying out local feature extraction on the thermal imaging thermal energy image set for testing the enhanced chip by using a convolution operation technology, so as to obtain convolution structure data; constructing a space-time 3D convolutional neural network according to the convolutional time sequence data and the convolutional structure data; and performing model training on the time-space 3D convolutional neural network by using the thermal imaging thermal energy image set tested by the enhanced chip, thereby obtaining a chip thermal energy detection model.

Optionally, step S23 specifically includes:

in this embodiment, the time sequence extraction is performed on the thermal imaging thermal energy image set for testing the enhanced chip according to a preset time division ratio of 1 second. The continuous image sequence is divided into a plurality of time periods according to a time division ratio. And taking the key frame image in each time period as input data to form convolution time sequence data.

in this embodiment, a convolution operation technique is used to extract local features of the thermal imaging thermal image set for enhanced chip test, so as to obtain convolution structure data, where the convolution operation can extract features at different positions on the image through a sliding window.

in the embodiment, convolution time sequence data and convolution structure data are used as input to construct a space-time 3D convolution neural network. Such a network can process both timing and spatial information, and is suitable for processing data having a time dimension.

In this embodiment, the thermal imaging thermal energy image set is tested by using the enhanced chip and used as training data, and is used as input of the space-time 3D convolutional neural network, and a corresponding label is set for thermal energy detection. The time space 3D convolutional neural network is trained by a back propagation algorithm and a gradient descent optimization method, and the aim is to enable the network to accurately predict the position and the intensity of the chip heat energy. And setting a proper loss function such as a mean square error or a cross entropy loss function, and optimizing network parameters so as to obtain a chip heat energy detection model.

Optionally, step S3 specifically includes:

in this embodiment, temperature test chip data is obtained through a chip management cloud platform. And extracting structural data related to the temperature according to the physical structure and layout of the chip. These structural data may include chip geometry, material information, heat spreader configuration, etc., and collate and organize the structural data to form structural data for the temperature test chip.

in this embodiment, according to the heat conduction theory and the numerical simulation method, a heat conduction equation is established according to the structural data of the temperature test chip. And then, carrying out temperature distribution description on the temperature test chip structure data by using a heat conduction equation, thereby obtaining the chip temperature distribution.

in the embodiment, the chip heat conduction model is constructed by taking the temperature test chip structure data and the chip temperature distribution condition as input and taking the material property of the chip, the thermal resistance of the radiator and other heat sources, boundary conditions and other factors into consideration.

In this embodiment, the structural data of the temperature test chip is input into the constructed chip heat conduction model. And (3) operating a chip heat conduction model, calculating the expected temperature of the temperature test chip by using an equation and parameters in the model, and obtaining expected temperature data of the temperature test chip according to a model calculation result.

Optionally, step S4 specifically includes:

in this embodiment, a thermal imager or a thermal infrared imager is used to scan the temperature test chip to obtain an infrared radiation image. The thermal imaging image of the temperature test chip is extracted by using image processing software.

in the embodiment, the image segmentation algorithm is utilized to carry out thermal region separation on the thermal imaging image of the temperature test chip, so that the thermal region image of the temperature test chip is obtained.

In this embodiment, a thermal area image of a temperature test chip is input into a chip thermal energy detection model, and the model can predict a temperature value of each pixel point in the thermal area, so as to obtain a first temperature of the test chip.

Optionally, step S5 specifically includes:

in this embodiment, the image processing technology is used to extract the brightness features of the thermal imaging image of the temperature test chip, where the brightness features may include statistical information of pixel values, such as mean, variance, and the like, or may be higher-level features, such as texture features, shape features, and the like.

in this embodiment, the feature-temperature feature matrix is obtained by creating a feature-temperature feature matrix, where each row of the feature matrix corresponds to a sample, and includes features of the temperature test chip and corresponding temperature values.

in this embodiment, a feature-temperature feature matrix is used as input data, where a feature is a feature for predicting a temperature, and a temperature feature is a target variable. And learning the relation between the characteristics and the temperature by utilizing a decision tree algorithm, and constructing a model capable of predicting the temperature.

In this embodiment, the characteristics of the temperature test chip are used as input, and the constructed second temperature estimation model is used to perform temperature prediction, so as to obtain the second temperature of the test chip.

Optionally, step S6 specifically includes:

acquiring chip temperature test environment data;

in this embodiment, the chip temperature test environment data is obtained through the chip management cloud platform.

wherein the method comprises the steps ofAn exponential function and a limit sign are used in part. k represents the correlation coefficient of the chip temperature and time, and t represents the time of the chip temperature test environment. The exponential function represents the temperature trend over time, and the limit sign represents the ratio of chip surface area to thermal conductivity for an infinite number of cycles. />A sinusoidal function is used in part. d represents the thickness of the chip and R represents the radius of the chip. Sinusoidal functionIndicating the effect of the structural features of the chip on temperature. />Proportional and logarithmic functions are used in part. C represents the specific heat capacity of the chip material, B represents the ratio of the surface area to the volume of the chip, and beta and alpha represent the second temperature and the first temperature of the test chip. The ratio represents the adjustment of the heat capacity of the material to the temperature, and the logarithmic function represents the correlation between the parameters. / >Part represents the ratio of the heat dissipation power of the environment to the chip to the heat generation power inside the chip. P represents the heat dissipation power of the external environment to the chip, and Q represents the internal heating power of the chip. The formula takes into account a number of factors, such as time, thermal conductivity, surface area, thickness, material properties, etc. By incorporating these factors into the calculation, the temperature profile of the chip can be more fully assessed. The exponential function in the formula represents the correlation of temperature and time, and can help predict the change trend of the chip temperature along with time. This is beneficial in assessing thermal characteristics of the chip, designing heat dissipation schemes, etc. The sine function in the formula represents the effect of the structural features of the chip on temperature. By taking into account the thickness and radius of the chip, the thermal profile of the chip and the effect of the structural parameters on temperature can be more accurately described. The proportional and logarithmic functions in the formula can adjust the correlation between the parameters to better match the actual situation. This is beneficial in optimizing chip design, accurately estimating temperature, etc.

The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. The chip temperature testing method is characterized by comprising the following steps of:

2. The method according to claim 1, wherein step S1 is specifically:

3. The method according to claim 2, characterized in that the potential thermal energy analysis in step S14 is in particular:

4. The method according to claim 1, wherein step S2 is specifically:

5. The method according to claim 4, wherein step S23 is specifically:

6. The method according to claim 1, wherein step S3 is specifically:

7. The method according to claim 1, wherein step S4 is specifically:

8. The method according to claim 1, wherein step S5 is specifically:

9. The method according to claim 1, wherein step S6 is specifically:

acquiring chip temperature test environment data;

10. A chip temperature testing system for performing a chip temperature testing method according to claim 1, the chip temperature testing system comprising: