CN117119794A

CN117119794A - One-time programmable memory, control method thereof, memory system and electronic equipment

Info

Publication number: CN117119794A
Application number: CN202210510711.8A
Authority: CN
Inventors: 赵思宇; 徐亮; 卜思童; 许俊豪; 方亦陈; 范人士
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-05-11
Filing date: 2022-05-11
Publication date: 2023-11-24
Also published as: WO2023216789A1

Abstract

The application provides a one-time programming memory, a control method thereof, a memory system and electronic equipment, relates to the technical field of semiconductors, and aims to solve the problems that the one-time programming memory is large in occupied area, small in number of memory cells in unit size and low in memory capacity. The one-time programmable memory includes a substrate, at least one memory cell. A memory cell is located on the substrate. The memory cell includes a transistor and at least one capacitor sequentially arranged in a first direction; the first direction is perpendicular to the substrate; wherein the transistor comprises a gate, a first pole and a second pole, the first pole being remote from the substrate relative to the second pole; the capacitor includes a first electrode and a second electrode, and a dielectric layer between the first electrode and the second electrode; the first electrode is connected to a first pole of the transistor. The one-time programmable memory is applied to the electronic equipment and used for storing data.

Description

One-time programmable memory, control method thereof, memory system and electronic equipment

Technical Field

The present application relates to the field of semiconductor technologies, and in particular, to a one-time programmable memory, a control method thereof, a memory system, and an electronic device.

Background

The one-time programmable memory (one time programmable memory, OTP memory) has the characteristics of non-volatility, only allowing programming once, once programmed, the data is permanently valid, and can maintain the state stored before power failure for a long time without power supply, and is commonly used for storing reliable and repeatable read data, such as: a boot program, an encryption key, analog device configuration parameters, etc.

In order to meet the demands of miniaturization and high integration of semiconductor integrated circuits, various memories in terminals are required to have both small specific area and large memory capacity. However, in the one-time programmable memory, the memory cells are disposed on the substrate in a planar array integrated manner, and occupy a large area of the substrate. The size of the memory cells is not easily reduced due to the device property requirements in the memory cells, making it difficult to integrate more memory cells within a limited size for the size of the one-time programmable memory.

Disclosure of Invention

The embodiment of the application provides a one-time programming memory, a control method thereof, a memory system and electronic equipment, which are used for solving the problems that the one-time programming memory occupies a larger area, the number of memory cells in unit size is smaller, and the memory capacity is lower.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme:

in a first aspect, a one-time-program memory is provided, the one-time-program memory comprising a substrate and at least one memory cell, the memory cell being located on the substrate; the memory cell includes a transistor and at least one capacitor sequentially arranged in a first direction; the first direction is perpendicular to the substrate; wherein the transistor comprises a gate, a first pole and a second pole, the first pole being remote from the substrate relative to the second pole; the capacitor includes a first electrode and a second electrode, and a dielectric layer between the first electrode and the second electrode; the first electrode is connected to a first pole of the transistor.

Thus, the memory cell of the one-time-programmable memory comprises the transistor and the capacitor, the first pole of the transistor is far away from the substrate relative to the second pole, the transistor is arranged on the substrate in a three-dimensional structure, and the orthographic projection area of the transistor on the substrate can be smaller. The transistor and the capacitor are arranged on the substrate in sequence along the first direction, so that the orthographic projection of the whole memory cell on the substrate can be smaller. In this way, the area of the orthographic projection of the transistor on the substrate is smaller, and the orthographic projection of the memory cell as a whole on the substrate can be smaller, so that the number of memory cells provided in a one-time programming memory of a certain size can be made larger, or the size of a one-time programming memory having the same number of memory cells can be made smaller.

In some embodiments, the transistor further comprises a semiconductor layer located between the first pole and the second pole along the first direction; the grid electrode is arranged around the semiconductor layer; the transistor further includes a gate insulating layer between the semiconductor layer and the gate electrode. Therefore, the size of the orthographic projection of the semiconductor layer on the substrate is smaller, the high-density integration of the memory cells is more facilitated, and the size of the one-time programming memory is further reduced.

In some embodiments, the first electrode is a columnar structure extending along the first direction; the second electrode is disposed around the first electrode. The arrangement is that the area of the orthographic projection of the first electrode on the substrate is smaller, and the orthographic projection of the capacitor on the substrate is also smaller, so that more capacitors can be formed on the substrate when the area of the substrate is fixed, more storage units are further arranged, and the storage density of the one-time programming memory is improved. At the same time, the size of the substrate can be reduced when a certain number of memory cells are arranged, and the size of the one-time programming memory can be further reduced.

In some embodiments, the memory cell includes a plurality of the capacitors, the plurality of the capacitors being sequentially arranged along the first direction, and first electrodes of the plurality of the capacitors being sequentially connected. In this way, the size of the orthographic projection of the plurality of capacitors on the substrate is smaller than that of the plurality of capacitors arranged in the direction parallel to the substrate, thereby facilitating realization of high-density integration of the memory cell and further reducing the size of the one-time programming memory.

In some embodiments, the transistor and the plurality of capacitors are each fabricated using a subsequent process.

In some embodiments, the material of the dielectric layer comprises a ferroelectric material. When the material of the dielectric layer is comprised of a ferroelectric material, the capacitor is more prone to breakdown during the programming phase of the memory cell, thereby storing the corresponding information.

In some embodiments, the one-time programming memory further includes a word line, a bit line, and at least one second electrode layer; a word line extending in a second direction, the word line being connected to the gate; a bit line extending in a third direction, the bit line being connected to a second pole of the transistor; the first electrode penetrates through the second electrode layer, and a portion of the second electrode layer surrounding the first electrode serves as a second electrode. Wherein the second direction intersects the third direction and is parallel to the substrate.

In some embodiments, the word line is integrally provided with a gate connected to the word line. Therefore, when the word line is formed, the grid electrodes of the transistors can be formed at the same time, so that the grid electrodes do not need to be formed independently in the preparation process of the one-time programming memory, the preparation process of the one-time programming memory is simplified, and the cost of the one-time programming memory is reduced.

In some embodiments, the one-time-programmable memory includes a plurality of memory cells; the memory cells are arranged in a plurality of rows along the second direction and a plurality of columns along the third direction; each layer of second electrode layer is connected with the second electrodes of the multi-row and multi-column capacitors of the same layer; the one-time programming memory further includes a word line layer and a bit line layer: the word line layer includes a plurality of word lines; one word line is connected with the gates of the transistors of one row of memory cells; a bit line layer is located between the transistor and the substrate; the bit line layer includes a plurality of bit lines, one bit line being connected to a second pole of a transistor of a column of memory cells.

In some embodiments, during a write phase, a word line connected to a selected transistor is used to receive a first word line drive signal to turn on the selected transistor; the bit line connected with the selected transistor is used for receiving a first bit line control signal, the second electrode layer connected with the selected capacitor is used for receiving a first programming signal, and the voltage difference between the first bit line control signal and the first programming signal causes the selected capacitor to be broken down; the selected capacitor is one of the capacitors in the memory cell that is electrically connected to the selected transistor.

In some embodiments, during a precharge phase, the word line is configured to receive a first word line drive signal to turn on the transistor; the bit line is used for receiving a second bit line control signal, the second electrode layer is used for receiving a second programming signal, and the second bit line control signal is equal to the second programming signal in voltage.

In some embodiments, during a read phase, a word line connected to a selected transistor is used to receive a first word line drive signal, turning on the selected transistor; the second electrode layer connected to the selected capacitor is for receiving a third programming signal, and the bit line connected to the selected transistor is for outputting a voltage of a first electrode of the selected capacitor, the voltage of the first electrode being indicative of information stored by the selected capacitor.

In some embodiments, during a standby phase, the word line is configured to receive a second word line drive signal, turning off the transistor; the bit line is used for receiving a second bit line control signal, the second electrode layer is used for receiving a second programming signal, and the second bit line control signal is equal to the second programming signal in voltage.

In some embodiments, during the write phase and the read phase, the other word lines are used to receive a second word line drive signal to turn off the unselected transistors; the other bit lines are used for receiving second bit line control signals, and the other second electrode layers are used for receiving second programming signals; the second bit line control signal is equal to the voltage of the second programming signal; the other word lines are word lines of the plurality of word lines except the word line connected with the selected transistor, and the other bit lines are bit lines of the plurality of bit lines except the bit line connected with the selected transistor; the other second electrode layers are ones of the plurality of second electrode layers except for the second electrode layer connected to the selected capacitor.

In a second aspect, there is provided a one-time programmable memory comprising: a word line, a bit line, at least one second electrode layer, and at least one memory cell. Each memory cell includes a transistor and at least one capacitor; one capacitor in each memory cell corresponds to one second electrode layer; the gate of the transistor is connected with the word line, the first electrode of the transistor is connected with the first electrode of the capacitor, the second electrode of the transistor is connected with the bit line, and the second electrode of the capacitor is connected with the second electrode layer.

In a third aspect, a control method of a one-time programmable memory is provided, the one-time programmable memory includes at least one memory cell, a word line, a bit line, and at least one second electrode layer; the memory cell comprises a transistor and at least one capacitor, wherein the grid electrode of the transistor is connected with the word line, the first electrode of the transistor is connected with the first electrode of the capacitor, the second electrode of the transistor is connected with the bit line, and the second electrode of the capacitor is connected with the second electrode layer; the control method comprises the following steps: transmitting a first word line driving signal to a word line connected to a selected transistor to turn on the selected transistor in a writing stage; transmitting a first bit line control signal to a bit line connected to the selected transistor and transmitting a first program signal to a second electrode layer connected to the selected capacitor to breakdown the selected capacitor; the selected capacitor is one of the capacitors in the memory that is electrically connected to the selected transistor.

In some embodiments, prior to the writing phase, the control method further comprises: transmitting a first word line driving signal to the word line to turn on the transistor in a precharge phase; and transmitting a second bit line control signal to the bit line, and outputting a second programming signal to the second electrode layer, wherein the second bit line control signal is equal to the second programming signal in voltage.

In some embodiments, the control method further comprises: transmitting a first word line driving signal to a word line connected to a selected transistor to turn on the selected transistor in a read stage; transmitting a third programming signal to the second electrode layer connected to the capacitor; detecting a voltage on a bit line connected to the selected transistor to read information stored by the selected capacitor; the selected capacitor is one of the capacitors in the memory that is electrically connected to the selected transistor.

In some embodiments, the detecting a voltage on a bit line connected to the selected transistor to read information stored by the selected capacitor includes reading first stored information when the voltage on the bit line connected to the selected transistor is detected as a voltage of a third programming signal; when the voltage on the bit line connected to the selected transistor is detected as zero voltage, the second stored information is read.

In some embodiments, the control method further comprises: transmitting a second word line driving signal to the word line to turn off the transistor in a standby period; and transmitting a second bit line control signal to the bit line, and outputting a second programming signal to the second electrode layer, wherein the second bit line control signal is equal to the second programming signal in voltage.

In some embodiments, the control method comprises: transmitting a second word line driving signal to the other word lines to turn off the unselected transistors in the writing phase and the reading phase; transmitting a second bit line control signal to the other bit lines; transmitting a second programming signal to the other second electrode layer; wherein the other word lines are word lines other than the word line connected to the selected transistor, and the other bit lines are bit lines other than the bit line connected to the selected transistor; the other second electrode layers are second electrode layers except for the second electrode layer connected to the selected capacitor.

In a fourth aspect, a memory system is provided that includes a three-dimensional dynamic random access memory and a one-time programming memory, the three-dimensional dynamic random access memory coupled to the one-time programming memory. The one-time programmable memory is the one-time programmable memory according to any one of the above embodiments.

In a fifth aspect, an electronic device is provided, the electronic device comprising a processor and a one-time programming memory; the processor is electrically connected with the one-time programming memory; the one-time programmable memory as in any one of the above embodiments.

The technical effects of any one of the design manners of the second aspect to the fifth aspect may be referred to the technical effects of the different design manners of the first aspect, and will not be repeated here.

Drawings

FIG. 1 is an equivalent circuit diagram of a one-time programmable memory according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a fuse structure according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a transistor according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a one-time programmable memory according to an embodiment of the present application;

FIG. 5 is an equivalent circuit diagram of another one-time programmable memory according to an embodiment of the present application;

FIG. 6 is a schematic diagram of another one-time programmable memory according to an embodiment of the present application;

FIG. 7 is a schematic cross-sectional view of the one-time programmable memory shown in FIG. 6 at A-A';

FIG. 8 is a schematic diagram of a configuration of a one-time programmable memory according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a configuration of a one-time programmable memory according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a configuration of a one-time programmable memory according to an embodiment of the present application;

FIG. 11 is a schematic cross-sectional view of the one-time programmable memory shown in FIG. 10 at B-B';

FIG. 12 is a schematic diagram of a configuration of a one-time programmable memory according to an embodiment of the present application;

FIG. 13 is an equivalent circuit diagram of the one-time programmable memory shown in FIG. 6;

FIG. 14 is an equivalent circuit diagram of the one-time programmable memory shown in FIG. 10;

FIG. 15 is a schematic process diagram of a chip according to an embodiment of the present application;

FIG. 16 is a block diagram of a storage system according to an embodiment of the present application;

fig. 17 is a block diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. Wherein, in the description of the present application, "/" means that the related objects are in a "or" relationship, unless otherwise specified, for example, a/B may mean a or B; the "and/or" in the present application is merely an association relationship describing the association object, and indicates that three relationships may exist, for example, a and/or B may indicate: there are three cases, a alone, a and B together, and B alone, wherein a, B may be singular or plural.

In the description of the present application, unless otherwise indicated, "a plurality" means two or more than two. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.

In order to clearly describe the technical solution of the embodiments of the present application, in the embodiments of the present application, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ.

In describing some embodiments, expressions of "coupled" and "connected" and their derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, the term "coupled" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also mean that two or more elements are not in direct contact with each other, but yet still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the disclosure herein.

In embodiments of the application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion that may be readily understood.

As shown in fig. 1 and 2, some embodiments of the present application provide a one-time-program memory 100, the one-time-program memory 100 including a substrate 101, and at least one memory cell 102 disposed on the substrate 101, the memory cell 102 including a fuse (eFuse) 11 and a transistor 12.

Referring to fig. 2, a fuse 11 is laid on a substrate 101, and the fuse 11 includes an anode 111 and a cathode 112. Wherein, illustratively, the area of the orthographic projection of anode 111 on substrate 101 is greater than the area of the orthographic projection of cathode 112 on substrate 101.

Illustratively, the fuse 11 further includes a connection 113 connecting between the anode 111 and the cathode 112. In a direction perpendicular to the anode 111 toward the cathode 112, the width h1 of the anode 111 is greater than the width h2 of the cathode 112, and the width h1 of the anode 111 is also greater than the width h3 of the connection portion 113.

At the junction of the anode 111 and the connection portion 113, the width of the fuse 11 is changed from h1 to h3, the cross-sectional area becomes smaller, and the resistance increases. In this way, the power consumption at the junction of the anode 111 and the connection portion 113 increases, and after a large current is passed for a while, the junction of the anode 111 and the connection portion 113 can be fused.

Illustratively, the material of the fuse 11 may include polysilicon.

As shown in fig. 3, transistor 12 includes a gate 121, a first pole 122, and a second pole 123. Wherein the first pole 122 and the second pole 123 may be obtained by doping the substrate 101. The gate electrode 121 may be positioned on the substrate 101, and the first and second electrodes 122 and 123 may be positioned at both sides of the gate electrode 121, respectively, in a direction parallel to the substrate 101. A gate insulating layer 124 may also be provided between the gate electrode 121 and the substrate 101.

Wherein the cathode 112 of the fuse 11 may be connected to the first pole 122 of the transistor 12.

In some examples, first pole 122 may be a drain and second pole 123 may be a source. In other examples, first pole 122 may be a source and second pole 123 may be a drain.

The one-time program memory 100 further includes a word line WL connected to the gate 121 of the transistor 12, a bit line BL connectable to the second pole 123 of the transistor 12, and a program line VL connected to the anode 111 of the fuse 11.

In the programming phase of the one-time programming memory 100, the word line WL may be used to receive a word line control signal for a preset time, so that the transistor 12 is turned on. The bit line BL may be used to receive a bit line control signal, and the program line VL may be used to receive a program signal, and a voltage difference between the program signal and the bit line control signal causes a large current to be generated in the fuse 11 with a low resistance value, so that the fuse 11 is blown within a preset time.

The specific value of the voltage of the word line control signal received by the word line WL is not limited in the present application, and the transistor 12 may be turned on. The voltage of the first control signal received by the word line WL may be a high voltage or a low voltage, for example.

The preset time for the word line WL to receive the first control signal is not particularly limited, as long as the fuse 11 can be ensured to be blown within the preset time. The preset time may be, for example, 1 microsecond.

The bit line control signal received by the bit line BL, the specific value of the voltage of the programming signal received by the programming line VL is not limited, as long as the fuse 11 can be blown. The voltage of the low level signal may be 0V, for example. The voltage of the programming signal may be 2.5V.

During a read phase of the one-time programming memory 100, the word line WL may be used to receive a word line control signal, causing the transistor 12 to turn on. The programming line VL may be used to receive a read signal and the bit line BL may be used to output a voltage on a second pole 123 of the transistor 12, the voltage on the second pole 123 being indicative of the stored information of the memory cell 102.

The specific value of the voltage of the read signal received by the program line PL is not limited in the present application, and the voltage of the read signal may be 2.0V, for example.

In the case where the voltage on the second pole 123 of the transistor 12 output from the bit line BL is the voltage of the read signal, the fuse 11 is not blown, and the read voltage signal is transmitted to the bit line BL through the fuse 11 and the transistor 12. In case the voltage on the second pole 123 of the transistor 12 output by the bit line BL is zero, the fuse 11 is blown.

In some examples, the stored information of memory cell 102 may be characterized as "1" when the voltage on second pole 123 is the voltage of the read signal, and the stored information of memory cell 102 may be characterized as "0" when the voltage on second pole 123 is zero.

It is understood that when the plurality of memory cells 102 are included in the one-time program memory 100, a plurality of word lines WL, a plurality of bit lines WL, and a plurality of program lines VL may be included in the one-time program memory 100.

When a portion of memory cells 102 in the one-time-program memory 100 is programmed, the portion of memory cells 102 may be referred to as selected memory cells, the transistors 12 in the selected memory cells may be referred to as selected transistors, and the fuses 11 in the selected memory cells may be referred to as selected fuses.

In the programming phase of the one-time programming memory 100, the word line WL connected to the selected transistor may receive the word line control signal, the bit line BL connected to the selected transistor may receive the bit line control signal, and the program line VL connected to the selected fuse may receive the program signal. In the read phase of the one-time program memory 100, a word line WL connected to a selected transistor may receive a word line control signal. The programming line VL connected to the selected fuse receives the read signal and the bit line BL connected to the selected transistor outputs the voltage on the second pole 123 of the selected transistor 12.

In the one-time programmable memory 100 provided in the above embodiment, the initial resistance (resistance value in the unprogrammed state) and the compiling yield of the fuse 11 are affected by the thickness of the fuse, and the location and compiling time (i.e. the preset time) of the fuse are also limited by the fuse shape. Therefore, in the case where the thickness of the fuse is constant, the shape and size of the fuse in the memory cell are not easily changed. In this way, the size of the memory cell is not easily reduced, so that the size of the one-time-programmable memory 100 is not easily further reduced. Meanwhile, the circuit structure of the sense amplifier connected with the memory cell is also laid on the substrate 101, which occupies most of the area of the substrate 101, but in order to ensure that the sense amplifier can bear a large current for a certain time, the circuit structure of the sense amplifier is not easy to be further reduced, so that the size of the one-time programming memory 100 cannot be further reduced.

As shown in fig. 4, in some embodiments of the present application, another one-time-programmable memory 200 is provided, and the one-time-programmable memory 200 may be an antifuse (anti-fuse) one-time-programmable memory, that is, the one-time-programmable memory 200 may include an antifuse structure therein. In contrast to the situation where the fuse is smaller in resistance in the initial state, the fuse is open after programming, and the resistance increases, the antifuse structure is larger in resistance in the initial state, and breaks down after programming, and the resistance decreases.

By way of example, the one-time-programmable memory 200 may include a substrate 201 and at least one memory cell 202 located on the substrate 201, the memory cell 202 including at least one transistor 21.

"memory cell 202 includes at least one transistor 21", either memory cell 202 includes one transistor 21 or memory cell 202 includes a plurality of transistors 21.

The transistor 21 may include a gate 211, a first pole 212, and a second pole 213. The first pole 212 and the second pole 213 may be obtained by doping the substrate 201. Wherein in some examples the first pole 212 may be a drain and the second pole 213 may be a source. In other examples, the first pole 212 may be a source and the second pole 213 may be a drain.

The gate electrode 211 may be positioned on the substrate 201, and the first and second electrodes 212 and 213 may be positioned at both sides of the gate electrode 211, respectively, in a direction parallel to the substrate 201. A gate insulating layer 214 may also be provided between the gate electrode 211 and the substrate 201. The gate insulating layer 214 may act as an antifuse structure.

Transistor 21 may also include a channel 215, and channel 215 may also be formed by doping substrate 201. A channel 215 is located between the first pole 212 and the second pole 213 in a direction parallel to the substrate 201. The gate 211 is located on the channel 215, and the gate insulating layer 214 is located between the channel 215 and the gate 211.

In some examples, transistor 21 may further include a lightly doped electrode 216, with lightly doped electrode 216 being located between first pole 212 and channel 215, and also being located between second pole 213 and channel 215. Transistor 21 may also include two lightly doped electrodes 216 between first pole 212 and channel 215, and between second pole 213 and channel 215, respectively. The orthographic projection of the lightly doped electrode 216 onto the substrate 201 partially overlaps with the orthographic projection of the gate insulating layer 214 onto the substrate 201.

Referring to fig. 5, the one-time program memory 200 may further include a bit line BL and a word line WL. The word line WL is connected to the gate 211 of the transistor 21, and the bit line BL may be connected to the first pole 212 of the transistor 21. The second pole 213 of the transistor 21 may be grounded.

In the programming phase of the one-time programming memory 200, the word line WL may be used to receive a first programming signal and the bit line BL may be used to receive a second programming signal, the voltage difference between the first programming signal and the second programming signal causing the gate insulating layer 214 of the transistor 21 to be broken down, shorting between the gate 211 and the second pole 213 of the transistor 21.

During a read phase of the one-time-program memory 200, the word line WL may be used to receive a read signal, and the bit line BL is used to output a current through the transistor 21, the current through the transistor 21 characterizing the memory state of the one-time-program memory 200.

When the current outputted from the bit line BL is a large current, the gate insulating layer 214 of the transistor 21 breaks down, the gate 211 and the first electrode 212 are shorted, and the resistance value of the transistor 21 is small. When the current output from the bit line BL is a small current, the gate insulating layer 214 of the transistor 21 is not broken down, and the resistance value of the transistor 21 is large.

When the current output from the bit line BL is a large current, the stored information of the memory cell 202 may be represented as "1", and when the current output from the bit line BL is a small current, the stored information of the memory cell 202 may be represented as "0".

It is understood that when the plurality of memory cells 202 are included in the one-time program memory 200, a plurality of word lines WL and a plurality of bit lines WL may be included in the one-time program memory 200.

When a portion of memory cells 202 in the one-time-program memory 200 are programmed, the portion of memory cells 202 may be referred to as selected memory cells, and the transistors 21 in the selected memory cells may be referred to as selected transistors.

Based on this, in the programming phase of the one-time programming memory 200, it may be that the word line WL connected to the selected transistor receives the first programming signal and the bit line BL connected to the selected transistor receives the second programming signal. In the read phase of the one-time program memory 200, a word line WL connected to a selected transistor receives a read signal, and a bit line BL connected to the selected transistor outputs a current flowing through a transistor 21.

Like the one-time programmable memory 100, the memory cell 202 of the one-time programmable memory 200 provided in the above embodiment is disposed on a substrate in a planar array integrated manner, the transistor 21 in the memory cell 202 is disposed on the substrate 201, the sensitivity amplifier connected to the bit line BL is also disposed on the substrate 201, the area of the substrate 201 is occupied, the device arrangement density of the devices on the substrate is small, and the area utilization rate of the memory 200 to the substrate 201 is low. Moreover, the manufacturing process of the memory 200 is complex, the process difficulty is increased, and the cost is high.

Based on the above-described problems, as shown in fig. 5 and 6, in some embodiments of the present application, there is provided yet another one-time programming memory 300. The one-time programmable memory 300 includes a substrate 301 and at least one memory cell 302. At least one memory cell 302 is located on substrate 301. The memory cell 302 includes a transistor 31 and at least one capacitor 32 arranged in sequence along a first direction Z. The first direction Z is perpendicular to the substrate 301.

The one-time-programmable memory 300 includes at least one memory cell 302, and the one-time-programmable memory 300 may include one memory cell 302 or the one-time-programmable memory 300 may include a plurality of memory cells 302. The number of the memory cells 302 in the one-time programmable memory 300 is not limited in the embodiment of the present application, as long as the memory requirements of the one-time programmable memory 300 can be satisfied.

The memory cell 302 includes a transistor 31 and at least one capacitor 32 sequentially arranged in the first direction Z, and may be such that the transistor 31 is located on a side of the capacitor 32 close to the substrate 301 as shown in fig. 5 and 6. Alternatively, "the memory cell 302 includes the transistor 31 and the at least one capacitor 32 sequentially disposed in the first direction Z", and it is possible that the transistor 31 is located on a side of the capacitor 32 away from the substrate 301.

The transistor 31 includes a gate 311, a first pole 312, and a second pole 313, wherein the first pole 312 is remote from the substrate 301 relative to the second pole 313.

The materials of the first pole 312 and the second pole 313 may both be conductive materials, such as metallic materials. In some examples, the material of the first and second poles 312 and 313 may be one or more of titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (W), molybdenum (Mo), indium TiN Oxide (ITO), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag), and the like.

The first pole 312 and the second pole 313 are both a film structure, for example, may be formed by deposition, sputtering, etc. instead of doping in the substrate 301, so that the memory cell 302 may be stacked in 3D on the substrate 301, to achieve high density integration of the memory cell 302, and reduce the size of the one-time programmable memory 300.

The material of the gate electrode 311 may also be a conductive material, such as a metal material. In some examples, one or more of titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (W), molybdenum (Mo), indium TiN Oxide (ITO), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag), and the like conductive materials may be used.

As shown in fig. 5 and 6, the transistor 31 may further include a semiconductor layer 314, the semiconductor layer 314 being in contact with both the first pole 312 and the second pole 313.

In some examples, the semiconductor layer 314 may be located between the first pole 312 and the second pole 313 along the first direction Z. The gate electrode 311 may be disposed around the semiconductor layer 314, and the transistor 31 further includes a gate insulating layer 315 between the semiconductor layer 314 and the gate electrode 311.

The semiconductor layer 314 may be silicon (Si), polysilicon, amorphous silicon, indium gallium zinc oxide (InGaZn) complex, zinc oxide (ZnO), indium Tin Oxide (ITO), titanium dioxide (TiO) ₂ ) Molybdenum disulfide (MoS) ₂ ) Tungsten disulfide (WS) ₂ ) One or more of the following semiconductor materials.

The semiconductor layer 314 may be a pillar structure extending in the first direction Z, for example. In this way, the size of the front projection of the semiconductor layer 314 on the substrate 301 is smaller, which is more advantageous for achieving high density integration of the memory cell 302, and for further reducing the size of the one-time programming memory 300.

Illustratively, as shown in fig. 7, the semiconductor layer 314 may have a hollow structure, and the transistor 31 may further include a filler layer 316 disposed inside the semiconductor layer 314.

In some examples, the fill layer 316 is in contact with both the first pole 312 and the second pole 313. In other examples, the fill layer 316 may be in contact with one of the first pole 312 and the second pole 313.

Wherein the material of the fill layer 316 may be silicon dioxide (SiO ₂ ) Alumina (Al) ₂ O ₃ ) Hafnium oxide (HfO) ₂ ) Zirconium oxide (ZrO) ₂ ) Titanium dioxide (TiO) ₂ ) Yttria (Y) ₂ O ₃ ) And silicon nitride (Si) ₃ N ₄ ) One or more of the insulating materials.

It will be appreciated that the semiconductor layer 314 is located between the first pole 312 and the second pole 313 along the first direction Z, and the gate electrode 311 is disposed around the semiconductor layer 314, and thus, the gate electrode 311 may be located between the first pole 312 and the second pole 313 along the first direction Z. Alternatively, along the first direction Z, the first pole 312 and the second pole 313 are located on two sides of the gate 311, respectively. The gate electrode 311 is insulated from the semiconductor layer 314 by the gate insulating layer 315, and also from each other between the first electrode 312 and the second electrode 313.

Wherein the material of the gate insulating layer 315 may be silicon dioxide (SiO ₂ ) Alumina (Al) ₂ O ₃ ) Hafnium oxide (HfO) ₂ ) Zirconium oxide (ZrO) ₂ ) Titanium dioxide (TiO) ₂ ) Yttria (Y) ₂ O ₃ ) And silicon nitride (Si) ₃ N ₄ ) One or more of the insulating materials.

In other examples, as shown in fig. 8, the semiconductor layer 314 may be located between the first pole 312 and the second pole 313 along the first direction Z. The gate electrode 311 may be located at one side of the semiconductor layer 314.

In still other examples, as shown in fig. 9, the semiconductor layer 314 may be located between the first pole 312 and the second pole 313 along the first direction Z. A cavity may be formed in semiconductor layer 314, and gate 311 is located in the cavity.

It is understood that the relative positional relationship between the semiconductor layer 314 and the first and second poles 312 and 313 is not limited to the relative positional relationship described in the above example. The relative positional relationship between the gate electrode 311 and the first and second poles 312 and 313 is also not limited to the one described in the above example.

Illustratively, the transistor 31 may be an N-channel metal oxide semiconductor (N-channel metal oxide semiconductor, NMOS) transistor, or may be a P-channel metal oxide semiconductor (P-channel metal oxide semiconductor, PMOS) transistor.

As shown in fig. 7, the capacitor 32 includes a first electrode 321 and a second electrode 322, and a dielectric layer 323 between the first electrode 321 and the second electrode 322. The first electrode 321 is connected to the first electrode 312 of the transistor 31.

The materials of the first electrode 321 and the second electrode 322 may be conductive materials, for example, one or more of titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (W), molybdenum (Mo), indium TiN Oxide (ITO), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag), and the like.

The material of the dielectric layer 323 may be zirconia (ZrO ₂ ) Hafnium oxide (HfO) ₂ ) Al doped HfO ₂ Si doped HfO ₂ Zr doped HfO ₂ La doped HfO ₂ Y-doped HfO ₂ One or more of an isoparaffinic material or a material doped with other elements based on the material.

When the material of the dielectric layer 323 is comprised of a ferroelectric material, the capacitor 323 is more likely to be broken down during the programming phase of the memory cell 302, thereby storing the corresponding information.

In some embodiments, as shown in fig. 5 and 6, the first electrode 321 is a columnar structure extending along the first direction Z. The second electrode 322 is disposed around the first electrode 321.

In this way, the area of the front projection of the first electrode 321 on the substrate 301 is smaller, and the front projection of the capacitor 32 on the substrate 301 is smaller, so that more capacitors 32 can be formed on the substrate 301 when the area of the substrate 301 is fixed, and further more memory cells 302 are arranged, thereby improving the storage density of the one-time programming memory 300. At the same time, the size of the substrate 301 and thus the size of the one-time programmable memory 300 can be reduced when a certain number of memory cells 302 are provided.

The memory cell 302 includes at least one capacitor 32, and may be such that the memory cell 302 includes one capacitor 32 as shown in fig. 5 and 6, or such that the memory cell 302 includes a plurality of capacitors 32 as shown in fig. 10 and 11.

Wherein the storage unit 302 includes a plurality of capacitors 32 therein, so that one piece of information can be stored in each capacitor 32, so that the storage unit 302 stores a plurality of pieces of information.

In the case where the memory unit 302 includes a plurality of capacitors 32, the plurality of capacitors 32 are sequentially disposed in the first direction Z, and the first electrodes 321 of the plurality of capacitors 32 are sequentially connected. In this way, the size of the orthographic projection of the plurality of capacitors 32 on the substrate 301 is smaller than that of the plurality of capacitors arranged in the direction parallel to the substrate, thereby facilitating realization of high-density integration of the memory cell 302 and further reducing the size of the one-time programming memory 300.

For example, the first electrodes 321 of the plurality of capacitors 32 of the same memory cell 302 may be of unitary construction. In this way, the first electrode of the capacitor 32 does not need to be singly used for a plurality of times, which is beneficial to simplifying the manufacturing process of the one-time programming memory 300 and reducing the manufacturing cost of the one-time programming memory 300.

In the above embodiment of the present application, the memory cell 302 of the one-time programmable memory 300 includes the transistor 31 and the capacitor 32, the first pole 312 of the transistor 31 is far from the substrate 301 relative to the second pole 313, the transistor 31 is disposed on the substrate 301 in a three-dimensional structure, and the area of the orthographic projection of the transistor 31 on the substrate 301 can be smaller. The transistor 31 and the capacitor 32 are arranged in sequence on the substrate 301 in the first direction Z, so that the orthographic projection of the memory cell 302 as a whole on the substrate 301 can also be smaller. In this way, the area of the orthographic projection of the transistor 31 on the substrate 301 is smaller, and the orthographic projection of the memory cell 302 as a whole on the substrate 301 can be smaller, so that the number of memory cells 302 provided in the one-time-programmable memory 300 of a certain size can be made larger, or the size of the one-time-programmable memory 300 having the same number of memory cells 302 can be made smaller.

In some embodiments, as shown in fig. 10 and 11, the one-time program memory 300 may further include a word line WL, a bit line BL, and at least one second electrode layer PL. Wherein, the word line WL extends along the second direction X, and the word line WL is connected to the gate 311. The bit line BL extends in the third direction Y and is connected to the second pole 313 of the transistor 31. The first electrode 321 penetrates the second electrode layer PL, and a portion of the second electrode layer PL surrounding the first electrode 321 serves as a second electrode 323. Wherein the second direction X intersects the third direction Y and is parallel to the substrate 301.

The one-time-programmable memory 300 includes at least one second electrode layer PL, and may be such that the one-time-programmable memory 300 includes one second electrode layer PL as shown in fig. 5. Alternatively, the one-time program memory 300 includes at least one second electrode layer PL, and it is also possible that the one-time program memory 300 includes a plurality of second electrode layers PL as shown in fig. 10. Fig. 10 illustrates that the one-time programming memory 300 includes 4 second electrode layers PL, which may be a second electrode layer PL0, a second electrode layer PL1, a second electrode layer PL2, and a second electrode layer PL3 sequentially distant from the substrate 301 in the first direction Z.

In the case that the plurality of memory cells 302 are included in the one-time program memory 300, a portion of the second electrode layer PL surrounding the first electrode 321 serves as the second electrode 323, so that the plurality of second electrodes 323 do not need to be formed separately, the manufacturing process of the one-time program memory 300 is simplified, and the cost of the one-time program memory 300 is reduced.

In some examples, as shown in fig. 12, the word line WL and the gate 311 connected to the word line WL are integrally provided. In this way, when forming the word line WL, the gates 311 of the plurality of transistors 31 may be formed at the same time, so that the plurality of gates need not be formed separately in the process of manufacturing the one-time program memory 300, thereby simplifying the process of manufacturing the one-time program memory 300 and reducing the cost of the one-time program memory 300.

In some embodiments, as shown in fig. 13 and 14, in the case where the one-time-programmable memory 300 includes a plurality of memory cells 302, the plurality of memory cells 302 are arranged in a plurality of rows along the second direction X and a plurality of columns along the third direction Y.

Referring to fig. 10, the one-time program memory 300 further includes a word line layer 33 and a bit line layer 34. The word line layer 33 includes a plurality of word lines WL. One word line WL is connected to the gate 311 of the transistor 31 of one row of memory cells 302. Bit line layer 34 is located between transistor 31 and substrate 301. The bit line layer 34 includes a plurality of bit lines BL, one bit line BL being connected to the second poles 313 of the transistors 31 of one column of memory cells 302.

In fig. 10, the word line layer 33 includes 4 word lines WL, and in the third direction Y, the 4 word lines WL may be a word line WL0, a word line WL1, a word line WL2, and a word line WL3, respectively. In fig. 10, the bit line layer 34 includes 4 bit lines BL as an example, and in the second direction X, the 4 bit lines BL may be bit lines BL0, BL1, BL2, and BL3, respectively.

Participating in fig. 10, each layer of second electrode layer PL is connected to the second electrodes 322 of the multi-row and multi-column capacitors 32 of the same layer.

It will be appreciated that the one-time programmable memory 300 may include not only the memory cell 302, the word line layer 33, the bit line layer 34, and the second electrode layer PL described above, but also control circuits that may include one or more of a decoder, a driver, a timing controller, a buffer, or an input-output drive, and may include other functional circuits. The control circuit can control the signal lines, namely the word lines, the bit lines and the like in the embodiment of the application.

Referring to fig. 15, the transistor 31 and the capacitor 32, the word line layer 33, the bit line layer 34 and the second electrode layer PL in the memory cell 302 may be manufactured by a back end of line (BEOL). The control circuit may be fabricated on the substrate by a front end of line process (front end of the line, FEOL). That is, the transistor 31 and the capacitor 32, the word line layer 33, the bit line layer 34, and the second electrode layer PL in the memory cell 302 are located on the side of the control circuit away from the substrate.

In this way, the transistor 31 and the capacitor 32, the word line layer 33, the bit line layer 34 and the second electrode layer PL in the memory cell 302 can be formed by a subsequent process, so that the circuit density in a unit area can be increased, and the memory performance in a unit area can be improved.

After the front-end-of-line FEOL is completed, the interconnect lines may also be fabricated by the back-end-of-line BEOL. The interconnect lines include both interconnect lines connecting devices in the control circuit and other portions of the signal lines described above.

The one-time programmable memory 300 according to the above embodiment of the present application includes a plurality of memory cells 302, and the memory cells 302 include a transistor 31 and a capacitor 32. Wherein the information stored in the memory cell 302 is different when the state of the capacitor 32 is different. Illustratively, when the capacitor 32 is in a normal state, the capacitor 32 corresponds to an open circuit, the capacitor 32 stores information "0", and after the capacitor is broken down, a path is formed at the capacitor 32, and the capacitor 32 stores information "1". The capacitor 32 is not recoverable after breakdown, so that the information stored in the capacitor 32 can be made valid for a long period of time.

The transistor 31 can be used not only to control the selection of the memory cell, but also to prevent the problem of excessive current in the circuit after breakdown of the capacitor.

When the memory cell 302 of the one-time programmable memory 300 includes a plurality of capacitors 32, information may be stored by only one capacitor 32, or the same information may be stored by a plurality of capacitors 32, for example, one information "0" may be stored by only one capacitor 32, or information "0" may be stored by a plurality of capacitors 32, thereby representing that the stored information of the memory cell is "0".

Alternatively, a plurality of capacitors 32 may store a plurality of pieces of stored information. For example, some of the plurality of capacitors 32 store information "1", and the remaining capacitors 32 store information "0", thereby characterizing a plurality of stored information of the memory cell, such as "0010", "0100", "1000", "0001", and the like.

The manner of storing information in the memory cell 302 of the one-time programmable memory 300 is not limited in the present application, as long as the storage requirement of the one-time programmable memory 300 can be satisfied.

In some embodiments, the write operation may be performed on the one-time program memory 300 using the word line WL, the bit line BL, and the second electrode layer PL to store information in the one-time program memory 300. When the plurality of memory cells 302 are included in the one-time-programmable memory 300, the write operation may be performed on the plurality of memory cells 302 at the same time, or may be performed on only a part of the memory cells 302. Referring to fig. 14, the memory cell 302 to which the write operation is performed is a selected memory cell, and the transistor 31 in the selected memory cell may be the selected transistor 31A. When a plurality of capacitors 32 are included in the memory cell 302, the capacitor 32 being programmed may also be referred to as a selected capacitor 32A.

In some examples, during the write phase, the word line WL connected to the selected transistor 31A may be used to receive a first word line drive signal to turn on the selected transistor 31A.

Illustratively, the selected transistor 31A may be an N-channel metal oxide semiconductor transistor, and the voltage of the first word line driving signal may be a high voltage, thereby turning on the selected transistor 31A. For example, the voltage value of the first word line driving signal may be 2.9V.

In fig. 14, a word line WL0 is illustrated as an example of a word line connected to the selected transistor 31A. It will be appreciated that when the selected transistor 31A is different, the word line connected to the selected transistor 31A is also different.

In some examples, during the write phase, the other word line WL is used to receive a second word line drive signal to turn off the unselected transistor 31B. The other word lines WL are word lines WL other than the word line WL connected to the selected transistor 31A.

For example, the unselected transistor 31B may be an N-channel metal oxide semiconductor transistor, and the voltage of the second word line driving signal may be a low voltage, thereby turning off the selected transistor 31A. For example, the voltage value of the second word line driving signal may be 0V.

In fig. 14, word lines WL1, WL2, and WL3 are shown as examples of other word lines. It will be appreciated that when the selected transistor 31A is different, the word line connected to the selected transistor 31B is also different.

In some examples, during the write phase, the bit line BL coupled to the selected transistor 31A is used to receive a first bit line control signal and the second electrode layer PL coupled to the selected capacitor 32A is used to receive a first programming signal, the voltage differential of the first bit line control signal and the first programming signal causing the selected capacitor 32A to breakdown. The selected capacitor 32A is one of the capacitors 32 in the memory cell that is electrically connected to the selected transistor 31A.

The voltage of the first program signal may be greater than the voltage of the first bit line control signal. The voltage difference between the first bit line control signal and the first program signal is greater than the breakdown voltage of the selected capacitor. For example, the voltage of the first program signal may be 3V, and the voltage of the first program signal may be 0V.

In fig. 14, bit line BL2 is taken as a bit line connected to selected transistor 31A, and second electrode layer PL2 is taken as an example of a second electrode layer connected to selected capacitor 32A. It will be appreciated that when the selected transistor 31A is different, the bit line connected to the selected transistor 31A is also different. When the selected capacitor 32A is different, the second electrode layer connected to the selected capacitor 32A is also different.

In some examples, during the write phase, the other bit lines BL are used to receive the second bit line control signal. The other second electrode layer is used for receiving a second programming signal. The second bit line control signal is equal to the voltage of the second program signal. When the memory cell 302 includes a plurality of capacitors 32, the unselected capacitor 32B is the other capacitor of the plurality of capacitors 32 other than the selected capacitor 32A. The other bit lines BL are bit lines BL other than the bit line BL connected to the selected transistor. The other second electrode layers PL are the second electrode layers PL other than the second electrode layer PL connected to the selected capacitor 32A.

The voltages of the second bit line control signal and the second programming signal may be 1V.

In fig. 14, bit lines BL0, BL1, and BL3 are taken as other bit lines, and second electrode layers PL0, PL1, and PL3 are taken as other second electrode layers as examples.

In some embodiments, the precharge operation may be performed on the one-time program memory 300 before the write operation is performed on the one-time program memory 300 using the word line WL, the bit line BL, and the second electrode layer PL. It is understood that the precharge operation of the one-time programmable memory 300 may be the precharge operation of all memory cells of the one-time programmable memory 300. By precharging all the memory cells, voltages are present on the first and second electrodes of the capacitors of all the memory cells, and even if the second electrode layer connected to the selected capacitor is connected to other unselected capacitors during the write operation of the one-time programming memory 300, the voltage difference between the first and second electrodes on the other unselected capacitors will not break down the unselected capacitors, thereby being beneficial to ensuring the accuracy of the stored information after the 300 write operation of the one-time programming memory.

Based on this, in some examples, during the precharge phase, the word line WL may be used to receive a first word line drive signal, turning on the transistor 31. The bit line BL may be used to receive a second bit line control signal, and the second electrode layer PL may be used to receive a second program signal, the second bit line control signal being equal to the second program signal in voltage.

In some embodiments, the one-time-program memory 300 may be read using the word line WL, the bit line BL, and the second electrode layer PL, which acquires the storage information in the one-time-program memory 300.

Based on this, in some examples, during the read phase, the word line WL connected to the selected transistor 31A is used to receive the first word line driving signal, turning on the selected transistor 31A. The second electrode layer PL connected to the selected capacitor 32A is used to receive a third programming signal, and the bit line BL connected to the selected transistor 31A is used to output the voltage of the first electrode 321 of the selected capacitor 32A, the voltage of the first electrode 321 being indicative of the information stored by the selected capacitor 32A.

In some examples, during the read phase, the other word line WL is used to receive the second word line drive signal to turn off the unselected transistor 31B. The other bit lines BL are used for receiving the second bit line control signal. The other second electrode layer PL is for receiving a second programming signal. The second bit line control signal is equal to the voltage of the second program signal. When the memory cell includes a plurality of capacitors, the unselected capacitor is the other capacitor than the selected capacitor among the plurality of capacitors.

In some embodiments, the one-time program memory 300 may be put into a standby state using the word line WL, the bit line BL, and the second electrode layer PL. It is understood that when the one-time programmable memory 300 is in the standby state, all the memory cells 302 are in the standby state.

In some examples, during the standby phase, the word line WL is used to receive a second word line driving signal, turning off the transistor 31. The bit line BL is configured to receive a second bit line control signal, and the second electrode layer PL is configured to receive a second program signal, where the second bit line control signal is equal to the second program signal in voltage.

Some embodiments of the present application also provide a one-time programming memory 300, a word line WL, a bit line BL, at least one second electrode layer PL, and at least one memory cell 302, each memory cell 302 including a transistor 31 and at least one capacitor 32. One capacitor 32 in each memory cell 302 corresponds to one second electrode layer PL. The gate 311 of the transistor 31 is connected to the word line WL, the first electrode 312 of the transistor 32 is connected to the first electrode 321 of the capacitor 32, the second electrode 313 of the transistor 31 is connected to the bit line BL, and the second electrode 322 of the capacitor 32 is connected to the second electrode layer PL.

Some embodiments of the present application provide a control method of the one-time programmable memory 300. The one-time programming memory 300 includes at least one memory cell 302, a word line WL, a bit line BL, and at least one second electrode layer PL. The memory cell 302 includes a transistor 31 and at least one capacitor 32, a gate 311 of the transistor 31 is connected to a word line WL, a first electrode 312 of the transistor 31 is connected to a first electrode 321 of the capacitor 32, a second electrode 313 of the transistor 31 is connected to a bit line BL, and a second electrode 322 of the capacitor 32 is connected to a second electrode layer PL. The control method may include:

during the write phase:

the first word line driving signal is transmitted to the word line WL connected to the selected transistor 31A to turn on the selected transistor 31A.

The first bit line control signal is transferred to the bit line BL connected to the selected transistor 31A and the first program signal is transferred to the second electrode layer PL connected to the selected capacitor 32A to break down the selected capacitor 32A. The selected capacitor 32A is one of the capacitors 32 in the memory cell that is electrically connected to the selected transistor 31A.

In the write phase, the selected transistor 31A is turned on and the first bit line control signal transmitted on the bit line BL connected to the second pole 313 of the selected transistor 31A is transmitted through the transistor to the first pole 312, i.e. to the first electrode 321 of the selected capacitor 32A. The portion of the second electrode layer PL surrounding the first electrode 321 serves as a second electrode 322, and the first programming signal is transmitted in the second electrode layer PL, i.e., the first programming signal is transmitted on the second electrode 322.

The first bit line control signal is applied to the first electrode 321 of the selected capacitor 32A, the first program signal is applied to the second electrode 322 of the selected capacitor 32A, and a difference between a voltage of the first bit line control signal and a voltage of the first program signal is greater than a breakdown voltage of the selected capacitor 32A, thereby causing the selected capacitor 32A to break down, thereby storing the first stored information.

Illustratively, the first stored information may be "1".

For example, the first program signal may be greater than the first bit line control signal. The voltage of the first program signal may be 2.9V and the voltage of the first bit line control signal may be 0V.

In the writing stage, the number of the selected transistors 31A and the selected capacitors 32A may be single or plural. When the number of the selected transistors 31A is plural, the plural selected transistors 31A may be connected to the same word line WL, and the plural selected transistors 31A may be connected to the plural word lines WL, respectively. Similarly, when the number of the selected transistors 31A is plural, plural selected transistors 31A may be connected to the same bit line BL, and plural selected transistors 31A may be connected to plural bit lines BL.

It will be appreciated that a plurality of unselected transistors 31B may be connected to the word line WL connected to the selected transistor 31A in addition to the selected transistor 31A, thereby turning on the plurality of unselected transistors 31B during the write phase. However, the bit lines connected to the selected transistor 31A and the unselected transistor 31B of the same word line WL are different, and therefore, in the writing stage, the first bit line control signal is transferred in the bit line BL connected to the selected transistor 31A and the second bit line control signal is transferred in the bit line BL connected to the unselected transistor 31B connected to the same word line WL as the selected transistor 31A. The selected capacitor is broken down under the voltage difference of the first bit line control signal and the first programming signal, and the unselected capacitor connected with the unselected transistor is not broken down under the voltage difference of the second bit line control signal and the first programming signal, and is in a normal working state.

In the one-time programming memory 300, the plurality of memory cells includes memory cells connected to other word lines in addition to the memory cells connected to the word line connected to the selected transistor 31A.

Based on this, in some embodiments, the control method may include:

during the write phase:

the second word line driving signal is transmitted to the other word lines WL to turn off the unselected transistors 31A. The second bit line control signal is transferred to the other bit lines BL. The second program signal is transmitted to the other second electrode layer PL. The other word lines WL are word lines WL other than the word line WL connected to the selected transistor 31A, and the other bit lines BL are bit lines BL other than the bit line BL connected to the selected transistor 31A. The other second electrode layers PL are the second electrode layers PL other than the second electrode layer PL connected to the selected capacitor 32A.

Thus, during the write phase, the transistors in the memory cells connected to the other word lines in the one-time programming memory 300 are turned off so that the capacitors in the memory cells connected to the other word lines are not affected by the voltage on the bit line BL connected to the selected transistor, and the stored information in the unselected memory cells is not changed from "0" to "1". Thereby ensuring the accuracy of the write-in of the stored information by the one-time programmable memory 300.

In some embodiments, prior to the write phase, the control method further comprises: in the phase of the pre-charge,

the first word line driving signal is transmitted to the word line WL to turn on the transistor 31. The second bit line control signal is transferred to the bit line BL and a second program signal is output to the second electrode layer PL, the second bit line control signal being equal to a voltage of the second program signal.

The "voltages of the second bit line control signal and the second program signal are equal" may be that the voltages of the second bit line control signal and the second program signal are completely equal, or that the voltages of the second bit line control signal and the second program signal are approximately equal.

Thus, during the precharge phase, all the transistors 31 are turned on, the second bit line control signal received by the bit line BL is transmitted to the first electrode 321 of the capacitor, the second programming signal received by the second electrode layer PL is transmitted to the second electrode 322 of the capacitor 32, the voltages on the first electrode 321 and the second electrode 322 of the capacitor 32 are equal or approximately equal, and the reactive power loss on the capacitor 32 is lost, which is beneficial to improving the service life of the capacitor 32.

In some embodiments, the control method may include:

in the course of the reading phase,

The third program signal is transmitted to the second electrode layer PL connected to the capacitor 32A.

Detecting a voltage on a bit line BL connected to the selected transistor 31A to read information stored in the selected capacitor 32A; the selected capacitor 32A is one of the capacitors 32 in the memory cell 302 that is electrically connected to the selected transistor 31A.

At this time, the bit line BL connected to the selected transistor 31A is used to read information stored in the selected capacitor.

For example, one word line WL and a plurality of bit lines BL may be used to read the stored information in the selected capacitor in a row of memory cells 302.

In some examples, detecting the voltage on the bit line BL to read the information stored by the selected capacitor 32A includes:

when the voltage on the bit line BL connected to the selected transistor is detected as the voltage of the third program signal, the first stored information is read.

At this time, the selected capacitor 32A is broken down in the writing stage, so that the third programming signal received by the second electrode layer PL is transmitted to the bit line BL with the selected transistor 31A through the broken-down capacitor 32, the turned-on selected transistor 31A.

In some examples, the bit line BL is coupled to a sense amplifier such that the selected capacitor may also be determined to store the first stored information when the voltage on the bit line BL coupled to the selected transistor is in a rising phase and has not yet reached the voltage of the third turn-on signal. By way of example, when the read time is 15ns and the read voltage 544mV, it may be determined that the selected capacitor stores the first stored information.

When the voltage on the bit line BL connected to the selected transistor is detected as zero voltage, the second stored information is read.

At this time, the selected capacitor 32A is guaranteed to be in a normal state in the writing phase, the third programming signal transmitted from the second electrode layer PL connected to the selected capacitor 32A cannot be transmitted to the bit line BL through the capacitor, and since the selected transistor 31A is connected to the selected capacitor 32A, the voltage of the first electrode 321 of the selected capacitor 32A at the precharge phase is discharged through the circuit to become zero voltage, and the voltage of the bit line BL connected to the selected transistor is also zero voltage.

In the one-time programming memory 300, the plurality of memory cells includes memory cells connected to other word lines in addition to the memory cells connected to the word line connected to the selected transistor. In the read phase, information stored in memory cells connected to other word lines may not be read. At this time, in some embodiments, the control method may include:

In the course of the reading phase,

the second word line driving signal is transmitted to the other word lines WL to turn off the unselected transistors 31A. The second bit line control signal is transferred to the other bit lines BL. The second program signal is transmitted to the other second electrode layer PL.

The other word lines WL are word lines WL other than the word line WL connected to the selected transistor 31A, and the other bit lines BL are bit lines BL other than the bit line BL connected to the selected transistor 31A. The other second electrode layers PL are the second electrode layers PL other than the second electrode layer PL connected to the selected capacitor 32A.

The one-time programmable memory 300 is used for storing information, and is not always outputting data after the writing phase is completed, and is in a standby state for most of the time.

Based on this, in some embodiments, the control method may include:

in the standby phase of the process,

a second word line driving signal is transmitted to the word line WL to turn off the transistor. The second bit line control signal is transferred to the bit line BL and a second program signal is output to the second electrode layer PL, the second bit line control signal being equal to a voltage of the second program signal.

By setting the standby phase, the one-time programmable memory 300 can be switched to the standby state after the precharge phase, the write phase and the read phase, and the power consumption of the one-time programmable memory 300 is reduced.

Dynamic random access memory (dynamic random access memory, DRAM) has a high density and low cost, and is widely used in computing systems such as servers, computers, and mobile terminals. The DRAM is composed of a transistor and a capacitor (one transistor and one capacitor,1T 1C), has a simple structure and large area advantage, and has wide prospect in the mass storage market. However, the dynamic random access memory needs to be refreshed periodically due to the leakage of the capacitor, and to ensure functions such as redundant hardware, the configuration parameters need to be stored by using the one-time programmable memory. The memory system with the one-time programming memory is more complex in structure and larger in size and the overall density of the memory system is lower than a DRAM which is composed of only one transistor and one capacitor and can increase the memory density with the reduction of the process size.

Based on this, as shown in fig. 16, some embodiments of the present application further provide a memory system 1000 including a dynamic random access memory 400 and a one-time programmable memory 300, wherein the dynamic random access memory 400 is coupled to the one-time programmable memory 300. The one-time programmable memory 300 is one-time programmable memory as described in any of the implementations above.

Thus, the one-time programmable memory 300 in the memory system 1000 may be smaller in size than the one-time programmable memory 300 in the related art when a certain amount of data is stored while including a certain number of memory cells 302, thereby making the memory system 100 smaller in size and higher in storage density.

As shown in fig. 16, the dynamic random access memory 400 may include a memory array 410, redundant columns 420, redundant rows 430, a row decoder 440, and a column decoder 450. The row decoder 440 includes row addresses of rows of memory cells in the memory array 410 and the column decoder 450 includes column addresses of columns of memory cells in the memory array 410. The row decoder 440 and the column decoder 450 are used to control the memory cells in the memory array 410, write data into the set memory cells, or read data from the set memory cells. The redundant rows 420 include a plurality of rows of memory cells and the redundant columns 430 include a plurality of columns of memory cells, the redundant rows 420 and the redundant columns 430 may be used to provide memory cells for replacement when a memory cell in the memory array 410 fails, and may be used to provide more memory cells when the number of memory cells in the memory array is insufficient.

Illustratively, two one-time programmable memories 300 may be included in the memory system 1000, one-time programmable memory 300 being coupled to a redundant row 420 and the other one-time programmable memory 300 being coupled to a redundant column. At this time, the one-time program memory 300 may also store a row address of each row of memory cells in the redundant row or a column address of memory cells within the redundant column, thereby serving to control one or more memory cells in the redundant row to store information or one or more memory cells in the redundant column to store information.

It is to be understood that the composition of the devices in the memory system 1000 provided by the present application may not be limited thereto.

In some examples, the memory cells 302 of the one-time programmable memory 300 may be fabricated with the memory cells in the memory array 410, the redundant columns 420, and the redundant rows 430 of the dynamic random access memory 400, thereby simplifying the fabrication process of the memory system and reducing the fabrication cost of the memory system.

In some examples, the memory array 410, the redundant columns 420, the memory cells in the redundant rows 430, and the memory cells of the one-time-programmable memory of the dynamic random access memory 400 may all be fabricated using a subsequent process. Thus, the integration density of the memory cells in the memory array 410, the redundancy columns 420 and the redundancy rows 430 of the dynamic random access memory 400 and the integration density of the memory cells of the one-time programmable memory are improved at the same time, which is further beneficial to realizing the high integration of the memory system.

The one-time programmable memory 300 can be applied to the memory system 1000 for ensuring the normal operation of the DRAM, and can be independently applied to the electronic device as a memory.

Based thereon, some embodiments of the application provide an electronic device 2000. As shown in fig. 17, some embodiments of the present application provide an electronic device 2000 including: memory 2100, processor 2200, input device 2300, output device 2400, and so forth. Those skilled in the art will appreciate that the configuration of the electronic device shown in fig. 17 does not constitute a limitation of the electronic device 2000, and the electronic device 2000 may include more or fewer components than those shown in fig. 17, or may combine some of the components shown in fig. 17, or may be arranged differently than the components shown in fig. 17.

The memory 2100 is used to store software programs and modules. The memory 300 mainly includes a storage program area and a storage data area, wherein the storage program area can store an operating system, application programs (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like; the storage data area may store data created according to the use of the electronic device (such as audio data, image data, phonebook, etc.), and the like. In addition, the memory 2100 includes an external memory 2110 and an internal memory 2120. The data stored in the external memory 2110 and the internal memory 2120 can be transferred to each other. The external memory 2110 includes, for example, a hard disk, a usb disk, a floppy disk, and the like. The internal memory 2120 includes, for example, dynamic random access memory (dynamic random access memory, DRAM), read only memory, and the like.

The processor 2200 is a control center of the above-described electronic device 2000, connects respective portions of the entire electronic device 2000 using various interfaces and lines, and performs various functions of the electronic device 2000 and processes data by running or executing software programs and/or modules stored in the memory 2100 and calling data stored in the memory 2100, thereby performing overall monitoring of the electronic device 2000. In the alternative, processor 2200 may include one or more processing units. For example, the processor 2200 may include a central processing unit (central processing unit, CPU), an artificial intelligence (artificial intelligence, AI) processor, a digital signal processor (digital signal processor, DSP) and a neural network processor, as well as other specific integrated circuits (application specific integrated circuit, ASIC) and the like. In fig. 17, the processor 2200 is exemplified by a CPU, which may include an operator 2210 and a controller 2220. The arithmetic unit 2210 acquires data stored in the internal memory 2120, processes the data stored in the internal memory 2120, and normally returns the processed result to the internal memory 2120. The controller 2220 may control the operator 2210 to process data, and the controller 2220 may also control the external memory 2110 and the internal memory 2120 to store data or read data.

The input device 2300 is for receiving input numeric or character information and generating key signal inputs related to user settings and function control of the electronic device 2000. By way of example, the input device 2300 may include a touch screen, as well as other input devices. Touch screens, also known as touch panels, collect touch operations by a user on or near the touch screen (e.g., operations by a user on or near the touch screen using any suitable object or accessory such as a finger, stylus, etc.), and actuate the corresponding connection device according to a predetermined program. Other input devices may include, but are not limited to, one or more of a physical keyboard, function keys (e.g., volume control keys, power switch keys, etc.), a trackball, mouse, joystick, etc. The controller 2220 in the above-described processor 2200 may also control the input device 2300 to receive an input signal or not. Further, entered numerical or character information received by the input device 2300, as well as key signal inputs generated in connection with user settings and function controls of the electronic device, may be stored in the internal memory 2120.

The output device 2400 is used to output signals corresponding to data input from the input device 2300 and stored in the internal memory 2120. For example, the output device 2400 outputs a sound signal or a video signal. The controller 2220 in the above-described processor 2200 may also control the output device 2400 to output a signal or not.

The thick arrow in fig. 17 is used to indicate the transmission of data, and the direction of the thick arrow indicates the direction of data transmission. For example, a one-way arrow between input device 2300 and internal memory 2120 indicates that data received by input device 2300 is transferred to internal memory 2120. For another example, a double-headed arrow between the operator 2210 and the internal memory 2120 indicates that data stored in the internal memory 2120 can be transferred to the operator 2210, and data processed by the operator 2210 can be transferred to the internal memory 2120. Thin arrows in fig. 17 represent components that the controller 2220 can control. By way of example, the controller 2220 may control external memory 2110, internal memory 2120, operator 2210, input device 2300, output device 2400, and the like.

Optionally, the electronic device 2000 may also include various sensors. Such as gyroscopic sensors, hygrometric sensors, infrared sensors, magnetometer sensors, etc., are not described in detail herein. Optionally, the electronic device 2000 may further include a wireless fidelity (wireless fidelity, wiFi) module, a bluetooth module, etc., which will not be described herein.

It is to be appreciated that the one-time programmable memory 300 of any of the present applications can be utilized as the memory 2100 in the electronic device 2000 described above. For example, the one-time programmable memory 300 provided in the embodiment of the present application may be used as the external memory 2110 in the memory 2100, or may be used as the internal memory 2120 in the memory 2100.

The technical effects achieved by the electronic device 2000 according to some embodiments of the present application are the same as those achieved by the one-time programmable memory 300 according to any of the embodiments described above, and will not be described herein.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A one-time programmable memory, comprising:

a substrate;

at least one memory cell located on the substrate; the memory cell includes a transistor and at least one capacitor sequentially arranged in a first direction; the first direction is perpendicular to the substrate;

wherein the transistor comprises a gate, a first pole and a second pole, the first pole being remote from the substrate relative to the second pole; the capacitor includes a first electrode and a second electrode, and a dielectric layer between the first electrode and the second electrode; the first electrode is connected to a first pole of the transistor.

2. The one-time programmable memory of claim 1, wherein the transistor further comprises a semiconductor layer, the semiconductor layer being located between the first pole and the second pole along the first direction;

the grid electrode is arranged around the semiconductor layer; the transistor further includes a gate insulating layer between the semiconductor layer and the gate electrode.

3. The one-time programmable memory of claim 1, wherein the first electrode is a pillar structure extending along the first direction; the second electrode is disposed around the first electrode.

4. The one-time programmable memory according to claim 3, wherein the memory cell includes a plurality of the capacitors, the plurality of the capacitors are sequentially arranged along the first direction, and first electrodes of the plurality of the capacitors are sequentially connected.

5. The one-time programmable memory of claim 1, wherein said transistor and said plurality of capacitors are each fabricated using a post process.

6. The one-time programmable memory of claim 1, wherein the material of the dielectric layer comprises a ferroelectric material.

7. The one-time programmable memory according to any one of claims 1 to 6, further comprising:

A word line extending in a second direction, the word line being connected to the gate electrode;

a bit line extending in a third direction, the bit line being connected to a second pole of the transistor;

at least one second electrode layer; the first electrode penetrates through the second electrode layer, and the part, surrounding the first electrode, of the second electrode layer serves as a second electrode;

wherein the second direction intersects the third direction and is parallel to the substrate.

8. The one-time programmable memory of claim 7, wherein the word line is integrally provided with a gate connected to the word line.

9. The one-time programmable memory of claim 7, wherein the one-time programmable memory comprises a plurality of memory cells; the memory cells are arranged in a plurality of rows along the second direction and a plurality of columns along the third direction; each layer of second electrode layer is connected with the second electrodes of the multi-row and multi-column capacitors of the same layer;

the one-time programmable memory further includes:

a word line layer including a plurality of word lines; one word line is connected with the gates of the transistors of one row of memory cells;

a bit line layer between the transistor and the substrate; the bit line layer includes a plurality of bit lines, one bit line being connected to a second pole of a transistor of a column of memory cells.

10. The one-time programmable memory of claim 9,

in the writing stage, a word line connected with a selected transistor is used for receiving a first word line driving signal so as to enable the selected transistor to be conducted; the bit line connected with the selected transistor is used for receiving a first bit line control signal, the second electrode layer connected with the selected capacitor is used for receiving a first programming signal, and the voltage difference between the first bit line control signal and the first programming signal causes the selected capacitor to be broken down; the selected capacitor is one of the capacitors in the memory that is electrically connected to the selected transistor.

11. The one-time programmable memory of claim 9,

in the precharge phase, the word line is used for receiving a first word line driving signal to turn on the transistor; the bit line is used for receiving a second bit line control signal, the second electrode layer is used for receiving a second programming signal, and the second bit line control signal is equal to the second programming signal in voltage.

12. The one-time programmable memory of claim 9,

in a reading stage, a word line connected with a selected transistor is used for receiving a first word line driving signal so as to enable the selected transistor to be conducted; the second electrode layer connected to the selected capacitor is for receiving a third programming signal, and the bit line connected to the selected transistor is for outputting a voltage of a first electrode of the selected capacitor, the voltage of the first electrode being indicative of information stored by the selected capacitor.

13. The one-time programmable memory of claim 9,

in a standby stage, the word line is used for receiving a second word line driving signal to turn off the transistor; the bit line is used for receiving a second bit line control signal, the second electrode layer is used for receiving a second programming signal, and the second bit line control signal is equal to the second programming signal in voltage.

14. The one-time programmable memory of claim 9,

in the writing phase and the reading phase, the other word lines are used for receiving a second word line driving signal so as to turn off the unselected transistors; the other bit lines are used for receiving second bit line control signals, and the other second electrode layers are used for receiving second programming signals; the second bit line control signal is equal to the voltage of the second programming signal; the other word lines are word lines of the plurality of word lines except the word line connected with the selected transistor, and the other bit lines are bit lines of the plurality of bit lines except the bit line connected with the selected transistor; the other second electrode layers are ones of the plurality of second electrode layers except for the second electrode layer connected to the selected capacitor.

15. A one-time programmable memory, comprising:

A word line, a bit line, and at least one second electrode layer;

at least one memory cell, each of the memory cells including a transistor and at least one capacitor; one capacitor in each memory cell corresponds to one second electrode layer;

the gate of the transistor is connected with the word line, the first electrode of the transistor is connected with the first electrode of the capacitor, the second electrode of the transistor is connected with the bit line, and the second electrode of the capacitor is connected with the second electrode layer.

16. A control method of a one-time programmable memory, wherein the one-time programmable memory comprises at least one memory cell, a word line, a bit line and at least one second electrode layer; the memory cell comprises a transistor and at least one capacitor, wherein the grid electrode of the transistor is connected with the word line, the first electrode of the transistor is connected with the first electrode of the capacitor, the second electrode of the transistor is connected with the bit line, and the second electrode of the capacitor is connected with the second electrode layer;

the control method comprises the following steps: in the course of the write phase of the writing,

transmitting a first word line driving signal to a word line connected to a selected transistor to turn on the selected transistor;

Transmitting a first bit line control signal to a bit line connected to the selected transistor and transmitting a first program signal to a second electrode layer connected to the selected capacitor to breakdown the selected capacitor; the selected capacitor is one of the capacitors in the memory cell that is electrically connected to the selected transistor.

17. The control method of claim 16, wherein prior to the write phase, the control method further comprises: in the phase of the pre-charge,

transmitting a first word line driving signal to the word line to turn on the transistor;

and transmitting a second bit line control signal to the bit line, and outputting a second programming signal to the second electrode layer, wherein the second bit line control signal is equal to the second programming signal in voltage.

18. The control method according to claim 16, characterized in that the control method further comprises: in the course of the reading phase,

transmitting a third programming signal to the second electrode layer connected to the capacitor;

detecting a voltage on a bit line connected to the selected transistor to read information stored by the selected capacitor; the selected capacitor is one of the capacitors in the memory cell that is electrically connected to the selected transistor.

19. The control method of claim 18, wherein the detecting the voltage on the bit line connected to the selected transistor to read the information stored by the selected capacitor comprises:

reading first stored information when it is detected that the voltage on the bit line connected to the selected transistor is the voltage of the third programming signal;

when the voltage on the bit line connected to the selected transistor is detected as zero voltage, the second stored information is read.

20. The control method according to claim 16, characterized in that the control method further comprises: in the standby phase of the process,

transmitting a second word line driving signal to the word line to turn off the transistor;

21. The control method according to claim 16, characterized in that the control method includes: in the write phase and the read phase,

transmitting a second word line driving signal to the other word lines to turn off the unselected transistors;

transmitting a second bit line control signal to the other bit lines;

Transmitting a second programming signal to the other second electrode layer;

wherein the other word lines are word lines other than the word line connected to the selected transistor, and the other bit lines are bit lines other than the bit line connected to the selected transistor; the other second electrode layers are second electrode layers except for the second electrode layer connected to the selected capacitor.

22. A memory system comprising a dynamic random access memory and a one-time programming memory, the dynamic random access memory coupled to the one-time programming memory; the one-time programmable memory is one-time programmable memory according to any one of claims 1 to 14, or one-time programmable memory according to claim 15.

23. An electronic device comprising a processor and a one-time programming memory; the processor is electrically connected with the one-time programming memory; the one-time programmable memory is one-time programmable memory according to any one of claims 1 to 14, or one-time programmable memory according to claim 15.