CN117118553A

CN117118553A - Clock synchronization method and communication device

Info

Publication number: CN117118553A
Application number: CN202210537892.3A
Authority: CN
Inventors: 明振宇; 许延伟; 章威; 李雨晴
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-05-17
Filing date: 2022-05-17
Publication date: 2023-11-24

Abstract

A clock synchronization method and a communication device, the method comprising: the first equipment receives a plurality of first messages sent by the second equipment, and determines deviation between a clock of the first equipment and a reference clock of the second equipment according to a plurality of first times and a plurality of second times corresponding to the plurality of first messages, so that the clock of the first equipment is calibrated based on the deviation. The first messages and the first times are in one-to-one correspondence, and the first times are the sending times of the corresponding first messages. The first times and the second times are in one-to-one correspondence, and one second time in the second times is the receiving time of the first message corresponding to one first time in the first times. By the method provided by the embodiment of the application, the first equipment does not need to feed back the message to the second equipment, so that the second equipment does not need to deploy related protocols of PTP, more equipment can be deployed in the network, and the problem of limited quantity of equipment in the network can be solved.

Description

Clock synchronization method and communication device

Technical Field

The present application relates to the field of synchronization technologies, and in particular, to a clock synchronization method and a communication device.

Background

The clock synchronization can synchronize time, frequency, phase and the like of each node in the network, so that each node can interact normally. For example, taking the example that node a needs to synchronize node B, both node a and node B are provided with a clock module and a processing module. The processing module can process the related message, collect the time stamp, and send the obtained message and the time stamp information, and the clock module can perform clock information, such as time deviation, frequency deviation, and the like, according to the received time stamp information, so as to adjust the local real-time clock to realize clock synchronization of each node. However, this procedure requires that the node to be synchronized (e.g. node B) send a message to the node to be synchronized (e.g. node a), which requires that a precision time protocol (precision time protocol, PTP) be deployed at node a, i.e. requiring that node a has PTP functionality, resulting in a limited number of nodes within the network.

Disclosure of Invention

The application provides a clock synchronization method and a communication device, which are used for solving the problem of limited number of nodes in a network.

In a first aspect, embodiments of the present application provide a clock synchronization method that may be performed by a first communication device, which may be a communication apparatus or a communication device capable of supporting functions required for the communication apparatus to implement the method, such as a system on a chip. The following describes an example in which the communication device is a first device. The first communication means is, for example, a first device, or a chip arranged in the first device, or other means for realizing the functionality of the first device. The method comprises the following steps:

The first equipment receives a plurality of first messages sent by the second equipment, and determines deviation between a clock of the first equipment and a reference clock of the second equipment according to a plurality of first times and a plurality of second times corresponding to the plurality of first messages, so that the clock of the first equipment is calibrated based on the deviation. The first messages and the first times are in one-to-one correspondence, and the first times are the sending times of the corresponding first messages. The first times and the second times are in one-to-one correspondence, and one second time in the second times is the receiving time of the first message corresponding to one first time in the first times.

The first device and the second device are located in the same network, the first device may be considered as a device requiring clock synchronization, and the second device may be considered as a reference clock source. In the embodiment of the application, the second device may be any device other than the first device in the network. In the embodiment of the application, any clock in the network can be used as a reference clock, so that an external clock source is not needed, and the deployment cost and the management cost of equipment can be reduced. The second device sends the message carrying the sending time to the first device, and the first device can calculate clock deviation, frequency deviation, phase difference or the like compared with the second device (i.e. the reference clock) according to the sending time of the first message and the time for receiving the first message, so as to realize clock synchronization of the first device and the second device. By the method provided by the embodiment of the application, the first equipment does not need to feed back the message to the second equipment, so that the second equipment does not need to deploy related protocols of PTP, more equipment can be deployed in the network, and the problem of limited quantity of equipment in the network can be solved.

In one possible implementation, the method further includes: the first equipment receives at least one second message sent by the third equipment, and each second message comprises the first time; the first device determines a deviation between a clock of the first device and a reference clock of the second device according to at least one first time and at least one third time corresponding to the at least one second message. The at least one first time corresponds to the at least one third time one by one, and one third time in the at least one third time is the receiving time of the second message corresponding to the third time.

The third device is a device located in the same network as the first device and the second device. The second message sent by the third device includes the first time, which can be understood that the third device receives the first message sent by the second device and forwards the first message to other devices in the network. Thus, even if the first device does not receive the first message broadcast or multicast by the second device, the second message carrying the first time can be received from the third device. The first device may thereby determine a deviation between the clock of the first device and the clock of the second device based on the first time in the second message received from the third device and the third time in which the second message was received. The success rate of the first device determining the deviation between the clock of the first device and the clock of the second device can be improved.

In a possible implementation, the offset includes a frequency offset, and the first device determines an offset between a clock of the first device and a reference clock of the second device according to the plurality of first times and the plurality of second times, including:

the first device maps the plurality of sets of time stamps to a two-dimensional coordinate system and determines a first straight line based on an objective function. Wherein one set of the plurality of sets of time stamps includes a first time and a corresponding fourth time. The two-dimensional coordinates take the first time as an abscissa and the fourth time as an ordinate, and the fourth time is the difference value between the second time and the first time. The slope of the first line is the frequency difference between the clock of the first device and the reference clock of the second device. The objective function is such that sets of time stamps within the two-dimensional coordinate system are located on the same side of the first line. It will be appreciated that a set of time stamps includes a time of transmission of a message and a corresponding time difference between a time of reception and a time of transmission of the message, and that multiple sets of time stamps are mapped to a two-dimensional coordinate system with the time of transmission as an abscissa and the time difference as an ordinate. The overall tilt trend of the sets of time stamps in the two-dimensional coordinate system may characterize a frequency difference between the clock of the first device and the reference clock of the second device. And the plurality of groups of time stamps in the two-dimensional coordinate system are positioned on the same side of the first straight line through the objective function, so that a more accurate frequency difference value is obtained.

In a possible implementation, the objective function satisfies:s.t.ax _i +b-y _i epsilon is less than or equal to epsilon, wherein x _i ＝t _1,i ，y _i ＝t _2,i -t _1,i Epsilon is a preset parameter, t _1,i And t _2,i -t _1,i Is the i-th group timestamp. By means of the objective function, a in the first straight line ax+b tends to be stable, so that more accurate frequency deviation is obtained.

In a possible implementation manner, the method further includes: the first device determines a value of the first straight line on a set of time stamps with a largest abscissa among the sets of time stamps as a phase deviation. The value of the first straight line on the group of time stamps with the largest abscissa among the groups of time stamps is used as the phase deviation, so that noise in the message transmission process can be filtered, and the end-to-end deployment of equipment is supported.

In a possible implementation, the first device determines the first phase deviation as a reference value for the phase adjustment. This maintains the clock phase bias and avoids clock synchronization failure due to accumulation of the phase bias or occurrence of a jump in the phase bias.

In a possible implementation, the first device calibrates a clock of the first device based on the offset, including:

the first device determines a frequency compensation value and calibrates the frequency of the clock of the first device according to the frequency compensation value. The frequency compensation value is the ratio of the frequency difference value to the clock frequency. Since the ratio of the frequency difference to the clock frequency, i.e. the frequency compensation value, affects the time increment value of the clock after each receipt of the pulse signal, the clock of the first device may be calibrated based on the frequency compensation value. And the digital phase-locked loop is not required to be locked, so that the requirement on the crystal oscillator stability can be reduced, and the crystal oscillator cost of the first equipment is reduced.

In a possible implementation, the first message is sent in a broadcast manner or in a multicast manner. Thus, any device in the network where the second device is located takes the clock of the second device as a reference clock, and clock synchronization of all devices in the network can be realized.

In a possible implementation manner, the first message is generated at the control plane and sent through the data plane port. It will be appreciated that generating the time stamp at the data plane is more accurate and reliable than at the control plane. Therefore, the first message is sent through the data plane port, so that the clock synchronization precision can be improved.

In a possible implementation, the first time is determined at the control plane or the data plane. The first time, namely the sending time of the first message, can be generated on the control plane or the data plane, so that the method is more flexible.

In a possible implementation, the first device and the second device communicate directly, i.e. support point-to-point deployment of the devices. Of course, other devices can be deployed between the first device and the second device, and the application range is wider.

In a second aspect, an embodiment of the present application provides a communication device, where the communication device has a function of implementing the functions of the embodiment of the method of the first aspect, and beneficial effects may be referred to the description of the first aspect, which is not repeated herein. The communication apparatus may be the first device of the first aspect, or the communication apparatus may be an apparatus, such as a chip or a chip system, capable of implementing the method provided by the first aspect.

In one possible design, the communication device comprises corresponding means (means) or modules for performing the method of the first aspect. For example, the communication device: including a processing unit (sometimes also referred to as a processing module or processor) and/or a transceiver unit (sometimes also referred to as a transceiver module or transceiver). These units (modules) may perform the corresponding functions in the method examples of the first aspect, which are specifically referred to in the detailed description of the method examples and are not described here in detail.

In a third aspect, an embodiment of the present application provides a communication device, which may be a communication device in the first aspect of the above embodiment, or a chip system provided in the communication device in the first aspect. The communication device comprises a communication interface and a processor, and optionally a memory. Wherein the memory is configured to store a computer program, and the processor is coupled to the memory and the communication interface, and when the processor reads the computer program or instructions, the processor causes the communication device to perform the method performed by the first apparatus in the above method embodiment.

In a fourth aspect, an embodiment of the present application provides a communication device including an input-output interface and a logic circuit. The input-output interface is used for inputting and/or outputting information. The logic circuit is for performing the method described in the first aspect.

In a fifth aspect, an embodiment of the present application provides a chip system, which includes a processor, and may further include a memory and/or a communication interface, for implementing the method described in the first aspect. In a possible implementation, the chip system further includes a memory for storing a computer program. The chip system may be formed of a chip or may include a chip and other discrete devices.

In a sixth aspect, an embodiment of the present application provides a communication system, where the communication system includes a first device and a second device, where the first device is configured to perform a method performed by the first device in the first aspect, and the second device is configured to perform a method performed by the second device in the first aspect. Alternatively, the communication system may further comprise a plurality of first devices and/or a plurality of second devices.

In a seventh aspect, the present application provides a computer readable storage medium storing a computer program which, when executed, implements the method of the first aspect described above.

In an eighth aspect, there is provided a computer program product comprising: computer program code which, when run, causes the method of the first aspect described above to be performed.

Advantageous effects of the above second to eighth aspects and implementations thereof reference may be made to the description of the advantageous effects of the first aspect and implementations thereof.

Drawings

Fig. 1 is a schematic diagram of a synchronous ethernet provided in an embodiment of the present application;

fig. 2 is a schematic diagram of implementing clock synchronization of two devices based on a timestamp according to an embodiment of the present application;

fig. 3 is an application scenario of an embodiment of the present application;

FIG. 4 is a flowchart of a clock synchronization method according to an embodiment of the application;

FIG. 5 is a schematic diagram of generating a timestamp on a data plane according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a control plane time stamp generation according to an embodiment of the present application;

fig. 7 is a schematic diagram of a broadcast scenario suitable for use in the embodiment of the present application;

fig. 8 is a schematic diagram of a multicast scenario applicable to an embodiment of the present application;

FIG. 9 is a schematic diagram of clock synchronization of two devices according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of a communication device according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of a communication device according to an embodiment of the present application.

Detailed Description

First, some terms or concepts related to the embodiments of the present application are introduced so as to facilitate understanding of schemes provided by the embodiments of the present application by those skilled in the art.

1) Clock synchronization includes three types of time synchronization, frequency synchronization, and phase synchronization. Where time synchronization refers to the absolute agreement of coordinated universal times (universal time coordinated, UTC) of different clocks. For example, the UTC of clock a and the UTC of clock B are the same, and then the time of clock a and clock B are synchronized. The UTC of the two clocks is different and it is also considered that there is a clock offset for both clocks. It should be understood that the clock offset is the relative difference between the two clocks. For example, at the same time, UTC of clock 1 is 12:00, UTC of clock 2 is 12:01, clock offset of clock 1 relative to clock 2 is-1 second, and clock offset of clock 2 relative to clock 1 is 1 second.

Frequency synchronization refers to the frequency of a signal remaining unchanged, e.g., the frequency of the signal tracking to a reference frequency over a period of time from a start time. The frequency synchronization does not require that the frequency of the signal coincide with the reference frequency at the start time. For example, the frequency of the signal a at the first time is f1, the frequency of the signal B at the second time is f2, f1 becomes f after the first time, and f2 becomes f after the second time. If f1 and f2 are different, the first time and the second time may be different, and the first time period and the second time period may be different. The frequency of the signals is not synchronized, and the signals can be considered to have frequency offsets at different times, also referred to as offset speeds (drift). It should be understood that the offset speed refers to the rate at which the offset between the two clocks changes over time, indicating the magnitude of the clock offset change over time. The unit time may be seconds or microseconds, etc.

Phase synchronization is based on frequency synchronization, where the two time differences of the signal remain unchanged. It is also understood that the phase is adjusted on the basis of frequency synchronization so that the phase tracks to the reference phase. Similar to frequency synchronization, phase synchronization does not require that the phase of the signal coincide with the reference phase at the start time. For example, the phase of the signal a at the first time is θ1, the phase of the signal B at the second time is θ2, and the phase of the signal a at the first time is θ1, and the phase of the signal B at the second time is θ2. The first time and the second time may be different if θ1 and θ2 are different.

2) Synchronous ethernet (synchronization ethernet, syncE) is a technique for clock synchronization. SyncE refers to that a receiving end recovers a clock of a transmitting end from a serial data code stream through an Ethernet physical layer (PHY) chip, so that clock synchronization is realized. For ease of understanding, please refer to fig. 1, which is a schematic diagram of a synchronous ethernet. Fig. 1 illustrates an example in which a network includes a device 1 and a device 2, where the device 1 is a transmitting end and the device 2 is a receiving end. As can be seen from fig. 1, the transmitting end and the receiving end both comprise physical layer chips, the transmitting end further comprises a clock 1, and the transmitting end is externally connected with a clock source 1; the receiving end also comprises a phase-locked loop and is externally connected with a clock source 2. It will be appreciated that since SyncE has the disadvantage of being relatively noisy in signal, noise needs to be handled by the phase locked loop.

The transmitting end transmits the serial data code stream to the receiving end through the physical layer chip, and the receiving end recovers the clock of the transmitting end according to the serial data code stream. It should be appreciated that the external clock source 1 may provide a reference time for the sender. Similarly, the external clock source 2 provides a reference time for the receiving end. The receiving end can adjust the local clock according to the clock of the sending end and the external clock source 2. The adjusted local clock can be regarded as a system clock of the receiving end, and the receiving end can perform service transmission according to the system clock. For example, the service module at the receiving end may acquire the system clock and transmit the service according to the system clock. For another example, the physical layer chip of the receiving end may acquire a system clock, and send a serial data code stream to the transmitting end according to the system clock.

3) The clock synchronization method based on the time stamp, namely, the device needing synchronization can send a first message and a first sending time of the first message to the synchronized device, the synchronized device records a first receiving time for receiving the first message, and sends a second message and a first receiving time and a second sending time of the second message to the device needing synchronization. And the equipment needing to be synchronized receives the second message and records the second receiving time of the second message. The device requiring synchronization can calculate clock information according to the first sending time, the first receiving time, the second sending time and the second receiving time, so as to adjust the local clock. Wherein the first transmit time and the first receive time may be considered as a set of unidirectional time stamps and the second transmit time and the second receive time as a set of unidirectional time stamps. That is, the unidirectional timestamp includes a transmission timestamp of a message recorded by a message transmitted from the transmitting end to the receiving end, and a reception timestamp of the message received by the receiving end.

For ease of understanding, please refer to fig. 2, the device to be synchronized is device 1, the synchronized device is device 2, the first transmission time is TXa, the first reception time is RXb, the second transmission time is txb, and the second reception time is rxa. Let the reference clock be t, the offset of the device 1 compared to t be Δt _a The offset of the device 2 compared to t is Δt _b Then the clock t of the device 1 is known _a ＝t+Δt _a Clock t of device 2 _b ＝t+Δt _b Clock offset=Δt between device 1 and device 2 _b -Δt _a . Assuming that the single Delay (OWD) of the message sent by device 1 to device 2 and the message sent by device 2 to device 1 are the same, device 1 may calculate:

the device 1 can adjust the local clock based on OWD and offset, e.g. t can be set _a Adjusted to t _b +offset-OWD, or, t _b +offset-OWD, thereby achieving clock synchronization of device 1 and device 2.

4) In the embodiments of the present application, the number of nouns, unless otherwise indicated, means "a singular noun or a plural noun", i.e. "one or more". "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. For example, A/B, means: a or B. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, or c, represents: a, b, c, a and b, a and c, b and c, or a and b and c, wherein a, b, c may be single or plural.

The ordinal terms such as "first," "second," and the like in the embodiments of the present application are used for distinguishing a plurality of objects, and are not used for limiting the size, content, sequence, timing, priority, importance, and the like of the plurality of objects. For example, the first message and the second message may be the same message or different messages, and the names do not indicate the content, priority, importance, or the like of the two messages. In addition, the numbers of the steps in the embodiments described in the present application are only for distinguishing different steps, and are not used for limiting the sequence of the steps.

In a distributed network, each node needs clock synchronization in order to ensure normal interaction of each node. For example, any one node may implement clock synchronization with other nodes based on SyncE technology, or may implement clock synchronization with other nodes based on a time-stamp clock synchronization method. However, as can be seen from fig. 1, implementing clock synchronization based on the SyncE technology requires that both the transmitting end and the receiving end are externally connected with clock sources, so as to improve accuracy of clock synchronization as much as possible, which obviously increases deployment cost. In addition, the receiving end needs to be provided with a phase-locked loop for processing noise, which requires the receiving end to be provided with a crystal oscillator with higher stability, thereby increasing the hardware cost of the receiving end. Moreover, syncE requires hop-by-hop deployment of devices, which also increases deployment costs and the cost of managing deployed devices. The clock synchronization method based on the time stamp of fig. 2 requires the receiving end to feed back the message to the transmitting end, which requires that PTP be deployed in the device to be synchronized, that is, that the device to be synchronized has PTP function. Nodes without PTP deployment cannot achieve clock synchronization, limiting the number of nodes in the network.

In view of this, a technical solution of the embodiment of the present application is provided. In the scheme, any clock in the network can be used as a reference clock, so that an external clock source is not needed, and the deployment cost and the management cost of the equipment are reduced. A device selected as a reference clock (may also be referred to as a device to be clock-synchronized) may send a message carrying a transmission time to a device requiring clock synchronization, which may implement clock synchronization with the device to be clock-synchronized based on a clock synchronization method of a time stamp. For example, the clocked device may send a first message carrying the sending time to a plurality of devices, and any of the plurality of devices may calculate a clock offset, a frequency offset, a phase difference, etc. of the clocked device as compared to the clock offset, the frequency offset, the phase difference, etc. of the clocked device based on the time of receiving the first message and the sending time of the first message, thereby achieving clock synchronization with the clocked device. Because any node in the network can be used as a reference clock, the clock synchronization of each node in the network can be realized by the method. And the equipment which does not need clock synchronization feeds back the message to the equipment which is synchronized by the clock, so that the equipment which needs clock synchronization does not need to deploy PTP, namely the requirement on the function of the equipment which needs clock synchronization is lower, thereby enabling the network to deploy more nodes.

In order to make the objects, technical solutions and advantages of the embodiments of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.

The technical solution provided by the embodiment of the present application may be applied to a system that needs clock synchronization, such as a distributed network (hereinafter, this is taken as an example). Fig. 3 is an application scenario of the embodiment of the present application. In fig. 3, n+1 clients are included, and the clock of any one of the n+1 clients is selected as the reference clock. For ease of distinction, the clients selected as reference clocks are referred to as clients S, then the remaining clients are, for example, clients 1-n. It will also be understood that client S is a device that is clock synchronized, and any of clients 1-n may achieve clock synchronization based on the clock of client S. The scheme provided by the embodiment of the application is described below with the scenario shown in fig. 3. The various clients in fig. 3 may interact with information through a network. The network here may be a medium access control (media access control, MAC) layer or a radio link control (radio link control, RLC) layer, or may be a radio resource control (radio resources control, RRC) layer. Among them, the MCA layer/RLC layer may also be referred to as an L2 layer, and the RRC layer may also be referred to as an L3 layer.

An embodiment of the present application provides a clock synchronization method, please refer to fig. 4, which is a flowchart of the method. In the following description, this method is taken as an example applied to the network architecture shown in fig. 3. The first device described below is, for example, any one of the clients 1 to n shown in fig. 3, and the second device described below is, for example, the client S shown in fig. 3.

S401, the second device sends a plurality of first messages, wherein each first message carries a first time, and the first time is the sending time of the corresponding first message.

The second device, which is the reference clock source, may send a plurality of first messages for use by devices requiring clock synchronization (first device is exemplified herein) to achieve clock synchronization with the second device. The first message carries the sending time of the first message. The first device receives the plurality of first messages, and clock deviation, phase deviation, frequency deviation and the like between the first device and the second device can be determined based on the sending time and the receiving time of each first message, so that clock synchronization with the second device is realized. It is understood that the time of transmission and the time of reception of a first message is a set of unidirectional time stamps. From this point of view, it is also considered that the first device may achieve clock synchronization with the second device based on multiple sets of unidirectional time stamps with the second device. For convenience of description, the following takes M first messages as an example, where M is an integer greater than or equal to 2. The sending time of the first message is called a first time, and the time of the first device receiving the first message is called a second time. It can be understood that the M first messages correspond to the M first times and the M second times, where the M first times and the M second times correspond to each other one by one. A set of one-way timestamps includes a first time and a second time corresponding to the first time.

The second device may determine the first time on the control plane or may determine the first time on the data plane. It is also understood that the second device may generate a transmission time stamp (first time) on the control plane or may generate a transmission time stamp (first time) on the data plane when transmitting the first message. For ease of understanding, the process of determining the first time by the second device is described below with reference to the accompanying drawings.

Please refer to fig. 5, which is a diagram illustrating a time stamp generated on a data plane. In fig. 5, the digital time is a Real Time Clock (RTC) provided by a clock board, such as RTC1 in fig. 5. The time of the control plane is the RTC provided by the crystal oscillator, for example, RTC2. The second device may identify a first message, which arrives at the physical port with a time stamp, i.e. a first time (RTC 1), generated by a PTP hardware clock (PTP hardware clock, PHC). The RTC1 may be stored in a register or may be placed in the load field of the first message. It will be appreciated that the first time of each first message may be stored in a register, with the first time of any one first message being read prior to overwriting.

Please refer to fig. 6, which is a diagram illustrating the generation of a time stamp at the control plane. In fig. 6, the time of the control plane is RTC provided by the crystal oscillator, for example, RTC2. Before the second device sends the first message, the second device may acquire the first time from the user state by using a system call acquire time function "clock_gettime", and then place the first time in a load field of the first message. It should be appreciated that the user mode is capable of running a program at the user layer in the operating system.

The embodiment of the application does not limit whether the first time is generated on the control plane or the first time is generated on the data plane. The first time can be generated on the control plane or the data plane according to the synchronous precision. For example, the synchronization accuracy requires nanoseconds, then the first time may be selectively generated at the data plane. The synchronization accuracy requires microseconds, then the first time may be selectively generated at the control plane.

Generating the time stamp on the data plane is more accurate and reliable than on the control plane. Therefore, in the embodiment of the application, the second device can generate the first message on the control plane and send the first message through the data plane port, thereby improving the precision of clock synchronization.

In a possible implementation, the second device may broadcast the first message or multicast the first message. I.e. the first message is sent in broadcast or multicast. In this way, any device in the network where the second device is located can take the clock of the second device as a reference clock, so that clock synchronization of all devices in the network can be realized. The second device may be any device in the network, from this point of view, any device in the network may broadcast or multicast the first message, and for the device receiving the first message, the clock of any device is used as a reference clock, so that no external reference clock source is required, and clock synchronization of each device in the network can also be achieved.

For example, please refer to fig. 7, which is a schematic diagram of an application scenario in an embodiment of the present application, fig. 7 illustrates a first message broadcast by a second device. The second device in fig. 7, i.e. the reference clock, any of clients 1-n may be directly or indirectly connected to the second device. The first device is any one of clients 1-n. For example, the second device may obtain the first time on the control plane, encapsulate the first message carrying the first time, and send the first message to the broadcast address through the data plane port. Any of clients 1-n may receive the first message. If the second device broadcasts a plurality of first messages, the second device can periodically acquire the first time on the control plane and package the first messages carrying the first time. Wherein the second device may broadcast locally, i.e. without being routed, the broadcast address may be a local address, e.g. 255.255.255.255. Alternatively, the second device may also broadcast across routes, e.g., the broadcast address may be a subnet address, e.g., 192.168.2.255. Alternatively, the broadcast address may be a full subnet address, e.g., 192.168.0.0. Specifically, as shown in fig. 7, the second device may broadcast the first message carrying the first time to the client 1-client n in the network using the broadcast internet protocol (internet protocol, IP) address and the broadcast MAC destination address. As shown in fig. 7, the broadcast address, i.e., the destination IP, is 192.168.1.255.

Fig. 8 is a schematic diagram of another application scenario in an embodiment of the present application, and fig. 8 illustrates a second device multicasting a first message. The second device in fig. 8, i.e. the reference clock, part of the clients 1-n may be connected directly or indirectly as a group with the second device. The second device may obtain the first time at the control plane, encapsulate the first message carrying the first time, and send the first message to the multicast address through the data plane port. A group of clients identified by a multicast address may receive a first message. Wherein the multicast address may be previously set for a group of clients, for example, the multicast address may range from 224.0.0.0 to 239.255.255.255.

Specifically, the second device may multicast the first message carrying the first time to a group of clients using the IP address and the broadcast MAC destination address. As shown in fig. 8, the destination IP, which is the multicast address, is 224.0.0.10. The second device may send the first message to the multicast address using a multicast routing algorithm to effect delivery of the first message in the wide area network. For example, the multicast routing algorithm may be based on a stand alone multicast protocol (protocol independent multicast, PIM) or may be based on bit index display replication (bit index explicit replication, BIER). As can be appreciated, PIM multicasting refers to building a multicast distribution tree, and performing reverse path forwarding (reverse path forwarding, RPF) inspection on multicast messages by using a unicast routing table to generate a multicast routing table for forwarding the multicast messages. BIER multicast refers to a bit index based display copy routing protocol, which is divided into three layers of Overlay, BIER and Underlay, and does not need to build a multicast distribution tree or store any multicast stream state by an intermediate node.

S402, the first device determines deviation between the clock of the first device and the clock of the second device according to a plurality of first times and a plurality of second times corresponding to a plurality of first messages.

When the first device receives each first message sent by the second device, a receiving timestamp (referred to herein as a second time) is generated according to the clock of the first device itself. Taking the second device to send M first messages as an example, for the first device, M first times in the M first messages and M second times corresponding to the M first times one to one may be obtained. I.e. the first device may obtain M sets of time stamps, one set of time stamps comprising the transmission time of a first message by the second device and the reception time of the first message by the first device.

The first device may determine a deviation between the clock of the first device and the clock of the second device from the M sets of time stamps. The deviation may be a clock deviation, a frequency deviation, a phase deviation, or at least two of the three deviations. That is, the first device may determine at least one of a clock bias, a frequency bias, or a phase bias between the clock of the first device and the clock of the second device according to the M sets of time stamps. In a possible implementation, the first device may periodically determine a deviation from the clock of the second device according to the time of transmission and the time of reception of the received plurality of first messages. Alternatively, the first device may determine, under passive triggering, a deviation from the clock of the second device according to the time of sending and the time of receiving the plurality of first messages.

The following describes how the first device determines a deviation between the clock of the first device and the clock of the second device.

The first device may map M sets of timestamps to a two-dimensional coordinate system, wherein a set of timestamps of the plurality of sets of timestamps includes a first time and a corresponding fourth time, the fourth time being a time difference between a second time and the first time of a message. The two-dimensional coordinates are on the abscissa at the first time and on the ordinate at the fourth time. It will be appreciated that the M sets of time stamps are discrete in a two-dimensional coordinate system, and that the overall tilt trend of the M sets of time stamps may characterize the frequency deviation drift between the clock of the first device and the clock of the second device. Therefore, a straight line can be determined in the M sets of time stamps, and the slope of the straight line is the frequency deviation drift between the clock of the first device and the clock of the second device. For convenience of description, this straight line is referred to herein as a first straight line. The first device determines a frequency deviation drift between the clock of the first device and the clock of the second device, essentially solving a first straight line.

The first device may determine the first straight line based on an objective function, which may be considered as a function that enables M sets of time stamps within the two-dimensional coordinate system to be located on the same side of the first straight line. For example, the objective function satisfies:

s.t.ax _i +b-y _i Epsilon is less than or equal to epsilon, wherein x _i ＝t _1,i ，y _i ＝t _2,i -t _1,i Epsilon is a preset parameter, t _1,i And t _2,i -t _1,i Is the i-th group timestamp. Solving for a and b results in a first line, i.e., first line y=ax+b.

In order to obtain better a and b, i.e. to determine the optimal first straight line, M sets of timestamps may also be denoised when solving the first straight line. For example, each time stamp point (t _1,i ,t _2,i -t _1,i ) The distance to the calculated first straight line, a distance sequence (i.e., comprising M distances) is obtained. The median absolute deviation discrimination method can be adopted to screen and remove noise points in the distance sequence until a tends to a stable value, thus obtainingAnd obtaining an optimal first straight line. It will be appreciated that the median absolute deviation discrimination method, i.e. for sequence x ₁ ,…,x _n And (3) recording: MAD: =media (x _i Media (x)), if |x _i -median(x)|>4.4478 ×MAD, then x _i And is regarded as a noise point.

Further, the first device may determine that the first line has a value of phase offset on a set of time stamps having a largest abscissa among the M sets of time stamps. And taking the value of the first straight line on the group of time stamps with the largest abscissa among the groups of time stamps as the phase deviation offset, and filtering out noise in the message transmission process, thereby supporting the end-to-end deployment of equipment. That is, no other devices need to be deployed between the first device and the second device, i.e., the first device and the second device may communicate directly. In addition, the first device can use the phase deviation offset0 determined by the first device for the first time as a reference value of phase adjustment, so that clock phase deviation can be maintained, and clock synchronization failure caused by accumulation of the phase deviation offset or jump of the phase deviation is avoided.

S403, the first device calibrates the clock of the first device based on a deviation between the clock of the first device and the clock of the second device.

The first device may compensate the frequency of the clock of the first device according to the frequency deviation drift, thereby achieving frequency synchronization with the clock of the second device. In the embodiment of the application, the first device can compensate the frequency of the clock of the first device according to the ratio of the frequency deviation drift to the clock frequency. For convenience of description, the ratio of the frequency deviation drift to the clock frequency is referred to herein as a frequency compensation value. It will be appreciated that the frequency offset will affect the time increment value of the clock after each receipt of the pulse signal, i.e. the first device will increment by 1/clock frequency + frequency offset after each receipt of the pulse signal. Thus, the clock of the first device may be calibrated based on the frequency compensation value. And the frequency compensation value is used for calibrating the frequency of the clock of the first equipment, a digital phase-locked loop is not required to be locked, and the requirement on the stability of the crystal oscillator can be reduced, so that the crystal oscillator cost of the first equipment is reduced. The first device uses the first calculated phase offset of 0 as a reference value of the phase adjustment, that is, the phase difference of the first device compared with the clock of the second device is stabilized at offset0.

For example, please refer to fig. 9, which is a schematic diagram of clock synchronization of the first device and the second device. The second device broadcasts a first message carrying the time of transmission. The second device receives the first message, generates a time stamp (first time and second time) at the data plane, and sends the generated time stamp to the control plane. The control plane may determine a deviation between the clock of the first device and the clock of the second device based on the time stamp and send the deviation to the data plane. Fig. 9 is an example of the offset as a frequency offset value. The data plane may compensate the frequency of the clock of the first device according to the frequency compensation value, thereby achieving synchronization with the clock of the second device.

In the embodiment of the application, the equipment needing clock synchronization can realize the clock synchronization with the equipment synchronized with the clock based on a plurality of groups of unidirectional time stamps between the equipment synchronized with the clock. Compared with the clock synchronization method shown in fig. 2, the PTP is deployed without clock synchronization equipment, that is, the functional requirement on equipment needing clock synchronization is lower, so that more nodes can be deployed in the network. In addition, the device to be clock synchronized can be any device in the network, namely any node in the network can be used as a reference clock, so that an external reference clock source is not needed, and the deployment cost can be reduced.

In consideration of the fact that the second device broadcasts or multicasts M first messages, the first device may receive part of the M first messages, so that the first device cannot determine a deviation between the clock of the first device and the clock of the second device according to the received first messages. For example, the second device broadcasts 2 first messages, and the first device receives 1 first message, so that the deviation between the clock of the first device and the clock of the second device cannot be determined.

For this reason, in the embodiment of the present application, after any device in the network receives the first packet, the first packet may be broadcast or multicast to other devices in the network. After receiving the first message broadcast by the second device, the third device in the network may broadcast or multicast the first message. For convenience of description, the third device will hereinafter forward the first message broadcast by the second device, which is referred to as the third device sending the second message. If the first device receives a plurality of second messages from the third device, a deviation between the clock of the first device and the clock of the second device may also be determined based on the first time and the third time respectively corresponding to the plurality of second messages. In this way, even if the first device does not receive a plurality of first messages from the second device, the deviation between the clock of the first device and the clock of the second device can be determined based on a plurality of second messages received from the third device, so as to avoid that the first device cannot determine the deviation between the clock of the first device and the clock of the second device as much as possible.

S404, the third device sends a plurality of second messages, and the first device receives the second messages correspondingly.

The third device may be located in the same network as the first device and the second device. The second device broadcasts or multicasts the first message and the third device may receive the first message from the second device. Similarly to the first device, the third device may also determine a deviation between the clock of the third device and the clock of the second device according to a first time corresponding to the plurality of first messages received from the second device and a time when the first message is received by the third device, respectively. The related content of the deviation between the clock of the first device and the clock of the second device may be specifically determined by referring to the foregoing first device, which is not described herein. It will be appreciated that after the third device determines a deviation between the clock of the third device and the clock of the second device, the third device may also synchronize with the clock of the second device based on the deviation. Thus, the third device can also be used as a reference clock source in the network, and so on, any device in the network can be used as a reference clock, so that an external reference clock is not needed.

In the embodiment of the present application, the third device may further forward the first packet. For example, the third device may broadcast or multicast a second message, the second message carrying the first time. So that the first device in the network may also receive the second message from the third device. Because the third device forwards the first message broadcast or multicast by the second device, even if the first device cannot receive the first message broadcast by the second device, the first device can also learn the first time from the second message received by the third device, so that the deviation between the clock of the first device and the clock of the second device is determined according to the first time corresponding to the second message and the third time for receiving the second message, and the deviation between the clock of the first device and the clock of the second device can be avoided.

It should be noted that, if the first device receives a plurality of first messages from the second device, a deviation between the clock of the first device and the clock of the second device may be determined based on the first time and the second time corresponding to the plurality of first messages, respectively. If the first device receives a plurality of second messages from the third device, a deviation between the clock of the first device and the clock of the second device may also be determined based on the first time and the third time respectively corresponding to the plurality of second messages. In addition, the first device receives the latest message, and can determine the deviation between the clock of the first device and the clock of the second device according to the sending time and the receiving time of the message and by combining the unidirectional timestamp (also called as the historical timestamp) corresponding to the received message. A plurality of first messages, or a plurality of second messages, may be received over a period of time. The first device may determine a deviation between the clocks of the first device and the second device based on the first time and the second time corresponding to the part of the first messages in the received plurality of first messages, respectively, or may determine a deviation between the clocks of the first device and the second device based on the first time and the second time corresponding to the whole of the received first messages, respectively. Similarly, the first device may determine a deviation between the clock of the first device and the clock of the second device based on the first time and the third time corresponding to the part of the second messages in the received plurality of second messages, respectively, and may also determine a deviation between the clock of the first device and the clock of the second device based on the first time and the third time corresponding to all of the received second messages, respectively.

S404 may be executed before S403 or S402. And S404 is an optional step that is not necessarily performed, and is therefore illustrated in fig. 4 by a broken line.

Experiments prove that the deviation between each device determination and the reference clock is stable through the method provided by the embodiment of the application. For example, referring to table 1, a comparison result of a frequency deviation determined based on the method provided by the embodiment of the present application and a frequency deviation determined based on fig. 2, i.e., the bidirectional timestamp, is shown. The larger the linear regression coefficient in table 1, the more stable the deviation between the individual device determination and the reference clock. Table 1 exemplifies two devices. Table 1 takes as an example that two devices are devices in an intranet, i.e. the time stamps involved are physical time stamps. Wherein "IP address"the devices are co-located, e.g., in market A; "IP address"in the same place, e.g., market B;is co-located, for example C market.

TABLE 1

In table 1, the frequency deviation average calculated by the unidirectional timestamp is the frequency deviation average calculated by the method provided by the embodiment of the present application, and the frequency deviation average calculated by the bidirectional timestamp is the frequency deviation average calculated by the method shown in fig. 2. As can be seen from table 1, the frequency deviation calculated by the method provided by the example of the present application is more stable.

For another example, referring to table 2, a comparison result of the frequency deviation determined based on the method provided by the embodiment of the present application and the frequency deviation determined based on fig. 2, i.e., the bidirectional timestamp, is also shown. Table 2 differs from table 1 in that the devices in table 2 are devices in a virtual network, i.e. the time stamps involved are virtual time stamps in the user state. Wherein "IP address"in the same place, e.g., market B;is co-located, for example C market.

TABLE 2

In table 2, the frequency deviation average calculated by the unidirectional timestamp is the frequency deviation average calculated by the method provided by the embodiment of the present application, and the frequency deviation average calculated by the bidirectional timestamp is the frequency deviation average calculated by the method shown in fig. 2. As can be seen from table 2, the frequency deviation calculated by the method provided by the example of the present application is more stable.

In the embodiment provided by the application, the method provided by the embodiment of the application is introduced from the angles of interaction among more devices in the setting network respectively from the device needing clock synchronization (namely, the first device) and the device to be clock synchronized (namely, the second device). In order to implement the functions in the method provided by the embodiment of the present application, the first device and the second device may include hardware structures and/or software modules, and implement the functions in the form of hardware structures, software modules, or a combination of hardware structures and software modules. Some of the functions described above are performed in a hardware configuration, a software module, or a combination of hardware and software modules, depending on the specific application of the solution and design constraints.

Communication devices for implementing the above method in the embodiments of the present application are described below with reference to the accompanying drawings.

Fig. 10 is a schematic block diagram of a communication device 1000 according to an embodiment of the present application. The communications apparatus 1000 can include a processing module 1010 and a transceiver module 1020. Optionally, a storage unit may be included, which may be used to store instructions (code or programs) and/or data. The processing module 1010 and the transceiver module 1020 may be coupled with the storage unit, for example, the processing module 1010 may read instructions (codes or programs) and/or data in the storage unit to implement the corresponding method. The above modules may be independently provided, or may be partially or fully integrated.

In some possible implementations, the communications apparatus 1000 can correspondingly implement the actions and functions of the first device in the foregoing method embodiments, where the communications apparatus 1000 can be the first device, a component (e.g., a chip or a circuit) applied to the first device, or a chip or a chipset in the first device or a part of a chip for performing the related method functions.

For example, the communication apparatus 1000 implements a method performed by the first device in the embodiment of the present application. The transceiver module 1020 is configured to receive a plurality of first messages sent by the second device, where each first message carries a first time, and the first time is a sending time of the corresponding first message. The processing module 1010 is configured to determine a deviation between a clock of the communication apparatus 1000 and a clock of the second device according to a plurality of first times and a plurality of second times corresponding to the plurality of first messages, and calibrate the clock of the communication apparatus 1000 based on the deviation, where the plurality of first times and the plurality of second times are in one-to-one correspondence, and one of the plurality of second times is a receiving time of the first message corresponding to one of the plurality of first times.

As an alternative implementation, the transceiver module 1020 is further configured to receive at least one second packet sent by the third device, where each second packet includes the first time of the first packet from the second device. The processing module 1010 is further configured to determine a deviation between the clock of the communication apparatus 1000 and the reference clock of the second device according to at least one first time and at least one third time corresponding to the at least one second message. The at least one first time corresponds to the at least one third time one by one, and one third time in the at least one third time is the receiving time of the second message corresponding to the one third time.

As an alternative implementation, the deviation includes a frequency deviation, and the processing module 1010 determines, according to a plurality of first times and a plurality of second times corresponding to the plurality of first messages, a deviation between a clock of the communication apparatus 1000 and a clock of the second device, including:

mapping a plurality of sets of time stamps to a second coordinate system, wherein one time stamp in the plurality of sets of time stamps comprises a first time and a corresponding fourth time, the two-dimensional coordinate takes the first time as an abscissa, the fourth time as an ordinate, and the fourth time is a difference value between the second time and the first time;

A first line is determined having a slope that is a frequency difference between the clock of the communication apparatus 1000 and the clock of the second device based on an objective function that causes sets of time stamps within a two-dimensional coordinate system to be located on the same side of the first line.

As an alternative implementation, the objective function satisfies:

s.t.ax _i +b-y _i epsilon is less than or equal to epsilon, wherein x _i ＝t _1,i ，y _i ＝t _2,i -t _1,i Epsilon is a preset parameter, t _1,i And t _2,i -t _1,i Is the i-th group timestamp.

As an alternative implementation, the processing module 1010 is further configured to determine a value of the first line on a set of timestamps with largest abscissa among the sets of timestamps as the phase deviation.

As an alternative implementation, the first determined phase deviation by the processing module 1010 is the reference value for the phase adjustment.

As an alternative implementation, the processing module 1010 is specifically configured to:

and determining a frequency deviation value, and calibrating the deviation of the clock according to the frequency deviation value, wherein the frequency deviation value is the ratio of the frequency deviation value to the time frequency.

As an alternative implementation, the first message is sent in a broadcast manner or in a multicast manner.

As an alternative implementation manner, the first message is generated at the control plane and sent through the data plane port.

As an alternative implementation, the first time is determined at the control plane or the data plane.

As an alternative implementation, the communication apparatus 1000 and the second device directly communicate.

It is to be appreciated that the processing module 1010 in embodiments of the present application may be implemented by a processor or processor-related circuit component, and the transceiver module 1020 may be implemented by a transceiver or transceiver-related circuit component or a communication interface.

Fig. 11 is a schematic block diagram of a communication device 1100 according to an embodiment of the present application. The communication apparatus 1100 may be a first device, and may implement the function of the first device in the method provided by the embodiment of the present application. The communication device 1100 may also be a device capable of supporting the first apparatus to implement the corresponding function in the method provided in the embodiment of the present application, where the communication device 1100 may be a chip system. In the embodiment of the application, the chip system can be formed by a chip, and can also comprise the chip and other discrete devices. Specific functions can be seen from the description of the method embodiments described above.

The communication apparatus 1100 includes one or more processors 1101 that are operable to implement or support the communication apparatus 1100 to implement the functionality of the first device in the method provided by the embodiments of the present application. Reference is made specifically to the detailed description in the method examples, and details are not described here. The processor 1101 may also be referred to as a processing unit or a processing module, and may implement certain control functions. The processor 1101 may be a general purpose processor or a special purpose processor, or the like. For example, it includes: a central processor, an application processor, a modem processor, a graphics processor, an image signal processor, a digital signal processor, a video codec processor, a controller, a memory, and/or a neural network processor, etc. The central processor may be used to control the communication device 1100, execute software programs, and/or process data. The different processors may be separate devices or may be integrated in one or more processors, e.g., integrated on one or more application specific integrated circuits.

Optionally, the communication device 1100 includes one or more memories 1102 therein for storing instructions 1104 that can be executed on the processor 1101 to cause the communication device 1100 to perform the methods described in the method embodiments above. The memory 1102 and the processor 1101 may be provided separately or may be integrated, and the memory 1102 and the processor 1101 may be considered to be coupled. The coupling in the embodiments of the present application is an indirect coupling or communication connection between devices, units, or modules, which may be in electrical, mechanical, or other forms for information interaction between the devices, units, or modules. The processor 1101 may cooperate with the memory 1102. At least one of the at least one memory may be included in the processor. The memory 1102 is not necessarily shown in fig. 11 by a broken line.

Optionally, the memory 1102 may also store data. The processor and the memory may be provided separately or may be integrated. In an embodiment of the present application, the memory 1102 may be a nonvolatile memory, such as a hard disk (HDD) or a Solid State Drive (SSD), or may be a volatile memory (volatile memory), for example, a random-access memory (RAM). The memory is any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to such. The memory in embodiments of the present application may also be circuitry or any other device capable of performing memory functions for storing program instructions and/or data.

Alternatively, the communication device 1100 may include instructions 1103 (which may also be sometimes referred to as codes or programs), which instructions 1103 may be executed on the processor, so that the communication device 1100 performs the method described in the above embodiments. The processor 1101 may store data therein.

Optionally, the communication device 1100 may also include a transceiver 1105 and an antenna 1106. The transceiver 1105 may be referred to as a transceiver unit, a transceiver module, a transceiver circuit, a transceiver, an input-output interface, etc. for implementing the transceiver function of the communication device 1100 through the antenna 1106.

The processor 1101 and transceiver 1105 described in the present application may be implemented on an integrated circuit (integrated circuit, IC), analog IC, radio frequency integrated circuit (radio frequency identification, RFID), mixed signal IC, ASIC, printed circuit board (printed circuit board, PCB), or electronic device, etc. The communication apparatus described herein may be implemented as a stand-alone device (e.g., a stand-alone integrated circuit, a mobile phone, etc.), or may be part of a larger device (e.g., a module that may be embedded in another device), and reference may be made specifically to the foregoing description of the terminal device and the network device, which is not repeated herein.

Optionally, the communication device 1100 may also include one or more of the following: wireless communication modules, audio modules, external memory interfaces, internal memory, universal serial bus (universal serial bus, USB) interfaces, power management modules, antennas, speakers, microphones, input/output modules, sensor modules, motors, cameras, or displays, among others. It is to be appreciated that in some embodiments, the communication device 1100 may include more or fewer components, or some components may be integrated, or some components may be split. These components may be hardware, software, or a combination of software and hardware implementations.

The communication device in the above embodiment may be the first device, the circuit, a chip applied to the first device, or other combination devices, components, etc. having the functions of the first device. When the communication apparatus is a first device, the transceiver module may be a transceiver, may include an antenna and radio frequency circuit, etc., and the processing module may be a processor, for example: a central processing module (central processing unit, CPU). When the communication device is a component having the above-mentioned first device function, the transceiver module may be a radio frequency unit, and the processing module may be a processor. When the communication device is a system-on-chip, the communication device may be a field programmable gate array (field programmable gate array, FPGA), an application specific integrated chip (application specific integrated circuit, ASIC), a system on chip (SoC), a CPU, a network processor (network processor, NP), a digital signal processing circuit (digital signal processor, DSP), a microcontroller (micro controller unit, MCU), a programmable controller (programmable logic device, PLD) or other integrated chip. The processing module may be a processor of a system-on-chip. The transceiver module or communication interface may be an input-output interface or interface circuit of a system-on-chip. For example, the interface circuit may be a code/data read-write interface circuit. The interface circuit may be configured to receive code instructions (the code instructions being stored in the memory, being readable directly from the memory, or being readable from the memory via other means) and to transmit to the processor; the processor may be configured to execute the code instructions to perform the methods of the method embodiments described above. For another example, the interface circuit may also be a signal transmission interface circuit between the communication processor and the transceiver.

When the communication device is a chip-like device or circuit, the device may comprise a transceiver unit and a processing unit. The receiving and transmitting unit can be an input and output circuit and/or a communication interface; the processing unit is an integrated processor or microprocessor or integrated circuit.

The embodiment of the application also provides a communication system, in particular to the communication system which comprises at least one first device and at least one second device. Illustratively, the communication system includes a first device and a second device for implementing the relevant functions of fig. 4 described above. Please refer to the related description in the above method embodiment, and the description is omitted here.

Embodiments of the present application also provide a computer-readable storage medium comprising instructions that, when executed on a computer, cause the computer to perform the method performed by the first device of fig. 4.

Embodiments of the present application also provide a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method performed by the first device of fig. 4.

The embodiment of the application provides a chip system, which comprises a processor and a memory, wherein the memory is used for realizing the function of first equipment in the method; or for implementing the functionality of the second device in the method described above. The chip system may be formed of a chip or may include a chip and other discrete devices.

It should be understood that, in various embodiments of the present application, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present application.

Those of ordinary skill in the art will appreciate that the various illustrative logical blocks (illustrative logical block) and steps (steps) described in connection with the embodiments disclosed herein can be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may be essentially contributing or part of the technical solution may be embodied in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a read-only memory (ROM), a RAM, a magnetic disk, or an optical disk, etc., which can store program codes.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A method of clock synchronization, comprising:

the method comprises the steps that first equipment receives a plurality of first messages sent by second equipment, wherein each first message carries a first time, and the first time is the sending time of the corresponding first message;

the first device determines deviation between clocks of the first device and the second device according to a plurality of first times and a plurality of second times corresponding to the plurality of first messages, wherein the plurality of first times and the plurality of second times are in one-to-one correspondence, and one second time in the plurality of second times is the receiving time of the first message corresponding to one first time in the plurality of first times;

the first device calibrates a clock of the first device based on the offset.

2. The method of claim 1, wherein the method further comprises:

The first device receives at least one second message sent by a third device, wherein each second message comprises the first time of the first message from the second device;

the first device determines deviation between a clock of the first device and a reference clock of the second device according to at least one first time and at least one third time corresponding to the at least one second message, wherein the at least one first time and the at least one third time are in one-to-one correspondence, and one third time in the at least one third time is the receiving time of the second message corresponding to the one third time.

3. The method of claim 1 or 2, wherein the deviation comprises a frequency deviation, the first device determining a deviation between a clock of the first device and a reference clock of the second device from the plurality of first times and the plurality of second times, comprising:

the first device maps a plurality of sets of time stamps to a two-dimensional coordinate system, wherein one set of time stamps in the plurality of sets of time stamps comprises a first time and a corresponding fourth time, the two-dimensional coordinate takes the first time as an abscissa, the fourth time as an ordinate, and the fourth time is a difference value between the second time and the first time;

The first device determines a first straight line based on an objective function, wherein a slope of the first straight line is a frequency difference between a clock of the first device and a clock of the second device, and the objective function enables the plurality of groups of time stamps in the two-dimensional coordinate system to be located on the same side of the first straight line.

4. A method according to claim 3, wherein the objective function satisfies:

5. The method of claim 3 or 4, wherein the method further comprises: the first device determines that a value of the first straight line on a group of time stamps with the largest abscissa among the plurality of groups of time stamps is a phase deviation.

6. The method of claim 5, wherein the first device first determines the phase offset as a reference value for phase adjustment.

7. The method of any of claims 3-6, wherein the first device calibrating a clock of the first device based on the bias comprises:

the first device determines a frequency compensation value, wherein the frequency compensation value is the ratio of the frequency difference value to the time frequency;

The first device calibrates the frequency of the clock according to the frequency compensation value.

8. The method according to any of claims 1-7, wherein the first message is sent in a broadcast manner or in a multicast manner.

9. The method according to any of claims 1-8, wherein the first message is generated at a control plane and sent through a data plane port.

10. The method of any of claims 1-9, wherein the first time is determined at a control plane or a data plane.

11. The method of any of claims 1-10, wherein the first device and the second device communicate directly.

12. A communication device, comprising a processing module and a transceiver module;

the receiving and transmitting module is used for receiving a plurality of first messages sent by the second equipment, wherein each first message carries a first time, and the first time is the sending time of the corresponding first message;

the processing module is configured to determine a deviation between a clock of the communication device and a clock of the second device according to a plurality of first times and a plurality of second times corresponding to the plurality of first messages, and calibrate the clock of the communication device based on the deviation, where the plurality of first times and the plurality of second times are in one-to-one correspondence, and one of the plurality of second times is a receiving time of the first message corresponding to one of the plurality of first times.

13. The communications apparatus of claim 12, wherein the transceiver module is further configured to receive at least one second message sent by a third device, each second message comprising the first time of the first message from the second device;

the processing module is further configured to determine a deviation between a clock of the communication device and a reference clock of the second device according to at least one first time and at least one third time corresponding to the at least one second message, where the at least one first time and the at least one third time are in one-to-one correspondence, and one third time in the at least one third time is a receiving time of the second message corresponding to the one third time.

14. The communication apparatus according to claim 12 or 13, wherein the deviation comprises a frequency deviation, and the processing module determines the deviation between the clock of the communication apparatus and the clock of the second device according to a plurality of first times and a plurality of second times corresponding to the plurality of first messages, comprising:

A first line is determined based on an objective function having a slope that is a frequency difference between a clock of the communication device and a clock of the second apparatus, the objective function being such that the plurality of sets of time stamps within the two-dimensional coordinate system are located on a same side of the first line.

15. The communications apparatus of claim 14, wherein the objective function satisfies:

16. The communication apparatus according to claim 14 or 15, wherein the processing module is further configured to determine a value of the first line as a phase deviation at a set of time stamps having a largest abscissa among the plurality of sets of time stamps.

17. The communication apparatus of claim 16, wherein the first determined phase offset by the processing module is a reference value for phase adjustment.

18. The communication device according to any of the claims 14-17, wherein the processing module is specifically configured to:

determining a frequency deviation value, wherein the frequency deviation value is the ratio of the frequency deviation value to time frequency;

and calibrating the deviation of the clock according to the frequency compensation value.

19. The communication device according to any of claims 12-18, wherein the first message is sent in a broadcast manner or in a multicast manner.

20. The communication device according to any of claims 12-19, wherein the first message is generated at a control plane and sent through a data plane port.

21. The communication device according to any of claims 12-20, wherein the first time is determined at a control plane or a data plane.

22. The communication apparatus according to any of claims 12-21, wherein the communication apparatus and the second device communicate directly.

23. A communication device, characterized in that the communication device comprises a processor and a memory for storing a computer program, the processor being adapted to execute the computer program stored on the memory, such that the communication device performs the method according to any of claims 1-11.

24. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program which, when executed by a computer, causes the computer to perform the method according to any of claims 1-11.

25. A computer program product, characterized in that the computer program product stores a computer program which, when executed by a computer, causes the computer to perform the method according to any of claims 1-11.