CN117117000A

CN117117000A - Transverse SiC-JFET device and preparation method thereof

Info

Publication number: CN117117000A
Application number: CN202311028203.7A
Authority: CN
Inventors: 张晓宇; 岳丹诚; 王畅畅
Original assignee: Suzhou Huatai Electronics Co Ltd
Current assignee: Suzhou Huatai Electronics Co Ltd
Priority date: 2023-08-15
Filing date: 2023-08-15
Publication date: 2023-11-24

Abstract

The embodiment of the application provides a transverse SiC-JFET device and a preparation method thereof. A lateral SiC-JFET device comprising: a substrate; a gate electrode and a drift region which are positioned on the substrate and are sequentially arranged; a gate contact metal compound located over the gate; a gate electrode having a vertical bottom and a lateral top connected laterally above the vertical bottom; the vertical bottom of the gate electrode is located above the gate contact metal compound; the lateral top of the gate electrode covers the edge of the gate electrode. The embodiment of the application solves the technical problem that the transverse electric field of the drift region is too low due to the too high electric field intensity near the grid electrode of the traditional transverse SiC-JFET device.

Description

Transverse SiC-JFET device and preparation method thereof

Technical Field

The application relates to the technical field of semiconductor devices, in particular to a transverse SiC-JFET device and a preparation method thereof.

Background

Junction Field-Effect Transistor (JFET), which is one of the simplest three-port Field-effect transistors, is a voltage-controlled semiconductor device in which a voltage is applied through a Gate (Gate) to control the flow of current from a Drain (Drain) to a Source (Source). The high-frequency power amplifier has the advantages of low noise, small size, high frequency response and the like, is commonly applied to switching devices, power amplifying devices and digital electronic circuits, and meets the requirements of different electronic equipment.

The third generation semiconductor material SiC material has a larger forbidden bandwidth (3.2 eV) than the traditional semiconductor Si material (1.1 eV), has the advantages of high temperature resistance and high pressure resistance, has higher breakdown voltage under the condition of occupying the same chip size and area, has the advantage of high pressure resistance, can be converted into the advantages of chip area and on resistance, reduces the cost, improves the device performance, is suitable for preparing power devices, has the advantage of high response speed, and is suitable for preparing radio frequency devices, meanwhile, the saturation drift speed of the SiC material is twice that of the Si material.

Fig. 1 is a conventional structure of a lateral JFET device. As shown in fig. 1, a substrate 1, a p-type epitaxial layer 2, an n-type drift region 3, a p+ -type semiconductor layer 4, an n+ -type source region layer 5, a p+ -type gate region layer 7, an n+ -type drain region layer 9, a source electrode 10, a gate electrode 11, a drain electrode 12, and an oxide layer 13. Under breakdown conditions, the grid electrode is applied with negative voltage to turn off, the potential of the drain end is raised, the voltage drop is mainly borne by the N-type drift region 3 and the P+ type grid region layer 7 of the transverse JFET device, an electric field peak value exists at a pn junction near the grid end in the electric field intensity, and an electric field peak value also exists in the N-type drift region 3 and the N+ type drain region layer 9 near the drain end. Along with the lifting of the potential of the drain terminal, the electric field at the junction of the N-type drift region close to the edge of the grid and the top P-type grid, and the electric field of the N-type drift region 3 and the N+ type drain region layer 9 close to the drain terminal are lifted until the critical breakdown field strength, at the moment, the electric field strength in the N-type drift region 3 is not lifted to a higher level, the lateral electric field is unevenly distributed, the breakdown voltage of the JFET device is low, and the power and the radio frequency performance of the SiC lateral JFET device are limited.

Therefore, the conventional lateral SiC-JFET device has an excessively high electric field strength near the gate, and the drift region has an excessively low lateral electric field, which is a technical problem that needs to be solved by those skilled in the art.

The above information disclosed in the background section is only for enhancement of understanding of the background of the application and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.

Disclosure of Invention

The embodiment of the application provides a transverse SiC-JFET device and a preparation method thereof, which are used for solving the technical problem that the transverse electric field of a drift region is too low due to too high electric field intensity near a grid electrode of the traditional transverse SiC-JFET device.

According to a first aspect of an embodiment of the present application, there is provided a lateral SiC-JFET device comprising:

a substrate;

a grid electrode and a drift region which are positioned on the substrate and are sequentially arranged;

a gate contact metal compound located over the gate;

a gate electrode having a vertical bottom and a lateral top connected laterally above the vertical bottom; the vertical bottom of the gate electrode is located above the gate contact metal compound; the lateral top of the gate electrode covers the edge of the gate electrode.

According to a second aspect of the embodiment of the present application, there is provided a method for manufacturing a lateral SiC-JFET device, including the steps of:

forming a grid electrode and a drift region which are sequentially arranged on a substrate;

forming a gate contact metal compound over the gate;

forming a gate electrode having a vertical bottom and a lateral top laterally connected above the vertical bottom; the vertical bottom of the gate electrode is located above the gate contact metal compound; the lateral top of the gate electrode covers the edge of the gate electrode.

By adopting the technical scheme, the embodiment of the application has the following technical effects:

the on-off of the lateral SiC-JFET device of the embodiment of the application is realized by voltage variation between a source electrode and a grid electrode 7. The lateral top of the gate electrode 17 covers the edge of the gate electrode 7, i.e. the lateral top of the gate electrode 17 passes over the edge of the gate electrode 7, so that when the lateral SiC-JFET device is turned off, the electric field strength at the junction of the drift region 8 and the gate electrode 7 can be suppressed, and at the same time the electric field strength near the position in the drift region corresponding to the edge of the lateral top of the gate electrode 17 can be raised, so that the electric field strength in the drift region uniformly decreases from the gate electrode 7 to the drain electrode 10. I.e. the electric field strength within the drift region, in particular at the junction of the drift region 8 and the gate 7, is evenly distributed such that the peak value of the electric field is suppressed at the junction of the drift region 8 and the gate 7. According to the transverse SiC-JFET device provided by the embodiment of the application, the electric field intensity in the drift region 8 is uniformly distributed, and the peak value of the electric field at the junction of the drift region 8 and the grid electrode 7 is reduced, so that the breakdown voltage of the transverse SiC-JFET device is higher under the condition that the lengths of the drift regions are the same; the size of the drift region is smaller under the condition that the breakdown voltage of the lateral SiC-JFET device is unchanged, so that the on-resistance of the lateral SiC-JFET device is smaller.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:

FIG. 1 is a schematic diagram of a conventional L-JFET structure;

fig. 2-1 is a schematic diagram of a lateral SiC-JFET device according to an embodiment of the present application;

fig. 2-2 are schematic diagrams of another lateral SiC-JFET device of an embodiment of the present application;

fig. 3 is a schematic diagram illustrating a step one of a method for fabricating a lateral SiC-JFET device according to an embodiment of the present application;

fig. 4 is a schematic diagram illustrating a completion step two of a method for fabricating a lateral SiC-JFET device according to an embodiment of the present application;

fig. 5 is a schematic diagram illustrating a third implementation step of a method for fabricating a lateral SiC-JFET device according to an embodiment of the present application;

fig. 6 is a schematic diagram of a completion step four of a method for fabricating a lateral SiC-JFET device according to an embodiment of the present application;

fig. 7 is a schematic diagram illustrating a completion step five of a method for fabricating a lateral SiC-JFET device according to an embodiment of the present application.

Reference numerals:

a substrate 1, a P-type epitaxial layer 2, an N-type epitaxial layer 3, a P+ -type semiconductor layer 4,

an N+ type source region layer 5, a P+ type gate region layer 7, an N+ type drain region layer 9, a source electrode 10, a gate electrode 11,

a drain electrode 12 and an oxide layer 13;

the embodiment of the application comprises the following steps:

a substrate 1, an epitaxial layer 2, a source 3, a first source contact region 4, a channel region 5,

a second source contact region 6, a gate electrode 7, a drift region 8, a drain implant region 9, a drain electrode 10,

the layer of oxide 11 is formed of a silicon oxide,

drain contact metal compound 12-1, source contact metal compound 12-2, gate contact metal compound 12-3,

the drain electrode 13 is provided with a drain electrode,

drain contact via 14-1, source contact via 14-2, gate contact via 14-3,

the back hole 15 is grounded,

a gate electrode 17 which,

drain metal layer 18-1, source metal layer 18-2, and gate metal layer 18-3.

Detailed Description

In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following detailed description of exemplary embodiments of the present application is provided in conjunction with the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present application and not exhaustive of all embodiments. It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other.

Example 1

As shown in fig. 2-1 and 2-2, the lateral SiC-JFET device of the embodiment of the present application includes:

a substrate;

a gate electrode 7 and a drift region 8 which are positioned above the substrate and are sequentially arranged;

a gate contact metal compound 12-3 located above the gate 7;

a gate electrode 17, the gate electrode 17 having a vertical bottom and a lateral top laterally connected above the vertical bottom; the vertical bottom of the gate electrode is located above the gate contact metal compound 12-3; the lateral top of the gate electrode 17 covers the edge of the gate electrode 7, so as to lower the electric field intensity at the junction of the drift region 8 and the gate electrode 7 when the lateral SiC-JFET device is turned off, and raise the electric field intensity near the position corresponding to the edge of the lateral top of the gate electrode 17 in the drift region 8, so that the electric field intensity is uniformly distributed in the drift region.

Specifically, the gate electrode 17 is a gate electrode having a T-shaped cross section.

In practice, as shown in FIGS. 2-1 and 2-2, the lateral SiC-JFET device further comprises:

a channel region 5 above the substrate 1 and below the gate 7;

and a drain electrode 10 located in the drift region 8 and spaced apart from the gate electrode 7.

As shown in fig. 2, the gate electrode 17 has the following dimensional requirements:

first, the dimension of the vertical bottom of the gate electrode 17 is limited by the gate contact metal compound 12-3, and the dimension of the vertical bottom of the gate electrode 17 is smaller than the dimension of the gate contact metal compound 12-3.

Second, the edge of the lateral top of the gate electrode 17 must be spaced apart from the edge of the drain electrode 10. I.e. the edge of the lateral top of the gate electrode 17 cannot go deep into the region of the drain electrode 10. The reason is that:

the electric field strength at the corresponding position of the lateral top edge of the gate electrode 17 is increased. If the electric field goes deep into the drain electrode 10, the originally high electric field near the drain electrode 10 (i.e. at the junction of the drift region and the drain electrode) increases, so that the electric field near the drain electrode is higher, the electric field in the drift region is lower, the electric field is unevenly distributed, and the breakdown voltage decreases.

As an alternative, a space is maintained between the edge of the lateral top of the gate electrode 17 and the edge of the drain electrode 10.

As an alternative, the lateral top of the gate electrode 17 crosses the channel region 5 by a length less than or equal to the distance between the channel region 5 and the drain electrode 10.

In practice, as shown in fig. 2-2, the lateral SiC-JFET device further includes:

a drain contact metal compound 12-1 located above the drain electrode 10;

a drain electrode 13, the drain electrode 13 having a vertical bottom and a lateral top laterally connected above the vertical bottom; the vertical bottom of the drain electrode is located above the drain contact metal compound 12-1;

wherein the lateral top of the drain electrode 13 covers the edge of the drain electrode 10, so as to lower the electric field intensity at the junction of the drift region 8 and the drain electrode 10 when the lateral SiC-JFET device is turned off, and raise the electric field intensity near the position corresponding to the edge of the lateral top of the drain electrode 13 in the drift region 8, so that the electric field intensity is uniformly distributed in the drift region;

there is a space between the edge of the lateral top of the drain electrode 13 and the edge of the lateral portion of the gate electrode.

The switching on and off of the lateral SiC-JFET device is achieved by a voltage variation between the source and gate 7. The lateral top of the drain electrode 13 covers the edge of the drain electrode 10, i.e. the lateral top of the drain electrode 13 passes over the edge of the drain electrode 10, so that when the lateral SiC-JFET device is turned off, the electric field strength at the junction of the drift region 8 and the drain electrode 10 can be suppressed, and at the same time, the electric field strength near the position corresponding to the edge of the lateral top of the drain electrode 13 in the drift region can be raised, so that the electric field strength in the drift region uniformly decreases from the gate 7 to the drain electrode 10. I.e. the electric field strength within the drift region, in particular at the junction of the drift region 8 and the drain 10, is evenly distributed such that there is no electric field peak at the junction of the drift region 8 and the drain 10. According to the transverse SiC-JFET device provided by the embodiment of the application, the electric field intensity in the drift region 8 is uniformly distributed, and no electric field peak value exists at the junction of the drift region 8 and the drain electrode 10, so that the breakdown voltage of the transverse SiC-JFET device is higher under the condition that the lengths of the drift regions are the same; the size of the drift region is smaller under the condition that the breakdown voltage of the lateral SiC-JFET device is unchanged, so that the on-resistance of the lateral SiC-JFET device is smaller.

Specifically, as shown in fig. 2-1, the drain electrode 13 has the following dimensions:

first, the dimension of the vertical bottom of the drain electrode 13 is limited by the drain contact metal compound 12-1, and the dimension of the vertical bottom of the drain electrode 13 is smaller than the dimension of the drain contact metal compound 12-1.

Second, the edge of the lateral top of the drain electrode 13 must be kept spaced from the edge of the channel region 5. I.e. the edge of the lateral top of the drain electrode 13 cannot protrude into the extent of the channel region 5. The reason is that:

the electric field strength at the corresponding position of the lateral top edge of the drain electrode is increased. If the electric field is deep into the channel region, the original high electric field near the channel region (namely the junction of the drift region and the grid electrode) is higher, so that the electric field near the grid electrode is higher, the electric field in the drift region is lower, the electric field is unevenly distributed, and the breakdown voltage is reduced.

Specifically, the drain electrode 13 is a T-shaped drain electrode in cross section.

As an alternative, the lateral top of the drain electrode 13 crosses the length of the drain electrode 10 less than or equal to the distance between the drain electrode 10 and the channel region 5.

a drain implant region 9 located under the drain 10;

wherein the lateral top of the drain electrode 13 covers the edge of the drain implant region 9 and protrudes into position above the drift region 8.

The concentration of the drain implant region 9 is lower than the concentration of the drain 10. The lateral top of the drain electrode 13 covers the edge of the drain injection region 9, so that when the lateral SiC-JFET device is turned off, the electric field intensity at the junction of the drift region 8 and the drain injection region 9 can be reduced, and at the same time, the electric field intensity near the position corresponding to the edge of the lateral top of the drain electrode 13 in the drift region can be raised, so that the electric field intensity in the drift region uniformly decreases from the gate 7 to the drain 10.

Specifically, the length of the top portion of the drain electrode 13 across the drain implant region 9 is less than or equal to the distance between the drain implant region 9 and the channel region 5.

Specifically, the drain implant region 9 is stepped, surrounding the bottom and sides of the drain 10.

In practice, as shown in FIGS. 2-1 and 2-2, the substrate comprises:

a substrate 1, wherein the substrate is an N+ substrate;

an epitaxial layer 2 is provided over the substrate from bottom to top.

The N+ substrate is a mature product of mass production, has higher precision and lower cost, and is suitable for the development of lateral SiC-JFET device products.

As another alternative, the base of the lateral SiC-JFET device may also be a high-resistance SiC substrate, epitaxial layer 2. The substrate is a high-resistance SiC substrate and the transverse SiC-JFET device of the epitaxial layer 2, and other structures are consistent with the transverse SiC-JFET device of which the substrate is an N+ substrate and the epitaxial layer 2.

High-resistance SiC substrates, although not having high mass productivity at present, result in slightly high cost, have excellent performance of lateral SiC-JFET devices with high-resistance SiC substrates, and are also an important direction for the development of lateral SiC-JFET device products. With the reduction of the cost of the high-resistance SiC substrate, the lateral SiC-JFET devices of the high-resistance SiC substrate are increasing.

As another alternative, the base is a high-resistance SiC substrate.

a source electrode 3 and the drift region 8 which are positioned above the substrate and are arranged in sequence;

the first source contact region 4, the second source contact region 6 and the channel region 5 are sequentially arranged above the source, and the channel region 5 and the drift region 8 are closely arranged;

the channel region 5 and the drift region 8 form the channel region 5 and the drift region 8 with independent structures through independent processes, so that the channel region 5 can be independently adjusted to have the on-off characteristics of the lateral SiC-JFET device, and the drift region 8 can be independently adjusted to adjust the breakdown voltage of the lateral SiC-JFET device.

The channel region 5 and the drift region 8 each form the channel region 5 and the drift region 8 each having an independent structure by independent processes, so that the channel region 5 and the drift region 8 can each be independently adjusted. Switching of the lateral SiC-JFET device is achieved by pinching off or opening the channel region by a voltage change between the source 3 and gate 7. The on/off characteristics of the device can be optimized by independently adjusting the implant dose of the channel region. The stress bearing of the lateral SiC-JFET device depends on the fact that the drift region 8 and the reverse biased PN formed by the epitaxial layer 2 are strong, and the breakdown voltage of the reverse biased PN junction formed by the drift region 8 and the epitaxial layer 2 is only related to the size and concentration of the drift region 8 and the epitaxial layer 2. Therefore, the breakdown voltage of the device can be flexibly adjusted by independently adjusting parameters such as the size, the implantation concentration and the like of the drift region 8, and the design of the breakdown voltage from tens of volts to hundreds of volts can be easily realized without being limited by a channel working region.

Specifically, the channel region 5 and the drift region 8 are independent of each other, wherein each independently includes:

1. the channel region 5 is prepared by an independent process, and the drift region 8 is prepared by an independent process; i.e. the channel region 5 and the drift region 8 are not formed by the same process;

2. the channel region 5 is independent of the drift region 8, the drift region 8 is also independent of the channel region 5, and the structures of the drift region and the channel region are not influenced;

3. the parameters of the channel region 5 can be independently controlled according to the requirements of the lateral SiC-JFET device during the preparation, and the parameters of the drift region 8 can also be independently controlled according to the requirements of the lateral SiC-JFET device during the preparation. Parameters include, but are not limited to, size, concentration, and the like.

In practice, when the base comprises a structure of substrate and epitaxial layer 2, the corresponding:

as shown in fig. 2-1 and 2-2, a first gap is provided between the source electrode 3 and the drift region 8; a second gap is formed between the gate 7 and the second source contact region 6 and between the gate 7 and the drift region 8; and the PN junction formed by the drift region 8 and the epitaxial layer 2, the PN junction formed by the drift region 8 and the source electrode 3, and the PN junction formed by the drift region 8 and the gate electrode 7 are broken down in the order of arrangement.

The drift region 8 and the epitaxial layer 2 form a PN junction, the drift region 8 and the source 3 form a PN junction, and the drift region 8 and the gate 7 form a PN junction, i.e., three PN junctions. The size of the first gap and the second gap may affect the breakdown voltage of the lateral SiC-JFET device.

As an example, when the breakdown voltage of the lateral SiC-JFET device of the embodiment of the present application is 150V, the breakdown voltage is sequentially 150-200V,50-100V, and 20-30V according to the results of the current simulation, where the PN junction formed by the drift region 8 and the epitaxial layer 2, the PN junction formed by the drift region 8 and the source 3, and the PN junction formed by the drift region 8 and the gate 7. By adjusting the widths of the first gap and the second gap, the breakdown of the two rear PN junctions can be effectively postponed, and the first PN junction is broken down preferentially.

If there is a greater need in the industry, the breakdown voltage of the lateral SiC-JFET device of the embodiments of the present application may be adjusted, particularly by adjusting the size of the drift region. Breakdown voltages include, but are not limited to, 200V or 500V or 1000V.

As an alternative, when the base is a structure of a high-resistance SiC substrate, the corresponding: the drift region 8 and the source electrode 3 form a PN junction, and the drift region 8 and the gate electrode 7 form a PN junction, i.e., two PN junctions. By adjusting the widths of the first gap and the second gap, the breakdown of the latter PN junction can be effectively postponed, and the first PN junction is preferentially broken down.

an oxide layer 11;

source contact metal compound 12-2 within the oxide layer and over first source contact region 4 and second source contact region 6;

source contact via 14-2 within the oxide layer and over source contact metal compound 12-2;

source metal layer 18-2 within the oxide layer and over source contact via 14-2;

a ground back hole 15 connected with the source metal layer 18-2 and penetrating to the bottom of the substrate from top to bottom;

the bottom of the substrate is grounded and connected with the heat dissipation structure.

The source terminal comprises a source 3, a first source contact region 4 and a second source contact region 6. Thus, the source terminal connection heat dissipation structure is also realized by the source contact metal compound 12-2, the source contact via 14-2, the source metal layer 18-2, and the ground back hole 15. The heat generated by the source end can be rapidly dissipated, so that the transverse SiC-JFET device can be suitable for radio frequency application.

a drain contact via 14-1 within the oxide layer and over the drain contact metal compound 12-1;

a drain metal layer 18-1 connected to the drain contact via 14-1;

a gate contact via 14-3 located within the oxide layer and above the gate electrode 17;

a gate metal layer 18-3 is connected to the gate contact via 14-3.

The drain terminal includes a drain 10, a drain implant 9, and a drain contact metal compound 12-1. The drain terminal connection is achieved through the drain contact metal compound 12-1, the drain contact via 14-1.

The gate terminal comprises a gate 7, a channel region 5, a source 3. The connection of the gate terminal is achieved by the gate contact metal compound 12-3, the gate contact via 14-3.

Specifically, the substrate 1 is an N-type SiC substrate, and the epitaxial layer 2 is a P-type SiC epitaxial layer.

The concentration of the N-type SiC substrate is high, and the resistivity thereof is low.

Specifically, the first source contact region 4 is a P-type first source contact region 4, and the second source contact region 6 is an N-type second source contact region 6.

The transverse SiC-JFET device provided by the embodiment of the application has the advantages that through the simulation design, the simulation device can easily achieve breakdown voltage of tens of volts to hundreds of volts, and the on-resistance is reduced by a plurality of times compared with that of a silicon-based device under the same breakdown voltage.

Example two

The preparation method of the transverse SiC-JFET device is used for preparing the transverse SiC-JFET device of the first embodiment. The preparation method of the lateral SiC-JFET device comprises the following steps:

forming a gate electrode 7 and a drift region 8 sequentially arranged over a substrate 1;

forming a gate contact metal compound 12-3 located above the gate 7;

forming a gate electrode 17 over the gate contact metal compound 12-3; the lateral top of the gate electrode 17 covers the edge of the gate electrode 7, so as to lower the electric field intensity at the junction of the drift region 8 and the gate electrode 7 when the lateral SiC-JFET device is turned off, and raise the electric field intensity near the position corresponding to the edge of the lateral top of the gate electrode 17 in the drift region 8, so that the electric field intensity is uniformly distributed in the drift region.

In practice, the method for manufacturing the lateral SiC-JFET device further includes:

forming a channel region 5 above the substrate 1 and below the gate 7;

forming a drain electrode 10 in the drift region 8 and spaced apart from the gate electrode 7;

wherein a space is maintained between an edge of a lateral top of the gate electrode 17 and an edge of the drain electrode 10.

forming a drain contact metal compound 12-1 over the drain electrode 10;

forming a drain electrode 13 over the drain contact metal compound 12-1;

As shown in fig. 2-2, the drain electrode 13 has the following dimensional requirements:

Second, the edge of the lateral top of the drain electrode 13 must be kept spaced from the edge of the channel region 5. I.e. the edge of the lateral top of the drain electrode 13 cannot protrude into the extent of the channel region 5.

forming a drain implant region 9 below the drain electrode 10;

forming an epitaxial layer 2 over a substrate 1;

forming a source electrode 3 and the drift region 8 which are positioned in the epitaxial layer and are sequentially arranged;

forming a first source contact region 4, a second source contact region 6 and a channel region 5 which are sequentially arranged above the source; wherein the channel region 5 is located under the gate 7;

In practice, a first gap is provided between the source 3 and the drift region 8; a second gap is formed between the gate 7 and the second source contact region 6 and between the gate 7 and the drift region 8; and the PN junction formed by the drift region 8 and the epitaxial layer 2, the PN junction formed by the drift region 8 and the source electrode 3, and the PN junction formed by the drift region 8 and the gate electrode 7 are broken down in the order of arrangement.

In practice, the method for manufacturing the lateral SiC-JFET device further comprises the following steps:

forming an oxide layer 11;

forming a source contact metal compound 12-2 located in the oxide layer and above the first source contact region 4 and the second source contact region 6, a gate contact metal compound 12-3 located above the gate 7, a drain contact metal compound 12-1 located above the drain 10;

forming a source contact via 14-2 in the oxide layer over the source contact metal compound 12-2, a gate contact via 14-3 over the gate contact metal compound 12-3, a drain contact via 14-1 over the drain contact metal compound 12-1;

forming a source metal layer 18-2 located in the oxide layer and located above the source contact via 14-2, a gate metal layer 18-3 connected to the gate contact via 14-3, and a drain metal layer 18-1 connected to the drain contact via 14-1;

forming a grounding back hole 15 connected with the source metal layer 18-2 and penetrating to the bottom of the substrate from top to bottom;

The following describes in detail a manufacturing method using a lateral SiC-JFET device for manufacturing an N-type SiC substrate as an example.

Step one: referring to fig. 3, an N-type SiC substrate 1 is used as a substrate material for fabricating a lateral field effect transistor JFET device, and a P-type SiC epitaxial layer is epitaxially grown on the N-type SiC substrate as a main region for forming the lateral JFET device.

Step two: referring to fig. 4, on the basis of the structure formed in fig. 3, each region of the SiC lateral JFET device is formed by sequential ion implantation and thermal annealing, the implantation levels being sequentially source 3, first source contact region 4, channel region 5, second source contact region 6, gate 7, drift region 8, drain implantation region 9, drain 10; and after ion implantation, carrying out high-temperature thermal annealing, and redistributing the implanted ions through a thermal process to form each region of the transverse JFET device.

The device is distributed from left to right and the source terminal comprises a source 3, a first source contact region 4 and a second source contact region 6. The source-to-ground connection may be subsequently achieved through metal-to-ground, making the lateral SiC-JFET device suitable for radio frequency applications.

The gate terminal comprises a gate 7, a channel 5, and a source 3. The negative voltage applied through gate 7 pinches off channel region 5 and source 3 assists in depletion pinch off.

The drain terminal comprises a drift region 8, a drain implant region 9, and a drain 10.

Step four: referring to fig. 5, on the basis of the structure formed in fig. 4, a thin oxide layer is deposited and openings are etched at the positions of the gate, the source and the drain, and the drain contact metal compound 12-1, the source contact metal compound 12-2 and the gate contact metal compound 12-3 are formed by removing the unreacted metal layer after the deposited metal reacts at a high temperature.

After forming the drain contact metal compound 12-1, the source contact metal compound 12-2, and the gate contact metal compound 12-3, a first oxide layer 11-1 of a suitable thickness is deposited, and an opening of the first oxide layer 11-1 is etched on the drain contact metal compound 12-1, drain metal is deposited to fill the opening, and metal is covered on the surface of the oxide layer to form a gate electrode metal layer, as shown in fig. 5.

Step five: referring to fig. 6, on the basis of the structure formed in fig. 5, a photoresist protection is formed on the gate electrode metal layer, and a gate electrode 17 having a T-shaped cross section is formed by plasma etching a metal region not covered with the photoresist, as shown in fig. 6. The lateral top boundary length of the formed T-shaped gate electrode 17 may be defined by the lithographic area, the length being required to be able to cover the edge of the gate 7, to penetrate into the drift region 8 and not into the gate's region. If necessary, the same method is used to form the drain electrode 13 with a T-shaped cross section (the lateral JFET device is usually a common drain device, the schematic diagram is left half, there is a symmetrical structure on the actual right side, and the lateral JFET device is actually the T-shaped drain electrode 13). The lateral top boundary length of the formed T-shaped drain electrode 13 may be defined by a photolithographic region, the length being required to be able to cover the edge of the drain 10, to penetrate into the drift region 8 and not into the region of the channel region 5. The gate electrode 17 and the drain electrode 13 are simultaneously provided, and then a space is maintained between the two gate electrodes 17 and the drain electrode 13. The height of the first oxide layer 11-1 determines the height of the vertical portions of the gate electrode 17 and the drain electrode 13 of the T-shape.

Referring to fig. 7, on the basis of the structure formed in fig. 6, a drain contact via 14-1, a source contact via 14-2, a gate contact via 14-3, a ground back via 15, a drain metal layer 18-1, a source metal layer 18-2, and a gate metal layer 18-3 are formed. The multi-layered metal layout wiring may be formed as required by the device.

In describing the present application and its embodiments, it should be understood that the orientation or positional relationship indicated by the terms "top", "bottom", "height", etc. are based on the orientation or positional relationship shown in the drawings, are merely for convenience of description and simplification of the description, and are not indicative or implying that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the present application.

In the present application and its embodiments, unless explicitly specified and limited otherwise, the terms "disposed," "mounted," "connected," "secured," and the like are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrated; the device can be mechanically connected, electrically connected and communicated; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.

In the present application and its embodiments, unless explicitly specified and limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, and may also include both the first and second features not being in direct contact but being in contact with each other by way of additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is less level than the second feature.

The above disclosure provides many different embodiments, or examples, for implementing different structures of the application. The foregoing description of specific example components and arrangements has been presented to simplify the present disclosure. They are, of course, merely examples and are not intended to limit the application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.

While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A lateral SiC-JFET device, comprising:

a substrate;

a gate electrode (7) and a drift region (8) which are positioned above the substrate and are arranged in sequence;

a gate contact metal compound (12-3) located over the gate (7);

a gate electrode (17), the gate electrode (17) having a vertical bottom and a lateral top connected laterally above the vertical bottom; the vertical bottom of the gate electrode is located above the gate contact metal compound (12-3); the lateral top of the gate electrode (17) covers the edge of the gate electrode (7).

2. The lateral SiC-JFET device of claim 1, further comprising:

-a channel region (5) above the substrate (1) and below the gate (7);

a drain electrode (10) located within the drift region (8) and spaced from the gate electrode (7);

wherein a space is maintained between an edge of a lateral top of the gate electrode (17) and an edge of the drain electrode (10).

3. The lateral SiC-JFET device of claim 2, characterized in that the length of the lateral top of the gate electrode (17) across the channel region (5) is less than or equal to the distance between the channel region (5) to the drain (10).

4. The lateral SiC-JFET device of claim 2, further comprising:

a drain contact metal compound (12-1) located over the drain (10);

a drain electrode (13), the drain electrode (13) having a vertical bottom and a lateral top connected laterally above the vertical bottom; the vertical bottom of the drain electrode is located above the drain contact metal compound (12-1);

wherein the lateral top of the drain electrode (13) covers the edge of the drain electrode (10);

a space is provided between an edge of a lateral top portion of the drain electrode (13) and an edge of a lateral portion of the gate electrode.

5. The lateral SiC-JFET device of claim 4, further comprising:

a drain implant region (9) located under the drain (10);

wherein the lateral top of the drain electrode (13) covers the edge of the drain implant region (9) and protrudes into position above the drift region (8).

6. The lateral SiC-JFET device of claim 4, further comprising:

a source electrode (3) and the drift region (8) which are positioned above the substrate and are sequentially arranged;

the first source contact region (4), the second source contact region (6) and the channel region (5) are sequentially arranged above the source;

wherein the channel region (5) and the drift region (8) are respectively a channel region (5) and a drift region (8) with independent structures.

7. The lateral SiC-JFET device of claim 6, wherein the substrate comprises:

a substrate (1) which is an N+ substrate or a high-resistance SiC substrate;

an epitaxial layer (2) arranged on the substrate from bottom to top;

-a first gap is provided between the source (3) and the drift region (8); a second gap is arranged between the grid electrode (7) and the second source electrode contact region (6) and between the grid electrode (7) and the drift region (8); and the PN junction formed by the drift region (8) and the epitaxial layer (2), the PN junction formed by the drift region (8) and the source electrode (3) and the PN junction formed by the drift region (8) and the gate electrode (7) are broken down in the arrangement sequence.

8. The lateral SiC-JFET device of claim 6 or 7, wherein the base is a high-resistance SiC substrate;

-a first gap is provided between the source (3) and the drift region (8); a second gap is arranged between the grid electrode (7) and the second source electrode contact region (6) and between the grid electrode (7) and the drift region (8); and the PN junction formed by the drift region (8) and the source electrode (3) and the PN junction formed by the drift region (8) and the grid electrode (7) are broken down in the sequence.

9. The lateral SiC-JFET device of claim 8, further comprising:

an oxide layer (11);

a source contact metal compound (12-2) located within the oxide layer and over the first source contact region (4) and the second source contact region (6);

a source contact via (14-2) located within the oxide layer and located over the source contact metal compound (12-2);

a source metal layer (18-2) located within the oxide layer and over the source contact via (14-2);

and the grounding back hole (15) is connected with the source electrode metal layer (18-2) and penetrates through the bottom of the substrate from top to bottom.

10. The lateral SiC-JFET device of claim 9, further comprising:

a drain contact via (14-1) located within the oxide layer and located over the drain contact metal compound (201-3);

a drain metal layer (18-1) connected to the drain contact via (14-1);

a gate contact via (14-3) located within the oxide layer and above the gate electrode (17);

and a gate metal layer (18-3) connected to the gate contact via (14-3).

11. A method of fabricating a lateral SiC-JFET device, comprising the steps of:

forming a grid electrode (7) and a drift region (8) which are sequentially arranged on a substrate;

forming a gate contact metal compound (12-3) over the gate electrode (7);

a gate electrode (17) having a vertical bottom and a lateral top connected laterally above the vertical bottom, the vertical bottom of the gate electrode being located above the gate contact metal compound (12-3); the lateral top of the gate electrode (17) covers the edge of the gate electrode (7).

12. The method of fabricating the lateral SiC-JFET device of claim 11, further comprising:

-forming a channel region (5) above the substrate (1) and below the gate (7);

forming a drain electrode (10) located within the drift region (8) and spaced from the gate electrode (7);

13. The method of fabricating the lateral SiC-JFET device of claim 12, further comprising:

forming a drain contact metal compound (12-1) over the drain electrode (10);

forming a drain electrode (13) having a vertical bottom and a lateral top connected laterally above the vertical bottom; the vertical bottom of the drain electrode is located above the drain contact metal compound (12-1);

14. The method of fabricating the lateral SiC-JFET device of claim 13, further comprising:

-forming a drain implant region (9) under the drain (10);

15. The method of fabricating the lateral SiC-JFET device of claim 14, further comprising:

forming a source electrode (3) and the drift region (8) which are positioned on the substrate and are sequentially arranged;

forming a first source contact region (4), a second source contact region (6) and the channel region (5) which are sequentially arranged above the source;