CN117116906A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN117116906A
CN117116906A CN202210529979.6A CN202210529979A CN117116906A CN 117116906 A CN117116906 A CN 117116906A CN 202210529979 A CN202210529979 A CN 202210529979A CN 117116906 A CN117116906 A CN 117116906A
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China
Prior art keywords
trench
dielectric layer
interconnect structure
substrate
interconnection
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CN202210529979.6A
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黄婷婷
费春潮
王亚平
田慧
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN202210529979.6A priority Critical patent/CN117116906A/en
Publication of CN117116906A publication Critical patent/CN117116906A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, wherein the substrate comprises a chip area, a sealing area surrounding the chip area and a cutting channel area positioned between adjacent sealing areas, a dielectric layer and an interconnection structure positioned in the dielectric layer are formed on the top of the substrate, and the interconnection structure comprises a first interconnection structure positioned in the sealing area and a second interconnection structure positioned in the cutting channel area; a trench is formed in the dielectric layer at a partial thickness between the first interconnect structure and the second interconnect structure, the trench surrounding the sealing region. And the crack generated by the tensile stress of the cutting equipment on the second interconnection structure is blocked by the groove, so that the probability of extending the crack to the sealing area is correspondingly reduced, the sealing effect of the first interconnection structure of the sealing area is improved, and the performance of the semiconductor structure is further improved.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In the semiconductor chip packaging process, the chip needs to be cut, and the cutting process is performed in the dicing street. The mechanical force of the cut may cause micro-cracks to form at the edges, especially near the corners. The resulting crack may propagate toward the central circuit area of the integrated circuit causing destruction of the circuit area therein. In order to protect the circuit area, a chip sealing ring (seal) is generally disposed between the circuit area and the dicing channel on the integrated circuit chip, and a conventional sealing ring is generally stacked by using multiple metal layers, and is usually a double sealing ring (two rings inside and outside) or a single sealing ring (only one ring). The chip seal ring prevents any cracks from penetrating into the circuit area inside the integrated circuit.
However, as the chip size becomes smaller, the dicing street size between chips is also gradually reduced, and the reduction of the dicing street size presents a serious challenge to the dicing (die saw) process at the later stage.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, which are beneficial to further performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate comprising a chip region and a sealing region surrounding the chip region; a dielectric layer on top of the substrate; a first interconnect structure located over the substrate of the sealing region and in the dielectric layer; and the groove is positioned in the dielectric layer with partial thickness, surrounds the first interconnection structure and is positioned on one side of the first interconnection structure away from the chip area.
Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a chip area, a sealing area surrounding the chip area and a cutting channel area positioned between adjacent sealing areas, a dielectric layer and an interconnection structure positioned in the dielectric layer are formed on the top of the substrate, and the interconnection structure comprises a first interconnection structure positioned in the sealing area and a second interconnection structure positioned in the cutting channel area; a trench is formed in the dielectric layer at a partial thickness between the first interconnect structure and the second interconnect structure, the trench surrounding the sealing region.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a method for forming a semiconductor structure, which comprises the steps of forming a groove in a dielectric layer with partial thickness between a first interconnection structure and a second interconnection structure, wherein the groove surrounds a sealing area. In the subsequent process of cutting the second interconnection structure and the substrate of the scribe line region, since a trench is formed in the dielectric layer having a partial thickness between the first interconnection structure and the second interconnection structure, the trench surrounds the sealing region, and when the second interconnection structure and the substrate of the scribe line region are cut, a crack generated due to a tensile stress generated by a cutting device on the interconnection structure is blocked by the trench, and accordingly, the probability that the crack extends to the sealing region is reduced, thereby improving the sealing effect of the first interconnection structure of the sealing region and further improving the performance of the semiconductor structure (for example, improving the electrical performance and reliability performance of a device).
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
FIG. 2 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;
fig. 3 to 4 are schematic structural views of another embodiment of the semiconductor structure according to the present invention;
fig. 5 to 7 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The performance of current semiconductor structures is to be improved. The reasons for the improvement in performance are now analyzed in connection with a semiconductor structure.
Fig. 1 is a schematic structural diagram of a semiconductor structure.
The semiconductor structure includes: a substrate 10, wherein the substrate 10 comprises a chip region 10C, a sealing region 10B surrounding the chip region 10C, and a dicing channel region 10A between adjacent sealing regions 10B; an inter-metal dielectric layer 19 on top of the substrate 10; a multilayer first interconnect structure 15 located in the intermetal dielectric layer 19 of the sealing region 10B; a multi-layered second interconnect structure 11 located in the intermetal dielectric layer 19 of the scribe line region 10A; a passivation layer 30 is located on top of the inter-metal dielectric layer 19, the first interconnect structure 15 and the second interconnect structure 11.
It has been found that, due to the continuous decrease in the feature size of the device, the distance between the first interconnect structure 15 and the second interconnect structure 11 in the direction parallel to the surface of the substrate 10 is smaller and smaller, and during the process of cutting the second interconnect structure 11 and the substrate 10 in the scribe line region 10A along the extending direction of the scribe line region 10A, the second interconnect structure 11 is easily subjected to tensile stress by the cutting device 29, and the crack 69 generated by the tensile stress easily extends toward the seal region 10B, so that the sealing effect of the first interconnect structure 15 in the seal region 10B is weakened, resulting in electrical failure of the first interconnect structure 15 in the seal region 10B, thereby affecting the performance of the semiconductor structure.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a chip area, a sealing area surrounding the chip area and a cutting channel area positioned between adjacent sealing areas, a dielectric layer and an interconnection structure positioned in the dielectric layer are formed on the top of the substrate, and the interconnection structure comprises a first interconnection structure positioned in the sealing area and a second interconnection structure positioned in the cutting channel area; a trench is formed in the dielectric layer at a partial thickness between the first interconnect structure and the second interconnect structure, the trench surrounding the sealing region.
In the embodiment of the invention, a groove is formed in the dielectric layer with partial thickness between the first interconnection structure and the second interconnection structure, and the groove surrounds the sealing area. In the subsequent process of cutting the second interconnection structure and the substrate of the scribe line region, since a trench is formed in the dielectric layer having a partial thickness between the first interconnection structure and the second interconnection structure, the trench surrounds the sealing region, and when the second interconnection structure and the substrate of the scribe line region are cut, a crack generated due to a tensile stress generated by a cutting device on the second interconnection structure is blocked by the trench, and accordingly, the probability that the crack extends to the sealing region is reduced, thereby improving the sealing effect of the first interconnection structure of the sealing region and further improving the performance (for example, improving the electrical performance and reliability performance of a device) of the semiconductor structure.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 2 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.
The semiconductor structure includes: a substrate 200, the substrate 200 including a chip region 200C and a sealing region 200B surrounding the chip region 200C; a dielectric layer 209 on top of the substrate 200; a first interconnect structure 202 located over the substrate 200 of the sealing region 200B and in the dielectric layer 209; a trench 211 is located in a portion of the thickness of the dielectric layer 209, the trench 211 surrounds the first interconnect structure 202 and is located on a side of the first interconnect structure 202 away from the chip region 200C.
The substrate 200 provides a process basis for subsequent processing.
In this embodiment, the substrate 200 is made of silicon. In other embodiments, the material of the base 200 may be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the base 200 may be other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate 200 may be a material suitable for process requirements or easy integration.
As an example, the substrate 200 is a chip-scale substrate 200, that is, the semiconductor structure is obtained by dicing a wafer.
In this embodiment, in the process of forming the semiconductor structure, the sealing region 200B provides a space for forming the first interconnection structure 202, and meanwhile, the sealing region 200B surrounds the chip region 200C, so as to protect the device structure in the chip region 200C, and reduce the probability of electrical failure of the device structure in the chip region 200C.
It should be noted that the chip area 200C in the substrate 200 may form various semiconductor devices, such as various suitable transistors, memories, passive devices, or field effect transistors.
In this embodiment, the dielectric layer 209 includes an inter-metal dielectric layer 207 and a passivation layer 208 on top of the inter-metal dielectric layer 207.
Specifically, the inter-metal dielectric layer 207 provides a spatial location for the formation of the first interconnect structure 202, while the inter-metal dielectric layer 207 also serves to electrically isolate adjacent first interconnect structures 202.
In this embodiment, the material of the inter-metal dielectric layer 207 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material (low-k dielectric material refers to a dielectric material having a relative dielectric constant of 2.6 or more and 3.9 or less), and ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material having a relative dielectric constant of less than 2.6).
It should be noted that the passivation layer 208 protects the top of the first interconnect structure 202, and reduces the risk of the first interconnect structure 202 coming into contact with the outside air.
In this embodiment, the passivation layer 208 includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.
The first interconnection structure 202 protects various semiconductor components in the chip area 200C, and reduces the probability of damaging the semiconductor components in the chip area 200C.
In this embodiment, the material of the first interconnection structure 202 is Al, and the resistivity of the material Al is low, which is beneficial to improving the electrical connection performance of the first interconnection structure 202. In other embodiments, the material of the first interconnection structure may also be a conductive material such as Cu.
In this embodiment, the first interconnect structure 202 is spaced apart from the trench 211 in a direction parallel to the surface of the substrate 200.
Specifically, the first interconnection structure 202 and the trench 211 are spaced apart in a direction parallel to the surface of the substrate 200, that is, a dielectric layer 209 is disposed between the first interconnection structure 202 and the trench 211, so that the dielectric layer 209 protects the sidewalls of the first interconnection structure 202, the probability that the sidewalls of the first interconnection structure 202 are exposed by the trench 211 is reduced, and correspondingly, the probability that the first interconnection structure 202 fails electrically is reduced, thereby improving the performance of the semiconductor structure.
It should be noted that the distance between the first interconnect structure 202 and the trench 211 in the direction parallel to the surface of the substrate 200 is not too large or too small. If the distance between the first interconnection structure 202 and the trench 211 in the direction parallel to the surface of the substrate 200 is too large, the trench 211 is easily undersized along the direction perpendicular to the sidewall of the trench 211 under the condition that the area of the substrate 200 is certain, resulting in an excessively large aspect ratio of the trench 211, and in the process of forming the semiconductor structure, the difficulty of forming the trench 211 is increased, and meanwhile, when the wafer dicing is performed, the effect that the crack generated due to the tensile stress generated by the dicing equipment on the dicing channel area is blocked by the trench 211 is reduced, and accordingly, the probability of electrical failure of the first interconnection structure 202 is increased, thereby affecting the performance of the semiconductor structure; if the distance between the first interconnect structure 202 and the trench 211 in the direction parallel to the surface of the substrate 200 is too small, the probability that the trench 211 exposes the sidewall of the first interconnect structure 202 is increased, and accordingly, the probability that the first interconnect structure 202 fails electrically is increased, thereby improving the performance of the semiconductor structure. For this purpose, in the present embodiment, the first interconnect structure 202 is spaced apart from the trench 211 by a distance of 1.8 micrometers to 2.2 micrometers in a direction parallel to the surface of the substrate 200.
In this embodiment, a multi-layer first interconnection structure 202 is formed on top of the substrate 200 in the sealing region 200B.
In this embodiment, the semiconductor structure further includes: a first interconnection plug 206 is located between the first interconnection structures 202 of adjacent layers, and the first interconnection plug 206 is used for realizing electrical connection between the first interconnection structures 202 of adjacent layers.
In this embodiment, the material of the first interconnection plug 206 is one or both of aluminum and tantalum nitride.
Specifically, the resistivity of the aluminum and tantalum nitride material is lower, so that the conductivity of the first interconnection plug 206 can be improved, and meanwhile, in the formation process of the first interconnection plug 206, the process of forming the first interconnection plug 206 is higher in stability due to the fact that the process of using the aluminum and tantalum nitride material is mature.
It should be noted that, in the process of forming the semiconductor structure, when the semiconductor structure is diced, the crack generated by the tensile stress generated by the dicing apparatus on the dicing street region is blocked by the trench 211, and accordingly, the probability that the crack extends to the sealing region 200B is reduced, so as to improve the sealing effect of the first interconnection structure 202 of the sealing region 200B, and further improve the performance of the semiconductor structure (for example, improve the electrical performance and reliability performance of the device).
In this embodiment, the trench 211 penetrates the passivation layer 208 and a portion of the thickness of the inter-metal dielectric layer 207.
Specifically, in the process of forming the semiconductor structure, when the semiconductor structure is subjected to wafer dicing, a crack is easily generated in the inter-metal dielectric layer 207 due to the tensile stress generated by the dicing apparatus on the dicing channel region, and in order to reduce the risk of the crack extending to the sealing region 200B, the trench 211 needs to penetrate through the passivation layer 208 and a part of the thickness of the inter-metal dielectric layer 207.
When the semiconductor structure is diced, the cracks generated by the tensile stress of the dicing device on the dicing street region are mainly concentrated in the topmost film structure, that is, the bottom of the trench 211 is lower than the bottom of the cracks, so that the probability of extending the cracks to the sealing region 200B can be reduced, and therefore, the trench 211 penetrates the inter-metal dielectric layer 207 with a part of the thickness.
It should be noted that, along the normal direction of the surface of the substrate 200, the distance from the bottom of the trench 211 to the top of the trench 211 should not be too large or too small. If the distance from the bottom of the trench 211 to the top of the trench 211 is too large, the aspect ratio of the trench 211 is easily caused to be too large, and in the process of forming the semiconductor structure, the process difficulty of forming the trench 211 is increased, and meanwhile, the risk that the trench 211 penetrates through the substrate 200 is increased, so that the performance of the semiconductor structure is affected; if the distance from the bottom of the trench 211 to the top of the trench 211 is too small, there is a risk that a crack generated by tensile stress may extend to the sealing region 200B through the inter-metal dielectric layer 207 at the bottom of the trench 211, and the probability of electrical failure of the first interconnect structure 202 is increased, thereby affecting the performance of the semiconductor structure. For this reason, in the present embodiment, the distance from the bottom of the trench 211 to the top of the trench 211 is 15.61 micrometers to 16.61 micrometers along the normal direction of the surface of the substrate 200.
It should be further noted that, along the direction perpendicular to the sidewall of the trench 211, the lateral dimension of the trench 211 should not be too large or too small. If the lateral dimension of the trench 211 is too large, in the case that the area of the substrate 200 is constant, the distance between the trench 211 and the first interconnection structure 202 is reduced, which increases the risk that the trench 211 exposes the sidewall of the first interconnection structure 202, increases the probability of electrical failure of the first interconnection structure 202, and thus affects the performance of the semiconductor structure; if the lateral dimension of the trench 211 is too small, the aspect ratio of the trench 211 is easily increased, and in the process of forming the semiconductor structure, the difficulty of forming the trench 211 is increased, and at the same time, when the wafer is cut, the effect that the crack generated by the tensile stress generated by the cutting device on the scribe line region is blocked by the trench 211 is reduced, and accordingly, the probability of electrical failure of the first interconnection structure 202 is increased, thereby affecting the performance of the semiconductor structure. For this reason, in the present embodiment, the lateral dimension of the trench 211 is 1.8 micrometers to 2.2 micrometers in the direction perpendicular to the sidewall of the trench 211.
Fig. 3 to 4 are schematic structural views of another embodiment of the semiconductor structure according to the present invention. Fig. 3 is a plan view, and fig. 4 is a sectional view of fig. 3 along the ab direction.
The points of the embodiment of the present invention that are the same as those of the first embodiment are not described herein, and the difference between the embodiment of the present invention and the first embodiment is that: the substrate 300 also includes a dicing street area 300A surrounding the sealing area 300B.
As an example, the substrate 300 is a wafer level substrate, that is, the semiconductor structure has not been diced. In other embodiments, the substrate may also be a chip-scale substrate, with the chip-scale substrate retaining a portion of the scribe line region.
In the semiconductor chip packaging process, the wafer needs to be diced to obtain a plurality of chips. The scribe line region 300A in the substrate 300 is a scribe line during wafer dicing.
The substrate 300 in the scribe line region 300A often has no semiconductor devices.
In this embodiment, the semiconductor structure further includes: a second interconnect structure 301 is located on the substrate 300 of the scribe line region 300A and in the dielectric layer 309, the second interconnect structure 301 having the same cross-sectional structure as the first interconnect structure 302.
Specifically, the second interconnection structure 301 is configured to be electrically connected to a test (e.g., WAT test) component and a test metal wire, where the test metal wire is electrically connected to the second interconnection structure 301 to detect whether the electrical performance of the semiconductor structure is good, so as to determine the performance and yield of the component in the substrate 300, and meanwhile, in the process of cutting the scribe line region 300A, the second interconnection structure 301 also plays a role of an alignment mark, which is beneficial for cutting the scribe line by the cutting device.
In this embodiment, the material of the second interconnection structure 301 is Al, and the resistivity of the material Al is low, which is beneficial to improving the electrical connection performance of the second interconnection structure 301. In other embodiments, the material of the second interconnection structure 301 may also be a conductive material such as Cu.
In this embodiment, a multi-layer second interconnection structure 301 is disposed on top of the substrate 300 of the scribe line region 300A.
In this embodiment, the semiconductor structure further includes: and second interconnection plugs 360, located between the second interconnection structures 301 of adjacent layers, wherein the second interconnection plugs 360 are used for realizing electrical connection between the second interconnection structures 301 of adjacent layers.
In this embodiment, the material of the second interconnection plug 360 is one or both of aluminum and tantalum nitride.
Specifically, the resistivity of the aluminum and tantalum nitride material is lower, so that the conductivity of the second interconnection plug 360 can be improved, and meanwhile, in the process of forming the second interconnection plug 360, the process of forming the second interconnection plug 360 is higher in stability due to the fact that the process of using the aluminum and tantalum nitride material is mature.
In this embodiment, the trench is located in the dielectric layer 309 at a partial thickness between the first interconnect structure 302 and the second interconnect structure 301.
It should be noted that the trench is located in the dielectric layer 309 of a partial thickness between the first interconnect structure 302 and the second interconnect structure 301, and the trench surrounds the sealing region 300B. In the process of forming the semiconductor structure, during the process of cutting the second interconnect structure 301 and the substrate 300 of the scribe line region 300A, since a trench is formed in the dielectric layer 309 having a partial thickness between the first interconnect structure 302 and the second interconnect structure 301, the trench surrounds the sealing region 300B, and when the second interconnect structure 301 and the substrate 300 of the scribe line region 300A are cut, a crack generated due to a tensile stress generated from the second interconnect structure 301 by a cutting device is blocked by the trench, and accordingly, a probability that the crack extends to the sealing region 300B is reduced, thereby improving a sealing effect of the first interconnect structure 302 of the sealing region 300B and further improving performance of the semiconductor structure.
Fig. 5 to 7 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 5, a substrate 100 is provided, including a chip region 100C, a sealing region 100B surrounding the chip region 100C, and a scribe line region 100A located between adjacent sealing regions 100B, a dielectric layer and an interconnect structure 103 located in the dielectric layer are formed on top of the substrate 100, and the interconnect structure 103 includes a first interconnect structure 102 located in the sealing region 100B, and a second interconnect structure 101 located in the scribe line region 100A.
The substrate 100 provides a process basis for subsequent processing.
In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the base may be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials, and the base may be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.
As an example, the substrate 100 is a wafer level substrate, that is, the semiconductor structure has not been diced. In other embodiments, the substrate may also be a chip-scale substrate, with the chip-scale substrate retaining a portion of the scribe line region.
It should be noted that, in the semiconductor chip packaging process, the chip needs to be cut, and the scribe line region 100A in the substrate 100 is a scribe line in the chip dicing process.
The substrate 100 in the scribe line region 100A often has no semiconductor devices.
In this embodiment, the sealing region 100B provides a spatial location for the first interconnection structure 102 to be formed later, the sealing region 100B separates the scribe line region 100A from the chip region 100C in the substrate 100, and the probability of damage to the circuit structure in the chip region 100C is reduced during the dicing of the chip along the scribe line region 100A.
It should be noted that the chip region 100C in the substrate 100 may form various semiconductor components, such as various suitable transistors, memories, passive devices, or field effect transistors.
The first interconnection structure 102 protects various semiconductor components in the chip area 100C, and reduces the probability of damaging the semiconductor components in the chip area 100C.
In this embodiment, the material of the first interconnection structure 102 is Al, and the resistivity of the material Al is low, which is beneficial to improving the electrical connection performance of the first interconnection structure 102. In other embodiments, the material of the first interconnection structure may also be a conductive material such as Cu.
In this embodiment, a plurality of layers of first interconnection structures 102 are formed on top of the substrate 100 in the sealing region 100B, and a first interconnection plug 106 is formed between adjacent first interconnection structures 102, where the first interconnection plug 106 is used to electrically connect adjacent layers of first interconnection structures 102.
In this embodiment, the material of the first interconnection plug 106 is one or both of aluminum and tantalum nitride.
Specifically, the resistivity of the aluminum and tantalum nitride material is lower, so that the conductivity of the first interconnection plug 106 can be improved, and meanwhile, in the formation process of the first interconnection plug 106, the process of forming the first interconnection plug 106 is higher in stability due to the fact that the process of using the aluminum and tantalum nitride material is mature.
The second interconnection structure 101 is configured to be electrically connected to a test (e.g., WAT test) component and a test metal wire, where the test metal wire is electrically connected to the second interconnection structure 101 to detect whether the electrical performance of the semiconductor structure is good, so as to determine the performance and yield of the component in the substrate 100, and meanwhile, in the process of cutting the scribe line region 100A, the second interconnection structure 101 also plays a role of an alignment mark, which is beneficial for cutting the scribe line by the cutting device.
In this embodiment, the material of the second interconnection structure 101 is Al, and the resistivity of the material Al is low, which is beneficial to improving the electrical connection performance of the second interconnection structure 101. In other embodiments, the material of the second interconnection structure 101 may also be a conductive material such as Cu.
In this embodiment, a plurality of layers of second interconnection structures 101 are formed on top of the substrate 100 of the scribe line region 100A, and second interconnection plugs 120 are formed between adjacent layers of second interconnection structures 101, and the second interconnection plugs 120 are used for electrically connecting adjacent layers of second interconnection structures 101.
In this embodiment, the material of the second interconnection plug 120 is one or both of aluminum and tantalum nitride.
Specifically, the resistivity of the aluminum and tantalum nitride material is lower, so that the conductivity of the second interconnection plug 120 can be improved, and meanwhile, in the process of forming the second interconnection plug 120, the process of forming the second interconnection plug 120 is higher in stability due to the fact that the process of using the aluminum and tantalum nitride material is mature.
In this embodiment, the dielectric layer 109 includes an inter-metal dielectric layer 107 and a passivation layer 108 on top of the inter-metal dielectric layer 107, the interconnect structure 103 is located in the inter-metal dielectric layer 107, and the top of the interconnect structure 103 is covered by the passivation layer 108.
Specifically, the inter-metal dielectric layer 107 provides a spatial location for forming the first interconnect structure 102 and the second interconnect structure 101, while the inter-metal dielectric layer 107 also serves to electrically isolate adjacent first interconnect structure 102 and second interconnect structure 101.
In this embodiment, the material of the inter-metal dielectric layer 107 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material (low-k dielectric material refers to a dielectric material having a relative dielectric constant of 2.6 or more and 3.9 or less), and ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material having a relative dielectric constant of less than 2.6).
It should be noted that, the passivation layer 108 protects the top of the interconnect structure 103, which reduces the risk of the interconnect structure 103 contacting with the outside air, and reduces the probability of damage to the top of the interconnect structure 103 caused by the etching process during the subsequent formation of the trench.
In this embodiment, the passivation layer 108 includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.
In this embodiment, the passivation layer 108 is formed by a chemical vapor deposition process.
Referring to fig. 6 to 7, wherein fig. 6 is a top view, and fig. 7 is a cross-sectional view of fig. 6 along the AB direction, a trench 111 is formed in the dielectric layer 109 of a partial thickness between the first interconnect structure 102 and the second interconnect structure 101, the trench 111 surrounding the sealing region 100B.
A trench 111 is formed in the dielectric layer 109 between the first interconnect structure 102 and the second interconnect structure 101 at a partial thickness, the trench 111 surrounding the sealing region 100B. Since the trench 111 is formed in the dielectric layer 109 having a partial thickness between the first interconnect structure 102 and the second interconnect structure 101 during the subsequent dicing of the second interconnect structure 101 and the substrate 100 of the scribe line region 100A, the trench 111 surrounds the sealing region 100B, and when the second interconnect structure 101 and the substrate 100 of the scribe line region 100A are diced, the crack generated due to the tensile stress generated by the dicing device on the second interconnect structure 101 is blocked by the trench 111, and accordingly, the probability that the crack extends toward the sealing region 100B is reduced, thereby improving the sealing effect of the first interconnect structure 102 of the sealing region 100B and further improving the performance of the semiconductor structure.
In this embodiment, the first interconnect structure 102 is spaced apart from the trench 111 in a direction parallel to the surface of the substrate 100.
Specifically, the first interconnection structure 102 and the trench 111 are spaced apart in a direction parallel to the surface of the substrate 100, that is, a dielectric layer 109 is formed between the first interconnection structure 102 and the trench 111, so that the dielectric layer 109 protects the additional side wall of the first interconnection structure 102, and in the subsequent process of cutting the second interconnection structure 101 and the substrate 100 in the scribe line region 100A, the probability that the trench 111 exposes the side wall of the first interconnection structure 102 is reduced, and correspondingly, the probability that the first interconnection structure 102 fails electrically is reduced, thereby improving the performance of the semiconductor structure.
When the semiconductor structure is diced, the cracks generated by the tensile stress of the dicing device on the dicing street area are mainly concentrated in the second interconnection structure 101 at the topmost layer, that is, the bottom of the trench 111 is lower than the bottom of the second interconnection structure 101 at the topmost layer, so that the probability that the cracks extend to the sealing region 100B can be reduced, and therefore, the trench 111 penetrates through the inter-metal dielectric layer 107 at a part of the thickness.
It should be further noted that the distance between the first interconnect structure 102 and the trench 111 in the direction parallel to the surface of the substrate 100 should not be too large or too small. If the distance between the first interconnect structure 102 and the second interconnect structure 101 is too large in the direction parallel to the surface of the substrate 100, the area of the substrate 200 is certain, which easily causes that the size of the trench 111 along the direction perpendicular to the sidewall of the trench 111 is too small, which causes that the aspect ratio of the trench 111 is too large, which increases the difficulty of forming the trench 111, and simultaneously, the effect that the crack generated by the tensile stress generated by the cutting device on the second interconnect structure 101 is blocked by the trench 111 in the subsequent process of cutting the second interconnect structure 101 and the substrate 100 in the scribe line region 100A is reduced, which correspondingly increases the probability of electrical failure of the first interconnect structure 102, thereby affecting the performance of the semiconductor structure; if the distance between the first interconnect structure 102 and the trench 111 in the direction parallel to the surface of the substrate 100 is too small, the probability that the trench 111 exposes the sidewalls of the first interconnect structure 102 is increased, and correspondingly, the probability that the first interconnect structure 102 fails electrically is increased, thereby improving the performance of the semiconductor structure. For this reason, in the present embodiment, the first interconnect structure 102 is spaced apart from the trench 111 by a distance of 1.8 micrometers to 2.2 micrometers in a direction parallel to the surface of the substrate 100.
In this embodiment, the process of forming the trench 111 in the dielectric layer 109 of a partial thickness between the first interconnect structure 102 and the second interconnect structure 101 includes a dry etching process.
Specifically, the dry etching process includes an anisotropic dry etching process. The anisotropic dry etching process has anisotropic characteristics, the longitudinal etching rate is far greater than the lateral etching rate, and the anisotropic dry etching process has high pattern transfer accuracy, and can reduce damage to other film layers while forming the trench 111 in the dielectric layer 109 with a partial thickness between the first interconnect structure 102 and the second interconnect structure 101.
In this embodiment, in the step of forming the trench 111 in the dielectric layer 109 having a partial thickness between the first interconnect structure 102 and the second interconnect structure 101, the trench 111 penetrates the passivation layer 108 and the inter-metal dielectric layer 107 having a partial thickness.
Specifically, during the subsequent dicing of the second interconnect structure 101 and the substrate 100 in the scribe line region 100A, a crack is easily generated in the second interconnect structure 101 and the inter-metal dielectric layer 107 due to the tensile stress generated by the dicing device on the second interconnect structure 101, and in order to reduce the risk of the crack extending to the seal region 100B, the trench 111 needs to penetrate through the passivation layer 108 and a part of the thickness of the inter-metal dielectric layer 107.
In this embodiment, the step of forming the trench 111 in the dielectric layer 109 with a partial thickness between the first interconnect structure 102 and the second interconnect structure 101 includes: forming a mask layer having a mask opening on top of the dielectric layer 109, the mask opening being located on top of the dielectric layer 109 between the first interconnect structure 102 and the second interconnect structure 101; the dielectric layer 109 having a partial thickness between the first interconnect structure 102 and the second interconnect structure 101 is patterned using the mask layer as a mask, and a trench 111 is formed in the dielectric layer 109 having a partial thickness between the first interconnect structure 102 and the second interconnect structure 101.
It should be noted that, along the normal direction of the surface of the substrate 100, the distance from the bottom of the trench 111 to the top of the trench 111 should not be too large or too small. If the distance from the bottom of the trench 111 to the top of the trench 111 is too large, the aspect ratio of the trench 111 is easily caused to be too large, which increases the difficulty of the process for forming the trench 111, and increases the risk of the trench 111 penetrating through the substrate 100, thereby affecting the performance of the semiconductor structure; if the distance from the bottom of the trench 111 to the top of the trench 111 is too small, there is a risk that cracks generated by tensile stress may easily extend to the sealing region 100B through the intermetal dielectric layer 107 at the bottom of the trench 111, increasing the probability of electrical failure of the first interconnect structure 102, thereby affecting the performance of the semiconductor structure. For this reason, in the present embodiment, the distance from the bottom of the trench 111 to the top of the trench 111 is 15.61 micrometers to 16.61 micrometers along the normal direction of the surface of the substrate 100.
It should be further noted that, along the direction perpendicular to the sidewall of the trench 111, the lateral dimension of the trench 111 should not be too large or too small. If the lateral dimension of the trench 111 is too large in the case that the distance between the first interconnect structure 102 and the second interconnect structure 101 is fixed, and the distance between the trench 111 and the first interconnect structure 102 is reduced in the case that the area of the substrate 200 is fixed, the risk that the trench 111 exposes the side wall of the first interconnect structure 102 is increased, and the probability of electrical failure of the first interconnect structure 102 is increased, thereby affecting the performance of the semiconductor structure; if the lateral dimension of the trench 111 is too small, the aspect ratio of the trench 111 is easily increased, which increases the difficulty of the process of forming the trench 111, and simultaneously, in the subsequent process of cutting the second interconnect structure 101 and the substrate 100 in the scribe line region 100A, the effect that the crack generated by the tensile stress generated by the cutting device on the second interconnect structure 101 is blocked by the trench 111 is reduced, and accordingly, the probability of electrical failure of the first interconnect structure 102 is increased, thereby affecting the performance of the semiconductor structure. For this reason, in the present embodiment, the lateral dimension of the trench 111 is 1.8 micrometers to 2.2 micrometers in the direction perpendicular to the sidewall of the trench 111.
In this embodiment, the process of cutting the buffer interconnection structure, the interconnection structure, and the substrate 100 in the scribe line region 100A along the extending direction of the scribe line region 100A includes a blade cutting process or a laser cutting process.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (16)

1. A semiconductor structure, comprising:
a substrate comprising a chip region and a sealing region surrounding the chip region;
a dielectric layer on top of the substrate;
a first interconnect structure located over the substrate of the sealing region and in the dielectric layer;
and the groove is positioned in the dielectric layer with partial thickness, surrounds the first interconnection structure and is positioned on one side of the first interconnection structure away from the chip area.
2. The semiconductor structure of claim 1, wherein the first interconnect structure is spaced apart from the trench in a direction parallel to the substrate surface.
3. The semiconductor structure of claim 2, wherein the first interconnect structure is spaced apart from the trench by a distance of 1.8 microns to 2.2 microns in a direction parallel to the substrate surface.
4. The semiconductor structure of claim 1, wherein the dielectric layer comprises an inter-metal dielectric layer and a passivation layer on top of the inter-metal dielectric layer;
the first interconnection structure is positioned in the inter-metal dielectric layer, and the top of the first interconnection structure is covered by the passivation layer;
the trench penetrates the passivation layer and a portion of the intermetal dielectric layer.
5. The semiconductor structure of claim 4, wherein the material of the inter-metal dielectric layer comprises one or more of silicon oxide, silicon nitride, and silicon oxynitride;
the material of the passivation layer includes one or more of silicon oxide, silicon nitride and silicon oxynitride.
6. The semiconductor structure of claim 1, wherein a distance from a bottom of the trench to a top of the trench is 15.61 micrometers to 16.61 micrometers along a normal direction of the substrate surface.
7. The semiconductor structure of claim 1, wherein a lateral dimension of the trench is 1.8 microns to 2.2 microns in a direction perpendicular to the trench sidewalls.
8. The semiconductor structure of claim 1, wherein the substrate further comprises a scribe line region surrounding the seal region;
the semiconductor structure further includes: a second interconnect structure located on the substrate of the scribe line region and in the dielectric layer, the second interconnect structure having the same cross-sectional structure as the first interconnect structure;
the trench is located in the dielectric layer at a partial thickness between the first interconnect structure and the second interconnect structure.
9. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a chip area, a sealing area surrounding the chip area and a cutting channel area positioned between adjacent sealing areas, a dielectric layer and an interconnection structure positioned in the dielectric layer are formed on the top of the substrate, and the interconnection structure comprises a first interconnection structure positioned in the sealing area and a second interconnection structure positioned in the cutting channel area;
a trench is formed in the dielectric layer at a partial thickness between the first interconnect structure and the second interconnect structure, the trench surrounding the sealing region.
10. The method of forming a semiconductor structure of claim 9, wherein in the step of forming the trench, the first interconnect structure is spaced apart from the trench in a direction parallel to the substrate surface.
11. The method of forming a semiconductor structure of claim 10, wherein the first interconnect structure is spaced apart from the trench by a distance of 1.8 microns to 2.2 microns in a direction parallel to the substrate surface.
12. The method of forming a semiconductor structure of claim 9, wherein forming a trench in the dielectric layer of a partial thickness between the first interconnect structure and the second interconnect structure comprises a dry etching process.
13. The method of forming a semiconductor structure of claim 9, wherein in the step of providing a substrate, the dielectric layer comprises an inter-metal dielectric layer and a passivation layer on top of the inter-metal dielectric layer, the interconnect structure is located in the inter-metal dielectric layer, and a top of the interconnect structure is covered by the passivation layer;
in the step of forming a trench in the dielectric layer of a partial thickness between the first interconnect structure and the second interconnect structure, the trench penetrates the passivation layer and the inter-metal dielectric layer of a partial thickness.
14. The method of forming a semiconductor structure of claim 9 or 13, wherein forming a trench in the dielectric layer of a partial thickness between the first interconnect structure and the second interconnect structure comprises: forming a mask layer with a mask opening on top of the dielectric layer, the mask opening being located on top of the dielectric layer between the first interconnect structure and the second interconnect structure; and patterning the dielectric layer with partial thickness between the first interconnection structure and the second interconnection structure by taking the mask layer as a mask, and forming a groove in the dielectric layer with partial thickness between the first interconnection structure and the second interconnection structure.
15. The method of forming a semiconductor structure of claim 9, wherein a distance from a bottom of the trench to a top of the trench is 15.61 micrometers to 16.61 micrometers along a normal direction of the substrate surface.
16. The method of forming a semiconductor structure of claim 9, wherein a lateral dimension of the trench is from 1.8 microns to 2.2 microns in a direction perpendicular to the trench sidewalls.
CN202210529979.6A 2022-05-16 2022-05-16 Semiconductor structure and forming method thereof Pending CN117116906A (en)

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