CN117116855A - Method and system for forming dipole layer in stacked fully-around gate transistors - Google Patents

Method and system for forming dipole layer in stacked fully-around gate transistors Download PDF

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Publication number
CN117116855A
CN117116855A CN202310572211.1A CN202310572211A CN117116855A CN 117116855 A CN117116855 A CN 117116855A CN 202310572211 A CN202310572211 A CN 202310572211A CN 117116855 A CN117116855 A CN 117116855A
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Prior art keywords
gap
layer
forming
substrate
fill
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CN202310572211.1A
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Inventor
邓少任
M·图米恩
V·万达伦
E·托伊斯
V·马德希瓦拉
韩镕圭
D·基亚佩
M·吉文斯
R-J·张
G·A·沃尼
T·布兰夸特
R·H·J·沃乌尔特
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ASM IP Holding BV
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ASM IP Holding BV
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523Pulsed gas flow or change of composition over time
    • C23C16/45525Atomic layer deposition [ALD]
    • C23C16/45527Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
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    • C23C16/4554Plasma being used non-continuously in between ALD reactions
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523Pulsed gas flow or change of composition over time
    • C23C16/45525Atomic layer deposition [ALD]
    • C23C16/45553Atomic layer deposition [ALD] characterized by the use of precursors specially adapted for ALD
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
    • H01L21/02315Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics

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Abstract

Methods and related systems for forming structures are disclosed. Embodiments of the presently described methods include using a sacrificial gap-fill fluid to selectively form a first layer on one or more first surfaces in a lower portion of the gap and a second layer on one or more second surfaces in an upper portion of the gap.

Description

Method and system for forming dipole layer in stacked fully-around gate transistors
Technical Field
The present disclosure relates generally to the field of semiconductor processing methods and systems, and to the field of integrated circuit fabrication. In particular, methods and systems suitable for forming dipole layers are disclosed.
Background
The shrinking size of semiconductor devices, such as Complementary Metal Oxide Semiconductor (CMOS) devices, has resulted in significant increases in the speed and density of integrated circuits. However, conventional device scaling techniques face significant challenges for future technology nodes.
For example, one challenge involves creating stacked transistors with different threshold voltages, such as for complementary field effect transistors comprising a first MOSFET and a second MOSFET stacked on top of each other, each independently selected from a p-channel MOSFET and an n-channel MOSFET.
Any discussion of problems and solutions, including those set forth in this section, has been included in the present disclosure merely to provide a background for the present disclosure and is not intended to be an admission that any or all of the information is known or constitutes prior art when the present invention was made.
Disclosure of Invention
This summary may introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to necessarily identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
Embodiments of a method of forming a structure are described herein. The method includes the step of providing a substrate. The substrate includes a gap. The gap includes a lower portion and an upper portion. The method further includes forming a first layer on one or more first surfaces in a lower portion of the gap and on one or more second surfaces in an upper portion of the gap. The method further includes forming a gap-fill fluid in a lower portion of the gap. The method further includes selectively etching the first layer relative to the gap-fill fluid. Thus, the first layer is removed from the one or more second surfaces in the upper portion of the gap. The method further includes forming a second layer on one or more second surfaces in the upper portion of the gap. The first layer and the second layer have different compositions. The method then includes the step of removing the gap-fill fluid.
Further described herein is another embodiment of a method of forming a structure. The method includes providing a substrate. The substrate includes a gap. The gap includes a lower portion and an upper portion. The lower portion includes a first set of nanoplatelets. The upper portion includes a second set of nanoplatelets. The method further includes forming a first layer over the first set of nanoplatelets and over the second set of nanoplatelets. The method further includes forming a gap-fill fluid in a lower portion of the gap. Thus, the first set of nanoplatelets are encapsulated in a gap-filling fluid. The method further includes selectively etching the first layer relative to the gap-fill fluid. Thus, the first layer is removed from the second set of nanoplatelets. The method further includes forming a second layer over the second set of nanoplatelets. It will be appreciated that the first and second layers have different compositions. The method further includes removing the gap-fill fluid.
In some embodiments, the step of removing the gap-fill fluid from the lower portion of the gap is followed by forming a high-k dielectric on the first layer and on the second layer. The substrate may then be annealed. Thus, the first gate dielectric is formed of the first layer and the high-k dielectric and the second gate dielectric is formed of the second layer and the high-k dielectric.
Further described herein is another embodiment of a method of forming a structure. The method includes providing a substrate. The substrate includes a gap. The gap includes a lower portion and an upper portion. The lower portion includes a first set of nanoplatelets. The upper portion includes a second set of nanoplatelets. The method also includes forming a high-k dielectric on the first set of nanoplatelets and on the second set of nanoplatelets. The method further includes forming a first layer on the high-k dielectric on the first set of nanoplatelets and on the high-k dielectric on the second set of nanoplatelets. The method further includes forming a gap-fill fluid in a lower portion of the gap. Thus, the first set of nanoplatelets are encapsulated in a gap-filling fluid. The method also includes selectively etching the first layer relative to the gap-fill fluid and relative to the high-k dielectric. Thus, the first layer is removed from the second set of nanoplatelets. The method further includes forming a second layer over the high-k dielectric over the second set of nanoplatelets. The first layer and the second layer have different compositions. The method further includes the step of removing the gap-fill fluid.
In some embodiments, at least one of the first set of nanoplatelets and the second set of nanoplatelets comprises a single crystalline semiconductor.
In some embodiments, the step of removing the gap-fill fluid is followed by a step of annealing the substrate. Thus, the first gate dielectric is formed of the first layer and the high-k dielectric. In addition, the second gate dielectric is formed from the second layer and the high-k dielectric.
In some embodiments, the gap-filling fluid comprises an oligomeric compound.
In some embodiments, the gap-filling fluid includes a plurality of imide functional groups.
In some embodiments, forming the gap-fill fluid includes exposing the substrate to a gap-fill precursor and exposing the substrate to a gap-fill reactant.
In some embodiments, forming the gap-fill fluid includes performing a cyclical gap-fill deposition process. The cyclical gap-fill deposition process includes a plurality of gap-fill deposition cycles including a gap-fill precursor pulse and a gap-fill reactant pulse. The gap-filling precursor pulse includes exposing the substrate to the gap-filling precursor. The gap-fill reactant pulse includes exposing the substrate to the gap-fill reactant.
In some embodiments, forming the gap-fill fluid includes generating a plasma.
In some embodiments, forming the gap-filling fluid is performed thermally.
In some embodiments, forming the first layer includes performing a cyclical first layer deposition process. Cycling the first layer deposition process includes a plurality of first layer deposition cycles. The first layer deposition cycle includes a first cycle precursor pulse and a first cycle reactant pulse. The first cyclical precursor pulse includes exposing the substrate to a first cyclical precursor. The first circulating reactant pulse includes exposing the substrate to a first circulating reactant.
In some embodiments, forming the second layer includes performing a cyclical second layer deposition process. Cycling the second layer deposition process includes a plurality of second layer deposition cycles. The second layer deposition cycle includes a second cycle precursor pulse and a second cycle reactant pulse. The second cyclical precursor pulse includes exposing the substrate to a second cyclical precursor. The second circulating reactant pulse includes exposing the substrate to a second circulating reactant.
In some embodiments, at least one of the first recycled reactant and the second recycled reactant comprises an oxygen reactant. The oxygen reactant is selected from O 2 、O 3 、H 2 O、H 2 O 2 、N 2 O、NO、NO 2 And NO 3
In some embodiments, at least one of the first cyclic precursor and the second cyclic precursor comprises a rare earth element.
In some embodiments, at least one of the first recycled precursor and the second recycled precursor comprises a late transition metal.
In some embodiments, the gap-filling precursor includes two or more anhydride functional groups.
In some embodiments, the gap-filling reactant includes two or more amine functional groups.
In some embodiments, at least one of the first metal precursor and the second metal precursor comprises a halogen.
In some embodiments, at least one of the first metal precursor and the second metal precursor comprises a carbon-containing ligand.
A substrate processing system is also described herein. The substrate processing system includes a gap-fill reaction chamber, a gap-fill etch chamber, a layer reaction chamber, a layer etch chamber, and a wafer transfer robot. The wafer transfer robot is arranged to move wafers between the gap-fill reaction chamber, the gap-fill etch chamber, the layer reaction chamber, and the layer etch chamber without any intervening vacuum interruption. The gap-fill reaction chamber is arranged for forming a gap-fill fluid on the wafer. The gap-fill etching chamber is arranged for removing gap-fill fluid from the wafer. The layer reaction chamber is arranged for forming a first layer and a second layer on a wafer. The gap-filling etching chamber is arranged for at least partially removing at least one of the first layer and the second layer from the wafer.
In some embodiments, the substrate processing system further comprises a controller arranged to cause the substrate processing system to perform the methods described herein.
These and other embodiments will become apparent to those skilled in the art from the following detailed description of certain embodiments, which is to be read in light of the accompanying drawings. The invention is not limited to any particular embodiment disclosed.
Drawings
A more complete appreciation of the embodiments of the present disclosure can be obtained by reference to the following detailed description and claims when considered in connection with the accompanying illustrative drawings.
A) -j) in fig. 1 shows an embodiment of a process for forming two different gate dielectrics for the nMOS and pMOS portions of a complementary field effect transistor (cFET).
A) -i) in fig. 2 shows another embodiment of a process for forming two different gate dielectrics for the nMOS and pMOS portions of a complementary field effect transistor (cFET).
Fig. 3 schematically shows a flow chart of an embodiment of the method described herein.
Fig. 4 schematically illustrates an embodiment of a structure 400 that may be formed using the methods described herein.
Fig. 5 illustrates another embodiment of a structure 500 that may be formed by embodiments of the methods disclosed herein.
Fig. 6a-6c illustrate further embodiments of structures 600 that may be formed by embodiments of the methods disclosed herein.
Fig. 7 illustrates an embodiment of a substrate processing system 700.
Fig. 8 illustrates another embodiment of a structure 800 according to an embodiment of the present disclosure.
Fig. 9 illustrates a system 900 according to yet another exemplary embodiment of the present disclosure.
Fig. 10 shows an embodiment of a precursor pulse.
Fig. 11 illustrates an embodiment of a cyclical deposition process.
It will be appreciated that the elements in the drawings are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the illustrated embodiments of the present disclosure.
Detailed Description
The description of the exemplary embodiments of the methods, structures, devices, and systems provided below is merely exemplary and is provided for illustrative purposes only; the following description is not intended to limit the scope of the disclosure or claims. Furthermore, recitation of multiple embodiments having stated features is not intended to exclude other embodiments having additional features or other embodiments incorporating different combinations of the stated features. For example, various embodiments are set forth as example embodiments and may be recited in the dependent claims. The exemplary embodiments or components thereof may be combined or may be applied separately from each other unless otherwise stated.
As set forth in more detail below, various embodiments of the present disclosure provide methods for forming a structure, a gate dielectric structure. The exemplary method may be used, for example, to form a complementary field effect transistor or part of such a device. Nevertheless, the invention is not necessarily limited to these examples unless otherwise indicated.
In the present disclosure, "gas" may include materials that are gases at Normal Temperature and Pressure (NTP), vaporized solids, and/or vaporized liquids, and may be composed of a single gas or a mixture of gases, as the case may be. Gases other than the process gas, i.e., gases introduced without passing through the gas distribution assembly, other gas distribution apparatus, etc., may be used, for example, to seal the reaction space, and may include a sealing gas, such as a rare gas. In some cases, the term "precursor" may refer to a compound that participates in a chemical reaction that produces another compound, particularly a compound that forms the membrane matrix or membrane backbone; the term "reactant" may be used interchangeably with the term precursor.
As used herein, the term "substrate" may refer to any underlying material or materials that may be used to form or may form devices, circuits, or films thereon. The substrate may include a host material, such as silicon (e.g., single crystal silicon), other group IV materials, such as germanium, or other semiconductor materials, such as group II-VI or group III-V semiconductor materials, and may include one or more layers overlying or underlying the host material. Further, the substrate may include various features, such as gaps, protrusions, etc., formed in or on at least a portion of the substrate layer. For example, the substrate may include a bulk semiconductor material and a layer of insulating or dielectric material covering at least a portion of the bulk semiconductor material. Additionally or alternatively, the exemplary substrate may include a bulk semiconductor material and a conductive layer overlying at least a portion of the bulk semiconductor material. Suitable substrate supports include pedestals, and the like.
As used herein, the terms "film" and/or "layer" may refer to any continuous or discontinuous structure and material, such as a material deposited by the methods disclosed herein. For example, the film and/or layer may comprise a two-dimensional material, a three-dimensional material, nanoparticles, a part or all of a molecular layer, or a part or all of an atomic layer or cluster of atoms and/or molecules. The film or layer may be partially or fully composed of a plurality of discrete atoms on the surface of the substrate and/or embedded in the substrate and/or in a device fabricated on the substrate. The film or layer may comprise a material or layer having pinholes and/or islands. The film or layer may be at least partially continuous. The film or layer may be patterned, e.g., subdivided, and may be included in a plurality of semiconductor devices.
As used herein, a "structure" may be or include a substrate as described herein. The structure may include one or more layers overlying the substrate, such as one or more layers formed according to the methods described herein. The device portion may be or include a structure.
The term "deposition process" as used herein may refer to the introduction of precursors (and/or reactants) into a reaction chamber to deposit a layer on a substrate. A "cyclical deposition process" is an example of a "deposition process".
The term "cyclical deposition process" or "cyclical deposition process" may refer to the sequential introduction of precursors (and/or reactants) into a reaction chamber to deposit a layer on a substrate, and includes processing techniques such as Atomic Layer Deposition (ALD), cyclical chemical vapor deposition (cyclical CVD), and hybrid cyclical deposition processes that include an ALD component and a cyclical CVD component.
The term "atomic layer deposition" may refer to a vapor deposition process in which a deposition cycle (typically a plurality of consecutive deposition cycles) is performed in a process chamber. The term atomic layer deposition as used herein is also meant to include processes specified by related terms, such as chemical vapor atomic layer deposition, atomic Layer Epitaxy (ALE), molecular Beam Epitaxy (MBE), gas source MBE, organometallic MBE, and chemical beam epitaxy, when performed with alternating pulses of precursor/reactive gas and purge gas (e.g., inert carrier gas).
Typically, for an ALD process, during each cycle, a precursor is introduced into the reaction chamber and chemisorbed to a deposition surface (e.g., a substrate surface that may include previously deposited material or other material from a previous ALD cycle) and a monolayer or sub-monolayer of material is formed that does not readily react with additional precursor (i.e., a self-limiting reaction). Thereafter, a reactant (e.g., another precursor or reactant gas) may then be introduced into the process chamber for converting the chemisorbed precursor to the desired material on the deposition surface. The reactants are able to react further with the precursor. In one or more cycles, such as in each step of each cycle, a purging step may be utilized to remove any excess precursor from the process chamber and/or any excess reactant and/or reaction by-products from the reaction chamber.
As used herein, the term "purge" may refer to a process of providing an inert or substantially inert gas to a reaction chamber between two pulses of gas that react with each other. For example, a purge may be provided between the precursor pulse and the reactant pulse, for example using an inert gas, such as a noble gas, to avoid or at least minimize gas phase interactions between the precursor and the reactant. It should be appreciated that the purging may be performed temporally or spatially, or both. For example, in the case of a time purge, purge steps may be used, such as in a time sequence of providing a first precursor to the reaction chamber, providing a purge gas to the reaction chamber, and providing a second precursor to the reaction chamber, wherein the substrate on which the layer is deposited does not move. For example, in the case of a space purge, the purge step may take the form of: the substrate is moved from a first position where a first precursor is continuously supplied to a second position where a second precursor is continuously supplied by a purge gas curtain.
As used herein, "precursor" includes gases or materials that may become gaseous, which may be represented by a chemical formula that includes elements that may be introduced during the deposition process described herein. The terms "precursor" and "reactant" may be used interchangeably.
Further, in this disclosure, any two numbers of a variable may constitute a viable range for that variable, and any range indicated may or may not include endpoints. Furthermore, any values of the variables noted (whether or not they are represented by "about") may refer to exact or approximate values, and include equivalents, and may refer to average values, intermediate values, representative values, multi-numerical values, and the like. Furthermore, in the present disclosure, the terms "comprising," consisting of, "and" having, "in some embodiments, independently mean" generally or broadly comprising, "" including, "" consisting essentially of, "or" consisting of.
In this disclosure, in some embodiments, any defined meaning is not necessarily excluded from the normal and customary meaning.
A method of forming a structure is described herein. The method includes the step of providing a substrate. The substrate includes a gap, such as a gap. A gap in a substrate may refer to a patterned recess, hole, via, trench, or depression in the substrate. In some embodiments, the substrate may include a plurality of adjacent gaps that may be interconnected. In some embodiments, the gap has sidewalls. Additionally or alternatively, the gap may include empty space and one or more nanoplatelets. In some embodiments, gaps may be located between adjacent surface features such as structures. The gap also includes a lower portion and an upper portion. Thus, in some embodiments, the sidewalls of the gap also have respective lower and upper portions.
In some embodiments, the methods described herein further comprise the step of forming a first layer on the sidewalls in the lower portion of the gap and on the sidewalls in the upper portion of the gap.
In some embodiments, the methods described herein further comprise forming a gap-fill fluid in the lower portion of the gap. This may be achieved, for example, by forming a relatively limited amount of gap-filling fluid that only partially fills the gap, e.g., only fills about half of the gap. Alternatively, the gap may be completely filled with the gap-filling fluid, and then the gap-filling fluid is partially removed so that the gap-filling fluid remains only in the lower portion of the gap.
In some embodiments, the lower gap extends through the lower 30% to 70% of the gap, or through the lower 40% to 60% of the gap.
The method further includes the step of selectively etching the first layer relative to the gap-fill fluid. Thus, the first layer in the upper portion of the gap is removed. It will be appreciated that the first layer is still present in the lower part of the gap, since in this position it is protected from the etchant by the gap filling fluid.
The method further includes the step of forming a second layer on one or more surfaces in the upper portion of the gap. It will be appreciated that the first and second layers have different compositions. In some embodiments, second layers are selectively formed on those second surfaces relative to the gap-fill fluid. This may advantageously facilitate the removal of the gap-filling fluid in a further processing step.
The method further includes the step of removing the gap-fill fluid. Suitable methods of removing the gap-filling fluid are disclosed elsewhere herein.
The methods described herein may be performed using a substrate that includes a gap that in turn includes one or more nanoplatelets. It should be understood that the term "nanoplatelets" as used herein includes the meaning of other elongated features such as nanowires, nanorods, and nanotubes. In some embodiments, the nanoplatelets have a critical dimension of at least 1nm to at most 50nm, or at least 1nm to at most 5nm, or at least 5nm to at most 20nm, or at least 20nm to at most 50 nm. Thus, methods of forming structures are further described herein. The method includes providing a substrate. The substrate includes a gap. The gap includes a lower portion and an upper portion. The lower portion includes a first set of nanoplatelets. The upper portion includes a second set of nanoplatelets.
The method further includes forming a first layer over the first set of nanoplatelets and over the second set of nanoplatelets. In some embodiments, the gap has sidewalls. In some embodiments, the first layer is also formed on the sidewalls of the gap.
The method further includes forming a gap-fill fluid in the lower portion of the gap, thereby encapsulating the first set of nanoplatelets in the gap-fill fluid. This may be achieved, for example, by forming a relatively limited amount of gap-filling fluid that only partially fills the gap, e.g., only fills about half of the gap. Alternatively, the gap may be completely filled with the gap-filling fluid, and then the gap-filling fluid is partially removed so that the gap-filling fluid remains only in the lower portion of the gap. In any event, it should be appreciated that upon completion of this processing step, the gap-filling fluid encapsulates the first set of nanoplatelets and does not encapsulate the second set of nanoplatelets. Furthermore, it should be understood that the expression "forming gap-filling fluid" may alternatively be described as "fluid deposition". Optionally, the formation of the gap-fill fluid may be followed by a step of annealing the substrate using a gap-fill fluid anneal, such as in a nitrogen or rare gas atmosphere. Suitable annealing temperatures may include a range of at least 100 ℃ to at most 500 ℃.
The method further includes selectively etching the first layer relative to the gap-fill fluid. Thus, the first layer is removed from the second set of nanoplatelets. It should be appreciated that the first layer is still present on the first set of nanoplatelets because at this location it is protected from the etchant by the gap-filling fluid.
The method further includes the step of forming a second layer over the second set of nanoplatelets. It will be appreciated that the first and second layers have different compositions.
Once the first and second layers are formed, the gap-fill fluid may be removed. Thus, a structure is formed in which a first layer is formed on a first set of nanoplatelets and a second layer is formed on a second set of nanoplatelets.
In some embodiments, the step of removing the gap-fill fluid from the lower portion of the gap is followed by forming a high-k dielectric on the first layer and on the second layer. Then, in some embodiments, the substrate may be annealed. Thus, a first gate dielectric may be formed from the first layer and the high-k dielectric and a second gate dielectric may be formed from the second layer and the high-k dielectric. It should be appreciated that the first gate dielectric and the second gate dielectric are different.
The methods described herein may also be performed using a substrate that includes a gap that in turn includes one or more nanoplatelets, such as nanoplatelets, nanorods, or nanowires, wherein the nanoplatelets are covered with a high-k dielectric prior to forming the first or second layer on the nanoplatelets. Thus, a method for forming a structure is further described. The method includes providing a substrate. The substrate includes a gap. In some embodiments, the gap includes a sidewall. The gap includes a lower portion and an upper portion. The lower portion includes a first set of nanoplatelets. The upper portion includes a second set of nanoplatelets. The method also includes forming a high-k dielectric on the first set of nanoplatelets and on the second set of nanoplatelets. The method also includes forming a first layer on the high-k dielectric on the first set of nanoplatelets and on the high-k dielectric on the second set of nanoplatelets.
The method further includes forming a gap-fill fluid in the lower portion of the gap, thereby encapsulating the first set of nanoplatelets in the gap-fill fluid. This may be achieved, for example, by forming a relatively limited amount of gap-filling fluid that only partially fills the gap, e.g., only fills about half of the gap. Alternatively, the gap may be completely filled with the gap-filling fluid, and then the gap-filling fluid is partially removed so that the gap-filling fluid remains only in the lower portion of the gap. In any event, it should be appreciated that upon completion of this processing step, the gap-filling fluid encapsulates the first set of nanoplatelets and does not encapsulate the second set of nanoplatelets.
The method also includes selectively etching the first layer relative to the gap-fill fluid and relative to the high-k dielectric. Thus, the first layer is removed from the second set of nanoplatelets. It should be appreciated that the first layer is still present on the first set of nanoplatelets because at this location it is protected from the etchant by the gap-filling fluid.
The method further includes the step of forming a second layer over the high-k dielectric over the second set of nanoplatelets. It will be appreciated that the first and second layers have different compositions.
Once the first and second layers are formed, the gap-fill fluid may be removed. Thus, a structure is formed in which a first layer is formed on a first set of nanoplatelets and a second layer is formed on a second set of nanoplatelets.
Then, in some embodiments, the substrate may be annealed. Thus, a first gate dielectric may be formed from the first layer and the high-k dielectric and a second gate dielectric may be formed from the second layer and the high-k dielectric. It should be appreciated that the first gate dielectric and the second gate dielectric are different.
In some embodiments, at least one of the first set of nanoplatelets and the second set of nanoplatelets comprises a single crystalline semiconductor. Suitable monocrystalline semiconductors include doped or undoped silicon. Undoped silicon may be referred to as intrinsic silicon. The doped silicon may include an n-type dopant, such as phosphorus, arsenic, or antimony. Additionally or alternatively, the doped silicon may include a p-type dopant, such as boron, aluminum, or indium. In some embodiments, the single crystal semiconductor includes silicon and a group 14 element, such as carbon, germanium, or tin.
In some embodiments, the step of removing the gap-fill fluid is followed by a step of annealing the substrate. Suitable annealing includes annealing the substrateSubjected to thermal energy. For example, annealing may include including N 2 The substrate is heated to a temperature of at least 300 ℃ and at most 600 ℃. Thus, the first gate dielectric is formed of the first layer and the high-k dielectric. In addition, the second gate dielectric is formed from the second layer and the high-k dielectric.
In some embodiments, the gap-filling fluid comprises an oligomeric compound. For example, the oligomeric compound may contain at least 2 and up to 100 repeating groups, for example 5, 10, 20 or 50 repeating groups.
Suitable gap-filling fluids include carbon-containing polymers such as polyimide, polyvinyltoluene, polyethylene, polypropylene, polyaramid, polyimide, polystyrene, polyamic acid, and polymethyl methacrylate. In some embodiments, the gap-filling fluid includes a plurality of imide functional groups.
In some embodiments, the gap-fill fluid may be deposited using the methods and apparatus described in U.S. patent No. 10695794B 2.
In some embodiments, forming the gap-fill fluid includes exposing the substrate to a gap-fill precursor and exposing the substrate to a gap-fill reactant. In some embodiments, the substrate is exposed to both the gap-filling precursor and the gap-filling reactant.
In some embodiments, forming the gap-fill fluid includes performing a cyclical gap-fill deposition process. The cyclical deposition process includes a plurality of gap-fill deposition cycles. A single gap-fill deposition cycle includes a gap-fill precursor pulse and a gap-fill reactant pulse. The gap-filling precursor pulse includes exposing the substrate to the gap-filling precursor. The gap-fill reactant pulse includes exposing the substrate to the gap-fill reactant.
In some embodiments, forming the gap-fill fluid includes generating a plasma. The plasma may be generated in a reaction chamber or in a separate plasma chamber, i.e., a remote plasma unit, operatively connected to the reaction chamber in which the gap-filling fluid is formed.
In some embodiments, forming the gap-filling fluid is performed thermally. For example, a polyimide gap fill fluid may be thermally formed.
In some embodiments, forming the first layer, forming the second layer, and forming the gap-fill fluid are all performed in the absence of a plasma. In other words, in some embodiments, forming the first layer, forming the second layer, and forming the gap-fill fluid are performed thermally. In other words, in some embodiments, the methods described herein do not include using a plasma to form an active species for a deposition process.
In some embodiments, forming the first layer includes performing a cyclical first layer deposition process. Cycling the first layer deposition process includes a plurality of first layer deposition cycles. The separate first layer deposition cycle includes a first cycle precursor pulse and a first cycle reactant pulse. The first cyclical precursor pulse includes exposing the substrate to a first cyclical precursor. The first circulating reactant pulse includes exposing the substrate to a first circulating reactant.
In some embodiments, forming the second layer includes performing a cyclical second layer deposition process. Cycling the second layer deposition process includes a plurality of second layer deposition cycles. The separate second layer deposition cycle includes a second cycle precursor pulse and a second cycle reactant pulse. The second cyclical precursor pulse includes exposing the substrate to a second cyclical precursor. The second circulating reactant pulse includes exposing the substrate to a second circulating reactant.
In some embodiments, at least one of the first layer and the second layer has a step coverage equal to or greater than about 50%, or greater than about 80%, or greater than about 90%, or about 95%, or about 98%, or about 99% or greater. It should be understood that the term "step coverage" may refer to the growth rate of a layer on the gap distal surface divided by the growth rate of that layer on the gap proximal surface, and expressed as a percentage. It should be understood that the distal portion of the gap may refer to a portion of the gap that is relatively far from the substrate surface, while the proximal portion of the gap feature refers to a portion of the gap feature that is closer to the substrate surface than the distal/lower/deeper portion of the gap feature.
At least one of the first layer and the second layer having a desired thickness may be formed by performing an appropriate number of cycles. The total number of cycles depends inter alia on the total layer thickness required. In some embodiments, at least one of the first layer and the second layer may be formed using the following cycle: at least 2 cycles to at most 5 cycles, or at least 5 cycles to at most 10 cycles, or at least 10 cycles to at most 20 cycles, or at least 20 cycles to at most 50 cycles, or at least 50 cycles to at most 100 cycles, or at least 100 cycles to at most 200 cycles, or at least 200 cycles to at most 500 cycles, or at least 500 cycles to at most 1000 cycles, or at least 1000 cycles to at most 2000 cycles, or at least 2000 cycles to at most 5000 cycles, or at least 5000 cycles to at most 10000 cycles.
In some embodiments, at least one of the first layer and the second layer has a thickness of at least 0.1nm to at most 5nm, or at least 0.2nm to at most 5nm, or at least 0.3nm to at most 4nm, or at least 0.4nm to at most 3nm, or at least 0.5nm to at most 2nm, or at least 0.7nm to at most 1.5nm, or at least 0.9nm to at most 1.0nm.
In some embodiments, at least one of the first layer and the second layer has a thickness of at most 5.0nm, or at most 4.0nm, or at most 3.0nm, or at most 2.0nm, or at most 1.5nm, or at most 1.0nm, or at most 0.8nm, or at most 0.6nm, or at most 0.5nm, or at most 0.4nm, or at most 0.3nm, or at most 0.2nm, or at most 0.1 nm.
It should be appreciated that in some embodiments of any cyclic process as described herein, one or more subsequent pulses may be separated by a purge step. Providing a purge step between subsequent pulses may minimize parasitic gas phase reactions between the precursor and the reactant.
In some embodiments, at least one of the first recycled reactant and the second recycled reactant comprises an oxygen reactant. The oxygen reactant is selected from O 2 、O 3 、H 2 O、H 2 O 2 、N 2 O、NO、NO 2 And NO 3
In some embodiments, at least one of the first cyclic precursor and the second cyclic precursor comprises a rare earth element. Suitable rare earth elements include lanthanum, cerium, praseodymium.
In some embodiments, at least one of the first cyclic precursor and the second cyclic precursor comprises a d-block element. Suitable d-block elements include scandium.
In some embodiments, at least one of the first recycled precursor and the second recycled precursor comprises a post-transition metal, such as aluminum.
In some embodiments, at least one of the first metal precursor and the second metal precursor comprises a halogen, such as chlorine, bromine, or iodine.
In some embodiments, at least one of the first metal precursor and the second metal precursor comprises a carbon-containing ligand.
In some embodiments, the gap-filling precursor includes two or more anhydride functional groups. Suitable gap-filling precursors include 1,2,4, 5-benzenetetracarboxylic anhydride.
In some embodiments, the gap-filling reactant includes two or more amine functional groups. Suitable gap-filling reactants include ethylenediamine, 1, 6-diaminohexane, 1, 4-phenylenediamine, and 4,4' -oxydiphenylamine.
A processing system is also described herein. The substrate processing system includes a gap-fill reaction chamber, a gap-fill etch chamber, a layer reaction chamber, a layer etch chamber, and a wafer transfer robot. The wafer transfer robot is arranged to move wafers between the gap-fill reaction chamber, the gap-fill etch chamber, the layer reaction chamber, and the layer etch chamber without any intervening vacuum interruption. The gap-fill reaction chamber is arranged for forming a gap-fill fluid on the wafer. The gap-fill etching chamber is arranged for removing gap-fill fluid from the wafer. The layer reaction chamber is arranged for forming a first layer and a second layer on a wafer. The gap-filling etching chamber is arranged for removing at least one of the first layer and the second layer from the wafer.
In some embodiments, the processing system further comprises a controller. The controller is arranged to cause the substrate processing system to perform the methods described herein.
Streamable as used hereinThe mobile material is relatively acidic (e.g., aqueous Hydrogen Fluoride (HF) and aqueous hydrogen chloride (HCl)) and alkaline (e.g., aqueous ammonia, NH 3 (aq)) may have a low wet etch rate. Such an acidic etchant may be advantageously used to etch at least one of the high-k dielectric, the first layer, and the second layer. For example, table 1 shows wet etch rate data for flowable polyimide materials.
The flowable material is formed using a cyclical deposition process that includes a plurality of gap-fill deposition cycles. The gap-fill deposition cycle includes a gap-fill precursor pulse and a gap-fill reactant pulse. The gap-filling precursor pulse includes exposing the substrate to the gap-filling precursor. The gap-fill reactant pulse includes exposing the substrate to the gap-fill reactant.
In an exemplary embodiment, the gap-fill precursor comprises 1,2,4, 5-benzenetetracarboxylic anhydride (PMDA) and the gap-fill reactant comprises 1, 6-Diaminohexane (DAH). Such precursor-reactant pairs can be used to cyclically form polyimide gap-fill fluids using a substrate temperature of at least 150 ℃ to at most 200 ℃ and a reaction chamber pressure of at least 0.1 torr to at most 50 torr. Suitable PMDA pulse times include from at least 100ms to at most 20000ms. Suitable DAH pulse times include from at least 50ms to at most 10000ms. The PMDA pulse may be followed by a PMDA purge lasting, for example, from at least 1000ms to at most 30000 ms. The DAH pulse may be followed by a DAH purge lasting, for example, from at least 1000ms to at most 20000ms.
Of course, other suitable gap-filling precursors or reactants may be used. For example, 1, 4-phenylenediamine may be used as a gap-filling reactant.
The flowable polyimide material can have excellent etch resistance to dilute aqueous HCl and dilute aqueous HF. Such an etchant may etch dipole materials and high-k dielectrics, such as metal oxides. Thus, such an etchant may be used to selectively etch at least one of a dipole material and a high-k dielectric with respect to a polyimide gap fill fluid.
In an exemplary embodiment, reference is made to fig. 1. Fig. 1 shows an embodiment of a process for forming two different gate dielectrics for nMOS and pMOS portions of a complementary field effect transistor (cFET). In this embodiment, two different dipole layers are formed on the intermediate layer 150, and then a high-k dielectric is formed on the two different dipole layers. The structure 100 is particularly shown in fig. 1 at various stages of processing.
In particular, a) in fig. 1 shows a structure 100 comprising a substrate 110. A dielectric substrate surface layer 120, such as a silicon oxide layer, is formed on the substrate. The structure 100 also includes spacers 130. For example, the spacers 130 may be made of a dielectric layer such as silicon nitride. There is a gap 135 between the spacers 130. Two sets of nanoplates 160, 170 are located in the gap: a first set of nanoplatelets 160 and a second set of nanoplatelets 170. In some embodiments, at least one of the first set of nanoplatelets 160 and the second set of nanoplatelets 170 can comprise silicon. Each set 160, 170 includes at least one nanoplatelet 140, and the surface of each nanoplatelet 140 includes an intermediate layer 150. In the illustrated embodiment, each set 160, 170 includes two nanoplates 140. However, configurations with three or more nanoplates per set are also possible. It should be understood that other nanoplatelets besides nanoplatelets may also be used. Examples of suitable nanoplates include nanorods, nanowires, and nanotubes.
B) in fig. 1 shows the structure 100 after the formation of the first dipole layer 165 using a conformal deposition technique. Suitable conformal deposition techniques include cyclical deposition techniques, such as Atomic Layer Deposition (ALD). A first dipole layer 165 is formed on the first set of nanoplatelets 160 and on the second set of nanoplatelets 170. In addition, a first dipole layer 165 is also formed on the dielectric substrate surface layer 120 and on the spacer 130. It should be appreciated that in some embodiments, the spacer 130 need not be monolithic, but may even be omitted. For example, the gap 135 may correspond to a blank space between two adjacent structures, such as shown in fig. 6a and 6 b.
C) in fig. 1 shows the structure 100 after the gap 135 has been filled with gap-filling fluid 180. Suitable gap-filling fluids include carbon-containing oligomers. Suitable carbon-containing oligomers include oligomeric hydrocarbons, oligomeric amides, oligomeric amines, oligomeric polyurethanes, and oligomeric polyimides. The gap-filling fluid covers the first set of nanoplatelets 160 and the second set of nanoplatelets 170.
D) in fig. 1 shows the structure 100 after the gap-fill fluid 180 has been partially etched away to expose the second set of nanoplatelets 170 while still covering the first set of nanoplatelets 160. In some embodiments, exposure to an oxygen-containing gas, such as O, may be used 2 、H 2 O 2 、H 2 O、O 3 、N 2 O, NO or NO 2 To etch gap-fill fluid 180. Alternatively, the gap-fill fluid 180 may be etched using a plasma that employs a plasma recipe that includes H 2 、N 2 And NH 3 One or more of the plasma gases. Thus, in some embodiments, the etching process may include exposing the substrate to a plasma. In some embodiments, the plasma may include oxygen atoms, oxygen radicals, oxygen plasma, or a combination thereof. In some embodiments, the plasma may include hydrogen atoms, hydrogen radicals, hydrogen plasma, or a combination thereof. In some embodiments, the plasma may also include rare gas species, such as Ar or He species. In some embodiments, the plasma may consist essentially of a rare gas species. In some cases, the plasma may include other species, such as nitrogen atoms, nitrogen radicals, nitrogen plasma, or combinations thereof.
Alternatively, a wet etchant solution may be used to remove the gap-fill fluid, such as a wet etchant solution, a polar solvent, or an alkaline solution. Suitable solvents may include dipolar amides such as N-methyl-2-pyrrolidone, dimethylacetamide and dimethylformamide. Other suitable solvents may include alkyl sulfoxides such as dimethyl sulfoxide, phenol derivatives such as m-cresol and o-chlorophenol, and chlorinated solvents such as chloroform.
In alternative embodiments, the etching step may be omitted and the structure of d) in fig. 1 may be obtained by filling half of the gap 135 with the gap filling fluid 180.
E) in fig. 1 shows the structure 100 after etching the first dipole layer 165 from the second set of nanoplatelets 170. The etchant used selectively etches the first dipole layer 165 relative to the gap-fill fluid 180. Thus, the first dipole layer on the second set of nanoplatelets 170 is etched away, while the first dipole layer 165 on the first set of nanoplatelets 160 is protected and remains intact by the gap fill fluid 180.
In some embodiments, the etchant may damage or affect the gap-fill fluid 180 in an undesirable manner, such as in a manner that compromises its growth-suppressing characteristics. Thus, in some embodiments, the remaining gap-filling fluid may optionally be completely removed, and the gap 135 may be partially refilled. As previously described, partial refill may occur by complete filling and subsequent etching, or by filling half of the gap 135. Thus, a structure 100 comprising a refill gap may be obtained, as indicated by f) in fig. 1.
G) in fig. 1 illustrates the structure 100 after forming the second dipole layer 175 using a conformal deposition technique such as ALD. It will be appreciated that the first and second dipole layers have different compositions. For example, one of the first dipole layer and the second dipole layer may include a post-transition metal oxide, such as alumina, and the other may include an oxide of a rare earth element, such as lanthanum oxide.
H) in fig. 1 shows the structure 100 after the gap-fill fluid 180 has been completely removed from the structure 100.
I) in fig. 1 shows the structure 100 after forming a high-k layer 190 on the first dipole layer 165 and the second dipole layer 175. In some embodiments, the high-k layer may be formed using a conformal deposition method, such as Atomic Layer Deposition (ALD). Suitable high-k layers include hafnium oxide.
J) in fig. 1 shows structure 100 wherein after annealing, a first gate dielectric 166 is formed over the first set of nanoplatelets 160 and a second gate dielectric 176 is formed over the second set of nanoplatelets. The first gate dielectric 166 and the second gate dielectric 176 comprise different dipoles. For example, the first gate dielectric 166 includes a p-type dipole and the second gate dielectric 176 includes an n-type dipole; or the first gate dielectric 166 comprises an n-type dipole and the second gate dielectric 176 comprises a p-type dipole. The structure 100 as shown in j) in fig. 1 is particularly advantageous for forming a complementary field effect transistor comprising a first set of nano-platelets and a first gate dielectric and a second transistor comprising a second set of nano-platelets and a second gate dielectric. Because the first gate dielectric and the second gate dielectric comprise different dipoles, their threshold voltages can be independently controlled.
In another exemplary embodiment, refer to FIG. 2. Fig. 2 shows another embodiment of a process for forming two different gate dielectrics for nMOS and pMOS portions of a complementary field effect transistor (cFET). The structure 200 is particularly shown in fig. 2 at various stages of processing.
In particular, a) in fig. 2 shows a structure 200 comprising a substrate 210. A dielectric substrate surface layer 220, such as a silicon oxide layer, is formed over the substrate. The structure 200 also includes spacers 230. For example, the spacers 230 may be made of a dielectric layer such as silicon nitride. A gap 235 exists between the spacers 230. Two sets of nanoplatelets 260, 270 are located in the gap: a first set of nanoplatelets 260 and a second set of nanoplatelets 270. In some embodiments, at least one of the first set of nanoplatelets 260 and the second set of nanoplatelets 270 can comprise silicon. Each set 260, 270 includes at least one nanoplatelet 240, and the surface of each nanoplatelet 240 includes an intermediate layer 250. In the illustrated embodiment, each set 260, 270 includes two nanoplatelets 240. However, configurations with three or more nanoplates per set are also possible. The high-k material 290 is present on the intermediate layer 250 of the first set of nano-platelets 260 and on the intermediate layer 250 of the second set of nano-platelets 270. In addition, a high-k material is also formed on the dielectric substrate surface layer 220 and on the spacers 230.
B) in fig. 2 illustrates structure 200 after formation of first dipole layer 265 using a conformal deposition technique. Suitable conformal deposition techniques include cyclical deposition techniques, such as Atomic Layer Deposition (ALD). A first dipole layer 265 is formed on the high-k material 290 overlying the first set of nano-sheets 260 and on the high-k material overlying the second set of nano-sheets 270. In addition, a high-k material is also formed on the first dipole layer 265 covering the dielectric substrate surface layer 220 and on the first dipole layer 265 covering the spacers 230.
C) in fig. 2 shows structure 200 after gap 235 is filled with gap-filling fluid 280. Suitable gap-filling fluids are described elsewhere herein, including carbon-containing oligomers. Suitable carbon-containing oligomers include oligomeric hydrocarbons, oligomeric amides, oligomeric amines, oligomeric polyurethanes, and oligomeric polyimides. The gap-filling fluid covers the first set of nanoplatelets 260 and the second set of nanoplatelets 270.
D) in fig. 2 shows structure 200 after gap-fill fluid 280 has been partially etched away to expose second set of nanoplatelets 270 while still covering first set of nanoplatelets 260. In some embodiments, exposure to an oxygen-containing gas, such as O, may be used 2 、H 2 O 2 、H 2 O or O 3 Or N 2 O, NO or NO 2 To etch gap-fill fluid 280. In some embodiments, a method including H may be used 2 、N 2 And NH 3 The gap fill fluid 280 is etched by the plasma gas of one or more of the above. In alternative embodiments, the etching step may be omitted and the structure of d) in fig. 1 may be obtained by filling half of the gap 235 with the gap-filling fluid 280.
E) in fig. 1 shows the structure 200 after etching away the first dipole layer 265 from the second set of nano-sheets 270. The etchant used selectively etches the first dipole layer 265 relative to the gap-fill fluid 280. Thus, the first dipole layer on the second set of nanoplatelets 270 is etched away, while the first dipole layer 265 on the first set of nanoplatelets 260 is protected and remains intact by the gap fill fluid 280.
In some embodiments, the etchant may damage or affect the gap-fill fluid 280 in an undesirable manner, such as in a manner that compromises its growth-suppressing characteristics. Thus, in some embodiments, the remaining gap-filling fluid may optionally be completely removed, and the gap 235 may be partially refilled. As previously described, partial refill may be performed by completely filling and subsequently forming the gap, or by filling half of the gap 235. Thus, a structure 200 comprising a refill gap may be obtained, as indicated by f) in fig. 2.
G) in fig. 2 illustrates the structure 200 after forming the second dipole layer 275 using a conformal deposition technique such as ALD. It will be appreciated that the first and second dipole layers have different compositions. For example, one of the first dipole layer and the second dipole layer may include a post-transition metal oxide, such as aluminum oxide, and the other may include an oxide of a rare earth element, such as lanthanum oxide or scandium oxide.
H) in fig. 2 shows the structure 200 after the gap-fill fluid 280 has been completely removed from the structure 200.
I) in fig. 2 shows structure 200 wherein after annealing, a first gate dielectric 266 is formed over first set of nanoplatelets 260 and a second gate dielectric 276 is formed over second set of nanoplatelets 270. The first gate dielectric 266 and the second gate dielectric 276 comprise different dipoles. For example, the first gate dielectric 266 comprises a p-type dipole and the second gate dielectric 276 comprises an n-type dipole; or the first gate dielectric 266 comprises an n-type dipole and the second gate dielectric 276 comprises a p-type dipole. The structure 200 as shown in i) in fig. 2 is particularly advantageous for forming a complementary field effect transistor comprising a first set of nano-platelets and a first gate dielectric and a second transistor comprising a second set of nano-platelets and a second gate dielectric. Because the first gate dielectric and the second gate dielectric comprise different dipoles, their threshold voltages can be independently controlled.
It should be appreciated that in some embodiments (not shown), additional layers may be formed prior to annealing. Examples of such additional layers may include transition metal nitrides, such as TiN, which may be formed using conformal deposition techniques, such as Atomic Layer Deposition (ALD).
In another exemplary embodiment, reference is made to fig. 3 and 4. Fig. 3 schematically shows a flow chart of an embodiment of the method described herein. Fig. 4 schematically illustrates an embodiment of a structure 400 that may be formed using the methods described herein.
The method according to the embodiment shown in fig. 3 comprises a step 310 of positioning the substrate on a substrate support. The substrate includes a gap 440 formed in the substrate material 430. Gap 440 includes a lower portion 401 and an upper portion 402. In some embodiments (not shown), the gap may include additional features, such as nanoplatelets. Indeed, the method according to the embodiment of fig. 3 may be used to form a structure as shown in the embodiments of fig. 1 and 2.
The method according to the embodiment shown in fig. 3 further comprises a step 320 of forming a first layer. The first layer may be formed using a conformal deposition technique and formed on the lower portion 401 and the upper portion 402 of the gap 440. Suitable conformal deposition techniques include cyclical deposition techniques, such as Atomic Layer Deposition (ALD).
The method according to the embodiment shown in fig. 3 further comprises a step 330 of forming a gap-filling fluid. The gap-filling fluid may be formed to fill the lower portion 401 of the gap 440 instead of the upper portion 402 of the gap 440. Alternatively, the gap filling fluid may be formed to fill not only the lower portion 401 of the gap 440, but then it may be partially etched such that after etching, it fills only the lower portion 401 of the gap 440, but not the upper portion 402 of the gap 440. Suitable gap-filling fluids are described elsewhere herein, including carbon-containing oligomers.
The method according to the embodiment shown in fig. 3 further comprises a step 340 of selectively etching the first layer in the upper portion 402 of the gap 440 with respect to the gap-filling fluid. The gap filling fluid protects the first layer in the lower portion 401 of the gap 440. Thus, the first layer in the upper portion 402 of the gap is etched away, while the first layer in the lower portion 401 of the gap 440 is protected and remains intact by the gap filling fluid.
In some embodiments, the etching step 340 may damage or affect the gap-fill fluid in an undesirable manner, such as in a manner that compromises its growth-suppressing characteristics. Thus, in some embodiments, the remaining gap-filling fluid may optionally be completely removed and the gap may be partially refilled, which is shown in fig. 3 as an optional step 350 of removing and reforming the gap-filling fluid. As previously mentioned, partial refill may be performed by completely filling and subsequently forming the gap, or by filling half of the gap. Thus, a structure including a refill gap can be obtained.
The method of the embodiment of fig. 3 then includes the step of forming a second layer 360. The second layer may be formed using a conformal deposition technique such as ALD. It will be appreciated that the first and second layers have different compositions. For example, one of the first and second layers may include a late transition metal, such as alumina, and the other may include an oxide of a rare earth element, such as lanthanum oxide. Advantageously, a second layer may be selectively deposited on the upper portion 402 of the gap 440 relative to the gap-filling fluid. Thus, in a further processing step 370, the gap-fill fluid may be easily removed, which is not shielded from the process gas by any enclosed overburden formed thereon.
Once the gap-fill fluid is removed, a structure 400 is formed as shown in fig. 4. Structure 400 includes a gap 440 formed in substrate material 430. Gap 440 includes a lower portion 401 and an upper portion 402. The first layer 410 is present on the surface of the lower portion 401 of the gap 440. The second layer 420 is present on the surface of the upper portion 402 of the gap 440.
In some embodiments, one of the first layer and the second layer comprises a d-block metal oxide, such as scandium oxide or a rare earth metal oxide, such as lanthanum oxide. The other of the first and second layers may comprise a post-transition metal oxide, such as gallium oxide or aluminum oxide.
In some embodiments, the high-k material includes a transition metal oxide, such as hafnium oxide. In some embodiments, hafnium oxide may be deposited using an ALD process that uses a hafnium precursor and an oxygen reactant. Suitable hafnium precursors include hafnium halides, such as HfCl 4 And alkylamide hafnium precursors, such as tetrakis (dimethylamide) hafnium (IV). Suitable oxygen reactants include H 2 O。
Fig. 5 illustrates another embodiment of a structure 500, which structure 500 may be formed by embodiments of the methods disclosed herein. Structure 500 includes a gap 540 formed in substrate material 530. Gap 540 includes lower portion 501 and upper portion 502. The first layer 510 is present on the surface of the lower portion 501 of the gap 540. The second layer 520 is present on the surface of the upper portion 502 of the gap 540. Two sets of nanoplates 560, 570 are located in gap 540: a first set of nanoplatelets 560 and a second set of nanoplatelets 570. In particular, a first set of nano-sheets 560 is located in the lower portion 501 of the gap 540 and a second set of nano-sheets 570 is located in the upper portion of the gap 540.
Fig. 6a illustrates another embodiment of a structure 600, which structure 600 may be formed by embodiments of the methods disclosed herein. Structure 600 includes gaps 640 formed between adjacent structural features 635. Adjacent structure features 635 may include other structures that are, for example, at the same stage of processing as structure 600. Indeed, it should be appreciated that in integrated circuit fabrication, billions or even trillions of structures 600 may be fabricated simultaneously, and that many structures 600 may be placed side-by-side. Gap 640 overlies a substrate that includes substrate material 630. Gap 640 includes lower portion 601 and upper portion 602. The first layer 610 is present on the surface of the lower portion 601 of the gap 640. The second layer 620 is present on the surface of the upper portion 602 of the gap 640. Two sets of nanoplatelets 660, 670 are located in gap 640: a first set of nanoplatelets 660 and a second set of nanoplatelets 670. In particular, a first set of nanoplatelets 660 is located in a lower portion 601 of gap 640 and a second set of nanoplatelets 670 is located in an upper portion of gap 640. A first layer 610 is formed over a first set of nanoplatelets 660 and a second layer 620 is formed over a second set of nanoplatelets 670.
Fig. 6b shows a structure 600 as in fig. 6a, except that the substrate is covered with a dielectric layer 636 and dielectric spacers 637 are located between the first set of nanoplatelets 660 and the second set of nanoplatelets 670. Dielectric layer 636 and dielectric spacer 637 may comprise any suitable dielectric, such as silicon oxide, silicon nitride, silicon carbide, and mixtures thereof.
Fig. 6c shows the structure 600 as shown in fig. 6c, but with a cross section perpendicular to the cross section shown in fig. 6 b. In particular, it is shown how the first set of nano-platelets 660 bridge the gap 640 between the first source 691 and the first drain 692. It is also shown how the second set of nano-platelets 670 bridge the gap 640 between the second source 643 and the second drain 644. Thus, the first set of nano-sheets 660 may form the channel region of the first transistor and the second set of nano-sheets 670 may form the channel region of the second transistor 670. In some embodiments, the source 693 of the second transistor may be epitaxially grown on the source 691 of the first transistor. In some embodiments, the drain 694 of the second transistor may be epitaxially grown on the drain 692 of the first transistor.
Fig. 7 illustrates an embodiment of a substrate processing system 700. The substrate processing system 700 includes a gap-filling reaction chamber 710. The gap-fill reaction chamber 710 is arranged to form a gap-fill fluid on the substrate. The substrate processing system 700 also includes a gap-fill etch chamber 715. The gap-fill etching chamber 715 is arranged to remove gap-fill fluid from the substrate. The substrate processing system 700 also includes a layer reaction chamber 720. The layer reaction chamber 720 is arranged for forming at least one of a first layer and a second layer on a substrate. The substrate processing system 700 also includes a layer etching chamber 725. The layer etching chamber 725 is arranged for at least partially removing at least one of the first layer and the second layer from the substrate. The substrate processing system 700 also includes a wafer transfer robot 730. The wafer transfer robot 730 is arranged to move wafers between the gap-fill reaction chamber, the gap-fill etch chamber, the layer reaction chamber, and the layer etch chamber without any intervening vacuum interruption. The substrate processing system 700 also includes a controller 740. The controller 740 is arranged to cause the substrate processing system to perform the methods described herein.
Fig. 8 illustrates another embodiment of a structure 800 according to an embodiment of the present disclosure. The structure 800 is suitable for forming nanoplates for inclusion in a fully-surrounding gate field effect transistor (GAA FET) (also known as a lateral nanowire FET) device or the like, which in turn may be part of a complementary field effect transistor.
In the example shown, structure 800 includes a semiconductor material 802, a dielectric material 804, a work function layer 806, and a conductive layer 808. Structure 800 may be formed overlying a substrate, including any of the substrate materials described herein. The work function layer 806 may be located between the conductive layer 808 and the dielectric material 806 as shown. Alternatively, the work function layer 806 may be located inside the conductive layer 808 (embodiment not shown). Suitable work function layers may include metals, metal carbides, metal nitrides, or mixtures thereof. Suitable metals include transition metals such as tungsten, molybdenum, ruthenium, post-transition metals such as aluminum, and rare earth metals such as lanthanum, cerium, and praseodymium. Suitable conductive layers may include metal nitrides, such as titanium nitride.
Semiconductor material 802 may comprise any suitable semiconductor material. For example, semiconductor material 802 may include a group IV, III-V, or II-VI semiconductor material. For example, semiconductor material 802 may include silicon.
Fig. 9 illustrates a system 900 according to yet another exemplary embodiment of the present disclosure. The system 900 may be used to form gap-fill fluids in the methods described herein and/or to form portions of structures or devices described herein.
In the illustrated example, the system 900 includes one or more reaction chambers 902, a gap-fill precursor gas source 904, a gap-fill reactant gas source 906, a purge gas source 908, an exhaust 910, and a controller 912.
The reaction chamber 902 may comprise any suitable reaction chamber, such as an ALD or CVD reaction chamber.
The gap-filling precursor gas source 904 can include a container and one or more precursors as described herein, alone or in combination with one or more carrier gases (e.g., noble gases). The gap-filling reactant gas source 906 can include a container and one or more reactants as described herein, alone or in combination with one or more carrier gases. The purge gas source 908 may include one or more noble gases as described herein. Although three gas sources 904-908 are shown, the system 900 may include any suitable number of gas sources. The gas sources 904-908 may be coupled to the reaction chamber 902 via lines 914-918, which lines 914-918 may each include a flow controller, valve, heater, etc.
The exhaust 910 may include one or more vacuum pumps.
The controller 912 includes electronic circuitry and software to selectively operate valves, manifolds, heaters, pumps, and other components included in the system 900. Such circuits and components are used to introduce precursor and purge gases from the respective sources 904-908. The controller 912 can control the timing of the gas pulse sequences, the temperature of the substrate and/or the reaction chamber, the pressure within the reaction chamber, and various other operations to provide proper operation of the system 900. The controller 912 may include control software to electrically or pneumatically control valves to control the flow of precursors, reactants, and purge gases into and out of the reaction chamber 902. The controller 912 may include modules, such as software or hardware components, such as FPGAs or ASICs, that perform certain tasks. The modules may advantageously be configured to reside on an addressable storage medium of the control system and configured to perform one or more processes.
Other configurations of the system 900 are possible, including different amounts and types of precursor and reactant sources, as well as purge gas sources. Further, it should be appreciated that there are many arrangements of valves, conduits, precursor sources, and purge gas sources that can be used to achieve the goal of selectively supplying gas into the reaction chamber 902. Further, as a schematic representation of the system, many components have been omitted for simplicity of illustration, and may include, for example, various valves, manifolds, purifiers, heaters, containers, vents, and/or bypasses.
During operation of the reactor system 900, a substrate, such as a semiconductor wafer (not shown), is transferred from, for example, a substrate processing system to the reaction chamber 902. Once the substrate is transferred to the reaction chamber 902, one or more gases, such as precursors, reactants, carrier gases, and/or purge gases, from the gas sources 904-908 are introduced into the reaction chamber 902.
Fig. 10 illustrates an embodiment of a precursor pulse, such as a gap-filling precursor pulse, a first precursor pulse, or a second precursor pulse, according to an exemplary method disclosed herein. The precursor pulse starts 1011 and a precursor sub-pulse 1012 is performed. The precursor sub-pulse is followed by a precursor sub-purge 1013. The precursor sub-pulse 1012 and precursor sub-purge 1013 are then repeated 1015 for a predetermined amount of times, e.g., from at least 1 to at most 10 times, until the precursor pulse ends 1014.
Fig. 11 illustrates an embodiment of a cyclical deposition process, such as for forming one of the gap-fill fluid, the first layer, and the second layer. Method 1100 begins 1111 by providing a substrate. Then, a plurality of deposition cycles 1115 are performed. The deposition cycle 1115 includes a precursor pulse 1112 and a reactant pulse 1113. After a predetermined amount of deposition cycles 1115, the method ends 1114.
The above-disclosed example embodiments do not limit the scope of the invention, as these embodiments are merely examples of embodiments of the invention, which is defined by the appended claims and their legal equivalents. Any equivalent embodiments are within the scope of this invention. Indeed, various modifications of the disclosure, such as alternative useful combinations of the described elements, in addition to those shown and described herein, will become apparent to those skilled in the art from this description. Such modifications and embodiments are also intended to fall within the scope of the appended claims.

Claims (20)

1. A method of forming a structure, comprising:
-providing a substrate comprising a gap, the gap comprising a lower portion and an upper portion;
-forming a first layer on one or more first surfaces in the lower part of the gap and on one or more second surfaces in the upper part of the gap;
-forming a gap filling fluid in the gap lower portion;
-selectively etching the first layer with respect to the gap-filling fluid, thereby removing the first layer from the one or more second surfaces in the upper portion of the gap;
-forming a second layer on one or more second surfaces in the upper part of the gap, the first and second layers having different compositions; and is also provided with
-removing the gap-filling fluid.
2. A method of forming a structure, comprising:
-providing a substrate comprising a gap, the gap comprising a lower portion comprising a first set of nanoplatelets and an upper portion comprising a second set of nanoplatelets;
-forming a first layer on the first set of nano-platelets and on the second set of nano-platelets;
-forming a gap-filling fluid in the gap lower portion, thereby encapsulating the first set of nano-platelets in the gap-filling fluid;
-selectively etching the first layer relative to the gap-filling fluid, thereby removing the first layer from the second set of nanoplatelets;
-forming a second layer on the second set of nano-platelets, the first and second layers having different compositions; and is also provided with
-removing the gap-filling fluid.
3. The method of claim 1 or 2, wherein the step of removing the gap-filling fluid from the gap lower portion is followed by:
-forming a high-k dielectric on the first layer and on the second layer; and is also provided with
-annealing the substrate to form a first gate dielectric from the first layer and the high-k dielectric; and forming a second gate dielectric from the second layer and the high-k dielectric.
4. A method of forming a structure, comprising:
-providing a substrate comprising a gap, the gap comprising a lower portion comprising a first set of nanoplatelets and an upper portion comprising a second set of nanoplatelets;
-forming a high-k dielectric on the first set of nano-platelets and on the second set of nano-platelets;
-forming a first layer on the high-k dielectric on the first set of nano-platelets and on the high-k dielectric on the second set of nano-platelets;
-forming a gap-filling fluid in the gap lower portion, thereby encapsulating the first set of nano-platelets in the gap-filling fluid;
-selectively etching the first layer with respect to the gap-filling fluid and with respect to the high-k dielectric, thereby removing the first layer from the second set of nano-platelets;
-forming a second layer on the high-k dielectric on the second set of nanoplatelets, the first and second layers having different compositions; and is also provided with
-removing the gap-filling fluid.
5. The method of any of claims 2-4, wherein at least one of the first set of nanoplatelets and the second set of nanoplatelets comprises a single crystalline semiconductor.
6. The method of claim 4 or 5, wherein the step of removing the gap-fill fluid is followed by a step of annealing the substrate to form a first gate dielectric from the first layer and high-k dielectric; and forming a second gate dielectric from the second layer and the high-k dielectric.
7. The method of any of claims 1-6, wherein the gap-filling fluid comprises an oligomeric compound.
8. The method of any of claims 1-7, wherein the gap-filling fluid comprises a plurality of imide functional groups.
9. The method of any of claims 1-8, wherein forming the gap-fill fluid comprises exposing a substrate to a gap-fill precursor and exposing a substrate to a gap-fill reactant.
10. The method of any of claims 1-8, wherein forming the gap-fill fluid comprises performing a cyclical gap-fill deposition process comprising a plurality of gap-fill deposition cycles comprising a gap-fill precursor pulse and a gap-fill reactant pulse, wherein the gap-fill precursor pulse comprises exposing the substrate to the gap-fill precursor, and wherein the gap-fill reactant pulse comprises exposing the substrate to the gap-fill reactant.
11. The method of any of claims 1-10, wherein forming the gap-filling fluid comprises generating a plasma.
12. The method of any of claims 1-10, wherein forming the gap-filling fluid is performed thermally.
13. The method of any of claims 1-12, wherein forming the first layer comprises performing a cyclical first layer deposition process comprising a plurality of first layer deposition cycles comprising a first cyclical precursor pulse and a first cyclical reactant pulse, wherein the first cyclical precursor pulse comprises exposing the substrate to the first cyclical precursor, and wherein the first cyclical reactant pulse comprises exposing the substrate to the first cyclical reactant.
14. The method of any of claims 1-13, wherein forming the second layer comprises performing a cyclical second layer deposition process comprising a plurality of second layer deposition cycles comprising a second cyclical precursor pulse and a second cyclical reactant pulse, wherein the second cyclical precursor pulse comprises exposing the substrate to the second cyclical precursor, and wherein the second cyclical reactant pulse comprises exposing the substrate to the second cyclical reactant.
15. The method of claim 10 or 14, wherein at least one of the first and second recycled reactants comprises an oxygen reactant selected from O 2 、O 3 、H 2 O、H 2 O 2 、N 2 O、NO、NO 2 And NO 3
16. The method of any of claims 13 to 15, wherein at least one of the first and second recycled precursors comprises a rare earth element or a late transition metal.
17. The method of any of claims 9-16, wherein the gap-filling precursor comprises two or more anhydride functional groups.
18. The method of any one of claims 9 to 17, wherein the gap-filling reactant comprises two or more amine functional groups.
19. The method of any of claims 13-18, wherein at least one of the first and second metal precursors comprises a halogen.
20. The method of any one of claims 13 to 19, wherein at least one of the first and second metal precursors comprises a carbon-containing ligand.
CN202310572211.1A 2022-05-24 2023-05-19 Method and system for forming dipole layer in stacked fully-around gate transistors Pending CN117116855A (en)

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