CN1171154C - Control chip group and its data processing method - Google Patents
Control chip group and its data processing method Download PDFInfo
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- CN1171154C CN1171154C CNB991256379A CN99125637A CN1171154C CN 1171154 C CN1171154 C CN 1171154C CN B991256379 A CNB991256379 A CN B991256379A CN 99125637 A CN99125637 A CN 99125637A CN 1171154 C CN1171154 C CN 1171154C
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Abstract
The present invention relates to a control chip group and a data processing method thereof. A data buffer of the inner queue of each control chip in the control chip group has fixed size and a fixed number, the sequence of read-write confirmation orders sent between control chips is completely responded according to a read-write order sending sequence, and one control chip can completely control the use situation of a buffer in the inner queue of the other control chip. The arbitration method between control chip groups sets a certain control chip to commonly master the control power of the bus between the control chips, the other control chip enjoys a high bus priority, and the specification of the bus between control chips without waiting periods is collocated. The data trading efficiency of the control chip group is enhanced, and the kinds and the number of signal lines in the control chip group are simplified.
Description
The present invention relates to a kind of chipset, the arbitration method of chip chamber bus in the data transactions method of chip chamber and the control chip group in the control chip group in particularly a kind of computer system, the control chip group.
What Fig. 1 illustrated is a kind of structure of using pci system in computer organization.Central processing unit 10 is couple to pci bus 14 via main bridge (host bridge) 12.14 of pci buss can couple the primary controller (master) of the compatible peripheral device of a plurality of PCI, graphics adapter (graphic adapter) 16a, expansion bus bridge (expansion busbridge) 16b, isdn adapter (LAN adapter) 16c and minicomputer system host bus adapter (SCSI host bus adapter) 16d that it can be as shown in the figure or the like.Each primary controller all can be sent and require signal (request REQ) require to use pci bus 14, and the arbiter (arbiter) in the main bridge 12 then can be sent approval signal, and (grant GNT) gives primary controller, agrees that it uses pci bus 14.
Data between the PCI phase capacitance device (as the north bridge in primary controller or the computer chipset) transmit and are mainly controlled by following adapter control signal.Periodic frame (cycle frame FRAME) is sent by initiator (it can be primary controller or north bridge), in order to the beginning of indicating an accessing operation and the duration.When the FRAME signal was sent, expression began to carry out by the data transactions (transaction) of pci bus, represents then that when the FRAME signal maintains low level data transactions continues to carry out.At this moment, address bus AD just can send effective address (valid address) during address phase, simultaneously can be at order/byte activation (command/byte enable, CBE[3:0]) line sends effective bus line command (satisfying the PCI specification), in order to destination apparatus is pointed out the desired data transactions kenel of initiator, wherein order/byte enable line is to be encoded into 16 kinds of different orders with 4, and it has specific definition in the PCI specification.After being right after the effective address of being sent, address bus AD just sends the data that will transmit, and is called data phase this period, sends the byte enable signal of coding back bus line command simultaneously at the CBE line, uses the transmission data.When the FRAME signal stops to send, just represent that transaction status transmits for the finishing touch data, or finished data and transmitted.Initiator is ready for signal, and (initiator ready, (target ready, TRDY), both are used, and can carry out data in order to indicate initiating means and destination apparatus to be ready for respectively and transmit IRDY) to be ready for signal with destination apparatus.Read action when carrying out one, IRDY signal indication initiator is ready to receive data; And when carrying out a write operation, TRDY signal indication destination apparatus is ready to receive data.(stop STOP), stops present data transactions behavior in order to indicating target matching requirements initiator to stop signal.
With reference to Fig. 2, it illustrates with pci bus adapter and carries out the time sequential routine figure of a read operation when carrying out.With pci bus carry out and finish that data shift during be called a bus transaction cycle (bustransaction) 20, it comprises an address phase (address phase) 22 and a plurality of data phases (data phase), as 24a, 24b and 24c.Each data phase 24a/b/c divides into latent period (wait cycle) 26a/b/c and data migration period (data transfercycle) 28a/b/c again respectively.The sequential chart that then cooperates Fig. 2 comes as the simple declaration of pci system operation and the effect of previously described PCI specification control signal with a read operation.
When period T 1, initiator (primary controller) is sent the REQ signal, to require the master control pci bus, if there are not other more matching requirements use pci buss of high priority this moment, then when period T 2, main bridge (arbiter) is sent the GNT signal, to allow initiator master control pci bus, during period T 3, initiator is sent the FRAME signal, represents that data shift to carry out beginning, and sends start address (start address) in the AD bus, in order to specify a destination apparatus, send a reading order at the CBE line simultaneously.And then the reading order of sending, CBE line can be sent byte enable signal (byte enable), and this byte enable signal (comprises 24a, 24b and 24c) during whole data phase can continue to send always.When period T 4, initiator is sent and is ready for signal IRDY, and expression can begin the sending and receiving data, and right destination apparatus at this moment also fails to be ready for, and be the latent period 26a of data phase 24a this period, is that initiator wait destination apparatus is ready for data.When period T 5, destination apparatus has been ready for and has been sent and has been ready for signal TRDY, and therefore during the data migration period 28a that IRDY and TRDY signal are all sent, initiator is from the destination apparatus reading of data.Destination apparatus finishes to send the TRDY signal in period T 6, transmits with the expression end data, and begins to prepare second data, and be the latent period 26a of data phase 24b this moment.When period T 7, TRDY sends once again, and the expression data are ready for, and during the data migration period 28b that IRDY and TRDY signal are all sent, initiator is from the destination apparatus reading of data.When initiator had little time reading of data, initiator finished to send the IRDY signal in period T 8, and still send because of the TRDY signal this moment, so this waits for that cycle 26c is started by initiator.After initiator is ready for, send the IRDY signal again in period T 9, this moment, initiator was from the destination apparatus reading of data during the data migration period 28c that IRDY and TRDY signal are all sent.No longer need reading of data because initiator when period T 9, has just been known, so initiator finishes to send the FRAME signal and the REQ signal is sent in end, when period T 10, arbiter finishes to send the GNT signal.So far, finish a read operation.
As mentioned above, in the PCI specification,, must use complicated control signal, waiting status and arbiter etc., and the signal of PCI defined have 45-50 signal pins at least in order to finish the data transactions of PCI specification.The system that structure in the present personal computer and Fig. 1 are illustrated is closely similar, wherein main bridge 12 is exactly the north bridge chips of motherboard inner control chipset, and South Bridge chip just comprises expansion bus bridge 16b, and the south bridge among the personal computer system is main and a certainly exist primary controller.Graphics adapter Mk as among the personal computer system is not connected to pci bus, and (accelerated graphic port, AGP) adapter is connected to north bridge chips but quicken port by a drawing.
Yet the data transactions of chip chamber in general control chip group, often do not need to use the so complicated function program of general multi-usage bus, for example: the data transactions of the north and south bridge of motherboard control chip group inside, do not need to use the so complicated program of complete pci bus, and the program of this kind complexity has been sacrificed many performance characteristics mostly in order to ensure being suitable for multiple applied environment.And trend along with Highgrade integration, arbitrary control chip may merge greater functionality, for example CPU and north bridge chips are merged into a chip, or be that control chip group itself is merged into a chip, make the pin on the packing chip become a very valuable resource, must reduce as far as possible to reduce the cost of control chip.Therefore in order to quicken the data transactions between the control chip group inside, and save the resource of chip pin, a kind of simplification but still satisfy that the special bus specification of data transactions is needs between control chip.For example: design a kind of simplifications a plurality of signal wires between the bridge of north and south, bus specification, and this bus specification are fast handled at chip internal must be similar to general PCI specification as far as possible, with chip in other modules compatible, avoid control chip to make too much modification.
Therefore, the present invention proposes the arbitration method of the data transactions method and the interior chip chamber bus of control chip group of chip chamber in a kind of control chip group, the control chip group, in order to the usefulness of raising control chip group exchanges data, and the kind and the quantity of the signal wire in the simplification control chip group.
The present invention proposes the data transactions method of chip chamber in a kind of control chip group and the control chip group, make control chip group internal control chip chamber transmit data, can transmit many orders or data continuously, without any latent period, do not have yet and stop or the situation of retry (retry), can save the time of using bus, improve the transmission benefit.
The present invention proposes the data transactions method of chip chamber in a kind of control chip group and the control chip group, can save the signal wire of signal wire, relevant data transaction cycles length of relevant waiting status in the bus and the relevant signal wire that stops the retry communication protocol etc.
The present invention proposes the arbitration method of bus between a kind of control chip group, can shorten the arbitration time when requiring bus.
The present invention proposes the arbitration method of bus between a kind of control chip group, can save the signal wire that relevant bus is agreed (grant).
The invention provides a kind of control chip group, comprising: one first control chip comprises: one first data are sent the receipts device, are coupled to a chip chamber bus, in order to by this chip chamber bus, receive and the transmission data-signal, finish a plurality of affairs that write; One read/write data formation is coupled to these first data and send the receipts device, reads/write the data of affairs in order to temporary those; One read/write transaction formation is coupled to these first data and send the receipts device, reads/writes the data length of affairs and read/write the address in order to temporary those; An and target controller, be coupled to this read/write data formation and this read/write transaction formation, this target controller reads/write according to what deposits at first in this read/write transaction formation at present that affairs are pairing reads/write the address and pairing data in this read/write data formation, after the data of reading/writing a destination apparatus with being about to are sent, these first data are sent and are received device and send one and read/write entry confirmation signal, and deposit at first in this read/write transaction formation at present read/write affairs are pairing read/write the address and in this read/write data formation pairing data all be released; And one second control chip, be coupled to this first control chip via this chip chamber bus, comprising: a read/write buffers sized registers, in order to store this read/write data formation can hold the sum of data; One read/write buffers counter register, in order to store this read/write transaction formation can hold the sum of reading/write affairs; One second data are sent the receipts device, are coupled to this chip chamber bus, in order to pass through this chip chamber bus, receive and the transmission data-signal, finish those and read/write affairs, when these second data send receive device receive this read/write entry confirmation signal after, send one and read/write successfully buffer release device signal; One writes the affairs generator, is coupled to these second data and send the receipts device, reads/write the data length of affairs in order to produce those, reads/write address and data; One read/write transaction writing circuit and formation, be coupled to these second data and send receipts device and this read/write transaction generator, read/write the data length of affairs in order to temporary those, and read/write successfully buffer release device signal according to this, calculating one of this read/write data formation in this first control chip at present will will be with reading/write the affairs number with one of read/write buffers data number and this read/write transaction formation; An and read/write comparer, be coupled to these second data and send receipts device, this read/write buffers sized registers, this read/write buffers counter register and this read/write transaction writing circuit and formation, in order to according to this will with read/write buffers data number, this will with read/write affairs number, this read/write transaction formation can hold the sum that the sum of reading/write affairs and this read/write data formation institute can hold data, notify these second data to send to receive device to send new read/write and go into the data-signal that affairs are correlated with.
The present invention has fixed size and quantity by the data buffer of each control chip internal queues in the control chip group, and chip chamber sends the order of read-write affirmation order and responds according to the order of sending read write command fully, make control chip can grasp the use situation of impact damper in another control chip internal queues fully, during order that each control chip sends, its related data must be ready to earlier, even the also affairs of all between control chip group situation transparence, thereby can save the signal wire of relevant waiting status in the bus, the signal wire of relevant data transaction cycles length and the relevant signal wire that stops the retry communication protocol etc.And can transmit many orders or data continuously,, also not have and stop or the situation of retry takes place, can save the time of using bus, improve the transmission benefit without any latent period.
The arbitration method of the bus between control chip group of the present invention, set a certain control chip and grasp the control of chip chamber bus usually, but another control chip is enjoyed higher trunk priority power, collocation does not have the chip chamber bus specification of latent period, just do not need the GNT signal wire, the right to use ownership of arbitration bus that can be errorless fast shortens the time of arbitrating, and, closely improve whole transmission benefit because the affairs of second control chip group require always to be agreed.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Fig. 1 illustrates a kind of structural representation that uses the pci bus system in the computer organization that is known in;
The primary controller that Fig. 2 illustrates a pci system carries out the sequential chart of read operation, in order to each control signal of simple declaration pci system;
Fig. 3 illustrates the block schematic diagram according to a kind of control chip group of a preferred embodiment of the present invention;
Fig. 4 illustrates according in one embodiment of the invention, transmits the timing diagram between data bit time (bit time) and bus clock pulse signal and the line trigger signal;
Fig. 5 A illustrates a kind of control chip group according to a preferred embodiment of the present invention, the wherein relevant inner structure block schematic diagram that writes affairs;
Fig. 5 B illustrates a kind of control chip group according to a preferred embodiment of the present invention, the wherein relevant correlation timing figure that writes affairs;
Fig. 6 A illustrates a kind of control chip group according to a preferred embodiment of the present invention, the wherein relevant inner structure block schematic diagram of affairs of reading; And
Fig. 6 B illustrates a kind of control chip group according to a preferred embodiment of the present invention, the wherein relevant correlation timing figure of affairs that reads;
Arbitration method for chip chamber bus in the data transactions method that proposes chip chamber in a kind of control chip group, the control chip group and the control chip group, can improve the usefulness of control chip group data transactions, and the kind and the quantity of the signal wire in the simplification control chip group, that is the bus between the simplification control chip.The present invention is an example with the control chip group that south bridge and north bridge were constituted in the computer main frame panel, redefine a plurality of command signals, be called high-transmission storer binding (High Through-put Memory Link is called for short HTML) at this and come the original complicated pci bus signal of abbreviation.In this preferred embodiment, original south bridge and the signal wire between the north bridge need 45 signal line, and the present invention replaces original pci bus signal wire with 15 command signal line.
With reference to Fig. 3 and table one, wherein Fig. 3 is the block schematic diagram according to a kind of control chip group of a preferred embodiment of the present invention, and Fig. 3 also illustrates south bridge in the control chip group and the signal wire between north bridge; And table one describes the meaning of these signal wires in detail, by Fig. 3 and table 1 as can be known, control chip group of the present invention comprises south bridge 30 and 32 liang of control chips of north bridge, 45 original between south bridge 30 and the north bridge 32 signal pins are reduced to 15, unnecessary pin just can provide as other purposes, to promote the function of control chip group.
Shown in Fig. 3 and table one, between south bridge 30 and the north bridge 32, keep original pci bus agreement specification fixed address data bus (AD bus), but it is reduced to only 8 bidirectional signal lines, other are as CBE, FRAME, IRDY, TRDY, STOP, DEVSEL, REQ and GNT equisignal line, be reduced to a two-way position activation BE signal wire, and up-link order (up link command) UPCMD, up-link triggering (up link strobe) UPSTB for being driven by south bridge 30; Also have by following biography link command (down link command) DNCMD that north bridge 32 drove, pass link down and trigger (down link strobe) DNSTB signal wire etc.South bridge 30 respectively drives an independently command signal line with north bridge 32, represents this preferred embodiment to have full duplex order transmitting function, can send bus line command separately at any time.And if when sending bus line command, obtain the bus right to use, just can on address data bus, send the address, and send the length information of present order at the BE signal wire, perhaps on address data bus, send data, and send the byte enable signal of these data at the BE signal wire.
Table one
| Signal | Driver | Explanation |
| CLK | The clock pulse signal of 66Mhz | |
| DNSTB | North bridge | Under pass link and trigger |
| UPSTB | South bridge | Up-link triggers |
| DNCMD | North bridge | Under pass link command |
| UPCMD | South bridge | The up-link order |
| BE | Northbridge/southbridge | The byte activation |
| AD[7:0] | Northbridge/southbridge | Address/data bus |
| VREF | Reference voltage | |
| COMP | Impedance ratio |
With reference to Fig. 4, it defines the sequential relationship between arbitrary data line transmission data bit time of the present invention and bus clock pulse signal and the line trigger signal.As seen from the figure, comprise two clock pulse signals that trigger STB a clock cycle, that is the operation frequency when up-link line trigger signal and following biography link line trigger signal actuating is 2 times of clock frequencies on the clock pulse signal line.Utilize the rise and fall edge of trigger pip can define four bit times 0～3 altogether, utilize these four bit times can obtain the data of 4 positions altogether, and can carry out the coding of bus line command.So 8 data lines, can obtain 32 data each clock cycle, and its effect equals in pci bus, 32 data lines is arranged simultaneously as the transmission data.And when representing length information, can draw 1-16 (4 positions) data length information a clock cycle as the BE signal wire.
Up-link order UPCMD and the following link command DNCMD that passes define various data transactions kenel.Comprised by the up-link order UPCMD that south bridge 30 drove: north bridge reads to south bridge to be confirmed that order C2PRA, north bridge write to south bridge and confirms to order C2PWA, south bridge to north bridge reading order P2CR, south bridge to north bridge write command P2CW etc.The encoding relation of itself and bit time then as shown in Table 2, please note REQ bus request signal, be to send at bit time 0, also underlapped with the order of other data transactions kenels, so at any time, even, can send this REQ signal simultaneously in the same clock cycle of sending the order of data transactions kenel.The following biography link command DNCMD that is driven by north bridge 3 comprises: north bridge is exported to export to south bridge memory read command fetch C2PMR, north bridge to south bridge to read to south bridge memory writer command C2PMW, south bridge to north bridge into write command C2PIOW, north bridge into reading order C2PIOR, north bridge to south bridge and is confirmed that order P2CRA, south bridge write to north bridge and confirm to order P2CWA, and the encoding relation of itself and bit time then as shown in Table 3.Note that the signal definition that there is no relevant GNT at present embodiment.
South bridge is corresponding with the order that north bridge chips is sent in the mentioned order, and after south bridge sent a plurality of P2CR and/or P2CW order in regular turn, the order that north bridge must be given an order according to south bridge was fully responded corresponding P2CRA and/or P2CWA order.After north bridge sent a plurality of C2PIOR, C2PMR, C2PIOW and C2PMW order in regular turn, south bridge must be responded corresponding C2PRA and C2PWA order in regular turn.And in the present embodiment, during order that each control chip sends, its related data must be ready to earlier.For example: when south bridge sends P2CW, must the data that will write are ready, when north bridge sends P2CRA, the sense data that pass back must be ready to fully, to avoid the situation that in the middle of the transmission data, has the data pause to continue.
Table two (up-link order UPCMD)
| Bit time 0REQ | Bit time 1PMSTR | Bit time 2MIO | Bit time 3WR | Explanation |
| - | 0 | - | 0 | C2PRA |
| - | 0 | - | 1 | C2PWA |
| - | 1 | 0 | 0 | P2CR |
| - | 1 | 0 | 1 | P2CW |
| - | 1 | 1 | 1 | NOP |
| 0 | - | - | - | REQ |
Table three (passing link command DNCMD down)
| Bit time 0 | Bit time 1PMSTR | Bit time 2MIO | Bit time 3WR | Explanation |
| - | 0 | 0 | 0 | C2PIOR |
| - | 0 | 0 | 1 | C2PIOW |
| - | 0 | 1 | 0 | C2PMR |
| - | 0 | 1 | 1 | C2PMW |
| - | 1 | 0 | 0 | P2CRA |
| - | 1 | 0 | 1 | P2CWA |
| - | 1 | 1 | 1 | NOP |
Fig. 5 A illustrates a kind of control chip group according to a preferred embodiment of the present invention, and the wherein relevant inner structure block schematic diagram that writes affairs is with reference to Fig. 5 A.The control chip group of this preferred embodiment comprises first control chip and second control chip, and for example: first control chip is a north bridge chips 500, and second control chip is a South Bridge chip 600.It links together by special chip chamber bus, is exactly the HTML of the present invention's definition.North bridge chips 500 comprises: data are sent and (for example: Memory Controller 520), write data formation 525 and write transaction queues 530 etc. are received device 510, target controller 520.South Bridge chip 600 comprises: data are sent and are received device 610, write buffer sized registers 535, write buffer counter register 540, write affairs generator 545, write transaction journal circuit and formation 550 and write comparer 555.
Data send receipts device 510 to be connected directly to HTML, are the data receiving and transmitting controllers that meets HTML adapter specification, can receive and the transmission data-signal by HTML, finish a plurality of affairs that write.Here we send P2CW order and related data from South Bridge chip 600 by abbreviation each time, and the P2CWA order of responding this P2CW order relatively to north bridge chips 500 is the write-once affairs.Write data formation 525 can be kept in the data that write affairs in regular turn.And write transaction queues 530, keep in all in regular turn and write the data length of affairs and write the address.Write the degree of depth decision north bridge chips of transaction queues 530 and can handle the number of writing affairs simultaneously, the degree of depth decision north bridge chips of write data formation 525 can be handled the sum of the data of writing affairs.Target controller 520 writes pairing address and the data length of writing of affairs according to what deposit at first at present in writing transaction queues 530, and in write data formation 525 pairing data, after the data that will be about to write destination apparatus (as: external memory storage) are sent, first data are sent receipts device 510 to send and are write entry confirmation signal (P2CWA order), and what deposit at first in writing transaction queues 530 at present writes pairing address and the data length of writing of affairs, and pairing data all can be released in write data formation 525, and just other data all can be inserted again in the memory location of temporary these data in the formation.
Write buffer counter register 540 in the South Bridge chip 600 and write buffer sized registers 535, store respectively and write 530 of transaction queues in the north bridge chips 500 and can hold sum and 525 sums that can hold data of write data formation that write affairs, in the present embodiment, write 530 of transaction queues can hold write affairs add up to 4, and 525 of write data formations can hold data add up to 16.These two numerals can be set when starting shooting by ROM-BIOS, also can just fix when design chips etc.
Data are sent and are received device 610, be coupled to HTML equally, can pass through HTML, receive and the transmission data-signal, finish all affairs that write, and after data send receipts device 610 to receive the P2CWA order, can send and write successfully buffer release device signal to writing transaction journal circuit and formation 550, can be in order to discharge the corresponding memory location that this time write the data length of affairs of storage in the formation.When writing affairs generator 545, produce a new data length that writes affairs, when writing address and data, also data length can be delivered to and write transaction journal circuit and formation 550.
Write transaction journal circuit and formation 550 and can calculate in the present north bridge chips 500, all of relevant write data formation 530 will be with write buffer data number, and write all of transaction queues 525 will be with writing the affairs number.This is owing to write in transaction journal circuit and the formation 550, temporary in regular turn have all to write the data length of affairs, because north bridge chips 500 sends P2CWA order is that the order of sending the P2CW order according to South Bridge chip 600 is fully responded, South Bridge chip 600 can be grasped the use situation of impact damper in north bridge chips 500 internal queues fully again.
Write transaction journal circuit and formation 550 can be at present about all of write data formation 530 will be with write buffer data number, and write transaction queues 525 all will give and write comparer 555 with writing the affairs number, write comparer 555 525 sums that can hold data of write data formation with above-mentioned information and 535 storages of write buffer sized registers, and the writing 530 of transaction queues and can hold the sum that writes affairs and come comparison of write buffer counter register 540 storage, if the both surpasses open ended sum, but just notification data send receipts device 610 to send the new data-signal that affairs are correlated with that writes.
With reference to Fig. 5 B, suppose that when time clock T1 the right to use of South Bridge chip address acquisition data bus also begins to write for the first time affairs.South Bridge chip is sent write command P2CW at up-link order UPCMD, send the address AD DR that writes at address data bus AD, and on byte activation BE, send length LEN=2 that will write, when time clock T2, South Bridge chip is sent the first stroke data that will write on AD, and on BE, send the byte activation of the first stroke data, when time clock T3, then send second and write data.Have uncompleted write affairs in the north bridge chips this moment.Because South Bridge chip is known north bridge chips and can be accepted the size that writes the number of affairs and write data queue simultaneously, therefore can judge whether north bridge chips can accept the new affairs that write again.If what north bridge chips was still free writes transaction queues 530 and write data queue 525 and can use, South Bridge chip can begin to write for the second time affairs again at time clock T4, and have two uncompleted write affairs in the north bridge chips this moment.South Bridge chip judges whether can begin to write for the third time affairs when T9.Realize writing affairs and can make writing transaction queues 530 or write data queue 525 and overflowing and do not have writing transaction queues 530 or write data queue 525 and overflowing and can't handle of north bridge chips of north bridge chips for the third time when South Bridge chip, South Bridge chip just can not start to write for the third time affairs at time clock T9.After north bridge chips writes the complete write store of data of affairs via Memory Controller with the first time, in time clock T9 under pass link command DNCMD and send to write and confirm order, tell South Bridge chip to write affairs (length LEN=2) for the first time and finish.South Bridge chip just knows that the transaction queues 530 that writes available in the north bridge chips increases by one, and the available data queue 525 that writes increases by two.South Bridge chip receives that leaking into of north bridge chips confirm order, knows that writing affairs for the first time finishes.Relevant writing transaction queues 530 and write data queue 525 disengaged, and the judgement north bridge chips can receive and write affairs for the third time, begins to write for the third time affairs in time clock T12.
Fig. 6 A illustrates a kind of control chip group according to a preferred embodiment of the present invention, the wherein relevant inner structure block schematic diagram of affairs of reading.With reference to Fig. 6 A.The control chip group of this preferred embodiment comprises north bridge chips 500 and South Bridge chip 600.It links together by special chip chamber bus, is exactly the HTML of the present invention's definition.North bridge chips 500 comprises: data are sent and (for example: Memory Controller 520), read data formation 625 and read transaction queues 630 etc. are received device 510, target controller 520.South Bridge chip 600 comprises: data are sent and are received device 610, read buffer sized registers 635, read buffer counter register 640, read affairs generator 645, read transaction journal circuit and formation 650 and read comparer 655.
Data send receipts device 510 to be connected directly to HTML, are the data receiving and transmitting controllers that meets HTML adapter specification, can receive and the transmission data-signal by HTML, finish a plurality of affairs of reading.Here we are called for short each time and send the P2CR order from South Bridge chip 600, respond the P2CRA order of P2CR order relatively this time and related data for once reading affairs to north bridge chips 500.Read data formation 625 can be kept in the data of reading affairs in regular turn.And read transaction queues 630, keep in all in regular turn and read the data length of affairs and read the address.Read the degree of depth decision north bridge chips of transaction queues 630 and can handle the number of reading affairs simultaneously, the degree of depth decision north bridge chips of read data formation 625 can be handled the number of the data of reading affairs.Target controller 520 is read pairing address and the data length read of affairs according to what deposit at first at present in reading transaction queues 630, after from destination apparatus (as: external memory storage) data being read, deposit in the read data formation 625.Then, first data send receive device 510 can send read confirmation signal (P2CRA order) and read to deposit at first in the transaction queues 630 to read affairs pairing after the data of read data formation 625, and what deposit at first in reading transaction queues 630 at present reads pairing address and the data length read of affairs, and pairing data all can be released in read data formation 625, and just the impact damper of temporary these data all can be inserted other data again in the formation.
Read buffer counter register 640 in the South Bridge chip 600 and read buffer sized registers 635, store respectively and read 630 of transaction queues in the north bridge chips 500 and can hold sum and 625 sums that can hold data of read data formation of reading affairs, in the present embodiment, read 630 of transaction queues can hold read affairs add up to 4, and 625 of read data formations can hold data add up to 16.These two numerals can be set when starting shooting by ROM-BIOS, also can just fix when design chips etc.
Data are sent and are received device 610, be coupled to HTML equally, can pass through HTML, receive and the transmission data-signal, finish all affairs of reading, and after data send receipts device 610 to receive the P2CRA order, read affairs generator 645 except the data of reading affairs of correspondence P2CRA order are this time given, also can send and read successfully buffer release device signal to reading transaction journal circuit and formation 650, can be in order to discharge the corresponding memory location of this time reading the data length of affairs of storage in the formation.When reading affairs generator 645, when producing a new data length of reading affairs and reading the address, also data length can be delivered to and read transaction journal circuit and formation 650.
Read transaction journal circuit and formation 650 and can calculate in the present north bridge chips 500, all of relevant read data formation 630 will be with read buffer data number, and read all of transaction queues 625 will be with reading the affairs number.This is owing to read in transaction journal circuit and the formation 650, temporary in regular turn have all to read the data length of affairs, because north bridge chips 500 sends P2CRA order is that the order of sending the P2CR order according to South Bridge chip 600 is fully responded, South Bridge chip 600 can be grasped the use situation of impact damper in north bridge chips 500 internal queues fully again.
Read transaction journal circuit and formation 650 can be at present about all of read data formation 630 will be with read buffer data number, and read transaction queues 625 all will give and read comparer 655 with reading the affairs number.Read comparer 655 625 sums that can hold data of read data formation with above-mentioned information and 635 storages of read buffer sized registers, and the reading 630 of transaction queues and can hold the sum of reading affairs and come comparison of read buffer counter register 640 storage, if the both surpasses open ended sum, but just notification data send receipts device 610 to send the new data-signal that affairs are correlated with of reading.
With reference to Fig. 6 B, suppose that when time clock T1 the right to use of South Bridge chip address acquisition data bus also begins to read for the first time affairs.South Bridge chip is sent reading order P2CR at up-link order UPCMD, sends the address AD DR that reads on address data bus AD, and sends length LEN=2 that will read on byte activation BE.Have uncompleted read affairs in the north bridge chips this moment, can accept to read the number of affairs and the size of determination data formation simultaneously because South Bridge chip is known north bridge chips, can therefore judge whether north bridge chips can accept the new affairs that read again.Read transaction queues 630 and read data queue 625 can be used if north bridge chips is still free, South Bridge chip can begin to read for the second time affairs (length LEN=3) again at time clock T2, have two uncompleted read affairs in the north bridge chips this moment, the South Bridge chip judgement starts to read affairs the 3rd time when time clock T3, with make north bridge chips read transaction queues 630 or read data queue 625 overflows and can't handle, so South Bridge chip can not begin to read for the third time affairs at time clock T3.After north bridge chips obtained to read the data of affairs and be stored in read data queue 625 for the first time via Memory Controller, it sent the data that read back to south bridge with regard to starting to read to confirm to order.The right to use of north bridge chips address acquisition data bus during time clock T7, under pass link command DNCMD and send to read and confirm order P2CRA, send the first stroke data that read affairs for the first time at address data bus.Send second data during time clock T8, this moment, South Bridge chip knew whether reading for the first time the relevant transaction queues 630 that reads of affairs has disengaged with read data queue 625, can start reading order for the third time and rejudge.Before starting for the third time reading order, South Bridge chip must be obtained the right to use of address data bus, therefore sends REQ at time clock T10 with up-link order UPCMD, requires to use bus to north bridge chips.North bridge chips confirms to order the data of inciting somebody to action the reading order second time to send in time clock T9-T10-T11 via reading.South Bridge chip obtains the right to use of bus when time clock T13, start reading order for the second time.
The embodiments of the invention of above-mentioned Fig. 5 A, 5B and Fig. 6 A, 6B explanation all be that first control chip is a north bridge chips for example, and second control chip are South Bridge chips, and are initiatively given an order by South Bridge chip that the control north bridge chips reads and writes data.Can know easily as those skilled in the art,, not limit and initiatively to give an order by South Bridge chip, that is first control chip can be South Bridge chip, and second control chip is a north bridge chips as long as corresponding structure is arranged in the bridge of north and south.
Fig. 5 A, 5B and Fig. 6 A, 6B are an embodiment, should be in order to restriction the present invention.Spirit of the present invention is:
1. start to write or when reading affairs, except sending address and order, also send the data length that will write or read, so do not need FRAME just can know when these affairs finish.
2. write or read affairs and wait for when finishing as a plurality of, write or read and confirm order writing or reading order before corresponding in regular turn, therefore can know the use situation of the other side's chip internal formation, and then judge and start new writing or reading order again, that is to say that flow control is by starting to write or the chip of reading order is done, and acceptance writes or the chip of reading order is received the order that internal queues is overflowed never, therefore needn't do flow control.
3. the scope of Ying Yonging should not be the north and south bridge chip, should can be applicable to the data that make any two chip chambers and transmit.
In sum; though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can doing various changes and retouching, so protection scope of the present invention should be as the criterion with claim institute confining spectrum.
Claims (9)
1. control chip group comprises:
One first control chip comprises:
One first data are sent the receipts device, are coupled to a chip chamber bus, in order to by this chip chamber bus, receive and the transmission data-signal, finish a plurality of affairs that write;
One read/write data formation is coupled to these first data and send the receipts device, reads/write the data of affairs in order to temporary those;
One read/write transaction formation is coupled to these first data and send the receipts device, reads/writes the data length of affairs and read/write the address in order to temporary those; And
One target controller, be coupled to this read/write data formation and this read/write transaction formation, this target controller reads/write according to what deposits at first in this read/write transaction formation at present that affairs are pairing reads/write the address and pairing data in this read/write data formation, after the data of reading/writing a destination apparatus with being about to are sent, these first data are sent and are received device and send one and read/write entry confirmation signal, and deposit at first in this read/write transaction formation at present read/write affairs are pairing read/write the address and in this read/write data formation pairing data all be released; And
One second control chip is coupled to this first control chip via this chip chamber bus, comprising:
One read/write buffers sized registers, in order to store this read/write data formation can hold the sum of data;
One read/write buffers counter register, in order to store this read/write transaction formation can hold the sum of reading/write affairs;
One second data are sent the receipts device, are coupled to this chip chamber bus, in order to pass through this chip chamber bus, receive and the transmission data-signal, finish those and read/write affairs, when these second data send receive device receive this read/write entry confirmation signal after, send one and read/write successfully buffer release device signal;
One writes the affairs generator, is coupled to these second data and send the receipts device, reads/write the data length of affairs in order to produce those, reads/write address and data;
One read/write transaction writing circuit and formation, be coupled to these second data and send receipts device and this read/write transaction generator, read/write the data length of affairs in order to temporary those, and read/write successfully buffer release device signal according to this, calculating one of this read/write data formation in this first control chip at present will will be with reading/write the affairs number with one of read/write buffers data number and this read/write transaction formation; And
One read/write comparer, be coupled to these second data and send receipts device, this read/write buffers sized registers, this read/write buffers counter register and this read/write transaction writing circuit and formation, in order to according to this will with read/write buffers data number, this will with read/write affairs number, this read/write transaction formation can hold the sum that the sum of reading/write affairs and this read/write data formation institute can hold data, notify these second data to send to receive device to send new read/write and go into the data-signal that affairs are correlated with.
2. control chip group as claimed in claim 1, wherein this chip chamber bus comprises: an address data bus, one length/byte enable signal line, a up-link command signal line, a up-link line trigger signal, once pass the link command signal wire, pass a link line trigger signal and a time clock signal wire once.
3. control chip group as claimed in claim 2, the operation frequency when wherein this up-link line trigger signal and this time pass the actuating of link line trigger signal is 2 times of clock frequencies on this clock pulse signal line.
4. control chip group as claimed in claim 1, wherein this first is respectively the north bridge control chip and the south bridge control chip of computer main frame panel with this second control chip, and this target controller is a Memory Controller, and this destination apparatus is an external memory storage.
5. control chip group as claimed in claim 4, wherein this read/write transaction formation can hold read/write affairs add up to 4, this read/write data formation can hold data add up to 16.
6. the data transactions method between the control chip group, in order to finish a plurality of reading/write affairs, this control chip group comprises one first control chip and one second control chip, and this first control chip comprises a read/write data formation, reads/write the data of affairs in order to temporary those; An and read/write transaction formation, read/write the data length of affairs and read/write the address in order to temporary those, this second control chip comprises that keeping in those reads/write a read/write transaction writing circuit and the formation and a read/write comparer of the data length of affairs, and this data transactions method comprises the following steps:
By the chip chamber bus provide this read/write transaction formation can hold read/write go into affairs the sum and this read/write data formation can hold the sum of data to second control chip;
This first control chip according to deposit at first in this read/write transaction formation at present read/write affairs are pairing read/write the address and in this read/write data formation pairing data, the data of reading/writing a destination apparatus with being about to are read/are write out;
This first control chip is sent one and is read/write entry confirmation signal;
This first control chip discharges reading/writing of depositing at first in this read/write transaction formation at present, and affairs are pairing reads/write the address and pairing data in this read/write data formation;
This second control chip produces corresponding one and newly reads/write the data length of affairs, reads/write address and data;
Entry confirmation signal is read/write to this second control chip according to this, make this read/write transaction writing circuit and formation, calculating one of this read/write data formation in present this first control chip will will be with reading/write the affairs number with one of read/write buffers data number and this read/write data formation; And
This read/write comparer according to this will with read/write buffers data number, this will with read/write affairs number, this read/write transaction formation can hold the sum that the sum of reading/write affairs and this read/write data formation institute can hold data, decide and make this second control chip to send this new reading/write the relevant data length of affairs and read/write address and data.
7. the data transactions method between the control chip group as claimed in claim 6, wherein this first with this second control chip be to couple by a chip chamber bus, this first is respectively the north bridge control chip and the south bridge control chip of computer main frame panel with this second control chip, and this chip chamber bus comprises: an address data bus, one length/byte enable signal line, a up-link command signal line, a up-link line trigger signal, once pass the link command signal wire, pass a link line trigger signal and a time clock signal wire once.
8. the data transactions method between the control chip group as claimed in claim 7, the operation frequency when wherein this up-link line trigger signal and this time pass the actuating of link line trigger signal is 2 times of clock frequencies on this clock pulse signal line.
9. the data transactions method between the control chip group as claimed in claim 7, wherein this destination apparatus is an external memory storage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB991256379A CN1171154C (en) | 1999-12-28 | 1999-12-28 | Control chip group and its data processing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB991256379A CN1171154C (en) | 1999-12-28 | 1999-12-28 | Control chip group and its data processing method |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02158428 Division CN1238794C (en) | 1999-12-28 | 1999-12-28 | Method for controlling clip set and its data processing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1302020A CN1302020A (en) | 2001-07-04 |
| CN1171154C true CN1171154C (en) | 2004-10-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB991256379A Expired - Lifetime CN1171154C (en) | 1999-12-28 | 1999-12-28 | Control chip group and its data processing method |
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| Country | Link |
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| CN (1) | CN1171154C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100431315C (en) * | 2002-06-07 | 2008-11-05 | 友讯科技股份有限公司 | Method for decreasing built-in Ethernet network controller transmitting-receiving efficency |
| KR20180094724A (en) * | 2017-02-16 | 2018-08-24 | 에스케이하이닉스 주식회사 | Memory system and operating method thereof |
| CN107291652B (en) * | 2017-07-05 | 2020-06-09 | 深圳市奈瑞特科学技术有限公司 | Parallel communication method |
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1999
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| CN1302020A (en) | 2001-07-04 |
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