CN117112227A

CN117112227A - Memory management method, system, device, storage medium and electronic equipment

Info

Publication number: CN117112227A
Application number: CN202311177554.4A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Moore Threads Technology Co Ltd
Current assignee: Moore Threads Technology Co Ltd
Priority date: 2023-09-12
Filing date: 2023-09-12
Publication date: 2023-11-24

Abstract

The present disclosure discloses a memory management method, a system, a device, a storage medium and an electronic device, where after a cache unit determines an acquisition request to be executed, a memory management unit determines a first page table corresponding to the acquisition request to be executed, when the first page table is a page table being acquired by the memory management unit, waiting information is sent to the first cache unit sending the acquisition request to be executed, so as to suspend processing the acquisition request to be executed, and when the first page table is not a page table being acquired by the memory management unit, the acquisition request to be executed is executed according to page table save information stored by the memory management unit itself. Therefore, the memory management unit can process the to-be-executed acquisition requests corresponding to different page tables simultaneously, so that the resource utilization rate of the memory management unit is ensured, and the management efficiency of the memory management system is improved.

Description

Memory management method, system, device, storage medium and electronic equipment

Technical Field

The present disclosure relates to the field of cache, and in particular, to a memory management method, system, device, storage medium, and electronic apparatus.

Background

Generally, in order to improve the processing efficiency of a computer, a cache (cache) unit, even a multi-level cache unit, is usually disposed in a memory of the computer. The buffer memory unit is used for storing the conversion relation between the virtual address and the physical address.

When a processor in a computer needs to execute a data processing task, a virtual address of data required by the data processing task can be determined, a physical address corresponding to the virtual address is determined from a cache unit according to the virtual address, and the data required by the data processing task is acquired according to the physical address.

In the above process, a case may occur that the physical address corresponding to the virtual address is not queried in the cache unit, and the cache unit may send the fetch request to the memory management unit (Memory Management Unit, MMU) according to the virtual address. And the memory management unit queries a physical address corresponding to the virtual address from the page table according to the virtual address carried in the acquisition request, and returns the physical address to the cache unit. The cache unit may then determine the physical address to which the virtual address corresponds.

However, since the memory management unit has limited execution resources, when the acquisition request is received, the memory management unit needs to be allocated with execution resources, which results in limited number of acquisition requests that the memory management unit can process simultaneously in the same period.

Based on this, in order to guarantee the resource utilization of the memory management unit, the present specification provides a memory management method.

Disclosure of Invention

The present disclosure provides a memory management method, system, device, storage medium and electronic apparatus, so as to partially solve the above-mentioned problems in the prior art.

The technical scheme adopted in the specification is as follows:

the present disclosure provides a memory management method, where the method is applied to a memory management unit, and the memory management unit communicates with a cache unit, and the method includes:

receiving an acquisition request to be executed, which is sent by a first cache unit, and determining a virtual address corresponding to the acquisition request to be executed;

determining a first page table corresponding to the virtual address;

responding to the first page table as a second page table, and sending waiting information to the first cache unit; the second page table is a page table which is being acquired by the memory management unit;

And responding to the first page table not being a second page table, and executing the acquisition request to be executed based on page table storage information corresponding to the memory management unit.

Optionally, the response to the first page table being the second page table, sending waiting information to the first cache unit specifically includes:

responding to the first page table as a second page table, and sending waiting information to the first cache unit according to the acquisition request to be executed, wherein the waiting information is used for enabling the first cache unit to send the acquisition request to be executed to the memory management unit again after a preset period of time;

the method further comprises the steps of:

receiving an acquisition request to be executed which is resent after the first cache unit is spaced by the preset period, and judging whether the first page table is a second page table or not;

and if not, executing the retransmitted acquisition request to be executed.

and responding to the first page table as a second page table, and sending waiting information to the first cache unit according to the to-be-executed acquisition request, wherein the waiting information is used for enabling the first cache unit to modify the state of the to-be-executed acquisition request into a waiting state.

Optionally, the method further comprises:

monitoring the state of the first page table, when the memory management unit is determined to acquire the first page table, transmitting a retry instruction to the first cache unit, and updating the page table storage information based on the first page table; the retry instruction is configured to modify a state of the to-be-executed acquisition instruction into an execution state;

and receiving an acquisition request to be executed, which is resent by the first cache unit according to the retry instruction, and executing the resent acquisition request to be executed.

Optionally, the page table save information is used to characterize a page table stored in the memory management unit;

based on page table storage information corresponding to the memory management unit, executing the to-be-executed acquisition request specifically includes:

when the memory management unit is determined to acquire the first page table based on page table storage information, determining the first page table from all page tables stored by the memory management unit, determining a corresponding physical address in the first page table according to the virtual address, and responding to the acquisition request to be executed based on the physical address;

And when the memory management unit does not acquire the first page table based on the page table storage information, allocating execution resources for the acquisition request to be executed, and executing the first page table through the execution resources.

Optionally, executing, by the execution resource, the first page table, specifically including:

marking the first page table as a second page table using the execution resource;

sending an acquisition request corresponding to the first page table to a downstream storage unit of the memory management unit;

receiving a first page table returned by the downstream storage unit according to the acquisition request;

and determining a corresponding physical address in the first page table according to the virtual address, and responding to the acquisition request to be executed based on the physical address.

The present specification provides a memory management system, which includes a memory management unit and a cache unit, where the memory management unit and the cache unit communicate; wherein:

the first cache unit is used for sending an acquisition request to be executed to the memory management unit;

the memory management unit is used for receiving the to-be-executed acquisition request sent by the first cache unit and determining a virtual address corresponding to the to-be-executed acquisition request; determining a first page table corresponding to the virtual address; responding to the first page table as a second page table, and sending waiting information to the first cache unit; the second page table is a page table which is being acquired by the memory management unit; and responding to the first page table not being a second page table, and executing the acquisition request to be executed based on page table storage information corresponding to the memory management unit.

The present specification provides a memory management apparatus, the apparatus being applied to a memory management unit, the memory management unit and a cache unit communicating, the apparatus comprising:

the receiving module is used for receiving an acquisition request to be executed, which is sent by the first cache unit, and determining a virtual address corresponding to the acquisition request to be executed;

the determining module is used for determining a first page table corresponding to the virtual address;

the first response module is used for responding to the first page table as a second page table and sending waiting information to the first cache unit; the second page table is a page table which is being acquired by the memory management unit;

and the second response module is used for responding to the fact that the first page table is not the second page table, and executing the acquisition request to be executed based on page table storage information corresponding to the memory management unit.

The present specification provides a computer readable storage medium storing a computer program which when executed by a processor implements the memory management method described above.

The present specification provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the memory management method described above when executing the program.

The above-mentioned at least one technical scheme that this specification adopted can reach following beneficial effect:

when the first page table is the page table which is being acquired by the memory management unit, sending waiting information to a first cache unit which sends the acquisition request to be executed so as to suspend processing the acquisition request to be executed, and when the first page table is not the page table which is being acquired by the memory management unit, executing the acquisition request to be executed according to page table storage information stored in the memory management unit. Therefore, the memory management unit can process the to-be-executed acquisition requests corresponding to different page tables simultaneously, so that the resource utilization rate of the memory management unit is ensured, and the management efficiency of the memory management system is improved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the specification, illustrate and explain the exemplary embodiments of the present specification and their description, are not intended to limit the specification unduly. In the drawings:

FIG. 1 is a schematic diagram of a scenario in which a memory management unit processes an acquisition request;

FIG. 2 is a flow chart of a memory management method provided in the present disclosure;

FIG. 3 is a schematic view of a scenario for processing an acquisition request provided in the present specification;

fig. 4 is a schematic structural diagram of a memory management system provided in the present disclosure;

FIG. 5 is a flow chart of a memory management method provided in the present disclosure;

fig. 6 is a schematic view of the electronic device corresponding to fig. 2 provided in the present specification.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the present specification more apparent, the technical solutions of the present specification will be clearly and completely described below with reference to specific embodiments of the present specification and corresponding drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present specification. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are intended to be within the scope of the present disclosure.

The following describes in detail the technical solutions provided by the embodiments of the present specification with reference to the accompanying drawings.

Generally, the memory management unit may receive the obtaining request sent by the cache unit, and according to the virtual address carried in the obtaining request, query the page table for the physical address corresponding to the virtual address, and return the physical address to the cache unit. In order to ensure high utilization of the memory management unit, the memory management unit is typically configured to handle multiple fetch requests.

However, for a page table, the page table can only be accessed by one fetch request during the same period. Taking the example that the memory management unit receives the a acquire request and the B acquire request in the same period, if the memory management unit executes the a acquire request and the B acquire request, the memory management unit needs to access a certain page table. Assuming that the memory management unit is executing the a fetch request, the B fetch request needs to wait for the memory management unit to process the a fetch request, and then the memory management unit may process the B fetch request when the page table is not accessed.

Because the memory management unit has limited execution resources, once the memory management unit receives the acquisition request, the execution resources are allocated to the acquisition request, so that the resource utilization rate of the memory management unit is inevitably reduced under the condition that the memory management unit receives a plurality of acquisition requests needing to access the same page table. As shown in fig. 1.

Fig. 1 is a schematic diagram of a scenario in which a memory management unit processes an acquisition request. Taking the case that the cache units sending the acquisition request to the memory management unit are the cache unit 1 and the cache unit 2, respectively, the acquisition request sent by the cache unit 1 to the memory management unit includes: acquisition request 1, acquisition request 2, acquisition request 3, and acquisition request 4. The acquisition request sent by the cache unit 2 to the memory management unit includes: acquisition request 5, acquisition request 6, acquisition request 7, and acquisition request 8. Wherein the request represented by the white rectangle is a request for accessing the page table 1, and the request represented by the shadow rectangle is a request for accessing the page table 2.

Assuming that the memory management unit receives each acquiring request sent by the cache unit 1, the memory management unit may receive each acquiring request sent by the cache unit 2 and process the acquiring request after the acquiring request 1, the acquiring request 2, the acquiring request 3 and the acquiring request 4 are executed. However, for the fetch request 1, the fetch request 2, the fetch request 3, and the fetch request 4, the page tables to be accessed are the same page table, and it is obvious that the memory management unit needs to execute each request sent by the cache unit 1 in sequence. This results in the memory management unit being able to process only one fetch request during the same time period. The resource utilization rate is low, and the memory management efficiency is low. For each request, a page table to be accessed by the request is used for representing the corresponding relation between the virtual address and the physical address to be acquired by the request and is stored in the page table.

Based on this, in order to improve the resource utilization rate of the memory management unit, the present disclosure provides a memory management method, which determines, when a to-be-executed fetch request is received, a first page table corresponding to the to-be-executed fetch request. When the first page table is the page table which is being acquired by the memory management unit, waiting information is sent to a first cache unit which sends the acquisition request to be executed so as to suspend processing the acquisition request to be executed. And when the first page table is not the page table which is being acquired by the memory management unit, executing the acquisition request to be executed according to the page table storage information corresponding to the memory management unit. Therefore, the page tables which are processed by the memory management unit in the same period and need to be accessed by the acquisition request to be executed are different, the resource utilization rate of the memory management unit is guaranteed, and the memory management efficiency is improved. The page table storage information is used for representing the page table stored in the memory management unit.

Fig. 2 is a flow chart of a memory management method provided in the present specification, specifically including the following steps:

s100: and receiving an acquisition request to be executed, which is sent by a first cache unit, and determining a virtual address corresponding to the acquisition request to be executed.

The present disclosure provides a memory management method, where an execution process of the memory management method may be executed by a memory management unit for performing memory management.

Based on the above brief description of the memory management method in the present specification, it can be seen that the memory management method in the present specification may first determine that the fetch request is to be executed.

Specifically, a processor in the computer communicates with the cache unit, and when the processor needs to acquire corresponding data to perform data processing, the processor may send the virtual address to the cache unit. The cache unit may determine data corresponding to the virtual address according to the virtual address and return the data to the processor. Or, the buffer unit may also determine a physical address corresponding to the virtual address according to the virtual address, and return the physical address to the processor, where the processor obtains corresponding data according to the physical address.

And when the cache unit does not find corresponding data or does not find a physical address corresponding to the virtual address according to the virtual address, sending an acquisition request to the memory management unit according to the virtual address.

Then, the memory management unit may receive the fetch request sent by the first cache unit, and use the fetch request as a fetch request to be executed. The first cache unit is a cache unit for sending the to-be-executed acquisition request.

Meanwhile, the memory management unit needs to determine a physical address corresponding to the virtual address according to the virtual address contained in the to-be-executed acquisition request, and returns the physical address to the first cache unit. Therefore, after receiving the to-be-executed acquire request, the memory management unit may parse the to-be-executed acquire request to determine the virtual address included in the to-be-executed acquire request.

Of course, the to-be-executed acquiring request may be only a virtual address, that is, the first cache unit directly sends the virtual address to be determined as the physical address to the memory management unit, and the memory management unit directly determines the physical address corresponding to the virtual address according to the virtual address. The content included in the to-be-executed acquisition request and how to determine the to-be-executed acquisition request may be set according to needs, which is not limited in this specification.

S102: and determining a first page table corresponding to the virtual address.

In one or more embodiments provided herein, typically, a page table is stored in a main memory of a computer, and a memory management unit obtains the page table from the main memory according to a virtual address, and determines a physical address corresponding to the page table from the obtained page table according to the virtual address. Thus, the memory management unit may first determine a first page table corresponding to the virtual address.

Specifically, the memory management unit stores the correspondence between each page table and the corresponding virtual address range.

The memory management unit can then determine, from among the page tables, a page table storing a correspondence relationship between the virtual address and its corresponding physical address, as a first page table, based on the virtual address.

Further, when the memory management unit accesses the page table according to the virtual address, it is generally necessary to retrieve the page table entry based on the upper bits of the virtual address, so that when the first page table is retrieved, the offset of the physical address in the first page table is determined based on the lower bits of the virtual address, and the physical address in the first page table is located. It can be seen that for each virtual address, the high order bits of that virtual address can be used to retrieve the first page table.

The memory management unit may then directly determine the upper bits of the virtual address, and determine, based on the upper bits, an identification of the first page table corresponding to the virtual address. The high order may be the first 10 bits, the first 20 bits, and the like of the virtual address, and the low order may be the last 10 bits, the last 20 bits, and the like of the virtual address, so that the memory management unit may directly use the high order of the virtual address as the identifier of the first page table to characterize that the to-be-executed acquisition request needs to access the page table corresponding to the high order of the virtual address.

The memory management unit may perform subsequent steps based on the identity of each page table.

S104: responding to the first page table as a second page table, and sending waiting information to the first cache unit; the second page table is a page table that is being acquired by the memory management unit.

S106: and responding to the first page table not being a second page table, and executing the acquisition request to be executed based on page table storage information corresponding to the memory management unit.

In the memory management method in the present specification, after receiving the to-be-executed acquire request, whether the to-be-executed acquire request is executed immediately may be determined based on whether the first page table corresponding to the to-be-executed acquire request is accessed. Wherein for each page table, there are two cases where the page table is accessed: one is that the page table is the page table being fetched by the memory management unit, and the other is that the memory management unit has fetched the page table, but before receiving the fetch request to be executed, the memory management unit has received other fetch requests to access the page table.

In the second case, only the page table stored in the memory management unit needs to be queried to determine the physical address corresponding to the acquisition request, so that the memory management unit can process the physical address in a shorter time. The memory management unit stores an A page table, and the memory management unit receives the acquisition request to be executed 1 and the acquisition request to be executed 2 in sequence in a short time period. Both the pending fetch request 1 and the pending fetch request 2 require access to the a page table. When the memory management unit processes the to-be-executed fetch request 2, the to-be-executed fetch request a is already processed by the memory management unit. This results in a determination of whether the page table is accessed, which is typically only done by considering whether the page table is the page table being fetched by the memory management unit.

Specifically, for each fetch request being executed by the memory management unit, the memory management unit may use a page table corresponding to the fetch request as a second page table, and store a page table identifier of the second page table. Alternatively, the memory management unit may use the page table that is being acquired as the second page table, and store the identity of the second page table.

The memory management unit may determine whether the first page table exists in each second page table according to the identifier of the first page table and the page table identifier of each second page table, that is, determine whether the first page table is the page table that the memory management unit is acquiring.

If so, it is characterized that the first page table is being fetched, i.e., the first page table is already occupied. Thus, the memory management unit may temporarily not execute the pending fetch request.

If not, the first page table is characterized as being not a page table which is being acquired by the memory management unit, that is, the first page table is unoccupied. The memory management unit executes the pending fetch request.

It should be noted that, the first page table in the present specification is a page table storing a correspondence relationship between a virtual address in an to-be-executed acquire request and a physical address corresponding to the virtual address, that is, the first page table is a page table to be accessed by the memory management unit when executing the to-be-executed acquire request. The second page table in this specification is the page table that the memory management unit is acquiring.

Further, in the present disclosure, when the first page table is occupied, the to-be-executed fetch request may be executed by the memory management unit until the first page table is not occupied. In this case, if the memory management unit stores the to-be-executed acquisition request, and sequentially executes each to-be-executed acquisition request according to the storage time of each to-be-executed acquisition request stored by the memory management unit, the corresponding execution efficiency is poor. Thus, in the event that the first page table is occupied, the memory management unit may send wait information to the first cache unit that sent the first page table,

specifically, in the case that the first page table is occupied, the memory management unit may determine, according to the to-be-executed acquire request, a first cache unit that sends the to-be-executed acquire request.

The memory management unit may then send a wait message to the first cache unit. The waiting information is used for enabling the first cache unit to send the waiting acquisition request to the memory management unit again after a preset period of time.

The first cache unit may receive the wait information and re-send a wait-to-execute fetch request to the memory management unit after a predetermined period of time according to the wait information.

The memory management unit may receive the fetch request and determine a first page table corresponding to the retransmitted fetch request, and further execute the retransmitted memory management unit when the first page table is not a second page table, i.e., the first page table is not occupied. That is, the memory management unit may determine whether the first page table is the second page table after receiving the resent fetch request to be executed. If yes, continuing to send waiting information to the first cache unit which sends the acquisition request to be executed. If not, the memory management unit can directly execute the to-be-executed acquisition request.

Meanwhile, the memory management unit can delete the to-be-executed acquisition request received by the memory management unit and continuously receive the to-be-executed acquisition requests sent by other cache units.

Through the above embodiment, the memory management unit may not store the to-be-executed acquisition request itself, but send the waiting information to the first cache unit, so that the first cache unit stores the to-be-executed acquisition request and subsequently resends the to-be-executed acquisition request to the memory management unit, thereby ensuring that page tables corresponding to each to-be-executed acquisition request in the memory management unit are different, so that the memory management unit can concurrently process a plurality of to-be-executed acquisition requests, and resource utilization rate is improved.

Further, in this specification, when the first page table is not occupied, it means that the memory management unit may occupy the page table according to the to-be-executed fetch request, that is, access the first page table according to the virtual address in the to-be-executed fetch request. Thus, when the first page table is not the second page table, the memory management unit may execute the pending fetch request.

Specifically, the memory management unit itself may store page table save information. The page table storage information is used for representing a page table stored by the memory management unit.

Therefore, the memory management unit can determine a first page table according to the page table storage information corresponding to the memory management unit, inquire the physical address corresponding to the virtual address from the first page table, and return the physical address to the first cache unit.

Based on the memory management method shown in fig. 2, when an acquisition request to be executed is received, a first page table corresponding to the acquisition request to be executed is determined, when the first page table is a page table being acquired by the memory management unit, waiting information is sent to a first cache unit sending the acquisition request to be executed so as to suspend processing the acquisition request to be executed, and when the first page table is not a page table being acquired by the memory management unit, the acquisition request to be executed is executed according to page table storage information stored by the memory management unit. Therefore, the page tables which are processed by the memory management unit in the same period and need to be accessed by the acquisition request to be executed are different, the resource utilization rate of the memory management unit is guaranteed, and the memory management efficiency is improved.

In addition, the memory management unit may have its corresponding execution resources, and the memory management unit may have limited execution resources. Wherein the execution resource may be used to characterize an upper bound of the fetch requests that the memory management unit may process concurrently. Taking the execution resource of the memory management unit as 4 as an example, the memory management unit can process 4 fetch requests simultaneously. Of course, the execution resource may also be a computing resource, that is, the memory management unit stores the computing resource that is occupied by both the fetch request and the execution fetch request. The specific definition of the execution resource and the meaning of the characterization can be set according to the needs, and the specification does not limit the definition.

In this case, if the first page table is in the occupied state, allocating the execution resources for the to-be-executed acquire request may cause the limited execution resources in the memory management unit to be occupied, thereby resulting in a lower resource utilization of the memory management unit. Therefore, when the first page table is the second page table, the memory management unit may allocate execution resources for the to-be-executed acquire request, and allocate execution resources for the to-be-executed acquire request when the first page table is not the second page table, so as to execute the to-be-executed acquire request.

Specifically, when the first page table is the second page table, the memory management unit may return waiting information to the first cache unit according to the to-be-executed fetch request. The waiting information may be used to prompt that a first page table corresponding to the to-be-executed acquire request is occupied, and prompt that the first cache unit resends the to-be-executed acquire request after a preset period of time.

Then, the first buffer unit may resend the to-be-executed acquisition request to the memory management unit after a preset period according to the received waiting information.

The memory management unit may receive the to-be-executed acquire request sent again by the first cache unit, and determine whether the first page table is the second page table according to the first page table corresponding to the to-be-executed acquire request sent again.

If yes, the memory management unit may continue to repeat the above steps. That is, the waiting information is continuously sent to the first buffer unit, and the to-be-executed acquisition request resent by the first buffer unit according to the waiting information is received until the to-be-executed acquisition request is executed.

If not, the memory management unit can allocate execution resources for the to-be-executed acquisition request, and execute the to-be-executed acquisition request according to the execution resources. That is, according to the virtual address corresponding to the to-be-executed fetch request, a first page table is determined, a physical address corresponding to the virtual address is queried from the first page table, and the physical address is returned to the first cache unit.

Further, as described above, when the first page table is not the second page table, it means that the first page table is not accessed, and there are two cases where the first page table is fetched and stored by the memory management unit, and the other is where the first page table is not fetched by the memory management unit yet.

Therefore, the memory management unit can determine the page table identifier of each third page table acquired by the memory management unit according to the page table storage information used for representing each page table stored by the memory management unit, and judge whether the memory management unit has acquired the first page table according to the page table identifier of the first page table and the page table identifier of each third page table. The third page table is a page table that has been obtained by the memory management unit and stored in the memory management unit.

If yes, the memory management unit can directly determine the physical address corresponding to the virtual address in the acquisition request to be executed from the page table stored by the memory management unit. The memory management system may then determine the first page table from among the page tables stored by the memory management unit itself based on the page table identification of the third page tables and the page table identification of the first page table. And then, determining a physical address corresponding to the virtual address from the first page table according to the virtual address in the to-be-executed acquisition request. Finally, the memory management unit may respond to the to-be-executed fetch request according to the physical address.

The memory management unit may directly return the physical address to the first cache unit according to the to-be-executed acquiring request, or may determine data stored in the physical address according to the physical address, and return the data stored in the physical address to the first cache unit. How the memory management unit responds to the acquisition request to be executed according to the physical address can be set according to the requirement, and the description is not limited.

If not, the memory management unit is characterized in that the memory management unit needs to acquire the first page table first, and then the response to the acquisition request to be executed can be determined from the first page table by the physical address of the response. The memory management unit may then allocate execution resources for the pending fetch request and execute the first page table with the execution resources.

The memory management unit executes the first page table to characterize a process that the memory management unit converts a physical address corresponding to an acquisition request to be executed into a virtual address according to the execution resource.

Specifically, the memory management unit may mark the first page table as a second page table by executing resources, and send an acquisition request corresponding to the first page table to a downstream storage unit of the memory management unit according to a page table identifier of the first page table. The fetch request of the first page table is used to fetch the first page table from the downstream memory location. The downstream storage unit may be specifically another memory management unit, and a storage unit of a disk for storing a page table.

The downstream storage unit may determine a first page table from each data stored in the downstream storage unit according to the received acquisition request, and return the first page table to the memory management unit.

Finally, the memory management unit may receive the first page table sent by the downstream storage unit, determine, in the first page table, a physical address corresponding to the virtual address according to the virtual address in the to-be-executed acquire request, and respond to the to-be-executed acquire request according to the physical address.

Furthermore, in order to avoid that the memory management unit cannot execute the acquisition request to be executed or cannot execute other tasks due to excessive data stored in the memory management unit, the memory management unit may further directly access the first page table from a downstream storage unit of the memory management unit, determine a physical address corresponding to the virtual address, and respond to the acquisition request to be executed based on the determined physical address.

Specifically, the memory management unit may send an acquisition request to the downstream storage unit, where the acquisition request includes a virtual address, and the acquisition request is used to determine a physical address corresponding to the virtual address.

The downstream storage unit may then determine a first page table based on the virtual address, and walk the physical address corresponding to the virtual address from the first page table, and return the physical address to the memory management unit based on the fetch request.

The memory management unit may receive the physical address returned by the downstream storage unit and respond to the to-be-executed fetch request according to the physical address.

Of course, the memory management unit may also directly pull the physical address corresponding to the virtual address or the first page table from the downstream storage unit, and how the memory management unit executes the first page table may be set according to the needs, which is not limited in this specification.

In addition, when the first page table is acquired through the execution resource, the memory management unit may further determine, through the execution resource, a storage location of the first page table according to a page table identifier of the first page table, and determine the first page table from the storage location of the first page table. And marking the first page table as a second page table, and acquiring the second page table until the memory management unit acquires the first page table. And finally, the memory management unit can execute the to-be-executed acquisition request, inquire the physical address corresponding to the virtual address from the acquired first page table, and return the physical address to the first cache unit.

Based on the same idea, the present disclosure further provides a schematic view of a scenario in which the memory management unit processes the acquisition request, as shown in fig. 3.

Fig. 3 is a schematic view of a scenario for processing an acquisition request provided in the present specification. Similarly, taking the example that the cache units sending the acquisition request to the memory management unit are the cache unit 1 and the cache unit 2, respectively, the acquisition request sent by the cache unit 1 to the memory management unit includes: acquisition request 1, acquisition request 2, acquisition request 3, and acquisition request 4. The acquisition request sent by the cache unit 2 to the memory management unit includes: acquisition request 5, acquisition request 6, acquisition request 7, and acquisition request 8. Wherein the request represented by the white rectangle is a request for accessing the page table 1, and the request represented by the shadow rectangle is a request for accessing the page table 2.

Thus, based on the memory management method in the present specification, the memory management unit may determine, after receiving the fetch request 1, a first page table corresponding to the fetch request 1: page table 1. It can be seen that page table 1 is unoccupied, then the memory management unit may execute the fetch request 1. Then, when the memory management unit receives the fetch request 2, it may determine that the first page table corresponding to the fetch request 2: page table 1. It can be seen that page table 1 is the page table being fetched by the memory management unit, and the memory management unit may not allocate execution resources for the fetch request 2. Similarly, the memory management unit may not allocate execution resources for the fetch request 3 and the fetch request 4 after receiving the fetch request 3 and the fetch request 4.

If the memory management unit receives the fetch request 5, determining a first page table corresponding to the fetch request 5: page table 2. It can be seen that page table 2 is unoccupied, the memory management unit may execute the fetch request 5. Similarly, after receiving the fetch request 6, the fetch request 7, and the fetch request 8, the memory management unit may determine page tables corresponding to the fetch requests 6, 7, and 8, respectively: page table 2. When page table 2 is the page table that the memory management unit is fetching, the memory management unit may not allocate execution resources for fetch request 6, fetch request 7, and fetch request 8.

Thus, the memory management unit may process two fetch requests simultaneously during the same period of time, and may also execute other page table corresponding fetch requests when they are received. Therefore, the memory management unit can process the acquisition requests corresponding to different page tables concurrently, so that the resource utilization rate and the memory management efficiency of the memory management unit are ensured.

In addition, if the first cache unit directly resends the to-be-executed acquiring request to the memory management unit after receiving the waiting information at intervals of a preset period, there may be a case that the first cache unit does not acquire the first page table completely within the preset period, so that the first page table is still the page table being acquired by the memory management unit. In order to avoid the above situation, the memory management unit may further monitor the state of the first page table, and send a retry instruction to the first cache unit when it is determined that the first page table has been acquired.

Specifically, the memory management unit may monitor the state of the first page table.

When the memory management unit determines that the first page table is acquired according to the monitoring data, the memory management unit can send a retry instruction to the first cache unit, and meanwhile, the memory management unit can update page table storage information according to the first page table.

The retry instruction is configured to modify a state of the to-be-executed acquire instruction into an execution state. Taking the page table save information as an example of the identification of the third page table that has been obtained by the memory management unit and stored in the memory management unit, the memory management unit may mark the first page table as the third page table and add the identification of the first page table to the page table save information. Taking the page table storage information as a page table identifier corresponding to each third page table and an address translation relationship corresponding to each third page table as an example, the memory management unit may directly mark the first page table as a third page table, and add the identifier of the first page table and the address translation relationship of the first page table to the page table storage information. How to update the page table save relationship according to the first page table can be set as required, which is not limited in this specification.

Then, the first buffer unit may receive the retry instruction sent by the memory management unit, modify the state of the to-be-executed acquire request from the waiting state to the executing state according to the retry instruction, and resend the to-be-executed acquire request to the memory management unit.

The memory management unit may receive the to-be-executed acquire request sent by the cache unit, and directly determine a first page table from each page table acquired by the memory management unit, and execute the to-be-executed acquire request according to the first page table.

Further, the number of the pending fetch requests stored in the memory management unit may be multiple, and the first page tables corresponding to the pending fetch requests in the pending state may not be the same page table. In this case, in order to avoid a situation that the first page table corresponding to the to-be-executed acquisition request sent to the memory management unit again by the first cache unit is different from the first page table corresponding to the retry instruction, the retry instruction sent to the first cache unit by the memory management unit may further carry the identifier of the target acquisition request.

Specifically, the memory management unit may store a correspondence between each to-be-executed acquiring request in a waiting state and each page table, and determine, according to the first page table, from each to-be-executed acquiring request in the waiting state, the to-be-executed acquiring request corresponding to the first page table as a target acquiring request.

Then, the memory management unit may determine a retry order including an identifier of the target fetch request according to the target fetch request, and send the retry order to the first cache unit.

The cache unit may receive the retry instruction, determine an identifier of a target acquisition request included in the retry instruction, and resend the target acquisition request to the memory management unit according to the identifier of the target acquisition request.

The memory management unit can receive the target acquisition request, determine a first page table corresponding to the target acquisition request from all page tables acquired by the memory management unit, execute the target acquisition request according to the first page table, and determine an execution result.

In this specification, it may also happen that the memory management unit receives, at the same time, an acquisition request to be executed sent by the cache unit a according to the retry instruction, and an acquisition request to be executed directly sent by the cache unit B, and if the page tables to be accessed by the two acquisition requests to be executed are the same, the memory management unit needs to execute the acquisition request to be executed sent by the retry instruction first, and then execute the acquisition request to be executed sent by the cache unit B. In order to avoid the situation that the memory management unit is difficult to distinguish the to-be-executed acquisition requests, the to-be-executed acquisition request sent to the memory management unit by the cache unit according to the retry instruction may also be the to-be-executed acquisition request in a waiting state.

Specifically, after receiving the retry instruction, the cache unit may further send an acquisition request to be executed in a waiting state to the memory management unit.

The memory management unit can receive the re-sent acquisition request to be executed in a waiting state by the cache unit and modify the state of the acquisition request to be executed into an execution state. Thus, the memory management unit may allocate execution resources for the pending fetch requests in the execution state.

In addition, a storage unit for storing the acquisition request to be executed may be provided in the computer. That is, the cache unit sends the to-be-executed acquisition request to the storage unit for storage, and the memory management unit pulls the to-be-executed acquisition request from the storage unit and executes the to-be-executed acquisition request. However, in general, the resources of the storage unit are limited, and the number of the acquisition requests to be executed that can be stored is limited. Once the storage unit stores a certain to-be-executed acquisition request, storage resources are allocated to the to-be-executed acquisition request.

In this case, if each to-be-executed fetch request stored in the storage unit includes to-be-executed fetch requests that need to access the same page table, the resource utilization of the memory management unit will be affected. In this regard, in the present specification, the storage resource of the storage unit may be used as the execution resource.

Specifically, when the memory unit receives the to-be-executed fetch request, the memory management unit may pull the to-be-executed fetch request, and determine a first page table to be accessed for executing the to-be-executed fetch request.

When the page table being acquired by the memory management unit includes the first page table, the memory management unit may send waiting information to the first cache unit that sends the to-be-executed acquire request, and no longer store the to-be-executed acquire request to the storage unit. That is, the fetch request to be executed that is pulled from the storage unit is deleted.

When the page table being fetched by the memory management unit does not include the first page table, the memory management unit may store the fetch request to be executed in the storage unit.

Based on the same thought, the present disclosure also provides a memory management system, as shown in fig. 4.

Fig. 4 is a schematic structural diagram of a memory management system provided in the present specification, where the memory management system includes a memory management unit and a cache unit, and the memory management unit and the cache unit communicate with each other, where:

the first cache unit may send a fetch request to be executed to the memory management unit. The first cache unit is a cache unit sending the to-be-executed acquisition request, and the first cache unit can be any cache unit in the memory management system.

The memory management unit can receive the to-be-executed acquisition request sent by the first cache unit and determine a virtual address corresponding to the to-be-executed acquisition request.

Then, the memory management unit can determine a first page table corresponding to the virtual address, and send waiting information to a first cache unit sending the first page table when the first page table is a second page table, wherein the second page table is the page table which is being acquired by the memory management unit. When the first page table part is the second page table, the memory management unit can execute the to-be-executed acquisition request based on page table storage information corresponding to the memory management unit.

Or in a plurality of embodiments, the first cache unit in the memory management system may refer to the description of the cache unit and the first cache unit in the steps S100-S106. Similarly, the memory management unit in the memory management system may refer to the description of the memory management unit in steps S100-S106. The present application is not described in detail herein.

Based on the memory management system shown in fig. 4, after the cache unit determines the to-be-executed acquire request, the memory management unit determines a first page table corresponding to the to-be-executed acquire request, when the first page table is a page table being acquired by the memory management unit, sends waiting information to the first cache unit sending the to-be-executed acquire request so as to suspend processing the to-be-executed acquire request, and when the first page table is not a page table being acquired by the memory management unit, the to-be-executed acquire request is executed according to page table save information corresponding to the first page table. Therefore, the memory management unit can process the to-be-executed acquisition requests corresponding to different page tables simultaneously, so that the resource utilization rate of the memory management unit is ensured, and the management efficiency of the memory management system is improved.

Based on the same thought, the present disclosure also provides a memory management device, as shown in fig. 5.

Fig. 5 is a schematic structural diagram of a memory management device provided in the present disclosure, where the device is applied to a memory management unit, and the memory management unit communicates with a cache unit, where:

the receiving module 200 is configured to receive an acquisition request to be executed sent by the first cache unit, and determine a virtual address corresponding to the acquisition request to be executed.

A determining module 202, configured to determine a first page table corresponding to the virtual address.

A first response module 204, configured to send waiting information to the first cache unit in response to the first page table being a second page table; the second page table is a page table that is being acquired by the memory management unit.

And the second response module 206 is configured to execute the to-be-executed fetch request in response to the first page table not being the second page table, so as to query the physical address corresponding to the virtual address from the first page table, and return the physical address to the first cache unit.

Optionally, the first response module 204 is configured to send, in response to the first page table being a second page table, waiting information to the first cache unit according to the to-be-executed acquisition request, where the waiting information is used to enable the first cache unit to resend the to-be-executed acquisition request to the memory management unit after a preset period of time; receiving an acquisition request to be executed which is resent after the first cache unit is spaced by the preset period, and judging whether the first page table is a second page table or not; and if not, executing the retransmitted acquisition request to be executed.

Optionally, the first response module 204 is configured to send, in response to the first page table being the second page table, waiting information to the first cache unit according to the to-be-executed obtain request, where the waiting information is used to enable the first cache unit to modify a state of the to-be-executed obtain request into a waiting state.

Optionally, the first response module 204 is configured to monitor a state of the first page table, send a retry instruction to the first cache unit when determining that the memory management unit has acquired the first page table, and update the page table save information based on the first page table; the retry instruction is configured to modify a state of the to-be-executed acquisition instruction into an execution state; and receiving an acquisition request to be executed, which is resent by the first cache unit according to the retry instruction, and executing the resent acquisition request to be executed.

Optionally, the second response module 206 is configured to, when it is determined that the memory management unit has acquired the first page table based on page table save information, determine the first page table from page tables stored by the memory management unit, determine a corresponding physical address in the first page table according to the virtual address, and respond to the to-be-executed acquisition request based on the physical address; when the memory management unit does not acquire the first page table based on the page table storage information, allocating execution resources for the acquisition request to be executed, and executing the first page table through the execution resources; the page table storage information is used for representing the page table stored in the memory management unit.

Optionally, the second response module 206 is configured to use the execution resource to mark the first page table as a second page table, send an acquisition request corresponding to the first page table to a downstream storage unit of the memory management unit, receive the first page table returned by the downstream storage unit according to the acquisition request, determine a corresponding physical address in the first page table according to the virtual address, and respond to the acquisition request to be executed based on the physical address.

The present specification also provides a computer readable storage medium storing a computer program operable to perform the memory management method provided in fig. 2 above.

The present specification also provides a schematic structural diagram of the electronic device shown in fig. 6. At the hardware level, the electronic device includes a processor, an internal bus, a network interface, a memory, and a non-volatile storage, as illustrated in fig. 6, although other hardware required by other services may be included. The processor reads the corresponding computer program from the nonvolatile memory into the memory and then runs the computer program to implement the memory management method described in fig. 2. Of course, other implementations, such as logic devices or combinations of hardware and software, are not excluded from the present description, that is, the execution subject of the following processing flows is not limited to each logic unit, but may be hardware or logic devices.

In the 90 s of the 20 th century, improvements to one technology could clearly be distinguished as improvements in hardware (e.g., improvements to circuit structures such as diodes, transistors, switches, etc.) or software (improvements to the process flow). However, with the development of technology, many improvements of the current method flows can be regarded as direct improvements of hardware circuit structures. Designers almost always obtain corresponding hardware circuit structures by programming improved method flows into hardware circuits. Therefore, an improvement of a method flow cannot be said to be realized by a hardware entity module. For example, a programmable logic device (Programmable Logic Device, PLD) (e.g., field programmable gate array (Field Programmable Gate Array, FPGA)) is an integrated circuit whose logic function is determined by the programming of the device by a user. A designer programs to "integrate" a digital system onto a PLD without requiring the chip manufacturer to design and fabricate application-specific integrated circuit chips. Moreover, nowadays, instead of manually manufacturing integrated circuit chips, such programming is mostly implemented by using "logic compiler" software, which is similar to the software compiler used in program development and writing, and the original code before the compiling is also written in a specific programming language, which is called hardware description language (Hardware Description Language, HDL), but not just one of the hdds, but a plurality of kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), lava, lola, myHDL, PALASM, RHDL (Ruby Hardware Description Language), etc., VHDL (Very-High-Speed Integrated Circuit Hardware Description Language) and Verilog are currently most commonly used. It will also be apparent to those skilled in the art that a hardware circuit implementing the logic method flow can be readily obtained by merely slightly programming the method flow into an integrated circuit using several of the hardware description languages described above.

The controller may be implemented in any suitable manner, for example, the controller may take the form of, for example, a microprocessor or processor and a computer readable medium storing computer readable program code (e.g., software or firmware) executable by the (micro) processor, logic gates, switches, application specific integrated circuits (Application Specific Integrated Circuit, ASIC), programmable logic controllers, and embedded microcontrollers, examples of which include, but are not limited to, the following microcontrollers: ARC 625D, atmel AT91SAM, microchip PIC18F26K20, and Silicone Labs C8051F320, the memory controller may also be implemented as part of the control logic of the memory. Those skilled in the art will also appreciate that, in addition to implementing the controller in a pure computer readable program code, it is well possible to implement the same functionality by logically programming the method steps such that the controller is in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. Such a controller may thus be regarded as a kind of hardware component, and means for performing various functions included therein may also be regarded as structures within the hardware component. Or even means for achieving the various functions may be regarded as either software modules implementing the methods or structures within hardware components.

The system, apparatus, module or unit set forth in the above embodiments may be implemented in particular by a computer chip or entity, or by a product having a certain function. One typical implementation is a computer. In particular, the computer may be, for example, a personal computer, a laptop computer, a cellular telephone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

For convenience of description, the above devices are described as being functionally divided into various units, respectively. Of course, the functions of each element may be implemented in one or more software and/or hardware elements when implemented in the present specification.

It will be appreciated by those skilled in the art that embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, the present specification may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present description can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The present description is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the specification. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable lesion detection device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable lesion detection device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable lesion detection device to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of computer-readable media.

Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.

It will be appreciated by those skilled in the art that embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, the present specification may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present description can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The description may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.

In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments.

The foregoing is merely exemplary of the present disclosure and is not intended to limit the disclosure. Various modifications and alterations to this specification will become apparent to those skilled in the art. Any modifications, equivalent substitutions, improvements, or the like, which are within the spirit and principles of the present description, are intended to be included within the scope of the claims of the present description.

Claims

1. A memory management method, wherein the method is applied to a memory management unit, the memory management unit communicates with a cache unit, and the method comprises:

determining a first page table corresponding to the virtual address;

2. The method of claim 1, wherein sending wait information to the first cache unit in response to the first page table being a second page table, comprises:

the method further comprises the steps of:

and if not, executing the retransmitted acquisition request to be executed.

3. The method of claim 1, wherein sending wait information to the first cache unit in response to the first page table being a second page table, comprises:

4. A method as claimed in claim 3, wherein the method further comprises:

5. The method of claim 1 wherein the page table save information is used to characterize a page table stored in the memory management unit;

6. The method of claim 5, wherein executing the first page table by the execution resource, comprises:

7. The memory management system is characterized by comprising a memory management unit and a cache unit, wherein the memory management unit and the cache unit are communicated; wherein:

8. A memory management device, wherein the device is applied to a memory management unit, the memory management unit communicates with a cache unit, the device comprising:

9. A computer readable storage medium storing a computer program, characterized in that the computer program, when executed by a processor, implements the method of any of the preceding claims 1-6.

10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the method of any of the preceding claims 1-6 when executing the program.