CN117110831A

CN117110831A - Test equipment, test system and test method

Info

Publication number: CN117110831A
Application number: CN202310851753.2A
Authority: CN
Inventors: 陈建宜; 刘高志; 林家弘; 林裕庭; 顾旻峰
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-07-29
Filing date: 2023-07-12
Publication date: 2023-11-24

Abstract

A test apparatus, a test system, and a test method. The test equipment comprises a socket of a test tool for providing a test signal. A Device Under Test (DUT) board is used to provide electrical routing. An Integrated Circuit (IC) die is disposed between the socket and the DUT board. The test signals are routed electrically through the DUT board to the IC die. The IC die includes a substrate in which a plurality of transistors are formed. The first structure contains a plurality of first metallization elements. The second structure contains a plurality of second metallization elements. The first structure is disposed over a first side of the substrate. The second structure is disposed on a second side of the substrate opposite the first side. A trench extends through the DUT board and partially into the IC die from the second side. The signal detection tool is used for detecting an electrical signal or an optical signal generated by the IC chip.

Description

Test equipment, test system and test method

Technical Field

The disclosure relates to a test device, a test system and a test method.

Background

The semiconductor integrated circuit (semiconductor integrated circuit, IC) industry has experienced an exponential growth. Technological advances in IC materials and designs have resulted in generations of ICs with smaller and more complex circuitry per generation than previous generations. In the course of IC evolution, functional density (i.e., the number of interconnects per die area) has increased substantially, while geometry size (i.e., the smallest component (or wire) that can be created using a fabrication process) has decreased.

However, as the downscaling process continues, the downscaling process has caused certain manufacturing challenges. For example, IC wafers that have experienced faults or other performance problems may be tested as part of a debug process to identify the source of the fault or performance problem. However, as IC wafers are manufactured at increasingly smaller technology nodes, debugging of IC wafers can become increasingly difficult. In general, existing circuit components (e.g., existing metallization components) on an IC wafer may block or otherwise interfere with the debug process. Thus, while existing IC wafer debug processes have been generally suitable for their intended purpose, they have not been entirely satisfactory in every aspect.

Disclosure of Invention

One aspect of the present disclosure relates to a test apparatus including a socket of a test tool for providing a test signal. A device-under-test (DUT) board is used to provide electrical routing. An integrated circuit (integrated circuit, IC) die is disposed between the socket and the DUT board. Test signals are routed electrically through the DUT board to the IC die. The IC die includes a substrate in which a plurality of transistors are formed. The first structure contains a plurality of first metallization elements. The second structure contains a plurality of second metallization elements. The first structure is disposed over the first side of the substrate. The second structure is disposed on a second side of the substrate opposite the first side.

Another aspect of the present disclosure relates to a test system including an integrated circuit (integrated circuit, IC) package assembly including an IC die and a printed circuit board (printed circuit board, PCB) substrate bonded to the IC die. The socket of the test tool is disposed over the first side of the IC package assembly. A device-under-test (DUT) board is disposed over the second side of the IC package assembly. The DUT board is used to route test signals provided by the test tool from the socket to the IC package assembly. The IC package assembly generates an electrical signal or an optical signal in response to receiving the test signal. The trench extends through the DUT board, through the PCB substrate, and partially into the IC die from the second side. The signal detection tool is disposed on the second side of the IC package assembly. The signal detection tool is used for detecting an electrical signal or an optical signal generated by the IC package. The electrical or optical signal propagates through the trench towards the second side.

Yet another aspect of the present disclosure relates to a test method including providing an integrated circuit (integrated circuit, IC) package assembly. An integrated circuit package includes an IC die. The IC die includes a semiconductor substrate, a first metallization structure disposed on a first side of the semiconductor substrate, and a second metallization structure disposed on a second side of the semiconductor substrate opposite the first side. The IC package assembly further includes a printed circuit board (printed circuit board, PCB) substrate bonded to the IC die from the second side. The IC package assembly is coupled to a device-under-test (DUT) board. The DUT board is coupled to the IC package assembly through the PCB substrate. A trench is formed that extends through the DUT board, through the PCB substrate, and partially into the IC die. The groove extends from the second side toward the first side. After the trench is formed, a socket of the test tool is coupled to the DUT board. The coupling of the sockets is performed such that after the socket coupling, the IC package assembly is positioned between the DUT board and the socket.

Drawings

The aspects of the present disclosure are better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. It is also emphasized that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.

Fig. 1A is a three-dimensional perspective view of a fin field effect transistor (fin-type field effect transistor, finFET) device of some embodiments of the present disclosure;

fig. 1B is a top view of a FinFET device in accordance with some embodiments of the present disclosure;

FIG. 1C is a three-dimensional perspective view of a multi-channel full-around Gate (GAA) device in accordance with some embodiments of the present disclosure;

fig. 2-8 illustrate a series of cross-sectional side views of an IC die and one or more test structures at various test stages according to an embodiment of the present disclosure;

FIG. 9 illustrates a top plan view of an IC die according to an embodiment of the present disclosure;

FIG. 10 is a schematic circuit diagram of a static random access memory (Static Random Access Memory, SRAM) cell according to various aspects of the present disclosure;

FIG. 11 is a block diagram of a manufacturing system according to various aspects of the present disclosure;

fig. 12 is a block diagram of a method of packaging and testing an IC device according to various aspects of the present disclosure.

[ symbolic description ]

90 integrated circuit device/IC device

110 substrate

120 three-dimensional active area/fin structure/fin

122 source/drain assembly

130 isolation structure

140 grid structure

150 full surrounding gate device/GAA device

155 layer(s)

160 gate spacer structure

165 capping layer

170 nano-structure

175 dielectric inter-spacer

180 conductive source/drain contacts

185 interlayer dielectric

200 IC die

210 transistor

220 interconnect structure

230 side of

231 side of

240 metal wiring

245 conductive column

250 interlayer dielectric

260, bonding layer

270 carrier substrate

280 Power delivery network/PDN

285 rail

290 conductive bump

300 ic package assembly

310 substrate

320 molding material

330 conductive bump

350 device under test board/DUT board

360 joining process

370 conductive bump

380 Material

400 groove forming process

410 trench/opening

420 depth of

430,440 width

480 coupling process

500 socket

510 conductive structure

520 height of

530 height of

540 height of

550 height of

600:test process

610 detection tool

620 signal

800 SRAM cell

900 integrated circuit manufacturing system

902,904,906,908,910,912,914,916 entity 918 communication network

1000 method

1010,1020,1030,1040 step

PU1 transistor

PU2 transistor

PD1 transistor

PD2 transistor

SN1 first storage node

SNB1 complementary first storage node

PG1 transistor

PG2 transistor

BL bit line

BLB complementary bit line

WL, word line

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms such as "below," "lower," "above," "upper," and the like may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Still further, when a number or range of numbers is described with "about," "approximately," etc., the term is intended to encompass numbers within a reasonable range including the recited number, such as within +/-10% of the recited number or other values understood by one of ordinary skill. For example, the term "about 5nm" encompasses dimensions ranging from 4.5nm to 5.5 nm.

The present disclosure relates generally to a unique manufacturing process flow for packaging an IC wafer, such as a Super Power Rail (SPR) wafer, so that the IC wafer can be easily debug without encountering interference problems with existing metallization components on the IC wafer. In more detail, a conventional IC chip generally includes a semiconductor substrate on (or in) which transistors are formed. The metallization assembly is then formed on one side (commonly referred to as the "front side") of the substrate. The metallization assembly may include metal lines or conductive pillars that are part of the multi-layer interconnect structure. When an IC wafer undergoes a debug process to identify a failure, electrical test signals may be sent to the IC wafer to facilitate operation of the IC wafer. The IC die may emit signals in response to being operated on, and an emission detection tool (e.g., an electron beam or e-beam machine) may be placed on a "backside" of the IC die (e.g., the side opposite the metallization components) to collect the emitted signals. Based on analysis of the signals emitted from the IC die under test, the source of the failure (e.g., the location of the failure and/or the cause of the failure) may be identified.

However, as IC wafers advance to more advanced technology nodes, some IC wafers (e.g., SPR wafers) have metallization components on both sides of the substrate. In other words, metallization components such as metal lines and conductive pillars may be present not only on the front side of the substrate, but also on the back side of the substrate. Thus, for an IC die to be debug, wherever the emission detection tool is disposed or is disposed on the IC die, signals emitted by the IC die may be blocked or otherwise blocked by metallization elements on the front or back side, which may make testing difficult and the results may be unsatisfactory.

To address the problems discussed above, the present disclosure utilizes novel packaging and testing process flows to repackage IC chips having metallization components on both sides, as discussed in more detail below with reference to fig. 1A, 1B, 1C, and 2-11. In more detail, fig. 1A-1B illustrate an exemplary FinFET device, and fig. 1C illustrates an exemplary GAA device. Fig. 2-8 illustrate cross-sectional side views of an IC package assembly and/or one or more test equipment at various package/test stages according to embodiments of the present disclosure. Fig. 9 illustrates a top plan view of an IC package assembly according to an embodiment of the present disclosure. Fig. 10 illustrates a memory device in which the IC package assembly of the present disclosure may be implemented. Fig. 11 illustrates a semiconductor manufacturing system that may be used to manufacture the IC devices of the present disclosure.

Referring now to fig. 1A and 1B, a three-dimensional perspective view and a top view, respectively, of a portion of an integrated circuit (Integrated Circuit, IC) device 90 are illustrated. The IC device 90 is implemented using field-effect transistors (FETs), such as three-dimensional fin-line FETs (finfets). The FinFET device has a semiconductor fin structure that protrudes vertically from a substrate. The fin structure is an active region from which source/drain region(s) and/or channel region(s) are formed. The source/drain region(s) may be referred to individually or collectively as a source or drain, depending on the context. The source/drain regions may also relate to providing regions for the source and/or drain of multiple devices. The gate structure is partially wrapped around the fin structure. In recent years, finFET devices have gained popularity due to their enhanced performance compared to conventional planar transistors.

As shown in fig. 1A, IC device 90 includes a substrate 110. The substrate 110 may comprise an elemental semiconductor, such as silicon, germanium, and/or other suitable materials; compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, and/or other suitable materials; an alloy semiconductor, such as SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP, gaInAsP, and/or other suitable materials. The substrate 110 may be a single layer of material having a uniform composition. Alternatively, the substrate 110 may include multiple material layers having similar or different compositions suitable for IC device fabrication. In one example, the substrate 110 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another example, the substrate 110 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or a combination thereof. Various doped regions, such as source/drain regions, may be formed in or on the substrate 110. The doped regions may be doped with an n-type dopant, such as phosphorus or arsenic, and/or a p-type dopant, such as boron, depending on design requirements. The doped regions may be formed directly on the substrate 110, in a p-well structure, in an n-well structure, in a dual-well structure, or using a raised structure. The doped regions may be formed by implantation of dopant atoms, in-situ doped epitaxial growth, and/or other suitable techniques.

The three-dimensional active region 120 is formed on the substrate 110. The active region 120 may include an elongated fin structure protruding upward from the substrate 110. Thus, the active region 120 may be interchangeably referred to hereinafter as fin structure 120 or fin 120. Fin structure 120 may be fabricated using suitable processes including photolithography and etching processes. The photolithography process may include forming a photoresist layer covering the substrate 110, exposing the photoresist to a pattern, performing a post exposure bake process, and developing the photoresist to form a mask element (not shown) including a resist. The masking element is then used to etch a recess into the substrate 110, leaving the fin structure 120 on the substrate 110. The etching process may include dry etching, wet etching, reactive ion etching (reactive ion etching, RIE), and/or other suitable processes. In some embodiments, fin structure 120 may be formed by a double patterning or multiple patterning process. Typically, a double patterning or multiple patterning process combines photolithography and self-aligned processes, allowing creation of patterns with, for example, a pitch smaller than what would otherwise be obtainable using a single direct photolithography process. As an example, a layer may be formed over a substrate and patterned using a photolithography process. Spacers are formed beside the patterned layer using a self-aligned process. The layers are then removed and the remaining spacers, or mandrels, may then be used to pattern fin structure 120.

IC device 90 also includes source/drain elements 122 formed over fin structure 120. The source/drain components 122 (also referred to as source/drain regions) may be referred to individually or collectively as the source or drain of a transistor, depending on the context. Source/drain elements 122 may include an epitaxial layer epitaxially grown on fin structure 120. The IC device 90 further includes an isolation structure 130 formed over the substrate 110. The isolation structures 130 electrically separate the various components of the IC device 90. Isolation structures 130 may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), low-k dielectric materials, and/or other suitable materials. In some embodiments, the isolation structure 130 may include shallow trench isolation (shallow trench isolation, STI) features. In one embodiment, isolation structure 130 is formed by etching a trench in substrate 110 during formation of fin structure 120. The trench may then be filled with the isolation material described above, followed by a chemical mechanical planarization (chemical mechanical planarization, CMP) process. Other isolation structures such as field oxide, local oxidation of silicon (local oxidation of silicon, LOCOS), and/or other suitable structures may also be implemented as isolation structure 130. Alternatively, the isolation structure 130 may comprise a multi-layer structure, for example, having one or more thermal oxide liner layers.

The IC device 90 also includes a gate structure 140, the gate structure 140 being formed over the fin structures 120 and engaging the fin structures 120 on three sides in the channel region of each fin 120. In other words, the gate structures 140 each wrap around the plurality of fin structures 120. The gate structure 140 may be a dummy gate structure (e.g., containing an oxide gate dielectric and a polysilicon gate electrode), or these gate structures may be High-k metal gate (HKMG) structures containing a High-k gate dielectric and a metal gate electrode, where HKMG structures are formed by replacing the dummy gate structures. Although not depicted herein, the gate structure 140 may include additional layers of material, such as a junction layer, capping layer, other suitable layers, or a combination thereof, over the fin structure 120.

Referring to fig. 1A-1B, the plurality of fin structures 120 are each oriented longitudinally in the X-direction, and the plurality of gate structures 140 are each oriented longitudinally in the Y-direction, i.e., generally perpendicular to the fin structures 120. In many embodiments, IC device 90 includes additional features such as gate spacers disposed along sidewalls of gate structure 140, hard mask layer(s) disposed over gate structure 140, and many other features.

Fig. 1C illustrates a three-dimensional perspective view of an exemplary multi-channel all-around (GAA) device 150. GAA devices have a plurality of elongated nanostructure channels that can be implemented as nanotubes, nanoplates, or nanowires. For consistency and clarity, similar components in fig. 1C and 1A-1B are identically labeled. For example, an active region such as fin structure 120 rises vertically upward from substrate 110 in the Z-direction. The isolation structures 130 provide electrical separation between the fin structures 120. Gate structure 140 is positioned over fin structure 120 and over isolation structure 130. Layer 155 is positioned over gate structure 140 and gate spacer structure 160 is positioned on sidewalls of gate structure 140. Capping layer 165 is formed over fin structure 120 to protect fin structure 120 from oxidation during formation of isolation structure 130.

A plurality of nanostructures 170 are disposed on each of the fin structures 120. The nanostructures 170 may comprise nano-plates, nanotubes, or nanowires, or some other type of nanostructure that extends horizontally in the X-direction. The portion of the nanostructure 170 under the gate structure 140 may serve as a channel for the GAA device 150. Dielectric intra-spacers 175 may be disposed between nanostructures 170. In addition, although not illustrated for simplicity, each stack of nanostructures 170 may be circumferentially wrapped by a gate dielectric as well as a gate electrode. In the illustrated embodiment, portions of the nanostructure 170 outside of the gate structure 140 may serve as source/drain features for the GAA device 150. However, in some embodiments, continuous source/drain features may be epitaxially grown over portions of fin structure 120 outside of gate structure 140. Regardless, conductive source/drain contacts 180 may be formed over the source/drain features to provide electrical connectivity to these source/drain features. An interlayer dielectric (interlayer dielectric, ILD) 185 is formed over the isolation structure 130 and around the gate structure 140 and the source/drain contacts 180. The interlayer dielectric 185 may be referred to as an ILD0 layer. In some embodiments, the interlayer dielectric 185 may comprise silicon oxide, silicon nitride, or a low-k dielectric material.

The FinFET devices of fig. 1A-1B and the GAA device of fig. 1C may be utilized to implement electrical circuits having various functionalities, such as memory devices (e.g., static random access memory (static random access memory, SRAM) devices), logic circuits, input/output (I/O) devices, application specific integrated circuit (application specific integrated circuit, ASIC) devices, radio Frequency (RF) circuits, drivers, microcontrollers, central processing units (central processing unit, CPU), image sensors, and the like, as non-limiting examples.

Fig. 2 illustrates a schematic broken cross-sectional side view of an IC die 200 containing the FinFET or GAA transistors of fig. 1A-1C discussed above, in accordance with various embodiments of the present disclosure. IC die 200 has metallization components on both its front side and its back side. As discussed above, this configuration of the metallization elements may cause signals emitted by the IC die 200 (and intended to be detected by the detection tool) to be blocked by the metallization elements, which may interfere with the debug process. To address this problem, the present disclosure relates to a novel packaging process flow such that signals emitted by an IC die can be detected by a detection tool without obstruction, as will be discussed in more detail below with reference to fig. 3-9.

Still referring to fig. 2, IC die 200 in the illustrated embodiment is a Super Power Rail (SPR) wafer. In that regard, in conventional wafer structures, source/drain contacts and gate contacts of transistors on a substrate connect source/drain features of the transistors to interconnect structures on the front side of the substrate. As IC devices shrink in size, the close proximity between source and gate contacts may reduce the process window used to form these contacts and may increase the parasitic capacitance between these contacts. To mitigate these concerns, the SPR wafer may implement backside source/drain contacts through the substrate of the SPR wafer to contact the source/drain features, and power rails are formed on the backside of the substrate to contact the backside source/drain contacts. Because the implementation of SPR structures eases congestion of contacts, SPR wafers require modern solutions for performance improvement on power delivery networks (power delivery network, PDN) of advanced technology nodes.

Additional details of IC die 200 are now discussed below. The IC die 200 includes a plurality of transistors 210. The transistor 210 may be formed in or on the substrate 110 discussed above, and the substrate 110 may include an elemental semiconductor, a compound semiconductor, an alloy semiconductor, and/or other suitable materials. Transistor 210 may include a FinFET transistor as shown in fig. 1B-1C and/or a GAA transistor as shown in fig. 1C. Transistor 210 may include an active region, such as fin structure 120 or a stack of nanostructures 170 discussed above in connection with fig. 1A-1C. Transistor 210 also includes High-k metal gate (HKMG) structure 140 discussed above, high-k metal gate structure 140 may be wrapped partially around the active region (e.g., around the fin structure). As discussed above, HKMG structures may be formed by replacing dummy gate structures, and these HKMG structures may each include a high-k gate dielectric and a metal-containing gate electrode. Exemplary materials for the high-k gate dielectric include hafnium oxide, zirconium oxide, aluminum oxide, hafnium oxide-aluminum oxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, or combinations thereof. The metal-containing gate electrode may include one or more work function metal layers and one or more fill metal layers. The work function metal layer may be used to tune the work function of the respective transistor. Exemplary materials for the workfunction metal layer may include titanium nitride (TiN), titanium aluminide (TiAl), tantalum nitride (TaN), titanium carbide (Tic), tantalum carbide (TaC), tungsten carbide (WC), titanium aluminum nitride (TiAlN), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or combinations thereof. The filler metal layer may serve as the main conductive portion of the gate electrode layer. For reasons of simplicity, the details of transistor 210 are not illustrated in fig. 2 or in subsequent figures.

The substrate 110 has two opposite sides, e.g., side 230 and side 231. Side 230 may also be interchangeably referred to hereinafter as the front side of IC die 200, and side 231 may also be interchangeably referred to hereinafter as the back side of IC die 200. The multi-layer interconnect structure 220 is formed on a side 230 of the substrate 110. Interconnect structure 220 includes a plurality of patterned dielectric layers and interconnect conductive layers. These interconnect conductive layers provide the circuitry, input/output, and interconnections (e.g., wiring) between various doped features formed in the substrate 110. For example, the interconnect structure 220 may include a plurality of interconnect layers, also referred to as metal layers (e.g., M1, M2, M3, etc.). Each of the interconnect layers includes a plurality of metal lines, such as metal line 240. The interconnect structure 220 may also include a plurality of conductive pillars 245 that electrically couple the various metal lines 240 together. The metal wiring 240 and the conductive posts 245 may contain a conductive material such as aluminum, copper, aluminum alloy, copper alloy, aluminum/silicon/copper alloy, titanium nitride, tantalum nitride, tungsten, cobalt, ruthenium, metal silicide, or a combination thereof. Interconnect structure 220 also includes an interlayer dielectric (interlayer dielectric, ILD) 250, interlayer dielectric 250 providing electrical and physical isolation between interconnect layers. The interlayer dielectric 250 may include a dielectric material such as an oxide material or a low-k dielectric. The metal wiring 240 and the conductive post 245 can be said to be embedded in the interlayer dielectric 250.

A bonding layer 260 is disposed over the interconnect structure 220. In some embodiments, the bonding layer 260 includes an oxide material. The bonding layer 260 bonds the carrier substrate 270 to the rest of the IC die 200. For example, the interconnect structure 220 is bonded to the carrier substrate 270 through the bonding layer 260. In some embodiments, the carrier substrate 270 comprises bulk silicon. In other embodiments, carrier substrate 270 comprises another suitable material that provides sufficient rigidity and/or mechanical support for other portions of IC die 200.

Although the interconnect structure 220, the bonding layer 260, and the carrier substrate 270 are positioned on the side 230 (e.g., front side) of the substrate 110, a power delivery network (power delivery network, PDN) 280 is formed on the side 231 (e.g., back side) of the substrate 110. PDN 280 is the structure that delivers power and ground voltages from conductive pad locations to the various components of IC die 200, such as transistor 210. In some embodiments, the PDN 280 includes multiple layers, where each layer includes one or more rails 285, such as a power rail and/or a ground rail. The power rail or ground rail may be in the form of a metal wire. The various layers of the PDN 280 may be electrically interconnected together by conductive pillars. Electrical connectivity to the PDN 280 (and the rest of the IC die 200) may be obtained through conductive bumps 290 (e.g., solder balls) positioned on the sides 231 of the PDN 280.

Because PDN 280 includes metal wiring and conductive pillars, such as interconnect structure 220, IC die 200 can be said to have metallization elements formed on both its front side 230 and its back side 231. In a conventional IC die having no PDN implemented on its backside (i.e., similar herein to backside 231), signals transmitted through the IC die may be detected by a detection tool placed on the backside of the IC die when the IC die is being debug, without obstructions or interference from metallization components. However, for the IC die 200 illustrated herein, the metal wiring and/or conductive pillars of the pdn 280 may at least partially block transmission of signals emitted through the IC die 200. To address this issue, the present disclosure relates to a packaging process in which an opening or trench is formed on the backside 231, the opening or trench extending at least partially through the PDN 280. This opening allows signals emitted by the IC die 200 to reach the signal detection tool disposed on the backside 231 without being obstructed, as discussed in more detail below.

Fig. 3-8 illustrate schematic broken side views of an IC die 200 incorporating other devices at various stages of a packaging/testing process, according to an embodiment of the present disclosure. Referring now to fig. 3, an IC package assembly 300, which may also be referred to as an IC die, includes an IC die 200 and a substrate 310. In some embodiments, the substrate 310 includes a printed circuit board (printed circuit board, PCB) that may include multiple layers each for routing electrical signals. For example, the PCB may include a plurality of metal wires in each of the layers, as well as conductive posts interconnecting metals from different layers. The PCB may also include dielectric materials that provide electrical and physical isolation for the metal wiring and conductive posts.

IC die 200 is bonded to substrate 310 through backside 231. For example, conductive bumps 290 and molding material 320 (e.g., organic material) are bonded between IC die 200 and substrate 310. Conductive bumps 290 allow electrical signals to be transmitted between IC die 200 and substrate 310, while molding material 320 provides electrical isolation and physical protection for conductive bumps 290 and other components on the surfaces of IC die 200 and substrate 310. Thus, various layers of the PCB may be utilized to perform additional electrical routing for the IC die 200. In some embodiments, the substrate 310 includes electrical routing components, but no active circuitry (e.g., no transistors). In some other embodiments, the substrate 310 may include additional circuitry that may provide the same functionality as the circuitry on the IC die 200 or may provide different functionality relative to the circuitry on the IC die 200. It should be noted that the plurality of conductive bumps 330 may also be implemented on the backside 231 of the substrate 310. Conductive bumps 330 are electrically coupled to the internal components of substrate 310 such that electrical access to substrate 310 (and, by extension, to IC die 200) is at least partially available through conductive bumps 330.

In some embodiments, IC package assembly 300 may be a device ready for sale to a customer. In other words, a customer may purchase the IC package assembly 300 from a manufacturer of the IC package assembly 300 and implement the IC package assembly 300 on modern electronic devices such as desktop or laptop computers, mobile phones, televisions, radios, automobiles, satellite positioning devices, home appliances, and the like. However, sometimes, copies of the IC package assembly 300 may experience a failure or fault condition during actual use or during testing before or after the IC package assembly 300 is shipped to a customer. This failed or erroneous copy of the IC package assembly 300 may then be tested as part of the debug process to identify the cause and/or source of the failure. In this debug process, it may be desirable to detect the signal emitted from the IC die 200 from the backside 231. To ensure that the metallization features of the PDN 280 do not block or interfere with the emission of signals from the IC die 200, an opening or trench will be formed by the backside 231, wherein the opening or trench extends at least partially through the PDN 280 to expose the target region of the transistor 210. The signals emitted from the target region of the transistor 210 may then be collected without obstructions from the PDN 280 by a signal detection tool placed on the backside 231, as discussed in more detail below.

Referring now to fig. 4, ic package assembly 300 is bonded to device-under-test (DUT) board 350 by bonding process (attachment process) 360. The DUT board 350 may be a first portion of an automated test equipment (automated test equipment, ATE) tool that is used to test IC wafers such as the IC package assembly 300 (or IC die 200). One or more layers of metallization components, such as metal wiring and/or conductive posts, may be included in the DUT board 350 in order to provide electrical routing. The DUT board 350 may also include a plurality of conductive bumps 370 (e.g., solder balls). The conductive bumps 370 are electrically connected to various metallization components in the DUT board 350. As part of the bonding process 360, a subset of the conductive bumps 370 may be connected to the conductive bumps 330 of the IC package assembly 300. In this way, electrical access to the internal electrical circuitry of the IC die 200 may be obtained through the DUT board 350. The interface between the IC package assembly 300 and the DUT board 350 may be covered by a suitable material 380 to protect the surfaces of the IC package assembly 300 and the DUT board 350 from external sources of contamination, such as dust particles or moisture. In some embodiments, the material 380 may include a molding compound, such as an organic material.

Referring now to fig. 5, IC package assembly 300 and DUT board 350 to which IC package assembly 300 is attached are flipped vertically such that front side 230 and back side 231 are upside down from front side 230 and back side 231 shown in fig. 4. In other words, front side 230 faces downward in fig. 5, and back side 231 faces upward in fig. 5. The trench formation process 400 is then performed on the IC package assembly 300 and the DUT board 350 to form a trench 410 (also interchangeably referred to as an opening 410). In some embodiments, the trench formation process 400 involves drilling the trench 410 using a small mechanical drill bit. In some embodiments, the diameter of the mechanical drill may be in the range of several micrometers, or tens of micrometers.

The trench 410 extends vertically (from the back side 231 toward the front side 230) through the DUT board 350, through the substrate 310, and partially through the IC die 200. Although not readily apparent from fig. 5, which is not drawn to scale, trench 410 has a high aspect ratio, which is the ratio of the depth 420 of the trench to its width 430 or 440. For example, depth 420 may be measured as the vertical dimension from the topmost surface of DUT board 350 to the exposed upper surface of IC die 200. In some embodiments, the depth 420 may be in a range between about 2 millimeters (mm) and about 4 mm. Width 430 may be measured as a horizontal or lateral dimension of the uppermost portion of trench 410. Width 440 may be measured as the horizontal or lateral dimension of the bottommost portion of trench 410 (or window just at the exposed portion of IC die 200). In some embodiments, width 430 may be the maximum width of groove 410 and width 440 may be the minimum width of groove 410.

Wherever the width of the trench 410 is measured, the width 430 is substantially less than the depth 420 of the trench 410. In some embodiments, width 430 is in a range between about 0.5 microns and about 3 microns, and width 440 is in a range between about 0.05 microns and about 0.3 microns. Due to the difference in size between the depth 420 and the width 430, the aspect ratio of the trench 410 may be large. In some embodiments, the aspect ratio (e.g., depth 420 to width 430, or depth 420 to width 440) of the trench 410 is in a range between about 1000:1 and about 2000:1.

As shown in fig. 5, a portion of IC die 200 is removed during trench formation process 400. The removed portion of the IC die 200 comes from the PDN 280 discussed above. This is more clearly illustrated in fig. 6, which again shows a cross-sectional side view of IC die 200, but with trench 410 already formed. The trench 410 extends vertically from the back side 231 toward the front side 230 through the PDN 280 and exposes some of the transistor 210. It should be appreciated that some of the metallization components (e.g., metal wiring or conductive pillars) of the PDN 280 may be at least partially removed by the formation of the trench 410. The removal of these metallization elements allows electrical or optical signals generated by transistor 210 (exposed by trench 410) to be freely emitted through trench 410 and detected by a detection tool as part of the debug process. It should be noted that while the illustrated embodiment of fig. 6 shows the trench 410 as extending vertically entirely through the PDN 280, this may not be the case in other embodiments. For example, in some alternative embodiments, the trench 410 may extend partially through the PDN 280 and alternatively expose one or more of the metallization components of the PDN 280.

It should also be appreciated that the removal of metallization components of the PDN 280 herein also does not substantially interfere with the functionality of the PDN 280, as the metallization components in the PDN 280 may be built-in with a degree of redundancy. In other words, the power rails and/or ground connections can be serviced by multiple metallization components of the PDN 280. The removal of a subset of these metallization components of the PDN does not substantially disrupt the functionality of the remaining metallization components that also act as power rails or ground connections, provided that a sufficient number of the remaining metallization components can properly back up the functionality of the removed metallization components.

Referring now to fig. 7, after the trenches 410 have been formed in the IC package assembly 300 and the DUT board 350, a coupling process 480 is performed to couple the socket 500 to the IC package assembly 300 and the DUT board 350. In some embodiments, socket 500 may be a second portion of an ATE tool (of which DUT board 350 is a part) that is used to test an IC wafer, such as IC die 200. In other words, socket 500 works in conjunction with DUT board 350 to facilitate testing of IC wafers such as IC die 200. Socket 500 is placed on front side 230 of IC die 200, but no physical contact is required between socket 500 and IC die 200. For example, in some embodiments, the space between socket 500 and IC die 200 may be filled with a buffer material to prevent potential damage to IC die 200. In other embodiments, the spacing between the socket 500 and the IC die 200 may be an air gap.

Socket 500 may provide electrical test signals that, when received by IC die 200, will force portions of IC die 200 to undergo various electrical operations. These electrical operations may include the intended electrical operations that should be performed by the IC die 200 during normal operation of the IC die 200. In some embodiments, the receptacle 500 may provide electrical signals that simulate signals generated by a controller or microcontroller. In any event, the test signal provided through socket 500 may force a target area of IC die 200 (e.g., the area exposed by trench 410) to perform certain operations as part of the debug process. As discussed above, the transistor 210 from the target region of the IC die 200 may be responsive to being forced to operate in a manner to transmit a signal based on a received test signal. The transmitted signal may propagate through the trench 410 without being obstructed by the metallization components of the PDN 280 of the IC die 200, which allows the transmitted signal to be detected by a detection tool (discussed below with reference to fig. 8).

In order for the test signals provided through the socket 500 to reach the intended targets of those test signals (e.g., various transistors from the exposed areas of the IC die 200), a plurality of conductive structures 510 are implemented on the backside 231 of the socket 500 to transmit or relay the test signals. In some embodiments, the conductive structure 510 may be a vertically collapsible conductive connector. In some embodiments, the conductive structure 510 may comprise a single pin spring connector. As shown in fig. 7, each of the conductive structures 510 may mate (or align) with a respective one of the conductive bumps 370 positioned on the front side 230 of the DUT board 350. After physical and electrical contact with the conductive bumps 370, the conductive structures 510 may transmit test signals provided by the socket 500 to the DUT board 350 through the conductive bumps 370. The DUT board then routes the test signals to the substrate 310, which in turn routes the test signals to the target transistors of the IC die 200.

It should be appreciated that the entities of the IC die 200, substrate 310, DUT board 350, and socket 500 are configured as one of the unique features (and inherent results) of the processes performed by the present disclosure. For example, the fact that the DUT board 350 and socket 500 are positioned on opposite sides (e.g., back side 231 and front side 230, respectively) of the IC die 200 is not found in conventional test structure configurations. However, this relative deployment between the DUT board 350 and the socket 500 also increases the distance between the DUT board 350 and the socket 500. To account for this increased distance, the present disclosure configures the height 520 (or vertical dimension) of the conductive structures 510 to be sufficiently long to reach the conductive bumps 370 positioned on the DUT board 350. In other words, the conductive structure 510 herein is substantially elongated as compared to an equivalent conductive structure implemented on a conventional socket. For example, however, the height of the equivalent conductive structures on conventional sockets may range between about 0.2 millimeters (mm) and about 0.3mm, and the height 520 may be at least 1.5 times longer and may range between about 0.38mm and about 0.48 mm.

The increased height 520 may also be reflected in various ratios to the height of one or more other components of the IC die 200. In some embodiments, the height 530 (or thickness) of the IC die 200 is in a range between about 10 microns and about 50 microns, and the ratio of the height 520 to the height 530 may be in a range between about 10:1 and about 20:1. In some embodiments, the height 540 (or thickness) of the substrate 310 is in a range between about 800 microns and about 1200 microns, and the ratio of the height 520 to the height 540 may be in a range between about 0.38:1 and about 0.48:1. In some embodiments, the height 550 of the IC package assembly 300 (e.g., the combined height of the IC die 200, the substrate 310, and the gap therebetween) is in a range between about 1.26mm and about 1.4mm, and the ratio of the height 520 to the height 550 may be in a range between about 0.3:1 and about 0.35:1. The corresponding ratios for conventional structures will be substantially lower than the values provided herein (e.g., at least 33% lower than these values). In addition, the relatively high height 520 enables physical and electrical coupling between the DUT board 350 and the socket 500 even though the IC die 200 is disposed between the DUT board 350 and the socket 500.

Referring now to fig. 8, a test process 600 is performed using the tools discussed above (e.g., DUT board 350 and socket 500) and a detection tool 610. The detection tool 610 may be used to detect a signal 620 (the signal 620 may be an electrical signal or an optical signal) transmitted through the IC die 200, wherein the signal 620 is transmitted in response to the IC die 200 being forced into a particular mode of operation after receiving a test signal from the socket 500. In some embodiments, the detection tool 610 comprises an electron beam (e-beam) machine.

The detection tool 610 (and/or ATE tool) may analyze the signal 620 and convert the signal 620 into a plot, a graph, an image, a plurality of numbers, or another suitable analysis result. Based on the analysis results generated by the detection tool 610 (or by the ATE tool), a machine or engineer/technician may identify the portion of the circuitry of the IC die 200 that caused the failure or failure. For example, based on the analysis results, a determination may be made that two transistors in region a of IC die 200 that should be electrically isolated are electrically shorted together in some manner. As another example, based on the analysis results, a determination may be made that a transistor in region B of IC die 200 is causing too much, or insufficient, current (e.g., greater than or less than a predetermined threshold). As yet another example, based on the analysis results, a determination may be made that microelectronic components (e.g., source/drain or gate) in region C of IC die 200 are missing or structurally defective due to manufacturing-related issues. It should be understood that these faults discussed above are merely examples and are not intended to be limiting.

Once the faults or their causes/sources are identified, they may be communicated to appropriate personnel (and/or machines) so that the manufacturing process of the IC wafer may be adjusted to reduce or eliminate the likelihood of future occurrence of such faults. Thus, device performance and/or yield may be improved. Furthermore, while the presence of metallization components on both the front side 230 and the back side 231 of the IC die 200 herein may complicate debugging of the IC die 200, the problems presented are adequately addressed by the solutions of the present disclosure discussed above. For example, by forming trenches that partially remove metallization components in the PDN 280 of the IC die 200, signals emitted by the IC die 200 during the test process 600 may be collected by the detection tool 610 without interference from the metallization components. In addition, as an inherent consequence of the physical configuration utilized to mount the IC die 200 to undergo the test process 600, the conductive structures 510 are also lengthened to account for the larger spacing between the DUT board 350 and the socket 500.

It should also be appreciated that while the metallization components of the PDN 280 have been used as exemplary materials that can be removed to prevent them from blocking the propagation of signals emitted through the IC wafer during the debug process, similar concepts may also be applied to other types of optically opaque and/or non-conductive materials. In other words, another type of IC wafer may include optically opaque and/or non-conductive material on both sides. To facilitate testing of an IC wafer as part of the debug process of such an IC wafer, the opening may be formed to remove a portion of the optically opaque or non-conductive material from one side of the IC wafer so that signals emitted by the IC wafer during testing thereof are still freely detectable through the opening by the detection tool.

To further illustrate various aspects of the present disclosure, a top view (also referred to as a plan view) of various components of the present disclosure is illustrated in fig. 9. In more detail, the top view of fig. 9 is obtained by looking down from the back side 231 towards the front side 230. Fig. 9 illustrates an IC die 200, a substrate 310, a DUT board 350, a socket 500, and a conductive structure 510 (e.g., in the form of a single pin spring connector), rather than part of a detection tool 610.

In the embodiment shown in fig. 9, trench 410 is shaped as a rectangle or square, however, this shape is not intended to be limiting, and trench 410 may be used in other embodiments to have other shapes, such as a circle, oval, triangle, or any shape, it should also be appreciated that the location of trench 410 is not fixed, but may be moved in various embodiments, for example, the embodiment of fig. 9 may configure trench 410 to be positioned near the center of IC die 200 because that area of the IC wafer where the failed circuitry is located is initially determined to be the area of the IC wafer where the failed circuitry is located, however, if the upper left corner area of IC die 200 is suspected to be the area of the IC wafer where the failed circuitry is contained, trench 410 may be formed at or near the upper left corner area of the wafer such that the transistor of the IC die 200 may pass through the lower left corner of the failed circuitry in the detection tool 610.

The IC die 200 (or IC package assembly 300) may be implemented in a variety of IC applications, including Memory devices such as Static Random-Access Memory (SRAM) devices. In that regard, fig. 10 illustrates an exemplary circuit schematic for a single port SRAM cell (e.g., a 1-bit SRAM cell) 800 in which the IC die 200 may be implemented. The single port SRAM cell 800 includes pull-up transistors PU1, PU2; pull-down transistors PD1, PD2; and pass gate transistors PG1, PG2. As shown in the circuit diagram, the transistors PU1 and PU2 are p-type transistors, and the transistors PG1, PG2, PD1, and PD2 are n-type transistors. According to various aspects of the present disclosure, the PG1, PG2, PD1, and PD2 transistors are implemented with thinner spacers compared to the PU1 and PU2 transistors. Because SRAM cell 800 includes six transistors in the illustrated embodiment, the SRAM cell may also be referred to as a 6TSRAM cell.

The drains of pull-up transistor PU1 and pull-down transistor PD1 are coupled together, and the drains of pull-up transistor PU2 and pull-down transistor PD2 are coupled together. Transistors PU1 and PD1 are cross-coupled with transistors PU2 and PD2 to form a first data latch. The gates of transistors PU2 and PD2 are coupled together and to the drains of transistors PU1 and PD1 to form a first storage node SN1, and the gates of transistors PU1 and PD1 are coupled together and to the drains of transistors PU2 and PD2 to form a complementary first storage node SNB1. The sources of pull-up transistors PU1 and PU2 are coupled to a supply voltage Vcc (also referred to as Vdd), and the sources of pull-down transistors PD1 and PD2 are coupled to a voltage Vss, which may be electrical ground in some embodiments.

The first storage node SN1 of the first data latch is coupled to the bit line BL through the pass gate transistor PG1, and the complementary first storage node SNB1 is coupled to the complementary bit line BLB through the pass gate transistor PG 2. The first storage node SN1 and the complementary first storage node SNB1 are complementary nodes that are typically at opposite logic levels (logic high or logic low). The gates of pass gate transistors PG1 and PG2 are coupled to word line WL. SRAM devices such as SRAM cell 800 may be implemented using "planar" transistor devices with FinFET devices and/or with GAA devices.

Fig. 11 illustrates an integrated circuit manufacturing system 900, which integrated circuit manufacturing system 900 may be used to manufacture IC die 200 and/or IC package assembly 300 of the present disclosure, in accordance with an embodiment of the present disclosure. The manufacturing system 900 includes a plurality of entities 902, 904, 906, 908, 910, 912, 914, 916 … … N connected by a communication network 918. The network 918 may be a single network or may be a variety of different networks, such as an intranet and the Internet, and may include both wired and wireless communication channels.

In one embodiment, entity 902 represents a service system for manufacturing collaboration; entity 904 represents a user, such as a product engineer monitoring a product of interest; entity 906 represents an engineer, such as a process engineer to control a process and related recipes, or an equipment engineer to monitor or tune the conditions and settings of a process tool; entity 908 represents a measurement tool for IC testing and metrology; entity 910 represents a semiconductor processing tool, such as an EUV tool used to perform a lithography process to define gate spacers of an SRAM device; entity 912 represents a virtual measurement module associated with processing tool 910; entity 914 represents an advanced process control module associated with processing tool 910 and yet other processing tools; and entity 916 represents a sampling module associated with processing tool 910.

Each entity may interact with other entities and may provide integrated circuit manufacturing, process control, and/or computing capabilities to other entities and/or receive such capabilities from other entities. Each entity may also include one or more computer systems for performing computations and for automating the operations. For example, the advanced process control module of entity 914 can comprise a plurality of computer hardware having software instructions encoded therein. Computer hardware may include hard drives, flash drives, compact disk-read Only Memory (CD-ROM), RAM Memory, display devices (e.g., monitors), input/output devices (e.g., mice and keyboards). The software instructions may be written in any suitable programming language and may be designed to achieve a particular task.

The integrated circuit fabrication system 900 enables interactions between entities for purposes of integrated circuit (integrated circuit, IC) fabrication and advanced process control for IC fabrication. In one embodiment, advanced process control includes adjusting process conditions, settings, and/or recipes for a processing tool of an associated wafer based on the measurements.

In another embodiment, measurements are measured from a subset of the processed wafers according to an optimal sampling rate determined based on process quality and/or product quality. In yet another embodiment, field and point metrology measurements are taken from selected fields and points of a subset of processed wafers based upon an optimal sampling field/point determined based upon various characteristics of process quality and/or product quality.

One of the capabilities provided by the IC fabrication system 900 may enable collaboration and information access in areas such as design, engineering, and processing, measurement, and advanced process control. Another capability provided by the IC fabrication system 900 may integrate the system between facilities, such as between a measurement tool and a processing tool. This integration enables facilities to coordinate activities of those facilities. For example, integrating the metrology tools and the processing tools may enable more efficient incorporation of manufacturing information into a manufacturing process or APC module, and may enable wafer data from in-line or in-situ measurements with the metrology tools integrated into the associated processing tools.

Fig. 12 is a flow chart illustrating a method 1000 of packaging and testing IC package components in accordance with various aspects of the present disclosure. The method 1000 includes a step 1010 for providing an integrated circuit (integrated circuit, IC) package assembly including an IC die. The IC die includes a semiconductor substrate, a first metallization structure disposed on a first side of the semiconductor substrate, and a second metallization structure disposed on a second side of the semiconductor substrate opposite the first side. The IC package assembly further includes a printed circuit board (printed circuit board, PCB) substrate bonded to the IC die from the second side.

The method 1000 includes a step 1020 of coupling an IC package assembly to a device-under-test (DUT) board. The DUT board is coupled to the IC package assembly through the PCB substrate.

Method 1000 includes a step 1030 for forming a trench that extends through the DUT board, through the PCB substrate, and partially into the IC die. The groove extends from the second side toward the first side. In some embodiments, step 1030 is performed such that the trench extends at least partially through the second metallization structure. In some embodiments, the first metallization structure comprises a plurality of metal layers and the second metallization structure comprises a power delivery network (power delivery network, PDN).

Method 1000 includes step 1040 for coupling a socket of a test tool to a DUT board after trench formation. The coupling of the sockets is performed such that after the socket coupling, the IC package assembly is located between the DUT board and the socket.

It should be appreciated that additional processes may be performed before, during, or after steps 1010-1040 of method 1000. For example, in some embodiments, the method 1000 may further include the step of applying test signals generated by a test tool through the socket and applying these test signals to the IC package assembly. Test signals are routed electrically through the DUT board and through the PCB substrate to the IC die. As another example, the method 1000 may further include the step of detecting, by a signal detection tool disposed on the second side of the IC package assembly, an electrical or optical signal emitted by the IC die in response to the applied test signal. As yet another example, the method 1000 may further include the step of analyzing one or more fault conditions of the IC package components based on the detected electrical signals or the detected optical signals. In some embodiments, the test signals are further electrically routed to the IC die through a plurality of retractable pins positioned between the socket and the DUT board. In some embodiments, the DUT board includes a plurality of conductive bumps. Each of the retractable pins is in direct physical contact with a respective one of the conductive bumps when the test signal is routed electrically to the IC die. In some embodiments, a ratio of a height of each of the retractable pins to a height of the IC package assembly is in a range between about 0.3:1 and about 0.35:1. In some embodiments, detecting comprises detecting an electrical signal or an optical signal by an electron beam tool such as a signal detection tool. Other steps may also be performed, but these other steps are not discussed in detail herein for simplicity reasons.

The present disclosure provides advantages over conventional devices. However, it will be appreciated that not all advantages have been discussed herein, that different embodiments may provide different advantages, and that no particular advantage is required for any embodiment. One advantage is that the present disclosure facilitates a debug process despite the presence of metallization components on both the front side and the back side of the IC device. In more detail, conventional IC devices may have metallization structures on the front side instead of the back side. Thus, a signal detection tool may be placed on the backside of the IC device to detect signals emitted by the IC device under test. However, this approach is more difficult for the IC devices herein because the IC devices may have an interconnect structure (including multiple metal layers) formed on their front sides and a power delivery network (power delivery network, PDN) formed on their back sides (e.g., containing power and ground rails in the form of metal wiring). During the debug process, an automated test equipment (automated testing equipment, ATE) tool may feed test signals to the IC device so that the IC device will operate in a predetermined manner and thus generate electrical or optical signals. These signals are intended to be detected by signal detection means placed at the back side of the IC device. To ensure that the metallization components of the PDN structure do not obstruct the transmission of these electrical or optical signals, openings or trenches extending from the back side of the IC device into the PDN are formed so that the electrical or optical signals propagate out of the openings or trenches. In more detail, the IC device may be an IC package assembly including an IC die and a PCB substrate bonded to the IC die. The IC package assembly is coupled between the DUT board and the socket of the test tool. The openings or trenches extend from the backside through the DUT board and PCB substrate (and at least partially through the IC die) such that electrical or optical signals emitted through the IC die can propagate out of the openings or trenches and reach the signal detection tool unobstructed. Based on analysis of the detected signals, the source of the failure that caused the performance problem of the IC device can be accurately and quickly identified. Other advantages may include compatibility with existing packaging/testing processes and ease of implementation and low cost.

The advanced lithography processes, methods, and materials described above may be used in a number of applications, including in IC devices using fin field effect transistors (fin-type field effect transistor, finFET). For example, the fins may be patterned to create relatively tight spacing between features, which the above disclosure is well suited for. In addition, spacers used in forming fins of finfets also known as mandrels may be processed in accordance with the above disclosure. It should also be appreciated that the various aspects of the present disclosure discussed above may be applied to multi-channel devices such as Gate-All-Around (GAA) devices. To the extent the present disclosure relates to fin structures or FinFET devices, such discussion may be equally applicable to GAA devices.

One aspect of the present disclosure relates to an apparatus. The socket of the test tool is used for providing a test signal. A device-under-test (DUT) board is used to provide electrical routing. An integrated circuit (integrated circuit, IC) die is disposed between the socket and the DUT board. Test signals are routed electrically through the DUT board to the IC die. The IC die includes a substrate in which a plurality of transistors are formed. The first structure contains a plurality of first metallization elements. The second structure contains a plurality of second metallization elements. The first structure is disposed over the first side of the substrate. The second structure is disposed on a second side of the substrate opposite the first side.

In some embodiments, the device under test board is disposed between a signal detection tool and the integrated circuit die; the integrated circuit die emits an electrical or optical signal in response to the test signal fed through the socket; and the signal detection tool is used for detecting an electric signal or an optical signal emitted by the integrated circuit die; analyzing the detected electrical signal or the detected optical signal; and identifying one or more regions of the integrated circuit die that are experiencing or have experienced one or more fault conditions based on an analysis of the detected electrical signal or the detected optical signal.

In some embodiments, the electrical or optical signal is propagated through the trench before reaching the signal detection tool.

In some embodiments, a trench extends through the device under test board and partially into the integrated circuit die from the second side.

In some embodiments, the second metallization element is an element of a power supply network, and wherein the trench extends vertically from the second side into the power supply network.

In some embodiments, the apparatus further comprises a printed circuit board substrate bonded between the integrated circuit die and the device under test board.

In some embodiments, the apparatus further comprises a plurality of single-pin spring connectors positioned on the socket, wherein the single-pin spring connectors are used to electrically route test signals from the socket to the device under test board.

In some embodiments, a ratio of a height of each of the single pin spring connectors to a height of the integrated circuit die is in a range between about 10:1 and about 20:1.

Another aspect of the present disclosure relates to a system. An integrated circuit (integrated circuit, IC) package assembly includes an IC die and a printed circuit board (printed circuit board, PCB) substrate bonded to the IC die. The socket of the test tool is disposed over the first side of the IC package assembly. A device-under-test (DUT) board is disposed over the second side of the IC package assembly. The DUT board is used to route test signals provided by the test tool from the socket to the IC package assembly. The IC package assembly generates an electrical signal or an optical signal in response to receiving the test signal. The trench extends through the DUT board, through the PCB substrate, and partially into the IC die from the second side. The signal detection tool is disposed on the second side of the IC package assembly. The signal detection tool is used for detecting an electrical signal or an optical signal generated by the IC package. The electrical or optical signal propagates through the trench towards the second side.

In some embodiments, an integrated circuit die includes a semiconductor substrate in which a plurality of transistors are formed; an interconnect structure disposed over the first side of the semiconductor substrate, wherein the interconnect structure contains a plurality of first metallization elements; and a power delivery network disposed over the second side of the semiconductor substrate, wherein the power delivery network contains a plurality of second metallization elements, and wherein the trench extends from the second side at least partially through the power delivery network.

In some embodiments, the receptacle includes a plurality of retractable conductive connectors; the device under test board comprises a plurality of conductive bumps; each of the retractable conductive connectors is electrically coupled to a respective one of a first subset of the conductive bumps; and the printed circuit board substrate is electrically coupled to a second subset of the conductive bumps.

In some embodiments, each of the collapsible conductive connectors has a first height; the integrated circuit package assembly has a second height; and a ratio of the first height to the second height is in a range between about 0.3:1 and about 0.35:1.

Yet another aspect of the present disclosure relates to a method. An integrated circuit (integrated circuit, IC) package assembly is provided. An integrated circuit package includes an IC die. The IC die includes a semiconductor substrate, a first metallization structure disposed on a first side of the semiconductor substrate, and a second metallization structure disposed on a second side of the semiconductor substrate opposite the first side. The IC package assembly further includes a printed circuit board (printed circuit board, PCB) substrate bonded to the IC die from the second side. The IC package assembly is coupled to a device-under-test (DUT) board. The DUT board is coupled to the IC package assembly through the PCB substrate. A trench is formed that extends through the DUT board, through the PCB substrate, and partially into the IC die. The groove extends from the second side toward the first side. After the trench is formed, a socket of the test tool is coupled to the DUT board. The coupling of the sockets is performed such that after the socket coupling, the IC package assembly is positioned between the DUT board and the socket.

In some embodiments, the method further comprises the steps of applying test signals generated by the test tool through the socket and applying the test signals to the integrated circuit package assembly, wherein the test signals are routed electrically through the device under test board and through the printed circuit board substrate to the integrated circuit die; detecting, by a signal detection tool disposed over the second side of the integrated circuit package assembly, electrical or optical signals emitted through the integrated circuit die in response to the applied test signals; and analyzing one or more fault conditions of the integrated circuit package assembly based on the detected electrical signal or the detected optical signal.

In some embodiments, the test signals are further electrically routed to the integrated circuit die through a plurality of retractable pins positioned between the socket and the device under test board.

In some embodiments, the device under test board includes a plurality of conductive bumps; and each of the retractable pins is in direct physical contact with a respective one of the conductive bumps when the test signal is routed electrically to the integrated circuit die.

In some embodiments, a ratio of a height of each of the retractable pins to a height of the integrated circuit package assembly is in a range between about 0.3:1 and about 0.35:1.

In some embodiments, the detecting includes detecting the electrical signal or the optical signal by an electron beam tool as the signal detecting tool.

In some embodiments, forming the trench therein is performed such that the trench extends at least partially through the second metallization structure.

In some embodiments, wherein the first metallization structure comprises a plurality of metal layers; and the second metallization structure includes a power supply network.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the detailed description that follows. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A test apparatus, comprising:

a socket of a test tool, the socket being used for providing test signals;

A device under test board for providing electrical routing; and

an integrated circuit die disposed between the socket and the device under test board, wherein the test signals are routed electrically through the device under test board to the integrated circuit die, and wherein the integrated circuit die comprises a substrate in which a plurality of transistors are formed, a first structure comprising a plurality of first metallization elements, and a second structure comprising a plurality of second metallization elements, wherein the first structure is disposed on a first side of the substrate, and wherein the second structure is disposed on a second side of the substrate opposite the first side.

2. The test apparatus of claim 1, wherein:

the device under test board is disposed between a signal detection tool and the integrated circuit die;

the integrated circuit die emits a plurality of electrical or optical signals in response to the test signals fed through the socket; and

the signal detection tool is used for:

detecting the electrical signal or the optical signal emitted by the integrated circuit die;

analyzing the detected electrical signal or the detected optical signal; and

One or more regions of the integrated circuit die experiencing or having experienced one or more fault conditions are identified based on an analysis of the detected electrical signal or the detected optical signal.

3. The test apparatus of claim 2, wherein a trench extends through the device under test board and partially into the integrated circuit die from the second side.

4. The test apparatus of claim 1, further comprising a printed circuit board substrate bonded between the integrated circuit die and the device under test board.

5. A test system, comprising:

an integrated circuit package assembly including an integrated circuit die and a printed circuit board substrate bonded to the integrated circuit die;

a socket of a test tool, the socket being disposed on a first side of the integrated circuit package assembly;

a device under test board disposed on a second side of the integrated circuit package assembly, wherein the device under test board is configured to route test signals provided by the test tool from the socket to the integrated circuit package assembly, wherein the integrated circuit package assembly generates electrical or optical signals in response to receiving the test signals, and wherein a trench extends through the device under test board, through the printed circuit board substrate, and partially into the integrated circuit die from the second side; and

A signal detection tool disposed on the second side of the integrated circuit package assembly, wherein the signal detection tool is configured to detect the electrical signal or the optical signal generated by the integrated circuit package, and wherein the electrical signal or the optical signal propagates through the trench toward the second side.

6. The test system of claim 5, wherein the integrated circuit die comprises:

a semiconductor substrate in which a plurality of transistors are formed;

an interconnect structure disposed over the first side of the semiconductor substrate, wherein the interconnect structure comprises a plurality of first metallization elements; and

a power delivery network disposed over the second side of the semiconductor substrate, wherein the power delivery network contains a plurality of second metallization elements, and wherein the trench extends from the second side at least partially through the power delivery network.

7. The test system of claim 5, wherein:

the receptacle includes a plurality of retractable conductive connectors;

the device under test board includes a plurality of conductive bumps;

each of the plurality of retractable conductive connectors is electrically coupled to a respective one of a first subset of the plurality of conductive bumps; and

The printed circuit board substrate is electrically coupled to a second subset of the plurality of conductive bumps.

8. A method of testing comprising the steps of:

providing an integrated circuit package assembly comprising an integrated circuit die, wherein the integrated circuit die comprises a semiconductor substrate, a first metallization structure disposed on a first side of the semiconductor substrate, and a second metallization structure disposed on a second side of the semiconductor substrate opposite the first side, and wherein the integrated circuit package assembly further comprises a printed circuit board substrate bonded to the integrated circuit die from the second side;

coupling the integrated circuit package assembly to a device under test board, wherein the device under test board is coupled to the integrated circuit package assembly through the printed circuit board substrate;

forming a trench extending through the device under test board, through the printed circuit board substrate, and partially into the integrated circuit die, wherein the trench extends from the second side toward the first side; and

after the trench is formed, a socket of a test tool is coupled to the device under test board, wherein the coupling of the socket is performed such that the integrated circuit package assembly is positioned between the device under test board and the socket after the socket is coupled.

9. The method of testing of claim 8, further comprising the steps of:

applying test signals generated by the test tool through the socket and applying the test signals to the integrated circuit package assembly, wherein the test signals are electrically routed through the device under test board and through the printed circuit board substrate to the integrated circuit die;

detecting electrical or optical signals emitted through the integrated circuit die by a signal detection tool disposed over the second side of the integrated circuit package assembly in response to the application of the test signals; and

one or more fault conditions of the integrated circuit package assembly are analyzed based on the detected electrical signal or the detected optical signal.

10. The method of claim 8, wherein the forming the trench is performed such that the trench extends at least partially through the second metallization structure.