CN117098390A

CN117098390A - Memory, preparation method thereof and electronic equipment

Info

Publication number: CN117098390A
Application number: CN202210505369.2A
Authority: CN
Inventors: 张珂豪; 黄伟川; 陈东奇; 焦慧芳; 林军
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-05-10
Filing date: 2022-05-10
Publication date: 2023-11-21
Also published as: WO2023216788A1; WO2023216788A9

Abstract

The application provides a memory, a preparation method thereof and electronic equipment, relates to the technical field of semiconductors, and is used for simplifying the preparation process of the memory, reducing the preparation cost of the memory and improving the yield of the memory. The memory includes a substrate, a transistor, a first dielectric layer, a first connection, a contact, and a second dielectric layer. A transistor is located on the substrate, the transistor including a first pole. The first dielectric layer is located on the transistor. The first connection portion passes through the first dielectric layer and is electrically connected with the first electrode. The contact part is positioned on the first connecting part and is electrically connected with the first connecting part. The end face of the contact part far away from the first connecting part is a first end face, the end face of the contact part electrically connected with the first connecting part is a second end face, the contact part further comprises a side face for connecting the first end face and the second end face, and the side face is a curved face. At least part of the second dielectric layer is located between any adjacent two of the contacts. The memory is applied to the electronic equipment to improve the yield of the electronic equipment.

Description

Memory, preparation method thereof and electronic equipment

Technical Field

The present application relates to the field of semiconductor technologies, and in particular, to a memory, a method for manufacturing the same, and an electronic device.

Background

In dynamic random access memory (dynamic random access memory, DRAM), ferroelectric random access memory (ferroelectric random access memory, feRAM) or other memory, the memory cells may include transistors and capacitors. The transistor is arranged on the substrate, the capacitor is positioned on one side of the transistor away from the substrate, and the transistor and the capacitor are electrically connected.

With the rapid development of the electronic industry and the demands of users, the size of a memory in an electronic device is gradually reduced, the integration density of a memory unit is higher and higher, and the size of the memory unit is smaller and smaller. The size of the source or drain electrode connected with the capacitor in the transistor is correspondingly reduced, and the difficulty of directly connecting the source or drain electrode with the capacitor is greater. Based on this, a contact layer is configured between the transistor and the capacitor in the related art so that the capacitor can be in contact with the contact layer having a large contact area and then electrically connected to the source or the drain.

However, in the process of patterning the contact layer, two Self-aligned dual imaging techniques (Self-Aligned Double Patterning, SADP) are required, two masks are used, the process is very complex, and the manufacturing cost is high.

Disclosure of Invention

The embodiment of the application provides a memory, a preparation method thereof and electronic equipment, which are used for simplifying the preparation process of the memory, reducing the preparation cost of the memory and improving the yield of the memory.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme:

in a first aspect, a method for manufacturing a memory is provided, the method comprising: a transistor is formed on a substrate, the transistor including a first pole, the first pole being a source or a drain. A first dielectric layer is formed overlying the transistor, the first dielectric layer including a first opening exposing a first pole of the transistor. A first connection is formed within the first opening. Selectively depositing a conductive material on a target end surface of the first connection portion to form an intermediate contact portion; the target end face is an end face of the first connection portion away from the substrate.

In the method for manufacturing the memory provided by the embodiment of the application, the intermediate contact part can be formed by directly selectively depositing the conductive material on the target end surface of the first connecting part, and the two self-alignment dual imaging technology is not needed, so that the manufacturing process of the memory is simpler, and the manufacturing cost of the memory is lower.

In addition, in the method for manufacturing the memory according to the embodiment of the application, two masks are not required to be used for forming the contact portion, so that the total number of masks used in the process for manufacturing the memory is reduced. Therefore, on one hand, the preparation cost of the memory can be further reduced, and on the other hand, the process of aligning two photomasks of the double imaging technology with different angles by two times and the process of aligning the two photomasks of the double imaging technology with different angles by two times by the photomask of the preparation bit line can be omitted, so that the preparation process of the memory is further simplified. Meanwhile, the reduction of the total number of photomasks used in the memory preparation process is beneficial to reducing the risk of contact short circuit among conductive film layers in the memory and affecting the yield of the memory due to deviation of alignment of each photomask.

In some embodiments, before selectively depositing the conductive material on the target end face of the first connection portion, the method further comprises: and carrying out surface treatment on the target end face. In this way, the surface energy of the target end face can be made larger, and the difference between the surface energy of the target end face and the surface energy of the surface of the first dielectric layer away from the substrate is also larger. The higher the surface energy, the faster the conductive material is deposited. Therefore, after the surface treatment is performed on the target end surface, when the conductive material is deposited, the deposition speed of the conductive material on the target end surface is higher, the deposition speed of the conductive material on the surface of the first dielectric layer far away from the substrate is lower, and at this time, the intermediate contact part can be selectively formed on the target end surface by controlling the deposition time, the deposition speed or other conditions.

In some embodiments, the surface treating the target end surface includes: exposing the target end face to a set gas environment; alternatively, a reducing solution is coated on the target end face.

In some embodiments, the forming a first connection within the first opening includes: forming a conductive layer overlying the first dielectric layer, the conductive layer including a portion embedded in the first opening; and flattening the conductive layer until the first dielectric layer is exposed so as to form the first connection part in the first opening.

In some embodiments, prior to the forming of the conductive layer overlying the first dielectric layer, further comprising: forming an intermediate adhesive layer covering a surface of the first dielectric layer remote from the substrate, and side walls and a bottom wall of the first opening; and removing the part of the intermediate bonding layer, which is positioned on the surface of the first dielectric layer, which is far away from the substrate, in the process of flattening the conductive layer until the first dielectric layer is exposed, so as to form bonding layers on the side wall and the bottom wall of the first opening.

In some embodiments, before the forming of the first connection portion in the first opening, the method further includes: and forming a second connecting part in the first opening, wherein the thickness of the second connecting part is smaller than that of the first dielectric layer. In this way, the contact resistance is smaller and the power consumption of each memory cell can be smaller, as compared with the case where the first electrode is in direct contact with the first connection portion including the metal material and the first electrode is in contact with the second connection portion including the polysilicon material.

In some embodiments, the method of making further comprises: forming a second dielectric layer covering the intermediate contact; removing the second dielectric layer with the first preset thickness, and removing the middle contact part with the second preset thickness, wherein the rest middle contact parts form contact parts; the first preset thickness is smaller than the thickness of the second dielectric layer, and the second preset thickness is smaller than the thickness of the middle contact portion.

Therefore, the second dielectric layer is sunk between the two adjacent middle contact parts, so that the two adjacent middle contact parts are mutually insulated, the problem that short circuit occurs between two adjacent storage units due to connection of the two adjacent middle contact parts is solved, and the yield of the memory is improved. According to the embodiment of the application, the middle contact part with the second preset thickness is removed, so that the surface of the contact part, which is far away from the substrate, is a plane, and the contact area between the contact part and the capacitor is large, thereby being beneficial to improving the contact stability between the contact part and the capacitor.

In some embodiments, the method of making further comprises: a capacitor is formed, the capacitor being connected to the contact.

In a second aspect, a memory is provided that includes a substrate, a transistor, a first dielectric layer, a first connection, a contact, and a second dielectric layer. Wherein a transistor is located on the substrate, the transistor comprising a first pole, the first pole being either a source or a drain. A first dielectric layer is over the transistor. The first connection portion is electrically connected with the first pole through the first dielectric layer. The contact part is positioned on the first connecting part and is electrically connected with the first connecting part. The end face of the contact part far away from the first connecting part is a first end face, the end face of the contact part electrically connected with the first connecting part is a second end face, the contact part further comprises a side face for connecting the first end face and the second end face, and the side face is a curved face. At least part of the second dielectric layer is positioned between any adjacent two of the contact portions.

In some embodiments, the first end is circular or oval.

In some embodiments, an end surface of the first connection portion electrically connected to the contact portion is a target end surface, and an area of the first end surface is larger than an area of the target end surface.

In some embodiments, the second end face has an area that is greater than an area of the target end face; the radial dimension of the contact portion gradually decreases in a direction perpendicular to and away from the substrate.

In some embodiments, the second end face includes a first sub-end face and a second sub-end face; the first sub-end surface is in contact with the first connecting part; the second sub-end surface at least partially surrounds the first sub-end surface, the second sub-end surface being in contact with a surface of the first dielectric layer remote from the substrate.

In some embodiments, a surface of the second dielectric layer remote from the substrate is flush with a surface of the contact remote from the substrate.

In some embodiments, the memory further comprises an adhesive layer. The bonding layer is positioned between the first connecting part and the first dielectric layer; the bonding layer comprises a first sub-bonding layer and a second sub-bonding layer, the first sub-bonding layer is arranged around the side face of the first connecting portion, and the second sub-bonding layer is located on the end face, far away from the contact portion, of the first connecting portion.

In some embodiments, the memory further comprises a second connection. The second connecting part is positioned between the first connecting part and the first pole and is electrically connected with the first connecting part and the first pole; the thickness of the second connection portion is smaller than that of the first dielectric layer.

In some embodiments, the memory further comprises a capacitor connected to the contact.

In a third aspect, an electronic device is provided that includes a processor and a memory, the processor coupled with the memory; the memory is the memory according to any one of the above embodiments.

The technical effects caused by any one of the design manners of the second aspect and the third aspect may refer to the technical effects caused by the different design manners of the first aspect, which are not repeated herein.

Drawings

FIG. 1 is a circuit diagram of a memory according to an embodiment of the present application;

FIG. 2 is a top view of a memory according to an embodiment of the present application;

FIG. 3A is a schematic cross-sectional view of the memory provided in FIG. 2 at C-C';

FIG. 3B is a schematic cross-sectional view of the memory provided in FIG. 2 at D-D';

FIG. 4 is a flow chart of a self-aligned dual imaging technique according to an embodiment of the present application;

FIG. 5 is a state diagram corresponding to each step of the flowchart shown in FIG. 4;

FIG. 6 is a flowchart of a method for manufacturing a memory according to an embodiment of the present application;

FIG. 7 is a schematic diagram of another memory according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a structure of a memory according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a memory according to another embodiment of the present application;

FIG. 10 is a flowchart of another method for manufacturing a memory according to an embodiment of the present application;

FIG. 11 is a schematic diagram of a structure of a memory according to another embodiment of the present application;

FIG. 12 is a flowchart of a method for manufacturing a memory according to an embodiment of the present application;

FIG. 13 is a flowchart of a method for manufacturing a memory according to an embodiment of the present application;

FIG. 14A is a schematic diagram of a memory according to another embodiment of the present application;

FIG. 14B is a top view of another memory device according to an embodiment of the present application;

FIG. 15 is a flowchart of a method for manufacturing a memory according to an embodiment of the present application;

FIG. 16A is a flowchart of a method for fabricating a memory according to another embodiment of the present application;

FIG. 16B is a flowchart of a method for fabricating a memory according to another embodiment of the present application;

FIG. 17 is a flowchart of a method for fabricating a memory according to another embodiment of the present application;

FIG. 18 is a schematic diagram of a memory according to another embodiment of the present application;

FIG. 19 is a schematic diagram of a memory according to another embodiment of the present application;

FIG. 20 is a flowchart of a method for manufacturing a memory according to an embodiment of the present application;

FIG. 21 is a schematic diagram of a memory according to another embodiment of the present application;

FIG. 22 is a top view of yet another memory provided in an embodiment of the present application;

fig. 23 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. Wherein, in the description of the present application, "/" means that the related objects are in a "or" relationship, unless otherwise specified, for example, a/B may mean a or B; the "and/or" in the present application is merely an association relationship describing the association object, and indicates that three relationships may exist, for example, a and/or B may indicate: there are three cases, a alone, a and B together, and B alone, wherein a, B may be singular or plural.

In the description of the present application, unless otherwise indicated, "a plurality" means two or more than two. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.

In order to clearly describe the technical solution of the embodiments of the present application, in the embodiments of the present application, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ.

Meanwhile, in the embodiments of the present application, words such as "exemplary" or "such as" are used to mean serving as examples, illustrations or explanations. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion that may be readily understood.

As shown in fig. 1 and 2, some embodiments of the present application provide a memory 100, the memory 100 including a plurality of memory cells 10, each memory cell 10 may include a transistor 11 and a capacitor 12. Wherein the transistor 11 is electrically connected to the capacitor 12.

Transistor 11 may include a gate 111, a source 112, and a drain 113. The "transistor 11 is electrically connected to the capacitor 12" may be such that the drain 113 of the transistor 11 is electrically connected to the capacitor 12, or such that the source 112 of the transistor 11 is electrically connected to the capacitor 12, as shown in fig. 1. Transistor 11 controls writing, modifying or reading of information in capacitor 12. That is, the transistor 11 as a selection device (or switching device) can control writing, modification, or reading of information in the capacitor.

Referring to fig. 3A, the capacitor 12 may include a first electrode 121 and a second electrode 122, and a capacitive dielectric layer 123 between the first electrode 121 and the second electrode 122. Therein, for example, referring to fig. 2, the first electrode 121 may be electrically connected to the drain electrode 113 of the transistor 11, and the second electrode 122 may be grounded.

It should be understood that the number of the memory cells 10 in the memory 100 is not limited in the present application, as long as the memory requirements of the memory 100 can be satisfied. The number of transistors 11 and capacitors 12 in the memory cell 10 is not limited in the present application, as long as writing, modification, or reading of data can be achieved. For example, as shown in fig. 1, a memory cell 10 may include a transistor 11 and a capacitor 12.

As shown in fig. 1, the memory 100 may further include a plurality of word lines WL and a plurality of bit lines BL, wherein the word lines WL may be connected to the gate 111 of the transistor 11, thereby controlling the on and off of the transistor 11. The bit line BL may be connected to the source 112 of the transistor 11 to write data into the capacitor 12 connected to the transistor 11 when the transistor 11 is turned on.

It is understood that for the memory 100, peripheral circuits such as a read amplifier circuit, a read/write circuit, and the like may be included in addition to the memory cell 10, the word line WL, and the bit line BL.

Fig. 2 is a top view of the memory 100, fig. 3A is a cross-sectional view of fig. 2 at C-C ', and fig. 3B is a cross-sectional view of fig. 2 at D-D'. Referring to fig. 2 to 3B, the memory 100 includes a substrate 101, and an active area AA, a word line WL, and a bit line BL disposed on the substrate 101. Wherein the word line WL extends in a first direction X parallel to the substrate 101 and the bit line BL extends in a second direction Y parallel to the substrate 101, the first direction X and the second direction Y intersecting. The active area AA extends in a third direction W parallel to the substrate 101, the third direction W having an angle with both the first direction X and the second direction Y.

In some examples, the first direction X may be perpendicular to the second direction Y. In the present application, the angle between the third direction W and the first direction X, the second direction Y is not limited, and the memory 100 can be designed reasonably according to the layout requirements.

The substrate 101 may include silicon (Si), for example, crystalline silicon, polycrystalline silicon, or amorphous silicon. Alternatively, the substrate 101 may include a semiconductor element, such as germanium (Ge). Alternatively, the substrate 101 may have a silicon-on-insulator (silicon on insulator, SOI) structure. For example, the substrate 101 may include a Buried Oxide (BOX) layer.

Referring to fig. 2, the active area AA has an overlapping area between the front projection on the substrate 101 and the front projections of two adjacent word lines WL on the substrate 101. The portion of the word line WL corresponding to the overlap region may serve as the gate 111 of the transistor 11. Along the extension direction of the active area AA, portions of the active area AA corresponding to the non-overlapping regions may serve as the source 112 and the drain 113 of the transistor 11.

At this time, the same active area AA may define two transistors 11, and the two transistors 11 share the same source 112 (or drain 113) to be connected. Alternatively, the sources 112 (or drains 113) of the two transistors 11 are connected.

In some examples, the active region AA may be obtained by doping the substrate 101. The doping particles in the same active area AA are the same, i.e. the structure of the source 112 and drain 113 of the transistor 11 is the same.

Referring to fig. 3A and 3B, in a direction perpendicular to the substrate 101 (i.e., a fourth direction Z), the word line WL is located between a surface of the active region AA (or the source 112) remote from the substrate 10 and the substrate 101.

The material of the word line WL may include a metal, for example, tungsten (W), cobalt (Co), ruthenium (Ru), or the like.

The number of the active areas AA, the word lines WL and the bit lines BL is not limited in the present application, and can be designed according to the storage requirements of the memory 100.

As shown in fig. 2 and 3A, the memory 100 may further include an isolation structure 102 on the substrate 101, where the isolation structure 102 isolates two adjacent active areas AA from each other. Illustratively, the surface of the isolation structure 102 remote from the substrate 101 may be flush with the surface of the active area AA remote from the substrate 101.

By way of example, the material of the isolation structure 102 may include silicon oxide, silicon nitride, silicon oxynitride, and the like.

As the integration level of the memory increases, the sizes of the source 112 and the drain 113 in the transistor 11 gradually decrease, the size of the orthographic projection of the source 112 and the drain 113 on the substrate 101 becomes smaller, and the difficulty of directly connecting the capacitor to the source or the drain increases. Based on this, as shown in fig. 3A and 3B, a contact layer 13 is prepared in the related art on a side of the transistor 11 away from the substrate 101, the contact layer 13 including a plurality of contact portions 131, and the area of the surface of the contact portion 131 contacting the source electrode 112 or the drain electrode 113 is smaller than the area of the surface of the contact portion 131 contacting the capacitor 12. In this way, the capacitor can be easily contacted with the contact portion 13, and thus electrically connected with the source 112 or the drain 113 again.

In the process of manufacturing the contact 131, the mask layer used for forming the contact 131 needs to be patterned by using a self-aligned dual imaging technique of two different angles. Fig. 4 is a process flow diagram of the self-aligned dual imaging technique, and fig. 5 is a state diagram corresponding to each step of the self-aligned dual imaging technique. Referring to fig. 4 and 5, the present application will be briefly described with respect to a one-time self-aligned dual imaging technique. The self-aligned dual imaging technique includes:

s1, forming a stacked structure 14 on the contact layer 13, where the stacked structure 14 includes a first mask layer 141, a second mask layer 142, a third mask layer 143, a mandrel layer 144, an anti-reflection layer 145, and a photoresist layer 146 in sequence along a direction perpendicular to the substrate 101 and away from the substrate 101.

Illustratively, the materials of the first and third mask layers 141 and 143 may be the same, e.g., the materials of the first and third mask layers 141 and 143 may each include an oxide (e.g., silicon oxide). The materials of the first mask layer 141 and the second mask layer 142 may be different. The material of mandrel layer 144 may include polysilicon (a-Si). The anti-reflective layer 145 may be a silicon-containing anti-reflective layer.

It is understood that the layers in the stacked structure 14 are not limited to the first mask layer 141, the second mask layer 142, the third mask layer 143, the mandrel layer 144, the anti-reflection layer 145 and the photoresist layer 146, and that other layers may be provided in the stacked structure 14 to meet the process requirements.

S2, patterning the photoresist layer 146 to form a photoresist pattern 1461. Illustratively, photoresist layer 146 may be etched using exposure, development, and the like.

And S3, etching the mandrel layer 144 based on the photoresist pattern 1461 to form a mandrel structure 1441.

Illustratively, mandrel layer 144 is etched based on photoresist pattern 1461, which may be based on photoresist pattern 1461 to etch anti-reflective layer 145 and photoresist layer 146, and then removing anti-reflective layer 145 over mandrel structure 1441.

S4, depositing a fourth mask layer 147, the fourth mask layer 147 covering the top and sidewalls of the mandrel structures 1441. As shown in fig. 5, the fourth mask layer 147 may also cover a portion of the third mask layer 143. The material of the fourth mask layer 147 may include oxide or silicon nitride.

By way of example, the fourth mask layer 147 may be deposited using an atomic deposition process.

And S5, etching the fourth mask layer 147 until the top of the mandrel structure 1441 is exposed, and forming a side wall 1471 in the portion, covered on the side wall of the mandrel structure 1441, of the fourth mask layer 147.

It is appreciated that the sidewalls 1471 covering the sidewalls of the different mandrel structures 1441 are not connected to each other.

S6, removing the mandrel structure 1441.

S7, etching the second mask layer 142 based on the side walls 1471 to obtain a plurality of mask patterns 1421. For example, the third mask layer 143 and the second mask layer 142 may be etched based on the sidewall 1471, and then the third mask layer 143 may be removed.

It will be appreciated that the above steps of the present application are simply illustrative of a self-aligned dual imaging technique, which does not include only the processing steps of steps S1-S7.

After the first self-aligned dual imaging technique is completed, a protective layer may be covered on the second mask layer 142, and then a third mask layer, a mandrel layer, an anti-reflection layer, and a photoresist layer are sequentially formed on a side of the protective layer away from the substrate, and the above etching steps are repeated.

After the second time using the self-aligned double imaging technique, the mask pattern 1421 is further modified, so that the contact layer 13 may be etched using the further modified mask pattern 1421 to form the contact 131.

The inventor discovers that the contact layer is etched by utilizing the double self-aligned double imaging technology, more process steps are needed, so that the process steps in the preparation process of the memory are correspondingly more, and the preparation process of the memory is more complex. And the contact layer is etched by using the two-time self-aligned dual-imaging technology, two different photomasks are required, and the manufacturing cost of the contact layer is relatively high, which results in the manufacturing cost of the memory 100 being also high.

Meanwhile, because the photomasks required by the double imaging technology of self-alignment at different angles are different, the alignment requirement between the two photomasks is higher in the process of etching the same film by using the two photomasks. When the relative positional relationship between the two masks is deviated, the contact portions 131 corresponding to different memory cells may be shorted, thereby affecting the yield of the memory.

It will be appreciated that when the bit lines BL are also fabricated using a self-aligned dual imaging technique, a mask is also required, and in this case, in order to ensure that the bit lines BL are matched to the contacts 131, the alignment requirements between the mask required to fabricate the bit lines BL and the mask required to fabricate the contacts 131 are correspondingly high. When the alignment relationship between the mask required for preparing the bit line BL and the mask required for preparing the contact 131 is deviated, the yield of the memory is also directly affected.

Based on this, as shown in fig. 6, some embodiments of the present application provide a method for manufacturing a memory 200, including steps S100 to S400.

S100, as shown in fig. 7, a transistor 210 is formed on a substrate 201, the transistor 210 including a first pole and a second pole. Wherein the first pole may be the source 211 and the second pole may be the drain 212; alternatively, the first pole may be the drain 212 and the second pole may be the source 211.

For example, referring to fig. 2 and 7, an active area AA and an isolation structure 202 may be first formed on a substrate 201, the active area AA extending in a third direction W parallel to the substrate 201. The isolation structure 202 is located between two adjacent active regions AA, which are insulated from each other. Then, a word line trench is formed in the active region AA and the isolation structure 202, a gate insulating layer 2131 is formed in the word line trench to cover sidewalls and bottom of the word line trench, and a word line WL is formed on the gate insulating layer 2131. The word line WL extends in a first direction X parallel to the substrate 201. Two separate word line trenches are formed in each active area AA, which divide the active area AA into a middle source 211 and two drains 212 located on both sides of the source 211 (alternatively, the two word line trenches divide the active area AA into a middle drain 212 and two sources 211 located on both sides of the drain 212). Wherein the middle source 211 and the drain 212 on one side thereof belong to one transistor 210, and the middle source 211 and the drain 212 on the other side thereof belong to the other transistor 210. Two word lines WL located within the same active area AA may serve as gates 213 for two transistors 210.

In some examples, the isolation structure 202 may be a single layer structure, in which case, for example, the material of the isolation structure 202 may include silicon oxide, silicon nitride, silicon oxynitride, and the like. In other examples, the isolation structure 202 may be a multi-layer structure, in which case the isolation structure 202 may include a first isolation layer 2021 in contact with the active region AA and a second isolation layer 2022 located on a side of the first isolation layer 2021 away from the active region AA. The material of the first isolation layer 2021 may include silicon oxide or a high dielectric constant oxide. The material of the second isolation layer may include silicon oxide, silicon nitride, silicon oxynitride, and the like. The material of the first insulating layer 2021 is different from the material of the second insulating layer 2022.

Wherein the first isolation layer 2021 and the second isolation layer 2022 are used to isolate the plurality of transistors 210. The first spacer 2021 may also be used to relieve stress generated on the substrate 201 after etching.

Illustratively, the material of the gate insulating layer 2131 may include silicon oxide or a high dielectric constant material. Wherein the dielectric constant of the high dielectric constant material is greater than that of silicon oxide. The high dielectric constant material may be, for example, aluminum oxide (Al ₂ O ₃ ) Zirconium oxide (ZrO) ₂ ) Tantalum pentoxide (Ta) ₂ O ₅ ) Yttria (Y) ₂ O ₃ ) Hafnium oxide (HfO) ₂ ) And titanium dioxide (TiO) ₂ ) One of them.

In some examples, the material of the word line WL may include a metal, e.g., tungsten (W), cobalt (Co), ruthenium (Ru), etc. In other examples, the material of the word line WL may include polysilicon.

Referring to fig. 7, after forming the word line WL (or the gate electrode 213) on the gate insulating layer 2131, an interlayer dielectric layer 2132 may be formed on a side of the word line WL away from the substrate 201. The interlayer dielectric layer 2132 may be formed of a nitride layer, an oxide layer, or a stacked structure of a nitride layer and an oxide layer. Interlayer dielectric layer 2132 may be used to insulate word line WL and other conductive film layers disposed on the substrate.

Referring to fig. 7, after forming the word line WL, a word line contact WC may also be formed on the word line WL before forming the interlayer dielectric layer 2132. The material of the word line contact WC may comprise polysilicon. The word line contact WC may also be used to connect the word line WL with other layers.

It is to be understood that the step of forming the transistor 210 over the substrate 201 in the present application is not limited thereto.

S200, as shown in fig. 8, a first dielectric layer 220 is formed to cover the transistor 210, the first dielectric layer 220 including a first opening 221, the first opening 221 exposing a first pole of the transistor 210. Fig. 8 illustrates the first drain electrode 212 as an example.

Illustratively, the material of the first dielectric layer 220 may include silicon oxide, silicon nitride, silicon oxynitride, or the like.

Illustratively, after forming the transistor 210 on the substrate 201 at step S100, the method of preparing may further include, before forming the first dielectric layer 220 covering the transistor 210 at step S200: a bit line BL is formed, the bit line BL extends in the second direction Y, and the bit line BL is electrically connected to the source 211 of the transistor 210. Referring to fig. 3B, the bit line BL may be located at a side of the active area AA remote from the substrate 201.

For example, referring to fig. 3B, a bit line contact BC may also be formed before forming the bit line BL, the bit line contact BC being located in the active area AA and contacting the source electrode 211.

S300, as shown in fig. 9, a first connection portion 230 is formed in the first opening 221.

In some examples, as shown in fig. 10, forming the first connection portion 230 within the first opening 221 in step 300 may include:

as shown in fig. 11, a conductive layer 240 is formed to cover the first dielectric layer 220, the conductive layer 240 including a portion embedded in the first opening 221.

By way of example, the material of the conductive layer 240 may include a metal, for example, tungsten (W), cobalt (Co), ruthenium (Ru), or the like.

Illustratively, it may be formed by a chemical vapor deposition (chemical vapor deposition, CVD) process, or an atomic layer deposition (atomic layer deposition, ALD) process.

In S320, referring to fig. 9 and 11, the conductive layer 240 is planarized until the first dielectric layer 220 is exposed, so as to form a first connection portion 230 in the first opening 221.

By way of example, the conductive layer 240 may be planarized using a chemical mechanical planarization (chemical mechanical polishing, CMP) process.

Illustratively, the surface of the first connection 230 remote from the substrate 201 may be flush, or approximately flush, with the surface of the first dielectric layer 220 remote from the substrate 201.

In some embodiments, as shown in fig. 12, before forming the conductive layer 240 covering the first dielectric layer 220 in step S310, the preparation method may further include:

S330, referring to fig. 11, an intermediate adhesive layer 250 is formed, and the intermediate adhesive layer 250 covers the surface of the first dielectric layer 220 away from the substrate 201, and the sidewalls and bottom wall of the first opening 221.

Based on this, in the planarization process of the conductive layer 240 to expose the first dielectric layer 220 in step S320, a portion of the intermediate adhesive layer 250 located on a surface of the first dielectric layer 220 remote from the substrate 201 may also be removed to form the adhesive layer 251 on the sidewalls and the bottom wall of the first opening 221.

In some embodiments, as shown in fig. 13, before forming the first connection part 230 in the first opening 221 in step S300, the manufacturing method further includes:

s340, referring to fig. 11, a second connection portion 260 is formed in the first opening 221, and a thickness of the second connection portion 260 is smaller than a thickness of the first dielectric layer 220.

For example, the second connection portion 260 may be formed in the first opening 221 after the first dielectric layer 220 covering the transistor 210 is formed in step S200 and before the intermediate adhesive layer 250 is formed in step S330.

Illustratively, the material of the second connection portion 260 may include polysilicon.

In the above embodiment of the present application, the second connection portion 260 is formed in the first opening 221 before the first connection portion 230 is formed in the first opening 221. In this way, the first electrode (source electrode 211 or drain electrode 212) is in contact with the second connection portion 260 including the polysilicon material, the contact resistance is smaller, and the power consumption of each memory cell can be smaller, as compared with the first electrode (source electrode 211 or drain electrode 212) being in direct contact with the first connection portion 230 including the metal material.

S400, as shown in fig. 14A, a conductive material is selectively deposited on the target end surface 231 of the first connection portion 230, forming the intermediate contact portion 270. The target end face 231 is an end face of the first connection portion 230 remote from the substrate 201.

Illustratively, the conductive material may be selectively deposited on the target end face 231 by an atomic layer deposition process.

By way of example, the conductive material may include a metal, such as tungsten (W), cobalt (Co), ruthenium (Ru), and the like.

In some examples, the conductive material may be the same as the material of the first connection portion 230.

In some examples, referring to fig. 14A, in a direction perpendicular to the substrate 201 (i.e., fourth direction Z), the intermediate contact 270 gradually decreases in size in a direction parallel to the substrate 201. Here, the "size of the intermediate contact 270 in the direction parallel to the substrate 201 is gradually reduced" may be that the size of the intermediate contact 270 in all directions parallel to the substrate 201 is gradually reduced.

In some examples, referring to fig. 14B, the area of the surface of the intermediate contact 270 that contacts the target end surface 231 is greater than the area of the target end surface 231. In this way, the contact reliability between the intermediate contact portion 270 and the target end surface 231 is advantageously improved.

In some examples, referring to fig. 14B, the surface of the intermediate contact portion 270 that contacts the target end surface 231 may be generally circular or elliptical.

Here, "substantially circular or oval" means that the shape of the surface of the intermediate contact portion 270 that contacts the target end surface 231 is circular or oval as a whole, but is not limited to a standard circular or oval shape. That is, "circular" herein includes not only a substantially circular shape but also a shape similar to a circular shape in consideration of process conditions, and "elliptical" herein includes not only a substantially elliptical shape but also a shape similar to an ellipse in consideration of process conditions.

In the method for manufacturing the memory 200 according to the above embodiment of the present application, the intermediate contact portion 270 can be formed by selectively depositing the conductive material directly on the target end surface 231 of the first connection portion 230, and the two self-aligned dual imaging techniques are not required, so that the manufacturing process of the memory 200 is simpler, and the manufacturing cost of the memory 200 is lower.

And since the method for manufacturing the memory 200 according to the above embodiment of the present application does not need to use two masks to form the contact portion, the total number of masks used in the manufacturing process of the memory 200 is reduced. In this way, on the one hand, the manufacturing cost of the memory can be further reduced, and on the other hand, the process of aligning two photomasks of the two-time different-angle self-aligned dual-imaging technology and the process of aligning two photomasks of the two-time different-angle self-aligned dual-imaging technology with the photomask for manufacturing the bit line BL can be omitted, so that the manufacturing process of the memory 200 is further simplified. Meanwhile, the reduction of the total number of photomasks used in the preparation process of the memory 200 is beneficial to reducing the risk of contact short circuit among conductive film layers in the memory and affecting the yield of the memory due to deviation of alignment of each photomask.

It can be appreciated that in the above embodiment of the present application, the conductive material is selectively deposited directly on the target end surface 231 of the first connection portion 230 to form the intermediate contact portion 270, so that shorting between the plurality of intermediate contact portions 270 can be avoided directly by adjusting the process conditions, and the yield of the memory 200 can be effectively ensured.

In some embodiments, as shown in fig. 15, before selectively depositing the conductive material on the target end surface 231 of the first connection portion 230 to form the intermediate contact portion 270 in step S400, the manufacturing method may further include:

s500, performing surface treatment on the target end surface 231.

In some examples, as shown in fig. 16A, the step S500 of performing surface treatment on the target end surface 231 may include:

s510, exposing the target end surface 231 to a set gas environment.

Exemplary, the set gas may include oxygen (O ₂ ) Hydrogen (H) ₂ ) Or plasma gas generated from oxygen and hydrogen.

In other examples, as shown in fig. 16B, step S500 of processing the target end surface 231 includes:

s520, a reducing solution is applied to the target end surface 231.

Wherein the reducing solution may comprise a weak acid solution, which is an acid having an ionization constant of less than 0.0001.

Illustratively, the weak acid solution may be a hydrofluoric acid dilution, or an ammonium chloride solution.

Illustratively, the weak acid solution may be coated on the target end face 231 by a spin coating process.

The above embodiment of the present application makes the surface energy of the target end surface 231 larger by performing the surface treatment on the target end surface 231, and the surface energy of the target end surface 231 is also greatly different from the surface energy of the surface of the first dielectric layer 220 away from the substrate 201. Since the larger the surface energy, the faster the deposition of the metal material. Therefore, after the target end surface 231 is surface-treated, when the conductive material is deposited, the deposition rate of the conductive material on the target end surface 231 is faster, the deposition rate of the conductive material on the surface of the first dielectric layer 220 away from the substrate 201 is slower, and the intermediate contact 270 can be formed on the target end surface 231 by controlling the deposition time, speed or other conditions.

In some embodiments, in step S400, before the conductive material is selectively deposited on the target end surface 231 of the first connection portion 230 and the intermediate contact portion 270 is formed, the surface of the target end surface 231 and the surface of the first dielectric layer 220 away from the substrate 201 may be simultaneously surface-treated, so that the surface energy of the target end surface 231 is greater, and the surface energy of the surface of the first dielectric layer 220 away from the substrate 201 is smaller, so as to further increase the difference between the surface energies of the target end surface 231 and the surface of the first dielectric layer 220 away from the substrate 201.

In some embodiments, as shown in fig. 17, the method for preparing the memory 200 further includes:

s600, as shown in fig. 18, a second dielectric layer 280 is formed to cover the intermediate contact 270.

For example, the second dielectric layer 280 covering the intermediate contact 270 may be formed by a chemical vapor deposition process, or an atomic layer deposition process.

Illustratively, the material of the second dielectric layer 280 may include silicon oxide, silicon nitride, silicon oxynitride, or the like.

It can be appreciated that when the second dielectric layer 280 covers the intermediate contact portion 270, the second dielectric layer 280 may be trapped between two adjacent intermediate contact portions 270, so that the two adjacent intermediate contact portions 270 are insulated from each other, which is beneficial to improving the problem of shorting between two adjacent memory cells caused by the connection of the two adjacent intermediate contact portions 270, and further is beneficial to improving the yield of the memory 200.

Referring to fig. 18, a thickness h1 of the second dielectric layer may be greater than a thickness h2 of the intermediate contact 270.

S700, referring to fig. 18 and 19, the second dielectric layer 280 with the first preset thickness h3 is removed, and the intermediate contact 270 with the second preset thickness h4 is removed, and the remaining intermediate contact 270 forms a contact 271. The first preset thickness h3 is smaller than the thickness h1 of the second dielectric layer 280, and the second preset thickness h4 is smaller than the thickness h2 of the intermediate contact 270.

Illustratively, the second dielectric layer 280 of the first preset thickness h3 may be removed by a chemical mechanical planarization process, and the intermediate contact 270 of the second preset thickness h4 may be removed.

Based on this, the surface of the second dielectric layer 280 away from the substrate 201 after the first preset thickness h3 is removed may be flush or approximately flush with the surface of the contact 271 away from the substrate 201.

The embodiment of the application removes the middle contact portion 270 with the second preset thickness h4, so that the surface of the contact portion 271 far away from the substrate 201 is a plane, and the contact area between the contact portion 271 and the capacitor is larger, thereby being beneficial to improving the contact stability between the contact portion 271 and the capacitor.

It will be appreciated that the thickness h1 of the second dielectric layer 280 is greater than the thickness h2 of the intermediate contact 270, and the chemical mechanical planarization process grinds the second dielectric layer 280 and the intermediate contact 270 toward the direction of the substrate 201, so that the first preset thickness h3 is greater than the second preset thickness h4 in the case that the ground surface of the second dielectric layer 280 away from the substrate 201 and the surface of the contact 271 away from the substrate 201 are flush.

In the above embodiment of the present application, specific values of the first preset thickness h3 and the second preset thickness h4 are not limited as long as the surface of the contact portion 271 away from the substrate 201 is made planar.

In some examples, the second preset thickness h4 may also be any value that makes the area of the surface of the contact portion 271 away from the substrate 201 larger than the area of the surface of the first connection portion 230 away from the substrate 201 (target end surface 231). In this way, the area of the surface of the contact portion 271 away from the substrate 201 is larger than the area of the surface of the first connection portion 230 away from the substrate 201 (the target end surface 231), the contact area of the capacitor with the contact portion 271 can be larger and the contact stability between the capacitor and the contact portion 271 can be better than when the capacitor is directly contacted with the first electrode (the source 211 or the drain 212) or the first connection portion 230.

In some embodiments, as shown in fig. 20, the method for preparing the memory 200 further includes:

s800, referring to fig. 21, a capacitor 290 is formed, and the capacitor 290 is connected to the contact 271.

Illustratively, the capacitor 290 may include a first electrode 291 and a second electrode 292, and a capacitive dielectric 293 between the first electrode 291 and the second electrode 292.

Wherein the capacitor 290 is connected to the contact 271 so as to be electrically connected to the transistor 210, the transistor 210 and the capacitor 290 constitute one memory cell of the memory 200.

As shown in fig. 21, some embodiments of the present application provide a memory 200, the memory 200 including a substrate 201, a transistor 210, a first dielectric layer 220, a first connection 230, a contact 271, and a second dielectric layer 280.

Wherein the substrate 201 comprises silicon (Si), e.g., crystalline silicon, polysilicon, or amorphous silicon. Alternatively, the substrate 201 may include a semiconductor element, such as germanium (Ge). Alternatively, the substrate 201 may have a silicon-on-insulator structure. For example, the substrate 201 may include a buried oxide layer.

A transistor 210 is located on the substrate 201, the transistor 210 including a source 211 and a drain 212, and a gate 213. The memory 200 may include a plurality of transistors 210, and the number of the transistors 210 in the memory 200 is not limited in the embodiment of the present application, as long as the memory requirement of the memory 200 can be satisfied.

In some examples, referring to fig. 14B, the memory 200 may further include a word line WL extending in a first direction X parallel to the substrate 201 and a bit line BL extending in a second direction Y parallel to the substrate 201, the first direction X intersecting the second direction Y. The word line WL and the bit line BL are located in the substrate 10.

Wherein the word line WL may be connected to the gates 213 of the plurality of transistors 210 at the same time. The bit line BL may be coupled to the source 211 of the transistor 210.

The first dielectric layer 220 is located on the transistor 210. Illustratively, the material of the first dielectric layer 220 may include silicon oxide, silicon nitride, silicon oxynitride, or the like.

The first connection 230 is electrically connected to the first electrode of the transistor 210 through the first dielectric layer 220. The first electrode is a source 211 or a drain 212. Fig. 21 illustrates the first drain electrode 212 as an example.

In some examples, the first dielectric layer 220 may include a first opening 221, and the first connection portion 230 may be electrically connected with the first electrode through the first opening 221. Illustratively, the material of the first connection portion 230 may include a metal, for example, tungsten (W), cobalt (Co), ruthenium (Ru), or the like.

The contact portion 271 is located on the first connection portion 230 and is electrically connected with the first connection portion 230. Referring to fig. 22, an end surface of the contact portion 271 away from the first connection portion 230 is a first end surface 272, an end surface of the contact portion 271 electrically connected with the first connection portion 230 is a second end surface 273, the contact portion 271 further includes a side surface 274 connecting the first end surface 273 and the second end surface 273, and the side surface 274 is a curved surface.

Illustratively, the material of the contact 271 may include a metal, e.g., tungsten (W), cobalt (Co), ruthenium (Ru), etc.

In some examples, the materials of the first connection portion 230 and the contact portion 271 may be the same. In other examples, the materials of the first connection portion 230 and the contact portion 271 may be different.

At least a portion of the second dielectric layer 280 is located between any adjacent two of the contacts 271. In this way, the second dielectric layer 280 may space any two adjacent contact portions 271 apart, so that the two adjacent contact portions 271 are insulated from each other, and the problem of shorting between the two contact portions 271 is avoided.

The memory 200 provided by the above embodiments of the present application is prepared by the method for preparing a memory provided by the above embodiments. Wherein, the contact 271 is formed by selectively depositing a conductive material on the target end surface 231 without using a double self-aligned double imaging technique, so that the manufacturing process of the memory 200 can be simplified and the manufacturing cost of the memory 200 can be reduced while the capacitor can be easily contacted with the contact 271.

Meanwhile, in the manufacturing process of the contact 271, two masks are not required, and thus the total number of masks used in the manufacturing process of the memory 200 is small. In this way, on the one hand, the manufacturing cost of the memory 200 can be further reduced, and on the other hand, the process of aligning two masks of the two-time different-angle self-aligned dual imaging technology and the process of aligning two masks of the two-time different-angle self-aligned dual imaging technology with the mask for preparing the bit line BL can be omitted, so that the manufacturing process of the memory 200 is further simplified. Meanwhile, the reduction of the total number of photomasks used in the preparation process of the memory 200 is beneficial to reducing the risk of contact short circuit among conductive film layers in the memory and affecting the yield of the memory due to deviation of alignment of each photomask.

In the above embodiment of the present application, the conductive material is selectively deposited directly on the target end surface 231 of the first connection portion 230 to form the intermediate contact portion 270, and then the contact portion 271 can be formed by removing part of the intermediate contact portion 270, so that short circuit between a plurality of intermediate contact portions 270 can be avoided directly by adjusting the process conditions, and the yield of the memory 200 can be effectively ensured.

In some embodiments, as shown in fig. 22, the first end surface 272 is circular or elliptical. In this way, the effective contact area of the first end surface 272 can be larger, and the connection stability between the first end surface 272 and the capacitor is better.

Wherein, "the first end surface 272 is circular or oval" means that the first end surface 272 is circular or oval as a whole, but is not limited to a standard circular or oval. That is, "circular" herein includes not only a substantially circular shape but also a shape similar to a circular shape in consideration of process conditions, and "elliptical" herein includes not only a substantially elliptical shape but also a shape similar to an ellipse in consideration of process conditions.

In some embodiments, as shown in fig. 21 and 22, the end surface of the first connection portion 230 electrically connected to the contact portion 271 is a target end surface 231, and the area of the first end surface 272 is larger than the area of the target end surface 231. In this way, the connection of the capacitor to the first end surface 272 of the contact portion 271 is easier to achieve and the connection of the capacitor to the transistor 210 is more stable than the connection of the capacitor directly to the target end surface 231 of the first connection portion 230.

In some embodiments, as shown in fig. 21 and 22, the area of the second end surface 273 is greater than the area of the target end surface 231. The radial dimension of the contact 271 gradually decreases in a direction perpendicular to the substrate 201 and away from the substrate 201.

In some embodiments, referring to fig. 21 and 22, the second end surface 273 includes a first sub-end surface 2731 and a second sub-end surface 2732. The first sub-end surface 2731 is in contact with the first connection part 230. The second sub-end surface 2732 at least partially surrounds the first sub-end surface 2731, and the second sub-end surface 2732 is in contact with a surface of the first dielectric layer 220 remote from the substrate 201.

In some embodiments, referring to fig. 21, a surface of the second dielectric layer 280 remote from the substrate 201 is flush with a surface of the contact 271 remote from the substrate 201.

In some embodiments, referring to fig. 21, the memory 200 further includes an adhesive layer 251, the adhesive layer 251 being located between the first connection portion 230 and the first dielectric layer 220. The adhesive layer 251 includes a first sub adhesive layer 2511 and a second sub adhesive layer 2512, the first sub adhesive layer 2511 being provided around a side surface of the first connection portion 230, the second sub adhesive layer 2512 being located at an end surface of the first connection portion 230 remote from the contact portion 271.

In some embodiments, referring to fig. 21, the memory 200 further includes a second connection portion 260, and the second connection portion 260 is located between the first connection portion 230 and the first electrode and is electrically connected with the first connection portion 230 and the first electrode. The thickness of the second connection portion 260 is smaller than that of the first dielectric layer 220. Fig. 21 illustrates the first drain electrode 212 as an example.

In some embodiments, referring to fig. 21, memory 200 further includes a capacitor 290, capacitor 290 being coupled to contact 271. Illustratively, the capacitor 290 may be a ferroelectric capacitor.

As shown in fig. 23, some embodiments of the present application provide an electronic device 1000 including: memory 300, processor 400, input device 500, output device 600, and the like. Those skilled in the art will appreciate that the configuration of the electronic device shown in fig. 23 is not limiting of the electronic device 1000, and the electronic device 1000 may include more or fewer components than those shown in fig. 23, or may combine some of the components shown in fig. 23, or may differ in arrangement of components from those shown in fig. 23.

The memory 300 is used to store software programs and modules. The memory 300 mainly includes a storage program area and a storage data area, wherein the storage program area can store an operating system, application programs (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like; the storage data area may store data created according to the use of the electronic device (such as audio data, image data, phonebook, etc.), and the like. In addition, the memory 300 includes an external memory 310 and an internal memory 320. The data stored in the external memory 310 and the internal memory 320 may be transferred to each other. External memory 310 includes, for example, a hard disk, a USB flash disk, a floppy disk, and the like. The internal memory 320 includes, for example, dynamic random access memory (dynamic random access memory, DRAM), read only memory, and the like.

The processor 400 is a control center of the electronic device 1000 described above, connects various parts of the entire electronic device 1000 using various interfaces and lines, and performs various functions of the electronic device 1000 and processes data by running or executing software programs and/or modules stored in the memory 300, and calling data stored in the memory 300, thereby performing overall monitoring of the electronic device 1000. Optionally, the processor 400 may include one or more processing units. For example, the processor 400 may include a central processing unit (central processing unit, CPU), an artificial intelligence (artificial intelligence, AI) processor, a digital signal processor (digital signal processor, DSP) and a neural network processor, but may also be other specific integrated circuits (application specific integrated circuit, ASIC) and the like. In fig. 23, the processor 400 is taken as an example of a CPU, and the CPU may include an operator 410 and a controller 420. The arithmetic unit 410 acquires the data stored in the internal memory 320, processes the data stored in the internal memory 320, and returns the processed result to the internal memory 320. The controller 420 may control the operator 410 to process data, and the controller 420 may also control the external memory 310 and the internal memory 320 to store data or read data.

The input device 500 is used to receive input numeric or character information and to generate key signal inputs related to user settings and function control of the electronic device 1000. By way of example, input device 500 may include a touch screen and other input devices. Touch screens, also known as touch panels, collect touch operations by a user on or near the touch screen (e.g., operations by a user on or near the touch screen using any suitable object or accessory such as a finger, stylus, etc.), and actuate the corresponding connection device according to a predetermined program. Other input devices may include, but are not limited to, one or more of a physical keyboard, function keys (e.g., volume control keys, power switch keys, etc.), a trackball, mouse, joystick, etc. The controller 420 in the above-described processor 400 may also control the input device 500 to receive an input signal or not. In addition, the entered number or character information received by the input device 500, as well as key signal inputs generated in connection with user settings and function controls of the electronic device, may be stored in the internal memory 320.

The output device 600 is used for outputting signals corresponding to data inputted from the input device 500 and stored in the internal memory 320. For example, the output device 600 outputs a sound signal or a video signal. The controller 420 in the above-described processor 400 may also control the output device 600 to output a signal or not.

The thick arrow in fig. 23 is used to indicate data transmission, and the direction of the thick arrow indicates the direction of data transmission. For example, a one-way arrow between the input device 500 and the internal memory 320 indicates that data received by the input device 500 is transferred to the internal memory 320. For another example, a double-headed arrow between the operator 410 and the internal memory 320 indicates that data stored in the internal memory 320 may be transferred to the operator 410, and data processed by the operator 410 may be transferred to the internal memory 320. Thin arrows in fig. 23 represent components that the controller 420 can control. By way of example, the controller 420 may control the external memory 310, the internal memory 320, the operator 410, the input device 500, the output device 600, and the like.

Optionally, the electronic device 1000 may also include various sensors. Such as gyroscopic sensors, hygrometric sensors, infrared sensors, magnetometer sensors, etc., are not described in detail herein. Optionally, the electronic device 1000 may further include a wireless fidelity (wireless fidelity, wiFi) module, a bluetooth module, etc., which will not be described herein.

It is understood that the memory 200 provided in the embodiment of the present application may be used as the memory 300 in the electronic device 1000. For example, the memory provided in the embodiment of the present application may be used as the external memory 310 in the memory 300, or may be used as the internal memory 320 in the memory 300. In addition, the memory 200 provided by the application can be used in independent memory chip particles to replace DRAM components in various DRAM systems.

The technical effects that the electronic device 1000 provided in some embodiments of the present application can achieve are the same as those that the memory 200 described in any of the above embodiments can achieve, and are not described herein.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A memory, comprising:

a substrate;

a transistor on the substrate, the transistor comprising a first pole, the first pole being either a source or a drain;

a first dielectric layer on the transistor;

a first connection portion electrically connected to the first electrode through the first dielectric layer;

a contact portion located on the first connection portion and electrically connected to the first connection portion; the end face, far away from the first connecting part, of the contact part is a first end face, the end face, electrically connected with the first connecting part, of the contact part is a second end face, the contact part further comprises a side face for connecting the first end face and the second end face, and the side face is a curved surface;

And a second dielectric layer, at least part of which is positioned between any two adjacent contact parts.

2. The memory of claim 1, wherein the first end is circular or elliptical.

3. The memory according to claim 1, wherein an end face of the first connection portion electrically connected to the contact portion is a target end face, and an area of the first end face is larger than an area of the target end face.

4. The memory of claim 1, wherein an area of the second end face is greater than an area of the target end face;

the radial dimension of the contact portion gradually decreases in a direction perpendicular to and away from the substrate.

5. The memory of claim 4, wherein the second end face comprises a first sub-end face and a second sub-end face; the first sub-end surface is in contact with the first connecting part; the second sub-end surface at least partially surrounds the first sub-end surface, the second sub-end surface being in contact with a surface of the first dielectric layer remote from the substrate.

6. The memory of claim 1, wherein a surface of the second dielectric layer remote from the substrate is flush with a surface of the contact remote from the substrate.

7. The memory of claim 1, further comprising:

an adhesive layer located between the first connection portion and the first dielectric layer; the bonding layer comprises a first sub-bonding layer and a second sub-bonding layer, the first sub-bonding layer is arranged around the side face of the first connecting portion, and the second sub-bonding layer is located on the end face, far away from the contact portion, of the first connecting portion.

8. The memory of claim 1, further comprising:

a second connection portion located between the first connection portion and the first pole and electrically connected to the first connection portion and the first pole; the thickness of the second connection portion is smaller than that of the first dielectric layer.

9. The memory according to any one of claims 1 to 8, further comprising:

and a capacitor connected to the contact portion.

10. A method of manufacturing a memory, comprising:

forming a transistor on a substrate, the transistor comprising a first pole, the first pole being a source or drain;

forming a first dielectric layer overlying the transistor, the first dielectric layer including a first opening exposing a first pole of the transistor;

Forming a first connection portion within the first opening;

selectively depositing a conductive material on a target end surface of the first connection portion to form an intermediate contact portion; the target end face is an end face of the first connection portion away from the substrate.

11. The method of manufacturing according to claim 10, further comprising, prior to selectively depositing the conductive material on the target end face of the first connection portion:

and carrying out surface treatment on the target end face.

12. The method of producing according to claim 11, wherein the surface-treating the target end face comprises:

exposing the target end face to a set gas environment; alternatively, a reducing solution is coated on the target end face.

13. The method of manufacturing according to claim 10, wherein the forming a first connection portion within the first opening comprises:

forming a conductive layer overlying the first dielectric layer, the conductive layer including a portion embedded in the first opening;

and flattening the conductive layer until the first dielectric layer is exposed so as to form the first connection part in the first opening.

14. The method of manufacturing according to claim 13, further comprising, prior to said forming a conductive layer covering said first dielectric layer:

forming an intermediate adhesive layer covering a surface of the first dielectric layer remote from the substrate, and side walls and a bottom wall of the first opening;

and removing the part of the intermediate bonding layer, which is positioned on the surface of the first dielectric layer, which is far away from the substrate, in the process of flattening the conductive layer until the first dielectric layer is exposed, so as to form bonding layers on the side wall and the bottom wall of the first opening.

15. The method of manufacturing according to claim 10, wherein before forming the first connection portion in the first opening, further comprising:

and forming a second connecting part in the first opening, wherein the thickness of the second connecting part is smaller than that of the first dielectric layer.

16. The production method according to any one of claims 10 to 15, characterized by further comprising:

forming a second dielectric layer covering the intermediate contact;

removing the second dielectric layer with the first preset thickness, and removing the middle contact part with the second preset thickness, wherein the rest middle contact parts form contact parts; the first preset thickness is smaller than the thickness of the second dielectric layer, and the second preset thickness is smaller than the thickness of the middle contact portion.

17. The method of manufacturing according to claim 16, further comprising:

a capacitor is formed, the capacitor being connected to the contact.

18. An electronic device comprising a processor and a memory, the processor coupled to the memory; the memory is a memory according to any one of claims 1 to 9.