CN117093847A

CN117093847A - Statistical delay characteristic calculation method and system based on Gaussian process regression

Info

Publication number: CN117093847A
Application number: CN202310667138.6A
Authority: CN
Inventors: 刘宣钰; 何召锋
Original assignee: Shanghai Gulun Electronics Co ltd
Current assignee: Shanghai Gulun Electronics Co ltd
Priority date: 2023-06-07
Filing date: 2023-06-07
Publication date: 2023-11-21

Abstract

The invention discloses a statistical delay characteristic calculation method based on Gaussian process regression, which comprises the following steps: acquiring a variation parameter in a target transistor; randomly sampling the variation parameters in the target transistor, and calculating a simulation result as a sample data set through simulation; inputting the sample data set into a Gaussian process regression model and training the model; performing model calculation on a sample data set based on the trained model to obtain a first test result, performing statistical analysis on the first test result to obtain a probability distribution condition of circuit delay, and calculating to obtain a mean value and a standard deviation; wherein, the statistical delay characteristic exists in the standard cell library in the form of standard deviation. The method is an optimization of the traditional Monte Carlo method, and aims to use a Gaussian process regression model to replace a traditional Monte Carlo circuit simulator calculation method, establish a high-quality statistical delay characteristic calculation model, meet the design requirements of the current integrated circuits, improve the calculation efficiency and save the cost.

Description

Statistical delay characteristic calculation method and system based on Gaussian process regression

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a statistical delay characteristic calculation method and system based on Gaussian process regression.

Background

The integrated circuit industry is one of the main high-tech industries supporting the development of the productivity of the current society, is also the basic stone of other high-tech technologies, accelerates the informatization and intelligence process of the society, and has penetrated into various industries of military, economic and civil life to become an irreplaceable part.

In the field of integrated circuit design, circuit design can be divided into full custom design and half custom design, and the full custom design is superior to the half custom design in terms of circuit performance, power consumption and other indexes, but because each transistor in the full custom circuit needs to be designed manually, the manpower and time cost input in the design process are extremely high, and the design method is not suitable for ultra-large scale integrated circuit design, therefore, a digital integrated circuit is usually subjected to modularized design by taking a standard unit circuit as a basis, namely the half custom design. The semi-custom design has high efficiency and strict parameter and specification requirements for standard unit circuits. The standard cell library contains various characteristic parameters of the standard cell circuit, such as area, delay, power consumption, etc., which are critical to the chip design. Today, ensuring the accuracy of circuit functions and timing constraints is a great challenge to chip designers. Static timing analysis (Static Timing Analysis, STA) is one of the most common and successful timing analysis methods in digital circuit design for the last 20 years, however, in recent years, the increase of predictability deviation in semiconductor devices, the lack of accuracy of the static timing analysis method under specific process conditions has raised a great deal of attention, and the lack of accurate and rapid high-performance timing analysis tools is a major problem in the current integrated circuit design face. The reason for this phenomenon is that the process fluctuation of integrated circuits below 65nm becomes more and more difficult to predict in terms of manufacturing, the electrical characteristics of the circuits become extremely sensitive to weak variations between semiconductor devices and device interconnections, the semiconductor parameters deviate from ideal values in the actual production process, the circuit parameters are also deviated in the actual application by the influence of external environments, and these small variations have a great influence On the performance of the whole circuit, which is called On-chip variation (On ChipVariation, OCV). The presence of the variable parameters increases the difficulty of timing analysis, and the STA method cannot completely guarantee the convergence of the timing characteristics of the circuit, so that a more advanced statistical static timing analysis method (StatisticalStatic Timing Analysis, SSTA) is created. SSTA expresses circuit delay in the form of probability distribution, describes the influence of a variation parameter on the circuit delay, calculates an error range, and the expression is called the statistical delay characteristic of the circuit. The calculation of the statistical delay characteristic must perform statistical characterization on the standard cell library, and this process consumes a lot of time, which is a bottleneck encountered in the circuit statistical analysis process.

The most commonly used method for calculating the statistical delay characteristics is the Monte Carlo (MC) method, which obtains the delay distribution of a circuit by randomly sampling, simulating calculation and statistical analysis on the variation parameters in the transistor, and the calculation accuracy and the calculation amount of the method are increased along with the increase of the sampling times. In order to obtain accurate Monte Carlo calculation results, the characterization of the standard cell library often requires weeks or even months, and the investment time and cost are high. Even if there is a certain limitation, the calculation result of Monte Carlo is still considered to be the most accurate by the industry, so the method is generally used as a reference for the precision of other methods, and meanwhile, improvement and optimization of the method are also important to research.

In terms of circuit statistical delay characteristic computation, in order to solve the above-mentioned problems, some electronic design automation (Electronic Design Automation, EDA) tool suppliers have developed simple and effective sensitivity analysis (Sensitivity Analysis, SA) techniques, however SA techniques ignore the potential correlation between device variation parameters and have not been widely adopted by the design industry. Ganapathy et al propose a circuit delay calculation method based on multiple regression, which can predict circuit delay under various working conditions, and the error between a model calculation result and a simulation result is less than 10%, but the circuit delay calculation method based on multiple regression only considers the influence of temperature factors on delay. Gao et al propose a method of combining a high-efficiency dimension reduction technique (Efficient Dimension Reduction, EDR) with an artificial neural network (Artificial Neural Network, ANN), which reduces the number of variable parameters used in the calculation process, and can reduce the simulation amount, but the dimension reduction process of the method is complex and key parameter information is easy to lose. Miguel et al propose a standard cell circuit statistical characterization method based on a combination of statistical experimental design (Statistical Design of Experiments, S-DoE) and Response surface modeling (Response SurfaceModeling, RSM), which is an improvement of the SA technique, retains the correlation between the varying parameters, improves the computational accuracy compared to SA, but still has a gap compared to the monte carlo method. Naswali et al propose a deep neural network model that calculates the relationship between circuit delay and Input transfer delay (Input transfer) and Output load (Output load), which is relatively complex and does not take into account the effects of circuit variation parameters.

In view of this, it is necessary to build a high-quality statistical delay characteristic calculation model, which meets the current design requirements of integrated circuits, improves design efficiency, saves cost, and has important significance for the development of the current integrated circuit industry.

Disclosure of Invention

The invention aims to provide a statistical delay characteristic calculation method and a system based on Gaussian process regression, which are used for optimizing a traditional Monte Carlo method, and the purpose is to replace a circuit simulator (Simulation Program with Integrated Circuit Emphasis, SPICE) calculation method in the traditional Monte Carlo by using a Gaussian process regression model. According to the invention, the transistor change parameters are used as the input of the model, the circuit delay is used as the output of the model, the calculation speed is high through the Gaussian process regression model, the model generalization performance is strong, the calculation result accords with the industrial standard, a large amount of resources and time are saved, and the calculation efficiency of the Gaussian process regression model is improved.

The invention provides a statistical delay characteristic calculation method based on Gaussian process regression, which comprises the following steps:

Acquiring a variation parameter in a target transistor;

randomly sampling the variation parameters in the target transistor, and calculating a simulation result as a sample data set through simulation;

inputting the sample data set into a Gaussian process regression model and training the Gaussian process regression model;

performing model calculation on the sample data set based on the trained Gaussian process regression model to obtain a first test result, performing statistical analysis on the first test result to obtain a probability distribution condition of circuit delay, and calculating to obtain a mean value and a standard deviation;

wherein, the statistical delay characteristic exists in the standard cell library in the form of standard deviation.

Preferably, before inputting the sample dataset into a gaussian process regression model, the method further comprises:

selecting a mean function and a kernel function to construct the Gaussian process regression model:

when the kernel function is a radial basis function:

wherein, the radial basis function formula stores super parameters: signal variance sigma ² _f And a feature scale l;

selecting a linear covariance function:

wherein m=diag (λ ₁ ,λ ₂ .....λ _n ) Lambda characterizes the characteristic length scale, controls the smoothness of the function,is the noise variance; delta _ij Is a kronecker function; and/or the number of the groups of groups,

Selecting a Matern covariance function:

setting a kernel function hyper-parameter initial value, and constructing a likelihood function L according to a Gaussian process regression model, wherein theta= (L, sigma) is as follows _f ) The optimal combination of the super-parameter theta values is solved through the formula:

wherein, assume for a given input sample: x= [ X ] ₁ ,x ₂ ,x ₃ ,....x _n ] ^T Output is y= [ y ] ₁ ,y ₂ ,y ₃ ,....y _n ] ^T Without noise: y is _i ＝f(x _i ) A priori distribution of output vector y: y-N (0, K (X, X)), K (X, X) is an N matrix, θ, σ _f And l are both hyper-parameters.

Preferably, the training the gaussian process regression model further comprises:

under the 40nm process condition, sequentially selecting preset combination logic units according to the number of the circuit transistors and the logic function complexity to test the reliability of the Gaussian process regression model;

aiming at different circuit structures, the number of input variables required by the Gaussian process regression model is different, and the calculation method of the input variables is as follows:

V＝v _global +v _local ·N，

wherein v is _global For the number of global variation parameters, v _local N is the number of transistors, which is the number of locally varying parameters.

Preferably, the inputting the sample dataset into a gaussian process regression model and training the gaussian process regression model comprises:

Taking the obtained training set as the input of an initial Gaussian process regression model, taking circuit delay as the output of the initial Gaussian process regression model, training the initial Gaussian process regression model to optimize super parameters, and obtaining a trained Gaussian process regression model;

testing the trained Gaussian process regression model by adopting a test set to obtain a model test result;

verifying the prediction accuracy of the trained Gaussian process regression model according to the model test result to obtain a verification result, and iteratively updating the Gaussian process regression model according to the verification result;

the sample data set is divided into a training set and a testing set according to a preset proportion.

Preferably, the obtaining the variation parameter in the target transistor includes:

determining the type and the number of parameters with deviation;

classifying and extracting the parameters with deviation to obtain extracted target variation parameters;

the target change parameters are normally distributed, and the average value is used as the standard value of the target change parameters.

Preferably, the variation parameters include a process variation parameter, a voltage variation parameter and a temperature variation parameter, wherein the process variation parameter includes a global variation parameter that deviations of all transistors on a chip are the same and a local variation parameter that deviations of transistors in different areas on the same chip are different; the voltage variation parameters comprise variation parameters of power supply voltage and variation parameters of internal voltage of the circuit; the temperature variation parameter includes a variation parameter of an ambient temperature and a variation parameter of a transistor temperature.

Preferably, the method further comprises the step of evaluating the trained gaussian process regression model:

performing simulation calculation on the sample data set by adopting a SPICE simulator to obtain a second test result;

and carrying out the same statistical analysis treatment on the first test result and the second test result to obtain the probability distribution condition of circuit delay, calculating to obtain a mean value and a standard deviation, comparing the final result with the running time, and updating a Gaussian process regression model according to the compared result.

The invention aims to provide a statistical delay characteristic computing system based on Gaussian process regression, which comprises the following components:

the parameter extraction module is used for acquiring the variation parameters in the target transistor;

the sampling module is used for randomly sampling the variation parameters in the target transistor, and calculating a simulation result through simulation to be used as a sample data set;

the model training module is used for inputting the sample data set into a Gaussian process regression model and training the Gaussian process regression model;

the calculation module is used for carrying out model calculation on the sample data set based on the trained Gaussian process regression model to obtain a first test result, carrying out statistical analysis on the first test result to obtain a probability distribution condition of circuit delay, and calculating to obtain a mean value and a standard deviation;

The invention aims to provide a statistical delay characteristic computing device based on Gaussian process regression, which comprises a memory and a processor, wherein the memory stores computer readable instructions, and the processor realizes the statistical delay characteristic computing method based on Gaussian process regression according to the embodiment of the invention when executing the computer readable instructions.

It is an object of the present invention to provide a computer readable medium storing a computer program which, when executed by one or more processors, implements a method for computing statistical delay characteristics based on gaussian process regression according to an embodiment of the present invention.

Aiming at the prior art, the invention has the following beneficial effects:

the invention provides a statistical delay characteristic calculation method and a system based on Gaussian process regression, which are used for optimizing a traditional Monte Carlo method, and aims to replace a traditional Monte Carlo circuit simulator (Simulation Program with Integrated Circuit Emphasis, SPICE) calculation method by using a Gaussian process regression model.

According to the invention, the transistor change parameters are used as the input of the model, the circuit delay is used as the output of the model, the calculation speed is high through the Gaussian process regression model, the model generalization performance is strong, the calculation result accords with the industrial standard, a large amount of resources and time are saved, and the calculation efficiency of the Gaussian process regression model is improved.

The method is improved on the basis of the Monte Carlo method, and solves the limitation of the simulation link in the calculation process of the Monte Carlo method. The model is used for constructing a data set for training by sampling the internal variation parameters of the transistor, and the trained Gaussian process regression model is used for replacing SPICE to complete subsequent work. The calculation amount and the simulation time of the model are far less than those of the Yu Mengte Carlo method, and the calculation accuracy accords with the industrial standard.

Drawings

FIG. 1 is a schematic diagram showing steps of a statistical delay characteristic calculation method based on Gaussian process regression in an embodiment of the invention;

FIG. 2 is a diagram showing an example of the generation cause of the variation parameter according to an embodiment of the present invention;

FIG. 3 is a flowchart illustrating a calculation based on Gaussian process regression according to an embodiment of the invention;

FIG. 4 shows experimental results under a 40nm process in an embodiment of the invention;

FIG. 5 shows experimental results under a 28nm process in an embodiment of the invention;

FIG. 6 shows the result of error distribution at 40nm in one embodiment of the present invention;

FIG. 7 shows the error distribution at 28nm in an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Example 1

As shown in fig. 1, the present invention provides a statistical delay characteristic calculation method based on gaussian process regression, which includes:

s1: acquiring a variation parameter in a target transistor; the variation parameters comprise a process variation parameter, a voltage variation parameter and a temperature variation parameter, wherein the process variation parameter comprises a global variation parameter with the same deviation of all transistors on a chip and a local variation parameter with different deviations of transistors in different areas on the same chip; the voltage variation parameters comprise variation parameters of power supply voltage and variation parameters of internal voltage of the circuit; the temperature variation parameter includes a variation parameter of an ambient temperature and a variation parameter of a transistor temperature. In the process of manufacturing and using the chips in the implementation, due to the change of the production conditions and the external environment during application, the running speeds of transistors of the same type on different chips of the same wafer and different areas of the same chip are different, so that the circuit parameters are deviated, namely OCV is generated, and the related circuit parameters are called as variation parameters. OCV significantly affects the performance parameters of the circuit, particularly the circuit delay, and the reasons for these parameter variations are shown in fig. 2:

(1) Process for producing a solid-state image sensor

The effect of the process is mainly a variation of the transistor device parameters. The transistor device is easy to dope impurities in the manufacturing process, so that the parameters such as the concentration, the density, the oxide thickness, the diffusion depth and the like of the device generate errors; meanwhile, during the manufacturing process, the length and width of the grid electrode of the transistor and the length and width of the interconnection line are slightly changed, errors caused by the changes are permanent, and the electric characteristics of the transistor are changed due to the change of physical parameters, so that the circuit performance is finally affected. From the circuit design perspective, there is a spatial correlation of process-induced bias, and transistor variation parameters for different chips on the same wafer, and for different regions on the same chip, to better map this spatial correlation, the transistor variation parameters are divided into two main categories: the bias of all transistors on the chip is the same global variation parameter, and the bias of transistors in different areas on the same chip is different local variation parameters.

(2) Voltage (V)

The voltage value specified in the design process of the circuit may be different from the value of the chip in actual use, and the voltage of the transistor in actual use is not stable. For a transistor, the transmission rate depends on the voltage, when the voltage is high, the delay increases slowly, the delay increases rapidly with the decrease of the voltage, and the delay changes in proportion to the voltage to a great extent. The reason for the unstable voltage is mainly that the power supply voltage is unstable and voltage drop exists in the circuit, the local voltage of the circuit is reduced due to parasitic resistance exists between circuit interconnection lines, and the reverse self-inductance voltage is generated due to the fact that the current is rapidly changed in a short time, and the self-inductance effect between the lines also reduces the voltage. Therefore, instability of the voltage in actual use causes instability of circuit delay, but blindly increasing the power supply voltage increases circuit loss, and how to find a suitable balance point is also an important link of circuit design.

(3) Temperature (temperature)

Currently, temperature variations are also important factors affecting circuit delay, and OCV includes two types of temperature variations, one is a change in ambient temperature and the other is a change in transistor temperature. Temperature has a significant impact on the performance of the circuit, and when the circuit is in operation, transistor temperature changes with the state of the entire circuit, which is mostly due to circuit power consumption. The power consumption of the circuit can change the temperature of surrounding areas, the mobility of electrons and holes in the transistor is affected, when the temperature is increased, the mobility of the electrons and the holes can be slowed down, the transmission rate of the transistor is slowed down, and the circuit delay is increased.

Specifically, the step S1 of acquiring the variation parameter in the target transistor includes:

determining the type and the number of parameters with deviation;

S2: randomly sampling the variation parameters in the target transistor, and calculating a simulation result as a sample data set through simulation; according to the embodiment of the invention, 1000 times of random sampling is carried out on each dimension of variation parameters, the result is calculated through the SPICE simulator to serve as all data sets of the experiment, meanwhile, the data sets are divided, 80% of data are used as training sets, and 20% of data are used as test sets.

S3: inputting the sample data set into a Gaussian process regression model and training the Gaussian process regression model; and taking the extracted transistor change parameters as the input of a model, taking circuit delay as the output of the model, and training the training set data.

S4: performing model calculation on the sample data set based on the trained Gaussian process regression model to obtain a first test result, performing statistical analysis on the first test result to obtain a probability distribution condition of circuit delay, and calculating to obtain a mean value and a standard deviation;

s5: and (3) evaluating the trained Gaussian process regression model:

The statistical delay characteristic exists in the standard cell library in the form of standard deviation, and the result of SPICE calculation is the circuit delay corresponding to each sampling and is not the statistical delay characteristic. The circuit statistical delay characteristic is the circuit delay distribution situation obtained by the statistical analysis of all simulation results, and the average value of the distribution is standard delay without deviation. The standard deviation sigma of the delay distribution of the circuit is generally recorded in the Liberty file, and is a writing format of statistical delay characteristics in the Liberty file and is also a two-dimensional lookup table. The two-dimensional index of the lookup table is the same as the common delay and the power consumption, and is respectively input transmission delay time and output total load.

The OCV has a great influence on the performance of the circuit, particularly on the circuit delay, and the difficulty of time sequence analysis is increased. In order to obtain more accurate SSTA results, a more accurate and efficient statistical delay characteristic calculation method is required. The Gaussian process regression (Gaussian Process Regression, GPR) adopted in the implementation is a common one in the supervised learning algorithm, the input samples contain training data and labels, the relation between the input features and the sample labels is mastered through analysis and calculation of the samples, and the optimal model is selected through continuous iteration and optimization of the model, so that the accuracy of model prediction is ensured, and the model performance is ensured. In short, gaussian process regression is one of regression analysis algorithms, a change trend is fitted by searching a rule of sample change, new data is predicted, and a kernel function of a model is important in the whole process.

The one-dimensional Gaussian distribution is uniquely determined by the mean value and the variance of the data, and if the one-dimensional Gaussian distribution is expanded into a multi-dimensional Gaussian distribution, the mean value and the variance of the data need to be changed from one to a plurality of data, namely the multi-dimensional Gaussian distribution is determined by a mean vector and a covariance matrix. If the random variables of the multidimensional Gaussian distribution are countless and are state quantities of discrete time, namely the random variables are functions changing along with time, wherein the mean value of each moment is represented by a mean value function, the variances of two different moments are represented by covariance functions, and the mean value of the new one-dimensional Gaussian distribution can be determined according to the mean value function, namely the infinite-dimensional Gaussian distribution is called a Gaussian process. The training flow of the Gaussian process regression model is shown in fig. 1, the basic idea is that the prior distribution of the Gaussian process is needed to be assumed, the posterior distribution is obtained by updating the Gaussian process after the training sample is calculated by the Bayesian theory, the selection of the kernel function in the process has great influence on the model result, the hyper-parameters exist in the kernel function, and the optimal hyper-parameter combination can be selected by using the maximum likelihood estimation method. Compared with machine learning methods such as a neural network and a support vector machine, the model has strong generalization capability, fewer model parameters needing to be adjusted, simple operation and easy realization, and a prediction result has probability significance, and the principle of Gaussian process regression is deduced as follows:

The gaussian process is obtained by expanding a multidimensional gaussian distribution to an infinite dimension, and can be determined by a mean function m (x) and a covariance function k (x, x'):

f(x)～GP(m(x),k(x,x′))，

wherein:

m(x)＝E[f(x)]，

k(x,x′)＝E[(f(x)-m(x))(f(x′)-m(x′))]，

where x, x' e R is the input variable, the mean function m (x) is typically set to 0 for simplicity of calculation. Assume for a given input sample: x= [ X ] ₁ ,x ₂ ,x ₃ ,....x _n ] ^T Output is y= [ y ] ₁ ,y ₂ ,y ₃ ,....y _n ] ^T Without noise:

y _i ＝f(x _i )，

by the above formula of f (x) and y _i The prior distribution of the output vector y can be obtained by the calculation formula of (a):

y～N(0,K(X,X))，

in the above formula, K (X, X) is an n matrix, and for a new input vector X, a predicted value y is obtained according to a gaussian process principle, and a training sample output vector y obeys a joint gaussian distribution:

the conditional probability of the predicted value y x can be obtained according to the bayesian theorem, namely, the posterior distribution of the gaussian process is as follows:

wherein:

cov(y*)＝K(x _* ，x _* )-K(x _* ，X)K(X，X) ^-1 K(X，x _* )，

in the presence of noise:

y _i ＝f(x _i )+ρ，

ρ is a noise factor, ρ to N (0, σ) _n ² )，Is the noise variance, and I is the identity matrix.

Wherein I is an identity matrix, and the joint Gaussian distribution is:

in the embodiment, when the model integral structure uses the Monte Carlo method to calculate the statistical delay characteristic, the simulation link has the limitation of long calculation time. The sampling times are generally 1000-3000 times, so that the workload of counting the time delay characteristic is expanded by thousands of times compared with the workload of common time delay. The embodiment of the invention optimizes the Monte Carlo calculation method based on the Monte Carlo calculation method, adopts a Gaussian process regression model to replace the traditional SPICE circuit simulation link, and aims to reduce the calculation cost brought by the simulation link, and the calculation flow based on the Gaussian process regression model is shown in the figure 3:

The model takes transistor change parameters as input, circuit delay as model output, and the experimental concrete operation steps are as follows:

(1) And extracting transistor variation parameters. The number of the variable parameters is different under different process conditions, especially the local variable parameters are independently changed by taking a transistor as a unit, so that the number of the input variables is different in different processes, different circuits and the like.

(2) And (5) randomly sampling. The method carries out 1000 times of random sampling on each dimension of variation parameters, calculates the result through the SPICE simulator to serve as all data sets of the experiment, divides the data sets, takes 80% of data as a training set and takes 20% of data as a testing set.

(3) And (5) model training. The method takes the extracted transistor change parameters as the input of a model, takes circuit delay as the output of the model, and trains training set data.

(4) And (5) carrying out result statistical analysis, and calculating a circuit distribution mean value and a standard deviation. The method uses a Gaussian process model and a SPICE simulator to calculate test set data respectively, the calculation result selects the same statistical analysis method, probability distribution of circuit delay is obtained, mean value and variance are calculated, and the result is compared with running time.

Specifically, the kernel function is the central moment of random output variables corresponding to two random input points in space, is used for measuring the similarity or correlation degree between different samples, the kernel function is critical to the Gaussian process model, the covariance function is the kernel function of the model according to the basic concept of the Gaussian process, the kernel function has a plurality of kinds, different kinds of kernel functions determine the performance of the Gaussian process model, the kernel function can influence the Gaussian distribution of predicted values and further influence the final predicted result, so the selection of a proper kernel function is the key of model establishment, and the common kernel function is as follows:

(1) Radial basis function (Radial Basis Function, RBF):

radial basis functions, also known as gaussian kernel functions, are currently the most commonly used kernel functions. There is a super-parameter in the radial basis function, signal variance sigma ² _f And a feature scale l. The Gaussian kernel function has the advantages of stable performance, compact form, fewer parameters and the like, and can enable a random process to be more stable and a result to be smoother, so that the function of the embodiment of the invention is used as the kernel function of the model.

(2) Linear covariance function:

where m=diag (λ ₁ ,λ ₂ .....λ _n ) Lambda characterizes the characteristic length scale, controls the smoothness of the function, Is the noise variance; delta _ij Is a kronecker function.

(3) Matern covariance function:

the above formula of each kernel function contains a certain amount of hyper-parameters, the setting of the hyper-parameters can directly influence the fitting effect of the model, if the kernel function is properly selected in an ideal state, the Gaussian process regression model can be suitable for all nonlinear systems, and conversely, the unreasonable setting of the hyper-parameters can possibly lead to the learning failure of the whole Gaussian process model. In summary, the hyper-parameter selection method is also an important point and a difficult point in the gaussian process modeling process. The kernel function described in this embodiment further includes: rational quadratic covarianceA function, a periodic covariance function, a neural network covariance function, a Bn spline curve kernel function, a Fisher kernel function and a String kernel function. For the calculation of two super parameters of a Gaussian kernel function, a maximum likelihood estimation method is a basic method for solving, and likelihood functions of a Gaussian process regression model structure are shown as follows, so that θ= (l, sigma) _f ) The optimal theta value combination can be solved by the formula.

In the embodiment of the invention, python is used as a programming language, pytorch1.3 is used as a network frame in the experiment, and the experiment is performed in a Linux operating system environment. Two groups of comparison experiments are carried out by selecting the 40nm process library and the 28nm process library which are existing in the prior art, and the simulator used in the experiments is a Nanospeck high-speed circuit simulator.

In various embodiments of the application, a 40nm process library is selected in the experiment, 40nm belongs to the mature process, and the device contains a small number of variable parameters and can be used for preliminarily testing the reliability of the model. In terms of circuit selection, simple combinational logic units are sequentially selected according to the number of circuit transistors and the complexity of logic functions: inverter INV, arithmetic unit: full adder ADDF, sequential logic Unit: d flip-flop DFF. There are 2 local variation parameters at 40nm process: the oxide thickness (DTOXE) and the threshold voltage (Vth) are independently variable for each device, so the number of input variables required by the model is different for different circuit structures, and the calculation method of the input variables is as follows:

V＝v _global +v _local ·N，

wherein v is _global For the number of global variation parameters, v _local N is the number of transistors, which is the number of locally varying parameters. The experiment is carried out under the conditions of standard voltage of 1.8V and room temperature of 25 ℃, and the specific experimental conditions are shown in table 1:

TABLE 1 40nm experimental conditions

In various embodiments of the application, the experiment II selects a 28nm process library, the 28nm process is more advanced than the 40nm process, the precision requirement is high, and the number of the variation parameters is increased. In terms of circuit selection, experiments II still select complex logic units according to the complexity of circuit structures and logic functions: two-input AND gate AND2, one-out-of-three data selector MUX3, sequential logic unit with set AND reset functions: the flip-flop SDQN. 8 local variation parameters exist under the 28nm process, the experiment is carried out under the standard voltage of 0.9V and the room temperature of 25 ℃, and the specific experimental conditions are shown in table 2:

TABLE 2 28nm experimental conditions

In this example, for accurate assessment of model accuracy, mean absolute error (Mean Absolute Error, MAE), mean absolute percent error (Mean Absolute Percentage Error, MAPE), root mean square error (Root MeanSquared Error, RMSE) and R are used herein ² The evaluation index as a model was evaluated, and the correlation formula was as follows:

in the middle ofy _i Representing the actual value, in this experiment, the SPICE simulator calculates the result, y _i Representing predicted values, in this embodiment model predicted results, N being the number of predicted values,is the mean value. The above indexes evaluate the model fitting effect from different angles, and MAE and RMSE essentially measure the absolute deviation between the predicted value and the actual value, the values and the actual value and the predicted value are in the same order of magnitude, and the statistical delay characteristic is measured in picoseconds (ps, 1 ps=10 ^-12 s); RMSE measures the relative deviation between the predicted value and the actual value as a percentage value; r is R ² The evaluation is an important index for reflecting the fitting effect of the model, is one of evaluation criteria for the performance of the model, and is R under the optimal condition ² =1, meaning that the predicted and actual values are identical, R ² The closer to 1 the value of (c) indicates the better the performance of the model, and conversely, the closer to 0 the worse the model performance. In this example, evaluation indexes of two experiments were counted as shown in table 3.

TABLE 3 model evaluation index

As can be seen from the experimental results in Table 3, the MAE and RMSE indices of all subjects were less than 0.2, the MAPE was less than 1%, and R ² The evaluation was greater than 0.9. The above index shows that the absolute deviation and the relative deviation between the predicted value and the actual value are smaller, and the prediction performance of the model is excellent. In order to more intuitively reflect the fitting effect of the model, the embodiment makes statistics on the specific distribution of the prediction result and the error condition. Referring to fig. 4 and 5, the fitting effect of experiment one and experiment two is shown, in which the abscissa represents the actual value, the SPICE simulator result, the ordinate represents the predicted value, and the gaussian process model calculation result. In the figure, the straight line y=x represents the ideal fitting condition that the predicted value is identical to the actual value, the points in the figure are model predicted results, and the distribution of the points is closer to the straight lineThe better the line demonstrates the model fitting effect. From fig. 4 and fig. 5, it is obvious that the model prediction results are distributed near the straight line, and the deviation is smaller, which proves that the regression prediction effect of the gaussian process model is better.

Fig. 6 and 7 show the error distribution of two experiments, in which the abscissa represents the predicted value, the ordinate represents the absolute error between the predicted value and the actual value, and the red line represents the relative error (AbsolutePercentage Error, APE) between the predicted value and the actual value, and the APE calculation method is as follows:

The straight line in fig. 6 represents 1% APE and 5% APE in fig. 7, and the errors of all data points in both experiments remain within the straight line range, i.e., the relative errors of all samples in the 40nm experiment are within 1% and the 28nm experiment is within 5%. In contrast, the overall effect of the 40nm experiment is better than 28nm because the variation parameters are increased and the statistical delay value is smaller overall under the 28nm process, so that the prediction difficulty of the model is increased, and meanwhile, under the condition that the absolute error of the model prediction is unchanged, the relative error is increased due to the reduction of the actual value. In practical industrial application, the acceptable error range of the statistical delay characteristic of the standard cell library is 10%, so that the prediction accuracy of the Gaussian process regression model meets the industrial standard. The statistical delay characteristics are in the form of standard deviation in the standard cell library, so the standard deviation of the delay profile is also calculated in this example, as shown in table 4.

Table 4 results of comparison with Monte Carlo method

Table 4 shows the results of the comparison of accuracy and computation time of the Gaussian process regression model and the Monte Carlo model, σ _M Sum sigma _G Standard deviation calculated using SPICE simulator and standard calculated using gaussian process regression model for monte carlo model, respectively And (3) difference. As can be seen from Table 4, the statistical delay characteristic calculation method based on the Gaussian process regression model has an average relative error of less than 2% and an improvement of about 10-80 times in calculation efficiency compared with the Monte Carlo method.

The embodiment of the invention relates to a statistical delay characteristic calculation method based on Gaussian process regression, which takes a transistor change parameter as the input of a model and takes circuit delay as the output of the model. In the sampling link of the variable parameter, the method is the same as the Monte Carlo method; in the calculation link, the Monte Carlo method selects the traditional SPICE simulation, the calculation speed is low, the simulation time is long, the calculation speed of the Gaussian process regression model is high, the generalization performance of the model is strong, and a great amount of resources and time are saved while the calculation result accords with the industrial standard. In this embodiment MAE, RMSE, MAPE and R are selected ² As model evaluation indexes, all indexes show good effects. Finally, the statistical analysis is performed on the calculation result of the gaussian process regression model, and the result shows that the average relative error of all the test data is less than 2%, and compared with the SPICE simulator, the calculation efficiency of the gaussian process regression model is improved by about 10-80 times.

Example two

Based on the same conception, the invention also provides a statistical delay characteristic calculation system based on Gaussian process regression, which comprises the following steps:

The evaluation module is used for evaluating the trained Gaussian process regression model and specifically comprises the following steps:

the comparison data acquisition unit is used for performing simulation calculation on the sample data set by adopting a SPICE simulator to obtain a second test result;

The comparison and updating unit is used for obtaining the probability distribution condition of circuit delay after the first test result and the second test result are subjected to the same statistical analysis processing, calculating to obtain a mean value and a standard deviation, comparing the final result with the running time, and updating a Gaussian process regression model according to the compared result.

The system adopted by the embodiment is improved on the basis of the Monte Carlo method, and the limitation of the simulation link in the calculation process of the Monte Carlo method is solved.

Example III

Based on the same conception, the application also provides electronic equipment, which comprises the statistical time delay characteristic calculation method based on Gaussian process regression.

Also, the present application also protects a computer-readable storage medium loaded with a computer program for implementing the statistical delay characteristic calculation method based on Gaussian process regression.

In the above embodiments, the implementation may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program. The computer program comprises one or more computer programs. When the computer program is loaded and executed on a computer, the flow or functions according to the embodiments of the present application are fully or partially produced. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer program may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer program may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, DDL (digital subscriber line)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a Digital Video Disc (DVD)), or a semiconductor medium (e.g., a solid state disk (DDD)), etc.

It should be noted that in the above-described embodiments, the terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," and "having" are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein should not be construed as necessarily requiring their performance in the particular order discussed or illustrated, unless specifically indicated to be performed in the order of the steps set forth. It should also be appreciated that additional or alternative steps may be employed.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A statistical delay characteristic calculation method based on Gaussian process regression is characterized by comprising the following steps:

acquiring a variation parameter in a target transistor;

2. The method for computing statistical delay characteristics based on gaussian process regression according to claim 1, wherein said inputting said sample dataset into a gaussian process regression model is preceded by:

when the kernel function is a radial basis function:

selecting a linear covariance function:

selecting a Matern covariance function:

3. The method of claim 1, wherein training the gaussian process regression model further comprises:

V＝v _global +v _local ·N，

4. The method of claim 1, wherein the inputting the sample dataset into a gaussian process regression model and training the gaussian process regression model comprises:

5. The method of claim 1, wherein the obtaining the variation parameter in the target transistor comprises:

Determining the type and the number of parameters with deviation;

6. The method for calculating the statistical delay characteristics based on Gaussian process regression according to claim 1, wherein the variation parameters comprise a process variation parameter, a voltage variation parameter and a temperature variation parameter, wherein the process variation parameter comprises a global variation parameter with the same deviation of all transistors on a chip and a local variation parameter with different deviations of transistors in different areas on the same chip; the voltage variation parameters comprise variation parameters of power supply voltage and variation parameters of internal voltage of the circuit; the temperature variation parameter includes a variation parameter of an ambient temperature and a variation parameter of a transistor temperature.

7. The gaussian process regression-based statistical delay characteristics calculation method according to claim 1, further comprising the step of evaluating a trained gaussian process regression model:

8. A statistical delay characteristic computing system based on gaussian process regression, comprising:

9. A statistical delay characteristic computing device based on gaussian process regression, comprising a memory and a processor, wherein the memory has stored therein computer readable instructions, which when executed by the processor, implement the statistical delay characteristic computing method based on gaussian process regression as claimed in any one of claims 1 to 7.

10. A computer readable medium storing a computer program which, when executed by one or more processors, implements the statistical delay characteristic calculation method based on gaussian process regression according to any of claims 1 to 7.