CN117082918A

CN117082918A - Display device and method of manufacturing the same

Info

Publication number: CN117082918A
Application number: CN202310538956.6A
Authority: CN
Inventors: 黄度渊; 金光民; 金起旭; 郭源奎
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2022-05-16
Filing date: 2023-05-12
Publication date: 2023-11-17

Abstract

A display device and a method of manufacturing the display device are disclosed. The display device includes a substrate, a pixel circuit including a first transistor and a second transistor, an organic light emitting diode connected to the pixel circuit, a connection line including a first connection line connected to the first transistor and a second connection line connected to the second transistor, and a disconnection portion disconnecting the first connection line and the second connection line from each other.

Description

Display device and method of manufacturing the same

Cross Reference to Related Applications

The present application is based on and claims priority of korean patent application No. 10-2022-0059839 filed in the korean intellectual property office at 2022, 5, 16 and 10-2023-0021589 filed in 2023, 2, 17, the disclosures of which are incorporated herein by reference in their entirety.

Technical Field

One or more embodiments relate to a display device and a method of manufacturing the display device.

Background

The display device visually displays the data. The display device is used as a display of a small product such as a mobile phone and the like or a large product such as a television and the like.

The display device includes a plurality of pixels that receive an electrical signal and emit light to display an image to the outside. Each pixel includes a display element. For example, an organic light emitting display device includes an Organic Light Emitting Diode (OLED) as a display element. In a general organic light emitting display device, a thin film transistor and an organic light emitting diode are formed on a substrate. The organic light emitting display device operates when the organic light emitting diode itself emits light.

Recently, as the uses of display devices are diversified, various attempts have been made to improve the quality of the display devices.

Disclosure of Invention

One or more embodiments include a display device and a method of manufacturing a display device that can perform array testing of pixel circuits such that yield of a manufacturing process is improved.

However, this purpose is an example, and the scope of the disclosure is not limited thereby.

Additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the embodiments of the disclosure.

According to one or more embodiments, a display device includes a substrate, a pixel circuit disposed on the substrate and including a first transistor and a second transistor, an organic light emitting diode connected to the pixel circuit, a connection line including a first connection line connected to the first transistor and a second connection line connected to the second transistor, and a disconnection portion disconnecting the first connection line and the second connection line from each other.

In an embodiment, the first connection line and the second connection line may be formed in the same layer and include the same material.

In an embodiment, the first transistor may include a first semiconductor layer disposed on the substrate and a first gate electrode insulated from the first semiconductor layer, and the second transistor may include a second semiconductor layer disposed on the substrate and a second gate electrode insulated from the second semiconductor layer.

In an embodiment, the pixel circuit may further include a first capacitor including a first lower electrode disposed on the substrate and a first upper electrode insulated from the first lower electrode, and a second capacitor including a second lower electrode spaced apart from the first lower electrode and including a second upper electrode insulated from the second lower electrode.

In an embodiment, the first gate electrode and the first lower electrode may be formed in the same layer and include the same material.

In an embodiment, the connection line may be disposed in the same layer as the first gate electrode.

In an embodiment, the connection line may be arranged in the same layer as the first upper electrode.

In an embodiment, the first connection line may be connected to the first semiconductor layer, and the second connection line may be connected to the second semiconductor layer.

In an embodiment, the display device may further include a first line connecting the first connection line and the first semiconductor layer, and a second line connecting the second connection line and the second semiconductor layer.

In an embodiment, the display device may further include a first organic insulating layer covering the first line,

wherein a first hole corresponding to the disconnection portion is defined in the first organic insulating layer.

In an embodiment, the display device may further include a third line disposed on the first organic insulating layer and a second organic insulating layer covering the third line, wherein a second hole corresponding to the disconnection portion is defined in the second organic insulating layer.

In an embodiment, the width of the first hole may be greater than the width of the second hole.

In an embodiment, the organic light emitting diode may include a pixel electrode, a light emitting layer, and an opposite electrode, and the pixel electrode may not overlap the disconnection portion.

In an embodiment, the display device may further include a pixel defining layer exposing at least a portion of the pixel electrode, wherein at least a portion of the pixel defining layer may be disposed in the disconnected portion.

In an embodiment, the pixel defining layer may be in direct contact with the connection line.

In accordance with one or more embodiments, a method of manufacturing a display device is disclosed, the method comprising: forming a pixel circuit including a first transistor and a second transistor over a substrate, and a connection line connecting the first transistor and the second transistor; performing an array test on the pixel circuit; and disconnecting the connection line.

In an embodiment, forming a pixel circuit including a first transistor and a second transistor and a connection line connecting the first transistor and the second transistor over a substrate may include: forming a first semiconductor layer and a second semiconductor layer on a substrate; forming a first insulating layer over the first semiconductor layer and the second semiconductor layer; forming a connection line on the first insulating layer; forming a second insulating layer on the connection line, wherein a first hole for exposing at least a portion of the connection line is defined in the second insulating layer; forming a first line and a second line on the second insulating layer; forming a first organic insulating layer on the first and second lines, wherein a second hole for exposing at least a portion of the connection line is defined in the first organic insulating layer; and forming a third line on the first organic insulating layer.

In an embodiment, the first transistor may further include a first gate electrode insulated from the first semiconductor layer, and the first gate electrode and the connection line may be formed in the same layer and include the same material.

In an embodiment, the first semiconductor layer and the connection line may be connected to each other through the first line.

In an embodiment, the second semiconductor layer and the connection line may be connected to each other through a second line.

In an embodiment, the method may further comprise: forming a second organic insulating layer on the third line after forming the third line, wherein a third hole for exposing at least a portion of the connection line is defined in the second organic insulating layer; and forming a pattern material on the connection line and the second organic insulating layer.

In an embodiment, the width of the second hole may be greater than the width of the third hole.

In an embodiment, when the connection line is disconnected, the pattern material may be etched to form the pixel electrode, and the connection line may be etched to form the disconnected portion.

In an embodiment, the pixel electrode may not overlap the disconnection portion.

In an embodiment, the method may further comprise: after the connection line is disconnected, a pixel defining layer for exposing at least a portion of the pixel electrode is formed.

In an embodiment, at least a portion of the pixel defining layer may be formed in the disconnected portion.

In an embodiment, the pixel circuit may include a first capacitor and a second capacitor.

In an embodiment, the first capacitor may include a first lower electrode and a first upper electrode insulated from the first lower electrode, and the second capacitor may include a second lower electrode spaced apart from the first lower electrode and a second upper electrode insulated from the second lower electrode.

Aspects, features and advantages other than those described above will become apparent from the following drawings, claims and detailed description of the disclosure.

Drawings

The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description when taken in conjunction with the accompanying drawings in which:

fig. 1 is a schematic plan view of a display device according to an embodiment;

fig. 2 is a schematic equivalent circuit diagram of a pixel circuit of a pixel included in a display device according to an embodiment;

fig. 3 is a schematic cross-sectional view of a display device according to an embodiment;

fig. 4 is a schematic plan view of a display device according to an embodiment;

Fig. 5 is a schematic cross-sectional view of a display device according to an embodiment;

fig. 6 is a schematic cross-sectional view of a display device according to an embodiment;

fig. 7 to 13 are schematic cross-sectional views of a method of manufacturing a display device according to an embodiment;

fig. 14 is a schematic equivalent circuit diagram of a pixel circuit in a process of manufacturing a display device according to an embodiment; and

fig. 15 is a schematic plan view of a display device in a manufacturing process according to an embodiment.

Detailed Description

Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. In this regard, the presented embodiments may take different forms and should not be construed as limited to the descriptions set forth herein. Accordingly, the embodiments are described below only by referring to the drawings to explain aspects of the present description. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression "at least one of a, b and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c, or variants thereof.

Various modifications may be applied to the presented embodiments, and specific embodiments will be shown in the drawings and described in part in the detailed description. Effects and features of the presented embodiments and methods of achieving the effects and features will be apparent with reference to the following detailed description with accompanying drawings. However, the presented embodiments may be implemented in various forms and are not limited to the embodiments presented below.

In the following embodiments, although terms such as "first", "second", etc. may be used to describe various elements, these elements should not be limited to the above terms.

In the following embodiments, unless the context clearly indicates otherwise, singular expressions in the specification include plural expressions.

In the following embodiments, it will be further understood that the terms "comprises" and/or "comprising," as used herein, specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

In the following embodiments, it will be understood that when an element such as a layer, film, region or plate is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present.

The size of the elements in the figures may be exaggerated for convenience of explanation. For example, since the sizes and thicknesses of the components in the drawings are arbitrarily shown for convenience of explanation, the following embodiments are not limited thereto.

In the specification, a expression such as "at least one of a and B" may include A, B, or a and B.

In the following embodiments, the meaning of the wiring "extending in the first direction or the second direction" includes not only extending in a linear shape in the first direction or the second direction but also extending in a zigzag or curved line.

In the following embodiments, when referred to as "in a plan view", this means when the object portion is viewed from above, and when referred to as "in a cross-sectional view", this means when the cross-section of the vertical cut object portion is viewed from the side. In the following embodiments, when referred to as "overlapping", it includes overlapping "in a plan view" and "in a sectional view".

Hereinafter, embodiments will be described in detail with reference to the drawings, and in the description with reference to the drawings, the same or corresponding constituent parts are denoted by the same reference numerals, and redundant description thereof will be omitted.

Fig. 1 is a schematic plan view of a display device 1 according to an embodiment.

Referring to fig. 1, the display device 1 may include a display area DA for implementing an image and a peripheral area PA arranged around the display area DA. The display device 1 can provide an image to the outside by using light emitted from the display area DA.

The substrate 100 may comprise various materials such as glass, metal, plastic, or the like. According to an embodiment, the substrate 100 may comprise a flexible material. The flexible material may be a well-flexible, bent, folded or curled material. For example, the flexible material may comprise ultra-thin glass, metal, or plastic.

Pixels PX including various display elements such as Organic Light Emitting Diodes (OLEDs) may be arranged in the display area DA of the substrate 100. The pixels PX are provided in plural so as to include a plurality of pixels PX, and the plurality of pixels PX are arranged in various forms (such as a stripe arrangement, a pentile arrangement, a mosaic arrangement, and/or the like), and an image can be realized.

In an embodiment, the display area DA may have a rectangular shape as shown in fig. 1 when viewed in a plan view. Alternatively, the display area DA may have a polygonal shape such as a triangle shape, a pentagon shape, a hexagon shape, or the like, a circular shape, an oval shape, an amorphous shape, or the like.

The peripheral area PA is arranged around the display area DA, and no image is displayed therein. Various wires transmitting an electrical signal to be applied to the display area DA and pads to which a printed circuit board or a driver IC chip is attached may be positioned in the peripheral area PA.

Fig. 2 is a schematic equivalent circuit diagram of a pixel circuit PC of a pixel PX included in a display device according to an embodiment.

Referring to fig. 2, the pixel PX may include an organic light emitting diode OLED as a display element and a pixel circuit PC connected to the organic light emitting diode OLED. The pixel circuit PC may include first to ninth transistors T1 to T9 and first and second capacitors Cst1 and Cst2.

The first transistor T1 may be a driving transistor that determines the magnitude of a drain current (i.e., a driving current) according to a gate-source voltage, and the second to ninth transistors T2 to T9 may be switching transistors that are turned on/off according to a gate-source voltage (substantially a gate voltage). The first to ninth transistors T1 to T9 may be thin film transistors.

In an embodiment, for each pixel circuit PC, there may be provided a first scan line GWL for transmitting the first scan signal GW, a second scan line GCL for transmitting the second scan signal GC, a third scan line GIL for transmitting the third scan signal GI, a fourth scan line GBL for transmitting the fourth scan signal GB, a first emission control line EML1 for transmitting the first emission control signal EM1, a second emission control line EML2 for transmitting the second emission control signal EM2, a Data line DL for transmitting the Data voltage Data (or the Data signal), a driving voltage line PL for transmitting the first power supply voltage ELVDD, a first initialization voltage line PL for transmitting the first initialization voltage Vint, a second voltage line initialization voltage line vin 2 for transmitting the second initialization voltage vant, a reference voltage line VRL for transmitting the reference voltage Vref, and a bias voltage line VBL for transmitting the bias voltage VBIAS. For example, it can be understood that the pixel circuit PC includes a first scan line GWL, a second scan line GCL, a third scan line GIL, a fourth scan line GBL, a first emission control line EML1, a second emission control line EML2, a data line DL, a driving voltage line PL, a first initialization voltage line VIL1, a second initialization voltage line VIL2, a reference voltage line VRL, and a bias voltage line VBL. At least one of the first scan line GWL, the second scan line GCL, the third scan line GIL, the fourth scan line GBL, the first emission control line EML1, the second emission control line EML2, the data line DL, the driving voltage line PL, the first initialization voltage line VIL1, the second initialization voltage line VIL2, the reference voltage line VRL, and the bias voltage line VBL may be shared by the adjacent pixel circuits PC.

The second transistor T2 may connect the data line DL with the first node N1 in response to the first scan signal GW. The second transistor T2 may have a second gate to which the first scan signal GW is applied through the first scan line GWL, a second source connected to the data line DL, and a second drain connected to the first node N1.

The first capacitor Cst1 may be connected between the first node N1 and the first power supply voltage ELVDD. The second capacitor Cst2 may be connected between the first node N1 and the second node N2.

The first transistor T1 may have a first gate connected to the second node N2, a first source connected to the driving voltage line PL through the ninth transistor T9, and a first drain connected to the organic light emitting diode OLED through the sixth transistor T6. The first transistor T1 may output a driving current to the organic light emitting diode OLED according to a gate-source voltage. The organic light emitting diode OLED may receive a driving current from the first transistor T1 and may emit light having a luminance according to an amount of the driving current.

The third transistor T3 may connect the second node N2 with the third node N3 in response to the second scan signal GC. The third transistor T3 may have a third gate electrode to which the second scan signal GC is applied through the second scan line GCL, a third source electrode connected to the second node N2, and a third drain electrode connected to the third node N3. In this state, the positions of the third source and the third drain may be switched to each other. Although fig. 2 shows that the third transistor T3 includes one transistor, the present disclosure is not limited thereto. The third transistor T3 may include two transistors connected in series with each other.

The fourth transistor T4 may apply the first initialization voltage Vint to the first gate of the first transistor T1 in response to the third scan signal GI. The fourth transistor T4 may have a fourth gate connected to the third scan line GIL, a fourth source connected to the first gate of the first transistor T1, and a fourth drain connected to the first initialization voltage line VIL 1. In this state, the positions of the fourth source and the fourth drain may be switched to each other. Although fig. 2 shows that the fourth transistor T4 includes one transistor, the present disclosure is not limited thereto. The fourth transistor T4 may include two transistors connected in series with each other.

The fifth transistor T5 may transmit the reference voltage Vref to the first node N1 in response to the second scan signal GC. The fifth transistor T5 may have a fifth gate connected to the second scan line GCL, a fifth source connected to the reference voltage line VRL, and a fifth drain connected to the first node N1. In this state, the positions of the fifth source and the fifth drain may be switched to each other.

The seventh transistor T7 may apply the second initialization voltage vant to an anode (e.g., a pixel electrode) of the organic light emitting diode OLED in response to the fourth scan signal GB. The seventh transistor T7 may have a seventh gate connected to the fourth scan line GBL, a seventh source connected to the anode of the organic light emitting diode OLED, and a seventh drain connected to the second initialization voltage line VIL 2. In this state, the positions of the seventh source and the seventh drain may be switched with each other.

The ninth transistor T9 may connect the driving voltage line PL with the first source of the first transistor T1 in response to the first emission control signal EM 1. The ninth transistor T9 may have a ninth gate connected to the first emission control line EML1, a ninth source connected to the driving voltage line PL, and a ninth drain connected to the first source of the first transistor T1. In this state, the positions of the ninth source electrode and the ninth drain electrode can be switched to each other.

The sixth transistor T6 may connect the first drain of the first transistor T1 with the anode of the organic light emitting diode OLED in response to the second emission control signal EM 2. The sixth transistor T6 may have a sixth gate connected to the second emission control line EML2, a sixth source connected to the first drain of the first transistor T1, and a sixth drain connected to the anode of the organic light emitting diode OLED. In this state, the positions of the sixth source and the sixth drain may be switched to each other.

The eighth transistor T8 may apply the bias voltage VBIAS to the first source of the first transistor T1 in response to the fourth scan signal GB. The eighth transistor T8 may have an eighth gate connected to the fourth scan line GBL, an eighth source connected to the first source of the first transistor T1, and an eighth drain connected to the bias voltage line VBL. In this state, the positions of the eighth source and the eighth drain can be switched to each other.

Although fig. 2 shows that the ninth transistor T9 and the sixth transistor T6 are connected to different emission control lines (i.e., the first emission control line EML1 and the second emission control line EML 2), the present disclosure is not limited thereto. The ninth transistor T9 and the sixth transistor T6 may be connected to one emission control line.

The organic light emitting diode OLED may include a pixel electrode (anode) and an opposite electrode (cathode) facing the pixel electrode, and the opposite electrode may receive the second power supply voltage ELVSS. For the plurality of pixels PX of fig. 1, the opposite electrode may be a common electrode.

Although fig. 2 shows that the first to ninth transistors T1 to T9 of the pixel circuit PC are P-type transistors, the present disclosure is not limited thereto. Various implementations are possible, for example, the plurality of transistors of the pixel circuit PC may be N-type transistors, some may be P-type transistors and others may be N-type transistors, and the like.

Fig. 3 is a schematic cross-sectional view of the display device 1 according to the embodiment. In detail, fig. 3 is a schematic cross-sectional view of the first transistor T1, the second transistor T2, the first capacitor Cst1, and the second capacitor Cst2 of fig. 2.

Referring to fig. 3, the display device 1 may include a substrate 100, a pixel circuit PC, and an organic light emitting diode OLED. The pixel circuit PC may include a first transistor T1, a second transistor T2, a first capacitor Cst1, and a second capacitor Cst2. The organic light emitting diode OLED may include a pixel electrode 210, a light emitting layer 220, and an opposite electrode 230.

The substrate 100 may comprise a glass material, a ceramic material, a metal material, or a flexible or bendable material. When the substrate 100 is flexible or bendable, the substrate 100 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

The substrate 100 may have a single-layer or multi-layer structure of the above-described materials, and for the multi-layer structure, the substrate 100 may further include an inorganic layer. In an embodiment, the substrate 100 may have an organic/inorganic/organic/inorganic structure.

A buffer layer 110 may be disposed on the substrate 100. The buffer layer 110 may reduce or prevent foreign matter, moisture, or outside air from penetrating from below the substrate 100. The buffer layer 110 may include an inorganic material such as an oxide or nitride, an organic material, or an organic/inorganic composite, and may have a single-layer or multi-layer structure of the inorganic material and the organic material.

The first transistor T1, the second transistor T2, the first capacitor Cst1, and the second capacitor Cst2 may be disposed on the substrate 100 or the buffer layer 110. The first transistor T1 may include a first semiconductor layer Act1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1. The second transistor T2 may include a second semiconductor layer Act2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2. The first capacitor Cst1 may include a first lower electrode CE1 and a first upper electrode CE2. The second capacitor Cst2 may include a second lower electrode CE3 and a second upper electrode CE4.

The first semiconductor layer Act1 and the second semiconductor layer Act2 may be disposed on the buffer layer 110. The first semiconductor layer Act1 and the second semiconductor layer Act2 may each include a silicon semiconductor. The first semiconductor layer Act1 and the second semiconductor layer Act2 may each include polysilicon. Alternatively, the first semiconductor layer Act1 and the second semiconductor layer Act2 may each include amorphous silicon. Alternatively, the first semiconductor layer Act1 and the second semiconductor layer Act2 may each include an oxide semiconductor, an organic semiconductor, and/or the like.

The first semiconductor layer Act1 may include a first channel C1, a first source electrode S1, and a first drain electrode D1. The first source S1 and the first drain D1 may be arranged on opposite sides of the first channel C1. The second semiconductor layer Act2 may include a second channel C2, a second source electrode S2, and a second drain electrode D2. The second source S2 and the second drain D2 may be arranged on opposite sides of the second channel C2.

A first insulating layer 111 may be disposed on the first semiconductor layer Act1 and the second semiconductor layer Act2. The first insulating layer 111 may cover the first semiconductor layer Act1 and the second semiconductor layer Act2. First insulationThe rim layer 111 may comprise an inorganic insulating material such as silicon oxide (SiO ₂ ) Silicon nitride (SiN) _X ) Silicon oxynitride (SiON), aluminum oxide (Al) ₂ O ₃ ) Titanium oxide (TiO) ₂ ) Tantalum oxide (Ta) ₂ O ₅ ) Hafnium oxide (HfO) ₂ ) Zinc oxide (ZnO) and/or the like.

The first gate electrode GE1 and the second gate electrode GE2 may be disposed on the first insulating layer 111. The first gate electrode GE1 may overlap the first semiconductor layer Act 1. In detail, the first gate electrode GE1 may overlap the first channel C1. The first gate electrode GE1 may be insulated from the first semiconductor layer Act1 with the first insulating layer 111 interposed therebetween. The second gate electrode GE2 may overlap the second semiconductor layer Act 2. In detail, the second gate electrode GE2 may overlap the second channel C2. The second gate electrode GE2 may be insulated from the second semiconductor layer Act2 with the first insulating layer 111 interposed therebetween. The first gate electrode GE1 and the second gate electrode GE2 may each include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and/or the like, and may be a multi-layer or single-layer including the above-described materials.

The first and second lower electrodes CE1 and CE3 may be disposed on the first insulating layer 111. The first and second lower electrodes CE1 and CE3 may be spaced apart from each other. Although fig. 3 illustrates that the second lower electrode CE3 is integrally formed with the first gate electrode GE1, the present disclosure is not limited thereto. The second lower electrode CE3 may be spaced apart from the first gate electrode GE 1.

The first lower electrode CE1 may be disposed in the same layer as the first gate electrode GE1, and may include the same material as the first gate electrode GE 1. For example, the first lower electrode CE1 and the first gate electrode GE1 may be formed in the same process. However, the present disclosure is not limited thereto. At least one of the first and second lower electrodes CE1 and CE3 may be disposed on the second insulating layer 113.

The second insulating layer 113 may be disposed on the first and second gate electrodes GE1 and GE2. The second insulating layer 113 may cover the first gate electrode GE1 and the second gate electrode GE2. The second insulating layer 113 may include an inorganic insulating material such as SiO ₂ 、SiN _X 、SiON、Al ₂ O ₃ 、TiO ₂ 、Ta ₂ O ₅ 、HfO ₂ ZnO and/or the like.

The first and second upper electrodes CE2 and CE4 may be disposed on the second insulating layer 113. The first upper electrode CE2 may at least partially overlap the first lower electrode CE 1. The first upper electrode CE2 and the first lower electrode CE1 may overlap each other with the second insulating layer 113 interposed therebetween. The second upper electrode CE4 may at least partially overlap the second lower electrode CE 3. The second upper electrode CE4 and the second lower electrode CE3 may overlap each other with the second insulating layer 113 interposed therebetween. The first and second upper electrodes CE2 and CE4 may each include a conductive material including Mo, al, cu, ti and/or the like, and may be formed as a multi-layer or single-layer including the above-described materials. At least one of the first and second upper electrodes CE2 and CE4 may be disposed on the third insulating layer 115, not on the second insulating layer 113.

In case of being insulated from each other, the first upper electrode CE2 and the first lower electrode CE1 may at least partially overlap each other. The first upper electrode CE2 and the first lower electrode CE1 may form a first capacitor Cst1. In case of being insulated from each other, the second upper electrode CE4 and the second lower electrode CE3 may at least partially overlap each other. The second upper electrode CE4 and the second lower electrode CE3 may form a second capacitor Cst2.

The third insulating layer 115 may be disposed on the first and second upper electrodes CE2 and CE4. The third insulating layer 115 may cover the first and second upper electrodes CE2 and CE4. The third insulating layer 115 may include an inorganic insulating material such as SiO ₂ 、SiN _X 、SiON、Al ₂ O ₃ 、TiO ₂ 、Ta ₂ O ₅ 、HfO ₂ ZnO and/or the like.

The first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 may be disposed on the third insulating layer 115. The first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 may mean electrodes electrically connected to the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2, respectively. Although not shown, the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 may be electrically connected to the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2, respectively, via contact holes defined in the first insulating layer 111, the second insulating layer 113, and the third insulating layer 115. The first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 may each include a conductive material including Mo, al, cu, ti and/or the like, and may be formed as a multi-layer or single-layer including the materials described above. For example, the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 may have a multi-layered structure of Ti/Al/Ti.

A first organic insulating layer 121 may be disposed on the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2. The first organic insulating layer 121 may cover the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2. The first organic insulating layer 121 may include an organic insulating material, such as a general polymer (such as polymethyl methacrylate (PMMA) or Polystyrene (PS)), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an arylene ether polymer, an amide polymer, a fluorine-based polymer, a p-xylyl polymer, a vinyl alcohol-based polymer, and/or a blend thereof.

In an embodiment, the pixel circuit PC may include a connection electrode CM. The connection electrode CM may be disposed on the first organic insulation layer 121. In this state, the connection electrode CM may mean an electrode disposed on the upper surface of the first organic insulating layer 121. Although not shown, the connection electrode CM may be electrically connected to a source electrode or a drain electrode of the transistor via a contact hole defined in the first organic insulating layer 121. The connection electrode CM may include a conductive material including Mo, al, cu, ti and/or the like, and may be formed in a multi-layer or single-layer including the above-described materials. For example, the connection electrode CM may have a Ti/Al/Ti multilayer structure.

A second organic insulating layer 123 may be disposed on the connection electrode CM. The second organic insulation layer 123 may cover the connection electrode CM. The second organic insulating layer 123 may include an organic insulating material such as a general polymer such as polymethyl methacrylate (PMMA) or Polystyrene (PS), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an arylene ether polymer, an amide polymer, a fluorine-based polymer, a p-xylyl polymer, a vinyl alcohol-based polymer, and/or a blend thereof.

On the second organic insulating layer 123, a pixel defining layer 180 and an organic light emitting diode OLED may be disposed. The pixel electrode 210 may be disposed on the second organic insulating layer 123. Although not shown, the pixel electrode 210 and the connection electrode CM may be electrically connected to each other via a contact hole defined in the second organic insulating layer 123. In other words, the organic light emitting diode OLED and the pixel circuit PC may be electrically connected to each other via a contact hole defined in the second organic insulating layer 123. The pixel electrode 210 may include a conductive oxide such as Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), zinc oxide (ZnO), indium oxide (In ₂ O ₃ ) Indium Gallium Oxide (IGO) or zinc aluminum oxide (AZO). Alternatively, the pixel electrode 210 may include a reflective film such as silver (Ag), magnesium (Mg), al, platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. Alternatively, the pixel electrode 210 may further include a reflective film made of ITO, IZO, znO or In above/below the reflective film described above ₂ O ₃ And (3) forming a film.

The pixel defining layer 180 defining an opening portion for exposing at least a portion of the pixel electrode 210 may be disposed on the pixel electrode 210. For example, the opening portion defined in the pixel defining layer 180 may expose a central portion of the pixel electrode 210. The pixel defining layer 180 may include an organic insulating material and/or an inorganic insulating material.

The light emitting layer 220 may be disposed on the pixel electrode 210. Although not shown, a first functional layer and a second functional layer may be disposed below and above the light emitting layer 220, respectively. The first functional layer may include a Hole Injection Layer (HIL) and a Hole Transport Layer (HTL), and the second functional layer may include an Electron Transport Layer (ETL) and an Electron Injection Layer (EIL). The light emitting layer 220 may include a low molecular weight material or a polymer material, and emits red light, green light, blue light, or white light.

The opposite electrode 230 may be disposed on the light emitting layer 220. The counter electrode 230 may include a material having a low work functionIs a conductive material of the above-mentioned metal-insulator-metal composite. For example, the opposite electrode 230 may include a (semi) transparent layer including Ag, mg, al, pt, pd, au, ni, nd, ir, cr, lithium (Li), calcium (Ca), an alloy thereof, or the like. Alternatively, the counter electrode 230 may also comprise a layer such as ITO, IZO, znO or In on a (semi) transparent layer comprising the above described materials ₂ O ₃ Is a layer of (c).

Fig. 4 is a schematic plan view of the display device 1 according to the embodiment, and fig. 5 is a schematic cross-sectional view of the display device 1 according to the embodiment. In fig. 4, some elements are omitted for convenience of explanation and explanation. Fig. 5 corresponds to a sectional view taken along the line I-I' of fig. 4. In fig. 5, the same reference numerals as those of fig. 3 denote the same elements, and thus redundant description thereof is omitted.

Referring to fig. 4 and 5, the display device 1 may include a connection line 130 and a disconnection portion 135. The connection line 130 may include a first connection line 131 and a second connection line 133. The disconnection portion 135 may be defined between the first connection line 131 and the second connection line 133.

The buffer layer 110 may be disposed on the substrate 100, and a first semiconductor layer Act1 of the first transistor T1 (see fig. 3) and a second semiconductor layer Act2 of the second transistor T2 (see fig. 3) may be disposed on the buffer layer 110. In detail, the first source S1 of the first transistor T1 and the second drain D2 of the second transistor T2 may be disposed on the buffer layer 110.

The first insulating layer 111 may be disposed on the first semiconductor layer Act1 and the second semiconductor layer Act2, and the connection line 130 may be disposed on the first insulating layer 111. As described above, the connection line 130 may include the first connection line 131 and the second connection line 133. In other words, the first and second connection lines 131 and 133 may be disposed on the first insulating layer 111. The first connection line 131 and the second connection line 133 may be formed in the same layer, and may include the same material. The first connection line 131 and the second connection line 133 may be formed in the same layer as the first gate electrode GE1 (see fig. 3) described above in fig. 3, and may include the same material as the first gate electrode GE 1.

In an embodiment, the first connection line 131 may have a shape protruding in a first direction (e.g., y direction) with respect to the second contact hole CNT2 in a plan view. Further, in a plan view, the second connection line 133 may have a shape protruding in a second direction (e.g., an x direction) crossing the first direction (e.g., a y direction) with respect to the fourth contact hole CNT 4. In other words, in a plan view, the first connection line 131 may have a protruding portion protruding in a first direction (e.g., y-direction) with respect to the second contact hole CNT2, and the second connection line 133 may have a protruding portion protruding in a second direction (e.g., x-direction) with respect to the fourth contact hole CNT 4.

In an embodiment, the display device 1 may include a disconnection portion 135. The disconnection portion 135 may be defined between the first connection line 131 and the second connection line 133. The disconnection portion 135 may disconnect the first connection line 131 and the second connection line 133 from each other. Accordingly, the first and second connection lines 131 and 133 may not be electrically connected to each other. Since the disconnection portion 135 is defined between the first connection line 131 and the second connection line 133, at least a portion of the upper surface of the first insulation layer 111 may be exposed.

In an embodiment, the second insulating layer 113 may be disposed on the connection line 130, and the third insulating layer 115 may be disposed on the second insulating layer 113. In detail, the second insulating layer 113 and the third insulating layer 115 may be disposed on the first connection line 131 and the second connection line 133.

In an embodiment, a first hole H1 corresponding to the break portion 135 may be defined in the second insulating layer 113 and the third insulating layer 115. The first hole H1 defined in the second and third insulating layers 113 and 115 may at least partially overlap the break-off portion 135. For example, the first hole H1 defined in the second insulating layer 113 and the third insulating layer 115 may at least partially overlap the break portion 135 when viewed from the thickness direction (e.g., the third direction (z direction)) of the substrate 100.

In an embodiment, the first line 141 and the second line 143 may be disposed on the third insulating layer 115. The first line 141 and the second line 143 may be formed in the same layer as the first source electrode SE1 (see fig. 3) described above in fig. 3, and may include the same material as the first source electrode SE 1. For example, the first line 141 may correspond to a portion of the first source electrode SE1, and the second line 143 may correspond to a portion of the second drain electrode DE2 (see fig. 3).

In an embodiment, the first line 141 may electrically connect the first semiconductor layer Act1 with the first connection line 131. In detail, the first line 141 may electrically connect the first source electrode S1 of the first semiconductor layer Act1 with the first connection line 131. As described above in fig. 3, since the first transistor T1 (see fig. 3) includes the first semiconductor layer Act1, it is understood that the first line 141 electrically connects the first transistor T1 with the first connection line 131. Accordingly, the first line 141 may electrically connect the first source S1 of the first transistor T1 with the first connection line 131. For example, one side of the first line 141 may be electrically connected to the first source electrode S1 of the first transistor T1 via the first contact hole CNT1 defined in the first, second, and third insulating layers 111, 113, and 115, whereas the other side of the first line 141 may be electrically connected to the first connection line 131 via the second contact hole CNT2 defined in the second and third insulating layers 113 and 115.

In an embodiment, the second line 143 may electrically connect the second semiconductor layer Act2 with the second connection line 133. In detail, the second line 143 may electrically connect the second drain electrode D2 of the second semiconductor layer Act2 with the second connection line 133. As described above in fig. 3, since the second transistor T2 (see fig. 3) includes the second semiconductor layer Act2, it is understood that the second line 143 electrically connects the second transistor T2 with the second connection line 133. Accordingly, the second line 143 may electrically connect the second drain D2 of the second transistor T2 with the second connection line 133. For example, one side of the second line 143 may be electrically connected to the second drain electrode D2 of the second transistor T2 via the third contact hole CNT3 defined in the first, second, and third insulating layers 111, 113, and 115, whereas the other side of the second line 143 may be electrically connected to the second connection line 133 via the fourth contact hole CNT4 defined in the second and third insulating layers 113 and 115.

In the embodiment, although the first source S1 and the first connection line 131 of the first transistor T1 are electrically connected to each other through the first line 141, and the second drain D2 and the second connection line 133 of the second transistor T2 are electrically connected to each other through the second line 143, since the disconnection portion 135 is defined between the first connection line 131 and the second connection line 133, a DC current path may not be formed between the first source S1 of the first transistor T1 and the second drain D2 of the second transistor T2. In other words, a DC current path may not be formed between the first transistor T1 and the second transistor T2. This will be described in detail below.

In an embodiment, the first organic insulating layer 121 may be disposed on the first line 141 and the second line 143. A second hole H2 corresponding to the break portion 135 may be defined in the first organic insulating layer 121. The second hole H2 defined in the first organic insulating layer 121 may at least partially overlap the break-off portion 135. For example, the second hole H2 defined in the first organic insulating layer 121 may at least partially overlap the break portion 135 when viewed from the thickness direction of the substrate 100.

In an embodiment, the first and second holes H1 and H2 may at least partially overlap each other. The width of the first hole H1 may be greater than the width of the second hole H2. For example, the width of the first hole H1 may be larger than the width of the second hole H2 in a plan view. The first organic insulating layer 121 may cover side surfaces of the second insulating layer 113 and the third insulating layer 115.

In an embodiment, a third line 145 may be disposed on the first organic insulating layer 121. The third line 145 may be formed in the same layer as the connection electrode CM (see fig. 3), and may include the same material as the connection electrode CM.

In an embodiment, the second organic insulating layer 123 may be disposed on the third line 145. A third hole H3 corresponding to the break portion 135 may be defined in the second organic insulating layer 123. The third hole H3 defined in the second organic insulating layer 123 may at least partially overlap the break portion 135. For example, the third hole H3 defined in the second organic insulating layer 123 may at least partially overlap the break portion 135 when viewed from the thickness direction of the substrate 100.

In an embodiment, the second and third holes H2 and H3 may at least partially overlap each other. The width of the second hole H2 may be greater than the width of the third hole H3. For example, the width of the second hole H2 may be greater than the width of the third hole H3 in a plan view. The second organic insulating layer 123 may cover a side surface of the first organic insulating layer 121.

In an embodiment, the pixel electrode 210 may be disposed on the second organic insulating layer 123. The pixel electrode 210 may not overlap the disconnection portion 135. In detail, the pixel electrode 210 and the break portion 135 may not overlap each other when viewed from the thickness direction of the substrate 100. In addition, the pixel electrode 210 may not overlap the first, second, and third holes H1, H2, and H3. The pixel electrode 210 may not overlap the connection line 130. However, the present disclosure is not limited thereto. The pixel electrode 210 may at least partially overlap the connection line 130. However, even in this case, the pixel electrode 210 may not overlap the disconnection portion 135.

In an embodiment, the pixel defining layer 180 may be disposed on the pixel electrode 210 and the second organic insulating layer 123. At least a portion of the pixel defining layer 180 may be disposed in the break-out portion 135. The pixel defining layer 180 may be disposed within the third hole H3. For example, the pixel defining layer 180 may cover a side surface of the second organic insulating layer 123. The pixel defining layer 180 may be in direct contact with the connection line 130. For example, the pixel defining layer 180 may be in direct contact with the first and second connection lines 131 and 133.

Fig. 6 is a schematic cross-sectional view of the display device 1 according to the embodiment. The embodiment of fig. 6 differs from the embodiment of fig. 5 in that the connection line 130 is arranged on the second insulating layer 113. In fig. 6, since the same reference numerals as those in fig. 5 denote the same elements, redundant description thereof is omitted.

Referring to fig. 6, the connection line 130 may be disposed on the second insulating layer 113. In other words, the first and second connection lines 131 and 133 may be disposed on the second insulating layer 113. The first connection line 131 and the second connection line 133 may be formed in the same layer, and may include the same material. The first and second connection lines 131 and 133 may be formed in the same layer as the first upper electrode CE2 (see fig. 3) described above in fig. 3, and may include the same material as the first upper electrode CE 2.

In an embodiment, the display device 1 may include a disconnection portion 135. The disconnection portion 135 may be defined between the first connection line 131 and the second connection line 133. The disconnection portion 135 may disconnect the first connection line 131 and the second connection line 133 from each other. Accordingly, the first and second connection lines 131 and 133 may not be electrically connected to each other. Since the disconnection portion 135 is defined between the first connection line 131 and the second connection line 133, at least a portion of the upper surface of the second insulation layer 113 may be exposed.

Fig. 7 to 13 are schematic cross-sectional views of a method of manufacturing a display device according to an embodiment.

Referring to fig. 7 to 13, a method of manufacturing a display device may include: a pixel circuit PC (see fig. 3) including a first transistor T1 (see fig. 3) and a second transistor T2 (see fig. 3) and a connection line 130 connecting the first transistor T1 and the second transistor T2 are formed on the substrate 100; performing an array test on the pixel circuit PC; and disconnecting the connection line 130.

Further, forming the pixel circuit PC including the first transistor T1 and the second transistor T2 and the connection line 130 connecting the first transistor T1 and the second transistor T2 on the substrate 100 may include: forming a first semiconductor layer Act1 and a second semiconductor layer Act2 on a substrate 100; forming a first insulating layer 111 on the first semiconductor layer Act1 and the second semiconductor layer Act2; forming a connection line 130 on the first insulating layer 111; forming a second insulating layer 113 defining a first hole H1 for exposing at least a portion of the connection line 130 on the connection line 130; forming a first line 141 and a second line 143 on the second insulating layer 113; forming a first organic insulating layer 121 defining a second hole H2 for exposing at least a portion of the connection line 130 on the first line 141 and the second line 143; and forming a third line 145 on the first organic insulating layer 121.

Further, after forming the third line 145, the method of manufacturing a display device may further include: forming a second organic insulating layer 123 defining a third hole H3 for exposing at least a portion of the connection line 130 on the third line 145; and forming a pattern material 210M on the connection line 130 and the second organic insulating layer 123.

Referring to fig. 7, a buffer layer 110 may be formed on a substrate 100, and a first semiconductor layer Act1 and a second semiconductor layer Act2 may be formed on the buffer layer 110. Further, a first insulating layer 111 may be formed on the first semiconductor layer Act1 and the second semiconductor layer Act2. The first insulating layer 111 may cover the first semiconductor layer Act1 and the second semiconductor layer Act2.

The connection line 130 may be formed on the first insulating layer 111. The connection line 130 may not overlap the first semiconductor layer Act1 and the second semiconductor layer Act2. Although not shown, the first gate electrode GE1 (see fig. 3), the second gate electrode GE2 (see fig. 3), the first lower electrode CE1 (see fig. 3), and the second lower electrode CE3 (see fig. 3) described above in fig. 3 may be formed on the first insulating layer 111. In other words, the connection line 130, the first gate electrode GE1, the second gate electrode GE2, the first lower electrode CE1, and the second lower electrode CE3 may be formed in the same process. The connection line 130, the first gate electrode GE1, the second gate electrode GE2, the first lower electrode CE1, and the second lower electrode CE3 may be formed in the same layer, and may include the same material.

Further, after forming the connection line 130, the first gate electrode GE1, the second gate electrode GE2, the first lower electrode CE1, and the second lower electrode CE3 on the first insulating layer 111, impurities (or ions) may be implanted into at least a portion of the first semiconductor layer Act1 and the second semiconductor layer Act 2. Accordingly, the first semiconductor layer Act1 may include a first source electrode S1, a first channel C1 (see fig. 3), and a first drain electrode D1 (see fig. 3), whereas the second semiconductor layer Act2 may include a second source electrode S2 (see fig. 3), a second channel C2 (see fig. 3), and a second drain electrode D2.

The second insulating layer 113 may be formed on the connection line 130, and the third insulating layer 115 may be formed on the second insulating layer 113. Although not shown, after the second insulating layer 113 is formed on the connection line 130, the first upper electrode CE2 (see fig. 3) and the second upper electrode CE4 (see fig. 3) described above in fig. 3 may be formed on the second insulating layer 113. In other words, the process of forming the first and second upper electrodes CE2 and CE4 may be performed between the process of forming the second insulating layer 113 and the process of forming the third insulating layer 115. As described above in fig. 3, in the case where the first upper electrode CE2 is insulated from the first lower electrode CE1, the first upper electrode CE2 and the first lower electrode CE1 may at least partially overlap each other. The first upper electrode CE2 and the first lower electrode CE1 may form a first capacitor Cst1. As described above in fig. 3, in the case where the second upper electrode CE4 is insulated from the second lower electrode CE3, the second upper electrode CE4 and the second lower electrode CE3 may at least partially overlap each other. The second upper electrode CE4 and the second lower electrode CE3 may form a second capacitor Cst2.

Although not shown, the connection line 130 may be formed on the second insulating layer 113. In this case, the connection line 130 may be formed in the same process as the first and second upper electrodes CE2 and CE 4. For example, the connection line 130, the first upper electrode CE2, and the second upper electrode CE4 may be formed in the same layer, and may include the same material.

In an embodiment, the first hole H1 may be formed in the second insulating layer 113 and the third insulating layer 115. For example, the first hole H1 may be formed by partially removing the second insulating layer 113 and the third insulating layer 115. At least a portion of the connection line 130 may be exposed through the first hole H1 defined in the second and third insulating layers 113 and 115. In this state, since a portion of the second insulating layer 113 and the third insulating layer 115 is removed, at least a portion of the connection line 130 may be removed together. In this case, the thickness of at least a portion of the connection line 130 exposed may be smaller than the thickness of the connection line 130 disposed under the second insulating layer 113.

In addition, the second and fourth contact holes CNT2 and CNT4 may be defined in the second and third insulating layers 113 and 115, whereas the first and third contact holes CNT1 and CNT3 may be defined in the first, second and third insulating layers 111, 113 and 115.

The first line 141 and the second line 143 may be formed on the third insulating layer 115. Although not shown, the first source electrode SE1 (see fig. 3), the first drain electrode DE1 (see fig. 3), the second source electrode SE2 (see fig. 3), and the second drain electrode DE2 (see fig. 3) described above in fig. 3 may be formed on the third insulating layer 115. In other words, the first and second lines 141 and 143 may be formed in the same process as the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE 2. Accordingly, the first line 141, the second line 143, the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 may be formed in the same layer, and may include the same material.

In an embodiment, the first semiconductor layer Act1 and the connection line 130 may be electrically connected to each other through the first line 141. The first semiconductor layer Act1 and the first line 141 may be electrically connected to each other through the first contact hole CNT1, and the first line 141 and the connection line 130 may be electrically connected to each other through the second contact hole CNT 2. Accordingly, the first semiconductor layer Act1 and the connection line 130 may be electrically connected to each other. For example, the first source electrode S1 of the first semiconductor layer Act1 and the connection line 130 may be electrically connected to each other through the first line 141. As described above in fig. 3, since the first transistor T1 (see fig. 3) includes the first semiconductor layer Act1, it is understood that the first transistor T1 and the connection line 130 are electrically connected to each other. Accordingly, the first source S1 of the first transistor T1 and the connection line 130 may be electrically connected to each other.

In an embodiment, the second semiconductor layer Act2 and the connection line 130 may be electrically connected to each other through the second line 143. The second semiconductor layer Act2 and the second line 143 may be electrically connected to each other through the third contact hole CNT3, whereas the second line 143 and the connection line 130 may be electrically connected to each other through the fourth contact hole CNT 4. Accordingly, the second semiconductor layer Act2 and the connection line 130 may be electrically connected to each other. For example, the second drain electrode D2 of the second semiconductor layer Act2 and the connection line 130 may be electrically connected to each other through the second line 143. As described above in fig. 3, since the second transistor T2 (see fig. 3) includes the second semiconductor layer Act2, it is understood that the second transistor T2 and the connection line 130 are electrically connected to each other. Accordingly, the second drain D2 of the second transistor T2 and the connection line 130 may be electrically connected to each other.

In the embodiment, since the first semiconductor layer Act1 and the connection line 130 are electrically connected to each other, and the second semiconductor layer Act2 and the connection line 130 are electrically connected to each other, the first semiconductor layer Act1 and the second semiconductor layer Act2 may be electrically connected to each other. For example, the first source electrode S1 of the first semiconductor layer Act1 and the second drain electrode D2 of the second semiconductor layer Act2 may be electrically connected to each other. Accordingly, a DC current path may be formed between the first source electrode S1 of the first semiconductor layer Act1 and the second drain electrode D2 of the second semiconductor layer Act 2. In other words, a DC current path may be formed between the first transistor T1 and the second transistor T2. In detail, a DC current path may be formed between the first source S1 of the first transistor T1 and the second drain D2 of the second transistor T2. This will be described in detail below.

Referring to fig. 8, a first organic insulating layer 121 defining a second hole H2 for exposing at least a portion of the connection line 130 may be formed on the first line 141 and the second line 143.

In an embodiment, at least a portion of the connection line 130 may be exposed through the second hole H2 defined in the first organic insulating layer 121.

In an embodiment, the second hole H2 may overlap the first hole H1. The width of the first hole H1 may be greater than the width of the second hole H2. For example, the width of the first hole H1 may be larger than the width of the second hole H2 in a plan view. The first organic insulating layer 121 may cover side surfaces of the second insulating layer 113 and the third insulating layer 115.

Referring to fig. 9, a third line 145 may be formed on the first organic insulating layer 121. Although not shown, the connection electrode CM (see fig. 3) described above in fig. 3 may be formed on the first organic insulating layer 121. In other words, the third line 145 and the connection electrode CM may be formed in the same process. The third line 145 and the connection electrode CM may be formed in the same layer, and may include the same material.

In an embodiment, after forming the third line 145 on the first organic insulating layer 121, an array test may be performed on the pixel circuit PC (see fig. 2). Array testing may be performed to detect poor electrical performance of the wires and/or transistors. In this state, the array test can be performed by a conventional method. For example, defects in the wires and/or transistors may be detected by inspecting the electrical properties of the transistors using array test equipment. This will be described in detail below.

Referring to fig. 10, a second organic insulating layer 123 defining a third hole H3 for exposing at least a portion of the connection line 130 may be formed on the third line 145.

In an embodiment, at least a portion of the connection line 130 may be exposed through the third hole H3 defined in the second organic insulating layer 123.

In an embodiment, the third hole H3 may overlap the second hole H2. The width of the second hole H2 may be greater than the width of the third hole H3. For example, the width of the second hole H2 may be greater than the width of the third hole H3 in a plan view. The second organic insulating layer 123 may cover a side surface of the first organic insulating layer 121.

Referring to fig. 11, a pattern material 210M may be coated on the connection line 130 and the second organic insulating layer 123. The pattern material 210M may be entirely formed on the connection line 130 and the second organic insulating layer 123.

The pattern material 210M may include a conductive oxide, such as ITO, IZO, znO, in ₂ O ₃ Either IGO or AZO. Alternatively, the pattern material 210M may include a reflective film including Ag, mg, al, pt, pd, au, ni, nd, ir, cr or a compound thereof. Alternatively, the pattern material 210M may further include a reflective film formed of ITO, IZO, znO or In disposed above/below the reflective film described above ₂ O ₃ And (3) forming a film.

Referring to fig. 12, the pixel electrode 210 may be formed by etching the pattern material 210M. When the pattern material 210M is etched, at least a portion of the connection line 130 is etched together so that the connection line 130 may be disconnected.

In detail, when the pattern material 210M is etched, the pixel electrode 210 may be formed, and in this state, at least a portion of the connection line 130 is etched together such that the connection line 130 may be divided into the first connection line 131 and the second connection line 133, and the disconnection portion 135 may be formed between the first connection line 131 and the second connection line 133. In detail, when the pixel electrode 210 is formed by etching the pattern material 210M, at least a portion of the connection line 130 exposed through the third hole H3 defined in the second organic insulating layer 123 is etched together so that the connection line 130 may be divided into the first connection line 131 and the second connection line 133, and the disconnection portion 135 may be formed between the first connection line 131 and the second connection line 133.

The disconnection portion 135 may be formed between the first connection line 131 and the second connection line 133. At least a portion of the upper surface of the first insulating layer 111 may be exposed through the break portion 135. Since the disconnection portion 135 is formed between the first connection line 131 and the second connection line 133, the first connection line 131 and the second connection line 133 may not be connected to each other. In other words, since the disconnection portion 135 is formed between the first connection line 131 and the second connection line 133, the first connection line 131 and the second connection line 133 may be disconnected (or shorted (opened), disconnected, separated, or spaced apart). Therefore, a DC current path may not be formed between the first connection line 131 and the second connection line 133. The connection line 130 serves to provide a DC current path between the first source S1 of the first transistor T1 and the second drain D2 of the second transistor T2, and since the connection line 130 is cut (or shorted (opened), disconnected, separated, or spaced apart) into the first connection line 131 and the second connection line 133, the DC current path may not be formed between the first source S1 of the first transistor T1 and the second drain D2 of the second transistor T2. In other words, a DC current path may not be formed between the first transistor T1 and the second transistor T2.

In an embodiment, an undercut shape may be formed in the connection line 130. In detail, an undercut shape may be formed by an end of the first connection line 131 adjacent to the break-off portion 135 and an end of the second connection line 133 adjacent to the break-off portion 135.

In an embodiment, the pixel electrode 210 may not overlap the break portion 135. In detail, the pixel electrode 210 and the break portion 135 may not overlap each other when viewed from the thickness direction of the substrate 100. In addition, the pixel electrode 210 may not overlap the first, second, and third holes H1, H2, and H3. The pixel electrode 210 may not overlap the connection line 130. However, the present disclosure is not limited thereto. The pixel electrode 210 may at least partially overlap the connection line 130.

Referring to fig. 13, a pixel defining layer 180 may be formed on the first insulating layer 111, the second organic insulating layer 123, and the pixel electrode 210. The pixel defining layer 180 may expose at least a portion of the pixel electrode 210.

At least a portion of the pixel defining layer 180 may be formed in the break-off portion 135. The pixel defining layer 180 may be formed in the third hole H3. For example, the pixel defining layer 180 may cover a side surface of the second organic insulating layer 123. The pixel defining layer 180 may be in direct contact with the connection line 130. For example, the pixel defining layer 180 may be in direct contact with the first and second connection lines 131 and 133. Further, the pixel defining layer 180 may be directly formed on the upper surface of the first insulating layer 111. However, the present disclosure is not limited thereto. As described above in fig. 6, when the connection line 130 is formed on the second insulating layer 113, the pixel defining layer 180 may be formed (or contact) with the upper surface of the second insulating layer 113.

In an embodiment, the light emitting layer 220 may be formed on the pixel electrode 210, and the opposite electrode 230 may be formed on the light emitting layer 220. The pixel electrode 210, the light emitting layer 220, and the opposite electrode 230 may form an organic light emitting diode OLED.

Fig. 14 is a schematic equivalent circuit diagram of a pixel circuit PC in a process of manufacturing a display device according to an embodiment, and fig. 15 is a schematic plan view of the display device in the manufacturing process according to an embodiment. In detail, fig. 14 and 15 are equivalent circuit diagrams and plan views, respectively, of the pixel circuit PC in an operation of performing an array test. The equivalent circuit diagram and the plan view of the pixel circuit PC of fig. 14 and 15 may correspond to the cross-sectional view of fig. 9.

As shown in fig. 2, when a capacitor (e.g., the second capacitor Cst 2) is arranged between the first node N1 and the second node N2, a DC current path is not formed between the first node N1 and the second node N2, so that it is difficult to perform an array test on the pixel circuit PC.

In other words, when the first transistor T1 and the second transistor T2 are not connected to each other through a line and/or a connection line, there is no DC current path between the first transistor T1 and the second transistor T2, so that it is difficult to perform an array test. In other words, it is difficult to detect poor electrical performance of the wiring and/or the transistor formed on the substrate 100.

For example, although the array test may be performed due to the DC current path existing along the Data line DL for transmitting the Data voltage Data (or the Data signal), the second transistor T2, the fifth transistor T5, and the reference voltage line VRL for transmitting the reference voltage Vref, it is difficult to perform the array test due to the capacitor (e.g., the second capacitor Cst 2) between the first node N1 and the second node N2 not existing an additional DC current path with respect to the Data voltage Data (or the Data signal). In other words, since the poor electrical properties of the first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are not detected in advance, a defect rate after manufacturing the display device may be increased, so that the yield of the manufacturing process may be reduced.

In the embodiment, since it is possible to perform an array test on the pixel circuit PC by using the connection line 130 formed on the first insulating layer 111 or the second insulating layer 113, a defect rate after manufacturing the display device may be reduced and a yield of a manufacturing process may be improved simultaneously. In detail, as shown in fig. 9, 14 and 15, the first source S1 of the first transistor T1 and the second drain D2 of the second transistor T2 may be electrically connected to each other through a connection line 130. Since the first source S1 of the first transistor T1 and the second drain D2 of the second transistor T2 are electrically connected to each other, a DC current path may be formed between the first transistor T1 and the second transistor T2. Since a DC current path is formed between the first transistor T1 and the second transistor T2, the Data voltage Data (or the Data signal) is transferred to the first transistor T1, and thus, array test may be performed on the first, third, fourth, sixth, seventh, eighth, and ninth transistors T1, T3, T4, T6, T7, T8, and T9. Accordingly, by allowing the array test of the pixel circuits PC through the connection lines 130, poor electrical performance of the wires and/or transistors on the arrangement substrate 100 can be detected in advance, and thus a defect rate after manufacturing the display device can be reduced, and thus the yield of the manufacturing process can be improved.

By disconnecting the connection lines 130 after performing the array test by using the connection lines 130, there is no need to arrange additional transistors and/or additional signal lines for the array test in the pixel circuit PC, so that a high-resolution display device can be easily realized.

In other words, by disconnecting the connection line 130 after the array test is performed on the pixel circuit PC, a high resolution display device can be realized by nine transistors (e.g., the first transistor T1 to the ninth transistor T9) and two capacitors (e.g., the first capacitor Cst1 and the second capacitor Cst 2). In detail, by forming the connection line 130 connecting the first transistor T1 and the second transistor T2 on the insulating layer (e.g., the first insulating layer 111 or the second insulating layer 113) and performing an array test through the connection line 130, a defect rate is reduced by disconnecting the connection line 130 in a process of forming the pixel electrode 210 without an additional separate process, so that a yield of a manufacturing process is improved, and thus, a high resolution display device can be provided by high-speed driving.

According to one or more embodiments configured as described above, by allowing array testing of pixel circuits, defects of transistors in operation can be detected in advance, so that a display device having improved product reliability can be realized. The scope of the present disclosure is not limited by the above effects.

It should be understood that the embodiments described herein should be considered in descriptive sense only and not for purposes of limitation. The description of features or aspects within each embodiment should generally be considered as applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.

Claims

1. A display device, comprising:

a substrate;

a pixel circuit disposed on the substrate and including a first transistor and a second transistor;

an organic light emitting diode connected to the pixel circuit;

a connection line including a first connection line connected to the first transistor and a second connection line connected to the second transistor; and

and a disconnection portion disconnecting the first connection line and the second connection line from each other.

2. The display device according to claim 1, wherein the first connection line and the second connection line are formed in the same layer and comprise the same material.

3. The display device according to claim 1, wherein the first transistor comprises a first semiconductor layer arranged over the substrate and a first gate electrode insulated from the first semiconductor layer, and wherein

The second transistor includes a second semiconductor layer disposed on the substrate and a second gate electrode insulated from the second semiconductor layer.

4. A display device according to claim 3, wherein the pixel circuit further comprises:

a first capacitor including a first lower electrode disposed on the substrate and a first upper electrode insulated from the first lower electrode; and

and a second capacitor including a second lower electrode spaced apart from the first lower electrode and a second upper electrode insulated from the second lower electrode.

5. The display device according to claim 4, wherein the first gate electrode and the first lower electrode are formed in the same layer and comprise the same material.

6. The display device according to claim 5, wherein the connection line is arranged in the same layer as the first gate electrode.

7. The display device according to claim 5, wherein the connection line is arranged in the same layer as the first upper electrode.

8. A display device according to claim 3, wherein the first connection line is connected to the first semiconductor layer, and the second connection line is connected to the second semiconductor layer.

9. The display device according to claim 8, further comprising:

a first line connecting the first connection line with the first semiconductor layer; and

and a second line connecting the second connection line with the second semiconductor layer.

10. The display device according to claim 9, further comprising:

a first organic insulating layer covering the first line,

11. The display device according to claim 10, further comprising:

a third line disposed on the first organic insulating layer; and

a second organic insulating layer covering the third line,

wherein a second hole corresponding to the disconnection portion is defined in the second organic insulating layer.

12. The display device of claim 11, wherein a width of the first aperture is greater than a width of the second aperture.

13. The display device according to claim 1, wherein the organic light emitting diode includes a pixel electrode, a light emitting layer, and a counter electrode, and

the pixel electrode does not overlap the disconnection portion.

14. The display device of claim 13, further comprising a pixel defining layer exposing at least a portion of the pixel electrode,

wherein at least a portion of the pixel defining layer is disposed in the disconnected portion.

15. The display device of claim 14, wherein the pixel defining layer is in direct contact with the connection line.

16. A method of manufacturing a display device, the method comprising:

forming a pixel circuit including a first transistor and a second transistor and a connection line connecting the first transistor and the second transistor over a substrate;

performing an array test on the pixel circuit; and

and disconnecting the connecting wire.

17. The method of claim 16, wherein the forming a pixel circuit including a first transistor and a second transistor on a substrate and a connection line connecting the first transistor and the second transistor comprises:

forming a first semiconductor layer and a second semiconductor layer on the substrate;

Forming a first insulating layer on the first semiconductor layer and the second semiconductor layer;

forming the connecting wire on the first insulating layer;

forming a second insulating layer on the connection line, wherein a first hole for exposing at least a portion of the connection line is defined in the second insulating layer;

forming a first line and a second line on the second insulating layer;

forming a first organic insulating layer on the first line and the second line, wherein a second hole for exposing at least a portion of the connection line is defined in the first organic insulating layer; and

a third line is formed on the first organic insulating layer.

18. The method of claim 17, wherein the first transistor further comprises a first gate electrode insulated from the first semiconductor layer, and

the first gate electrode and the connection line are formed in the same layer and include the same material.

19. The method of claim 17, wherein the first semiconductor layer and the connection line are connected to each other through the first line.

20. The method of claim 17, wherein the second semiconductor layer and the connection line are connected to each other through the second line.

21. The method of claim 17, further comprising: after the formation of the third line,

forming a second organic insulating layer on the third line, wherein a third hole for exposing at least a portion of the connection line is defined in the second organic insulating layer; and

and forming a pattern material on the connection line and the second organic insulating layer.

22. The method of claim 21, wherein the width of the first aperture is greater than the width of the second aperture.

23. The method of claim 21, wherein the width of the second aperture is greater than the width of the third aperture.

24. The method of claim 21, wherein, when the connection line is broken, the pattern material is etched to form a pixel electrode, and the connection line is etched to form a broken portion.

25. A method according to claim 24, wherein the pixel electrode does not overlap the disconnected portion.

26. The method of claim 24, further comprising: after the connection line is disconnected, a pixel defining layer for exposing at least a portion of the pixel electrode is formed.

27. The method of claim 26, wherein at least a portion of the pixel defining layer is formed in the disconnected portion.

28. The method of claim 27, wherein the pixel defining layer is in direct contact with the connection line.

29. The method of claim 16, wherein the pixel circuit further comprises a first capacitor and a second capacitor.

30. The method of claim 29, wherein the first capacitor comprises a first lower electrode and a first upper electrode insulated from the first lower electrode, and

the second capacitor includes a second lower electrode spaced apart from the first lower electrode and a second upper electrode insulated from the second lower electrode.