CN117080284A - Divided triple-well type on-chip solar cell and division optimization method thereof - Google Patents
Divided triple-well type on-chip solar cell and division optimization method thereof Download PDFInfo
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Abstract
The invention discloses a solar cell on a divided triple-well type wafer and a dividing optimization method thereof, which comprises a doped region, a light-sensitive PN junction and a surface metal electrode, wherein the light-sensitive PN junction is covered on the edge and the bottom of the doped region, and the surface metal electrode is a metal wire covered on the surface of the doped region. The method comprises the following steps: firstly, the photocurrent densities of a bottom light sensing area and a side light sensing area of a solar cell photodiode on a triple-well type wafer are calculated respectively, a bottom photocurrent coefficient and a side photocurrent coefficient can be calculated according to the geometric characteristics of the bottom light sensing area and the side light sensing area respectively, and finally, the optimal segmentation condition of the doped area is constructed. The invention seeks to obtain a formula and a method of an optimal combination mode of doped regions of a solar cell on a triple-well type wafer by distinguishing light sensation PN in the vertical direction and the horizontal direction. The invention is used as a solar cell on a divided triple-well type chip and a dividing optimization method thereof, and can be widely applied to the technical field of solar cells.
Description
Technical Field
The invention relates to the technical field of solar cells, in particular to a segmented triple-well type on-chip solar cell and a segmentation optimization method thereof.
Background
In recent years, with the development and popularization of the internet of things technology, various sensors, transceivers and processors are used and needed in a large amount as network nodes of the internet of things, but as a power supply, a power grid or a battery limits the application scene, the mobile capability and the service life of the network nodes to a large extent, so that the network nodes of the internet of things with the energy collecting function and the capability of realizing self-sufficient power supply are future development trends, an energy collecting system based on an on-chip solar cell is applied in the fields of the internet of things, a micro sensor, a wearable device and the like, and an energy collecting system using solar energy as an energy source mainly comprises an on-chip solar cell and a voltage converting circuit, and the energy utilization rate of the energy collecting system is the product of the photoelectric conversion efficiency of the on-chip solar cell and the voltage conversion efficiency of the voltage converting circuit. The method is characterized in that the photoelectric conversion efficiency of the solar cell is improved, so that the energy utilization rate of the energy collection system can be improved, however, the photoelectric conversion efficiency of the solar cell on the single-well plate manufactured by adopting the standard CMOS process is generally lower, and the photoelectric conversion efficiency of the solar cell on the chip cannot be improved through an improved process like that of a common photovoltaic cell due to the limitation of the standard CMOS process, so that the optimal design of the structure of the solar cell on the chip realized under the standard CMOS process is a main means for improving the photoelectric conversion efficiency of the solar cell on the chip;
Furthermore, in order to improve the photoelectric conversion efficiency of the solar cell on the chip, some scholars begin to study from the angle of PN junction shape, design the shape of P+/N-well, the efficiency is improved by 6%, through holes are dug in the N-well, test results show that when the side length of the holes is 1.4 mu m, the short circuit current of the solar cell on the chip is improved by 1% compared with that of the solar cell without the dug holes, the solar cell on the chip is formed by connecting a plurality of N+ slender strips in parallel in the P-well, the effect is better than that of a single rectangular N+/P-well with the same area, and in addition, the solar cell on the triple-well plate is manufactured by utilizing doped regions with different depths and concentrations in the triple-well structure, and compared with the solar cell on the single-well plate, the solar cell on the triple-well plate has more bottom light-sensitive PN junctions, so that the solar cell on the triple-well plate has stronger photoelectric conversion capability;
however, both of the above ways of improving the photoelectric conversion efficiency consider only the photo-induced PN junction in one direction, which means that the photoelectric conversion efficiency of the on-chip solar cell will be further improved if the photo-induced PN junctions in both directions are considered at the same time. However, how to divide the triple wells to achieve the maximum photoelectric conversion efficiency is an unavoidable problem, and a large number of combination modes exist among the divided triple wells, so that the unreasonable combination modes cannot improve the photoelectric conversion capability of the on-chip solar cell, and the unreasonable combination modes may cause adverse effects.
Disclosure of Invention
In order to solve the technical problems, the invention aims to provide a divided triple-well type on-chip solar cell and a division optimization method thereof, wherein a formula and a method for obtaining an optimal combination mode of doped regions of the triple-well type on-chip solar cell are sought by distinguishing light sensation PN in two directions of vertical and horizontal.
The first technical scheme adopted by the invention is as follows: the utility model provides a solar cell on three well type piece that is cut apart, includes doped region, light sense PN junction and surface metal electrode, the edge and the bottom of doped region cover have light sense PN junction, surface metal electrode for cover in the metal wire of doped region surface, wherein:
the doped region is used for providing dopants with different doping concentrations;
the photoinduced PN junction is used for separating photo-generated electron hole pairs to generate photo-generated current;
the surface metal electrode is used for collecting and conveying photo-generated carriers of the doped region to generate solar cell output current.
Further, the doped region includes an n+ doped region, a P-sub doped region, a DNW doped region and a PW doped region, wherein the P-sub doped region is a substrate of a solar cell on a divided triple-well type wafer, the DNW doped region is wrapped in the P-sub doped region, the PW doped region is wrapped in the DNW doped region, and the n+ doped region is wrapped in the PW doped region, wherein:
The N+ doped region is used for providing high-concentration N-type doping and forms a shallow PN junction with the PW doped region and the P-sub doped region respectively;
the DNW doped region is used for providing low-concentration n-type doping, and respectively forms a sub-deep PN junction with the PW doped region and a deep PN junction with the P-sub doped region;
the PW doped region is used for providing low-concentration P-type doping, and forms the shallow PN junction with the N+ doped region and the sub-deep PN junction with the DNW doped region respectively;
the P-sub doped region is used for forming a substrate of the solar cell on the divided triple-well type wafer through the low-concentration P-type doping.
Further, the light-sensitive PN junction includes a side light-sensitive PN junction and a bottom light-sensitive PN junction, where the side light-sensitive PN junction is a longitudinal PN junction formed at an edge of the doped region, and the bottom light-sensitive PN junction is a longitudinal PN junction formed at a bottom of the doped region, where:
the side light-sensitive PN junction is used for separating photo-generated electron hole pairs of the side light-sensitive PN junction to form photocurrent of the side light-sensitive PN junction;
the bottom light-sensitive PN junction is used for separating photo-generated electron hole pairs of the bottom light-sensitive PN junction to form photocurrent of the bottom light-sensitive PN junction.
Further, the surface metal electrode includes an n+ surface metal electrode, a DNW surface metal electrode, a PW surface metal electrode, and a P-sub surface metal electrode, where the n+ surface metal electrode is disposed on the upper surface of the n+ doped region, the DNW surface metal electrode is disposed on the upper surface of the DNW doped region, the PW surface metal electrode is disposed on the upper surface of the PW doped region, and the P-sub surface metal electrode is disposed on the upper surface of the P-sub doped region, where:
The N+ surface metal electrode is used for collecting and conveying photo-generated carriers generated by the N+ doped region to form an N+ doped region photocurrent;
the DNW surface metal electrode is used for collecting and conveying photo-generated carriers generated by the DNW doped region to form DNW doped region photocurrent;
the PW surface metal electrode is used for collecting and conveying photogenerated carriers generated by the PW doped region to form PW doped region photocurrent;
the P-sub surface metal electrode is used for collecting and conveying photo-generated carriers generated by the P-sub doped region to form a P-sub doped region photocurrent.
Further, the substrate of the divided triple-well type on-chip solar cell further comprises a substrate formed by N-base silicon, wherein for the substrate of the divided triple-well type on-chip solar cell formed by the N-base silicon, the triple-well structure is an N-type substrate N-sub, a deep P-well region DPW, an N-well region NW and a P-type high doping region P+, and for the substrate of the divided triple-well type on-chip solar cell formed by the low-concentration P-type doping, the triple-well structure is an N+ doping region, a P-sub doping region, a DNW doping region and a PW doping region.
The second technical scheme adopted by the invention is as follows: a segmentation optimization method of a segmented triple-well type on-chip solar cell comprises the following steps:
Acquiring the photocurrent density of a photo-induced PN junction through a photocurrent density formula of a photo-induced region of a photo-diode, wherein the photocurrent density of the photo-induced PN junction comprises the photocurrent density of a side photo-induced PN junction and the photocurrent density of a bottom photo-induced PN junction;
introducing an auxiliary coefficient, and determining the area of the side light-sensitive PN junction and the area of the bottom light-sensitive PN junction;
determining a light sensation coefficient of the side light sensation PN junction according to the light current density of the side light sensation PN junction and the area of the side light sensation PN junction;
determining a light sensation coefficient of the bottom light sensation PN junction according to the light current density of the bottom light sensation PN junction and the area of the bottom light sensation PN junction;
determining the coverage area of the surface metal electrode, wherein the coverage area of the surface metal electrode is the sum of the coverage area of the N+ surface metal electrode, the coverage area of the DNW surface metal electrode and the coverage area of the PW surface metal electrode;
dividing a doped region to obtain a divided doped region, wherein the doped region comprises the N+ doped region, the DNW doped region and the PW doped region;
and constructing optimal segmentation conditions of the doped region according to the segmented doped region, the coverage area of the surface metal electrode, the light sensation coefficient of the side light sensation PN junction and the light sensation coefficient of the bottom light sensation PN junction.
Further, the step of introducing an auxiliary coefficient to determine the area of the side light-sensitive PN junction and the area of the bottom light-sensitive PN junction specifically includes:
acquiring the width of an N+ doped region and the width of the P-sub doped region;
setting the size of the photoinduced PN junction to be larger than the size of the doped region by considering the peripheral response of the photoinduced carriers on the doped region;
constructing the auxiliary coefficient according to the ratio of the size of the light-sensitive PN junction to the size of the doped region;
and determining the area of the side light-sensitive PN junction and the area of the bottom light-sensitive PN junction according to the auxiliary coefficient.
Further, the step of constructing an optimal division condition of the doped region according to the divided doped region, the coverage area of the surface metal electrode, the light-sensing coefficient of the side light-sensing PN junction and the light-sensing coefficient of the bottom light-sensing PN junction specifically includes:
based on the segmented doped region, acquiring the side length of the N+ doped region, the side length of the PW doped region and the side length of the DNW doped region which are respectively l 1 、l 2 And l 3 The number of divided N+ doped regions, the number of divided PW doped regions and the number of divided DNW doped regions are respectively N 1 、n 2 And n 3 ；
According to the coverage area of the N+ surface metal electrode and the side length l of the N+ doped region after being divided 1 And the number N of divided N+ doped regions 1 Calculating the photo-generated current after the N+ doped region is divided;
according to the coverage area of the PW surface metal electrode and the side length l of the PW doped region after being divided 2 And the number n of divided PW doped regions 2 Calculating the photo-generated current of the PW doped region after being divided;
according to the coverage area of the DNW surface metal electrode and the side length l of the DNW doped region after being divided 3 And the number n of divided DNW doped regions 3 Calculating photo-generated current after the DNW doped region is segmented;
accumulating the photo-generated current after the N+ doped region is divided to obtain the photo-generated current of the N+ doped region;
accumulating the photo-generated current of the DNW doped region after being divided to obtain the photo-generated current of the DNW doped region;
accumulating the divided photogenerated currents of the PW doped region to obtain the photogenerated currents of the PW doped region;
integrating the photo-generated current of the N+ doped region, the photo-generated current of the DNW doped region and the photo-generated current of the PW doped region to obtain the photo-generated current of the solar cell on the divided triple-well type sheet;
Deriving the photo-generated current of the solar cell on the divided triple-well type wafer to obtain the value of the side length of the N+ doped region after division, the value of the side length of the DNW doped region after division and the value of the side length of the PW doped region after division;
and constructing the optimal segmentation condition of the doped region according to the segmented side length value of the N+ doped region, the segmented side length value of the DNW doped region and the segmented side length value of the PW doped region by combining the light sensation coefficient of the side light sensation PN junction, the light sensation coefficient of the bottom light sensation PN junction and the coverage area of the surface metal electrode.
Further, the expression of the optimal segmentation condition of the doped region is as follows:
in the above, l 0 A represents the light sensation coefficient of the bottom light sensation PN junction, b represents the light sensation coefficient of the side light sensation PN junction, d 0 Representing the spacing of two divided doped regions S 0 The coverage area of the surface metal electrode is shown.
Further, the solar cell on the triple-well type wafer is segmented through optimal segmentation conditions, wherein the DNW doped regions in the P-sub doped regions are segmented into a plurality of segmented DNW doped regions, the PW doped regions in each segmented DNW doped region are segmented into a plurality of segmented PW doped regions, and the N+ doped regions in each segmented PW doped region are segmented into a plurality of segmented N+ doped regions.
The battery and the segmentation method have the beneficial effects that: the invention adopts the divided triple-well structure to manufacture the solar cell on the chip, so that the light-sensitive PN junctions in the vertical and horizontal directions are increased simultaneously, thereby obtaining the solar cell on the chip with higher photoelectric conversion efficiency, further focusing on the light-sensitive PN area of the photodiode, distinguishing the light-sensitive PN in the vertical and horizontal directions, respectively calculating the photocurrent densities of the bottom light-sensitive area and the side light-sensitive area of the solar cell on the triple-well chip, respectively calculating the bottom photocurrent coefficient and the side photocurrent coefficient according to the geometric characteristics of the bottom light-sensitive area and the side light-sensitive area, finally constructing the optimal dividing condition of the doped area, searching the optimal dividing combination mode, and being applicable to solving the optimal divided device structures of the solar cells on the triple-well chip with different technologies and different areas.
Drawings
FIG. 1 is a schematic diagram of a divided triple-well on-chip solar cell according to the present invention;
FIG. 2 is a flow chart of steps of a method for optimizing the division of a divided triple-well type on-chip solar cell according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an N+/P-sub single well type on-chip solar cell according to an embodiment of the present invention;
FIG. 4 is a schematic view of a segmented N+/P-sub single well on-chip solar cell in accordance with an embodiment of the present invention;
FIG. 5 is a schematic diagram of a triple-well on-chip solar cell according to an embodiment of the present invention;
fig. 6 is a schematic plan view of a solar cell on a triple-well type wafer divided according to an embodiment of the present invention.
Reference numerals: 1. an N+ doped region; 2. a P-sub doped region; 3. a lateral light-sensitive PN junction; 4. a bottom light-sensitive PN junction; 5. a surface metal electrode; 5-1, N+ surface metal electrode; 5-2, PW surface metal electrode; 5-3, DNW surface metal electrode; 5-4, P-sub surface metal electrodes; 6. a DNW doped region; 7. and PW doped region.
Detailed Description
The invention will now be described in further detail with reference to the drawings and to specific examples. The step numbers in the following embodiments are set for convenience of illustration only, and the order between the steps is not limited in any way, and the execution order of the steps in the embodiments may be adaptively adjusted according to the understanding of those skilled in the art.
The integration of energy harvesting systems and functional circuits into the same chip as miniature electronic products with self-powered functionality has been verified and implemented in many reports. The integrated solar cell on the chip by adopting the CMOS standard process improves the integration level of the chip, is beneficial to the miniaturization of electronic products, can simplify the manufacturing process to obtain lower manufacturing cost, and mainly comprises the solar cell on the chip and a voltage conversion circuit. The energy utilization rate of the energy collection system is the product of the photoelectric conversion efficiency of the on-chip solar cell and the voltage conversion efficiency of the voltage conversion circuit. This means that the energy utilization of the energy collection system can be improved by improving the photoelectric conversion efficiency of the solar cell;
However, the photoelectric conversion efficiency of the solar cell on the single-well plate manufactured by the standard CMOS process is generally low. The photoelectric conversion efficiency of the solar cell on the single-well plate made of the P+/N-well structure is only 2.1 percent. The photoelectric conversion efficiency of the solar cell on the single-well plate made of the N+/P-sub structure is 5.73%. The photoelectric conversion efficiency of the solar cell on the single-well plate manufactured by the NW/P-sub structure is highest, but the photoelectric conversion efficiency can only reach 7.45%, and the lower photoelectric conversion efficiency ensures that the solar cell with a larger area can meet the energy consumption required by a functional circuit. This is clearly contrary to our best high integration, miniaturization and low cost. And due to the limitation of a standard CMOS process, the on-chip solar cell cannot be like a common photovoltaic cell, and the photoelectric conversion efficiency of the on-chip solar cell is improved by improving the process. Therefore, for the on-chip solar cell realized under the standard CMOS process, through the optimized design of the structure of the on-chip solar cell is the main means for improving the photoelectric conversion efficiency, in other researches, the solar cell on the three-well chip is manufactured by utilizing the doped regions (DNW, PW and n+) with different depths and concentrations in the triple-well structure (a triple-well structure), and compared with the solar cell on the single-well chip, the solar cell on the three-well chip has more bottom light-sensitive PN junctions 4, thereby also having stronger photoelectric conversion capability, but both the ways of improving the photoelectric conversion efficiency only consider the light-sensitive PN junctions in one direction, which means that if the light-sensitive PN junctions in two directions are considered simultaneously, the photoelectric conversion efficiency of the solar cell on the chip is further improved. However, how to divide the triple wells to achieve the maximum photoelectric conversion efficiency is an unavoidable problem, and a large number of combination modes exist among the divided triple wells, so that the unreasonable combination modes cannot improve the photoelectric conversion capability of the on-chip solar cell, and the unreasonable combination modes can also cause adverse effects;
Based on the above, the invention aims to overcome the defect of low photoelectric conversion efficiency of the existing on-chip integrated solar cell, and provides a divided triple-well type photodiode structure so as to improve the photoelectric conversion efficiency of the on-chip solar cell. However, since the three doped regions DNW, PW, n+ of the triple-well photodiode can be divided, there are a large number of combinations between them. Therefore, in order to find the optimal combination mode of the segmentation, the invention also deduces a set of formulas and methods for finding the optimal combination mode of the triple well through modeling the photodiode, and can be used for solving the device structures of the optimal segmentation of the solar cells on the triple well type chips with different processes and different areas; the invention adopts the design concept of increasing the side light-sensitive PN junction 3 by utilizing the segmented doping region to be used for a triple-well structure, realizes a novel structure that the side light-sensitive PN junction 3 and the bottom light-sensitive PN junction 4 can be increased simultaneously, and the solar cell on the chip manufactured by utilizing the novel structural design has higher photoelectric conversion efficiency, and the solar cell with the novel structure is called as: a solar cell on the divided triple-well type wafer; the design concept of dividing the doped region to increase the lateral light-sensitive PN junction 3 is derived from the existing research mentioned in the background art, and the core concept of the concept is that more lateral light-sensitive PN junctions 3 can be obtained by using a plurality of small doped regions to replace a large doped region under the same area; the side light-sensitive PN junction 3 refers to a longitudinal PN junction formed at the edge of the doped region, and the bottom light-sensitive PN junction 4 refers to a transverse PN junction formed at the bottom of the doped region; by "on-chip solar cell" is meant a photodiode that is integrally fabricated on a chip for achieving photoelectric conversion.
Referring to fig. 1, the invention provides a divided triple-well type on-chip solar cell, comprising a doped region, a photosensitive PN junction and a surface metal electrode 5, wherein the edge and the bottom of the doped region are covered with the photosensitive PN junction, the surface metal electrode 5 is a metal wire covered on the surface of the doped region, wherein:
the doped region is used for providing dopants with different doping concentrations;
further, the doped region further comprises an N+ doped region 1, a P-sub doped region 2, a DNW doped region 6 and a PW doped region 7, wherein the P-sub doped region 2 is a substrate of the solar cell on the divided triple-well type wafer, the DNW doped region 6 is wrapped in the P-sub doped region 2, the PW doped region 7 is wrapped in the DNW doped region 6, the N+ doped region 1 is wrapped in the PW doped region 7, and the N+ doped region 1 is used for providing high-concentration N-type doping and forms a shallow PN junction with the PW doped region 7 and the P-sub doped region 2 respectively; the DNW doped region 6 is used for providing low-concentration n-type doping, and respectively forms a sub-deep PN junction with the PW doped region 7 and a deep PN junction with the P-sub doped region 2; the PW doped region 7 is used for providing low-concentration P-type doping, and forms a shallow PN junction with the N+ doped region 1 and a sub-deep PN junction with the DNW doped region 6 respectively; the P-sub doped region 2 is used for forming a substrate of the solar cell on the divided triple-well type wafer through low-concentration P-type doping; the photoinduced PN junction is used for separating the photo-generated electron hole pairs to generate photoinduced PN junction photocurrent;
The divided triple-well on-chip solar cell can also be realized by adopting N-base silicon. Triple well structure corresponding to P-base silicon: the triple well structure of P-sub, DNW, PW and N+ substrate silicon is as follows: n-sub (N-type substrate), DPW (deep P-well region), NW (N-well region), p+ (P-type highly doped region).
The photoinduced PN junction is used for separating photogenerated electron-hole pairs to generate photogenerated current;
further, the photo-induced PN junction further comprises a side photo-induced PN junction 3 and a bottom photo-induced PN junction 4, wherein the side photo-induced PN junction 3 is a longitudinal PN junction formed at the edge of the doped region, the bottom photo-induced PN junction 4 is a longitudinal PN junction formed at the bottom of the doped region, the side photo-induced PN junction 3 is used for separating photo-generated electron-hole pairs of the side photo-induced PN junction 3 to form photocurrent of the side photo-induced PN junction 3, and the bottom photo-induced PN junction 4 is used for separating photo-generated electron-hole pairs of the bottom photo-induced PN junction 4 to form photocurrent of the bottom photo-induced PN junction 4;
in this embodiment, a photodiode approximation model is used for a solar cell on a triple-well type sheet, and under a constraint condition, a combination mode of a theoretical optimal triple-well (DNW, PW, n+) is obtained by calculating and deducing the model, the solar cell on the triple-well type sheet designed by adopting the combination mode has the maximum photocurrent, and the solar cell on the triple-well type sheet obtained by calculating and solving with the aid of the proposed model is called: an optimized-divided triple-well on-chip solar cell; the term "limiting conditions" refers to parameters determined by the process and layout mode used in the present invention, the process used is 0.18 μm standard CMOS, and the fabricated on-chip solar cell has an area of 0.1mm 2 The method comprises the steps of carrying out a first treatment on the surface of the The triple well refers to a device structure formed by manufacturing a deep N well low doped region DNW in a P-type substrate P-sub, forming a doped region PW in the P well in the DNW, and finally injecting an N type high doped region N+ in the PW; by "inter-triple-well combination" is meant that the use of different division modes for the three doped regions of different concentrations and depths of DNW, PW, n+ respectively will result in different device structures, e.g., combination mode DNW: PW: n+=1:2:4 indicates that bits are to be writtenThe DNW in the P-sub is divided into 1 block (i.e. no division is made), PW in the DNW is divided into 2 blocks, and N+ in each PW is divided into 4 blocks; for another example, combining DNWs: PW: n+=4:2:1 means dividing the DNWs located in P-sub into 4 blocks, dividing PW located in each DNW into 2 blocks, and dividing n+ located in each PW into 1 block (i.e., not dividing).
The surface metal electrode 5 is used for collecting and transporting photo-generated carriers in the doped region to generate solar cell output current.
Further, the surface metal electrode 5 further comprises an N+ surface metal electrode 5-1, a DNW surface metal electrode 5-3, a PW surface metal electrode 5-2 and a P-sub surface metal electrode 5-4, wherein the N+ surface metal electrode 5-1 is arranged on the upper surface of the N+ doped region 1, the DNW surface metal electrode 5-3 is arranged on the upper surface of the DNW doped region 6, the PW surface metal electrode 5-2 is arranged on the upper surface of the PW doped region 7, the P-sub surface metal electrode 5-4 is arranged on the upper surface of the P-sub doped region 2, and the N+ surface metal electrode 5-1 is used for collecting and conveying photogenerated carriers generated by the N+ doped region 1 to form photocurrent of the N+ doped region 1; the DNW surface metal electrode 5-3 is used for collecting and conveying photo-generated carriers generated by the DNW doped region 6 to form a DNW doped region 6 photocurrent; the PW surface metal electrode 5-2 is used for collecting and conveying photogenerated carriers generated by the PW doped region 7 to form PW doped region photocurrent; the P-sub surface metal electrode 5-4 is used for collecting and conveying photo-generated carriers generated by the P-sub doped region 2 to form a P-sub doped region 2 photocurrent;
In the embodiment, the invention also establishes a photodiode approximate model capable of focusing on the light-sensitive PN junction and the surface metal electrode 5; the surface metal electrode 5 refers to a contact electrode of a doped region of the photodiode and a metal wire for connecting and leading out the contact electrodes, the division leads to the increase of the surface metal electrode 5 while the increase of the light-sensitive PN junction is caused, and the increase of the surface metal electrode 5 can shield more incident light, thereby negatively affecting the photoelectric conversion capability of the photodiode; the basic model of the photodiode approximation model is shown in fig. 3, and can be used for optimizing other structures, such as a single-well photodiode shown in fig. 4 or a triple-well photodiode shown in fig. 5, and the model is an approximation model which is suitable for trend analysis and aided design and is not suitable for accurate calculation because the considered model idealizes irregular doping areas and partial process parameters cannot obtain accurate values because of commercial confidentiality of wafer manufacturers, and certainly means that the approximation model can be suitable for various process procedures and only needs to obtain approximate orders of magnitude of parameters such as doping concentration, depth and the like of the used process; the approximate model is characterized in that the influence of division on the light band conversion capability of the photodiodes can be highlighted by reflecting the side light sensation PN junction 3 and the bottom light sensation PN junction 4 of the photodiodes with different structures and the surface metal electrode 5 of the side light sensation PN junction.
Referring to fig. 2, a method for optimizing the division of a solar cell on a divided triple-well type wafer includes the steps of:
s1, acquiring the photocurrent density of a side light-sensitive PN junction 3 and the photocurrent density of a bottom light-sensitive PN junction 4 through a photocurrent density formula of a light-sensitive area of a photodiode;
specifically, J is the photo-generated current density of the photo-sensing region, and the calculation formula of the incident light intensity per unit area, the calculation formula of the quantum efficiency and the calculation formula of the light absorption coefficient are all brought into the calculation formula of the photo-current density of the photo-sensing region of the photodiode, so that the photo-current density of the photo-sensing region of the photodiode can be calculated, and the calculation formula of the photo-current density of the photo-sensing region of the photodiode is specifically shown as follows:
in the above formula, J represents the photocurrent density of the photosensitive region of the photodiode, e represents the basic charge, QD (λ, d) represents the quantum efficiency, Φ inc (λ, ts) represents incident light intensity per unit area, λ represents incident light wavelength, ts represents blackbody temperature, and d represents incident depth of incident light;
in the calculation formula of the photocurrent density of the photodiode light sensing region, the quantum efficiency QE (λ, d) is the average number of photoelectrons generated per unit time and the number of incident photons Ratio of; e represents the basic charge, and is the charge quantity of one electron, which is 1.602×10 -19 C. Incident light intensity per unit area phi inc (λ, ts) is a function of the wavelength λ of the incident light and the temperature Ts of the black body, and the calculation formula of the incident light intensity per unit area is specifically as follows:
in the above, phi inc (lambda, ts) represents incident light intensity per unit area, lambda represents incident light wavelength, ts represents blackbody temperature, F s Representing the solar geometric factors, c, h, k B Respectively represent the constant of the light velocity, the Planck constant and the Boltzmann constant;
the number of photons with the wavelength lambda in unit area and unit time is expressed, and the number can be deduced through a blackbody radiation formula and a photon energy calculation formula. Since for solar cells Ts is a constant (the sun is considered approximately as a 6000k black body), only the wavelength λ of the incident light needs to be considered, therefore Φ inc The incident light intensity can be reduced to a function that is dependent only on the wavelength lambda of the incident light, c, h, k B Respectively the constant of the light velocity, the Planck constant and the Boltzmann constant, F s Called the sun geometry factor, which reflects the geometrical relationship between the sun and the earth, F due to the almost constant spherical diameter and relative position of the sun and the earth itself s Also considered as constant, take on a value of 2.15X10 -5 Pi. The quantum efficiency QE (λ, d) is the ratio of the average number of photoelectrons generated per unit time to the number of incident photons, and is a function of the wavelength λ of the incident light and the incident depth d, as shown in the calculation formula of quantum efficiency:
QE(λ,d)＝1-exp[-α(λ)d]
in the above formula, QE (λ, d) represents quantum efficiency, and α represents a light absorption coefficient of single crystal silicon;
where α is referred to as the light absorption coefficient, which in the present invention represents the thickness of the single crystal silicon material required for the incident light having a wavelength λ to be completely absorbed, the expression is specifically as follows:
in the above, E gj (T) represents the band gap energy across which electrons transition from the valence band to the conduction band at a different energy level, E pi Represents phonon energy in a monocrystalline silicon lattice, T represents an ambient temperature at which the monocrystalline silicon is located, v represents a frequency of incident light, k represents a Boltzmann constant, A ij Representing fitting coefficients, A d Representing correction coefficients, E gd (T) represents band gap energy, and α (hv, T) represents light absorption coefficient;
the light absorption coefficient alpha of monocrystalline silicon is determined by the phonon energy E in the crystal lattice p1 、E p2 Band gap energy E across which electrons transition from valence band to conduction band at different energy levels g1 、E g2 、E gd The ambient temperature T at which the silicon single crystal is located and the frequency v of the incident light are commonly determined. A is a fitting coefficient, and ensures that the calculated value and the measured value of the light absorption capacity of silicon in the energy range of 1.1-4.0 eV (namely, the wavelength of 0.25-1.127 μm) at room temperature (t=300 k) are more fit. The parameters mentioned above can all be looked up in table 1.
TABLE 1 constant values of empirical formula for silicon absorption coefficient
As shown in fig. 3, an on-chip solar cell made of heavily doped n+ and P-type substrate P-sub, the light sensing region can be considered as two parts. One part is a bottom light-sensitive PN junction 4 formed by the bottom boundary of the N+ region and the P-sub along the horizontal direction; the other part is a lateral light sense PN junction 3 formed by the peripheral boundary of the N+ region and the P-sub along the vertical direction; since their light-sensitive PN junctions differ in spatial geometry, theyThe photo-generated currents (i.e. photo-generated current densities) per unit area are respectively J b And J e And (3) representing. Because the photocurrent of the photodiode is equal to the product of the photocurrent density and the area of the light sensing region, the next step is to solve for the area of the light sensing region of the photodiode.
S2, introducing an auxiliary coefficient, and determining the area of the side light-sensitive PN junction 3 and the area of the bottom light-sensitive PN junction 4;
specifically, the width of the N+ doped region 1 and the width of the P-sub doped region 2 are obtained; taking the peripheral response of the photogenerated carriers on the doped region into consideration, setting the size of the light-sensitive PN junction to be larger than that of the doped region; constructing an auxiliary coefficient according to the ratio of the size of the light-sensitive PN junction to the size of the doped region; determining the area of the side light-sensitive PN junction 3 and the area of the bottom light-sensitive PN junction 4 according to the auxiliary coefficient;
In this embodiment, the width W of the N+ side depletion region can be calculated by the following formula DN Width W of depletion region on P-sub side DP The calculation formulas of the width of the N+ side depletion region and the width of the P-sub side depletion region are as follows:
in the above, W DP Represents the width of the P-sub side depletion region, W DN Represents the width of the N+ side depletion region, N A Represents acceptor doping concentration, N D Represents the donor doping concentration, ε s Represents the dielectric constant, ψ, of a silicon material bi Representing the built-in potential difference, q represents the amount of meta-charge;
where d is the depth of implantation of the n+ doped region 1 (which can also be regarded approximately as the junction depth of n+ and P-sub), but it is notable that due to the diffusion motion of the photogenerated carriers, the region near the outside of the depletion region can collect the photogenerated carriers to some extent, a phenomenon called peripheral response. The actual light sensing area is larger than the depletion region due to the presence of the peripheral response. But in the light sensing region the probability of collecting photogenerated carriers located further from the depletion region is lower. Therefore, in order to achieve both model accuracy and computation convenience, we assume that the probability of collecting photogenerated carriers in the entire photosensitive region is equal to that of the depletion region, and at the same time, as compensation, the assumed photosensitive region should be smaller than the range of the real photosensitive region, so as to ensure that the same number of carriers can be collected in the assumed photosensitive region and the real photosensitive region. This makes the assumed size of the light sensitive area necessarily larger than the size of the depletion region and smaller than the size of the actual light sensitive area, so the present invention introduces a factor k larger than 1 to assist in representing the size of the light sensitive area in the model, i.e. the size of the light sensitive area in the model is k times the size of the associated depletion region. However, the coefficient k is related to the doping concentration, the diffusion length of the photo-generated carriers, the surface recombination and other factors forming the depletion region, and because the factors to be considered are too many and most of the process parameters are known only in a fuzzy value range, accurate values cannot be obtained through calculation, so that the approximate value of k is obtained through device simulation.
S3, determining a light sensation coefficient of the side light sensation PN junction 3 according to the photocurrent density of the side light sensation PN junction 3 and the area of the side light sensation PN junction 3;
s4, determining a light sensation coefficient of the bottom light sensation PN junction 4 according to the light current density of the bottom light sensation PN junction 4 and the area of the bottom light sensation PN junction 4;
in this embodiment, according to the geometrical distribution of the bottom and side light sensing regions in space, the above parameters are substituted into the calculation formula of the photocurrent density of the light sensing region of the photodiode to obtain the photo-generated current J of the bottom light sensing region of unit area b Is a formula of (1) and a photo-generated current J of a unit area side photosensitive area e Is expressed as follows:
in the above, J b Photo-generated current representing the area of the bottom photo-sensing region, J e A photo-generated current representing a unit area of the lateral photosensitive region;
in order to make the formula look more concise, the invention introduces a bottom light sensing area coefficient a and a side light sensing area coefficient b, and the corresponding relation distribution is as follows:
a＝J bottom
b＝k·(W DP +W DN )·J b
in the above formula, a represents the light sensation coefficient of the bottom light sensation PN junction 4, b represents the light sensation coefficient of the side light sensation PN junction 3, J bottom Indicating the photocurrent density, J, of the bottom-side photosensitive PN junction 4 b Represents the photocurrent density of the lateral light-sensitive PN junction 3, k represents the auxiliary coefficient, W DP Represents the width, W, of the P-sub doped region 2 DN Represents the width of the n+ doped region 1;
the N+ doped region 1 has a side length of l n So that the total short-circuit current of the on-chip photodiode is given by:
in the above, I SC Indicating the total short-circuit current of the photodiode, l n A value representing the length of the divided edge,representing the area of the doped region after segmentation.
S5, determining the coverage area of the surface metal electrode 5, wherein the coverage area of the surface metal electrode 5 is the sum of the coverage area of the N+ surface metal electrode 5-1, the coverage area of the DNW surface metal electrode 5-3 and the coverage area of the PW surface metal electrode 5-2;
s6, dividing a doped region to obtain a divided doped region, wherein the doped region comprises the N+ doped region 1, the DNW doped region 6 and the PW doped region 7;
s7, constructing the optimal segmentation condition of the doped region according to the segmented doped region, the coverage area of the surface metal electrode, the light sensitivity coefficient of the side light sensitive PN junction and the light sensitivity coefficient of the bottom light sensitive PN junction
Specifically, the photo-generated current after the n+ doped region 1 is divided, the photo-generated current after the DNW doped region 6 is divided, and the photo-generated current after the PW doped region 7 is divided are calculated, respectively; wherein, according to the coverage area of the N+ surface metal electrode and the side length l of the N+ doped region after being divided 1 And the number N of divided N+ doped regions 1 1 Calculating the photo-generated current after the N+ doped region 1 is divided; according to the coverage area of the PW surface metal electrode and the side length l of the divided PW doped region 6 2 And the number n of divided PW doped regions 6 2 Calculating the photo-generated current after the PW doped region 6 is divided; according to the coverage area of the DNW surface metal electrode and the side length l of the DNW doped region 7 after being divided 3 And the number n of divided DNW doped regions 7 3 Calculating the photo-generated current after the DNW doped region 7 is segmented; accumulating the divided photo-generated currents of the N+ doped region 1 to obtain the photo-generated currents of the N+ doped region 1; accumulating the photo-generated current of the DNW doped region 6 after being divided to obtain the photo-generated current of the DNW doped region; accumulating the divided photogenerated currents of the PW doped region 7 to obtain the photogenerated current of the PW doped region 7; integrating the photo-generated current of the N+ doped region 1, the photo-generated current of the DNW doped region and the photo-generated current of the PW doped region 7 to obtain the photo-generated current of the solar cell on the divided triple-well type sheet; deriving the photo-generated current of the solar cell on the divided triple-well type wafer to obtain the value of the side length of the N+ doped region 1 after division, the value of the side length of the DNW doped region 6 after division and the value of the side length of the PW doped region 7 after division; according to the value of the side length of the N+ doped region 1 after being divided, the value of the side length of the DNW doped region 6 after being divided and the value of the side length of the PW doped region 7 after being divided, combining the light sensation coefficient of the side light sensation PN junction 3 and the light sensation coefficient of the bottom light sensation PN junction 4 to construct the optimal dividing condition of the doped region;
In the present embodiment, in order to increase the collection energy of the photodiode for light energyAs shown in fig. 4, a large n+ doped region 1 is divided into a plurality of small n+ doped regions 1, and a large number of lateral light sensing regions are fabricated. Taking into account the design rules of the 0.18 μm process and the required distance between the contact electrode and the metal tracks, C0 represents the required distance between the N+ doped regions 1) P-sub, d 0 Representing the spacing l between the small N+ doped region 1 and the small N+ doped region 1 0 For the side length of the small N+ doped region 1, L 0 Is the total side length of the photodiode, S 0 Representing the metal coverage area caused by the contact electrode and wiring, reflects the loss of incident light, and because the shielding area caused by the metal coverage is mostly located directly above the bottom light-sensing area, only a small portion passes above the side light-sensing area, we mainly consider the overlapping portion of the shielding area and the bottom light-sensing area, while the overlapping portion of the side light-sensing area and the metal shielding area is ignored. The short-circuit current of each small N+ doped region 1 is calculated according to the general short-circuit current formula of the on-chip photodiode, and then the total photo-generated current of the on-chip photodiode can be obtained by accumulating all the photo-generated currents of the small N+ doped regions 1, which is specifically shown as follows:
In the above, I SC0 Indicating the total photo-generated current of the on-chip photodiode, l 0 Representing the side length of the small N + doped region 1,represents the number of small N+ doped regions 1 after division, S 0 Indicates the metal coverage area caused by contact electrode and wiring, < >>Representing the area of the doped region;
wherein n is 0 The method can be calculated by the following formula, and is specifically as follows:
in the above, L 0 Representing the total side length of the photodiode, d representing the spacing distance between the same doped regions, c representing the distance from the doped region to the edge of the base region where it is located;
by deriving the total photo-generated current of the on-chip photodiode, l can be obtained 0 When the optimal dividing condition of the doped region is met, the total photo-generated current I of the single-well photodiode SC0 Reaching a maximum. This shows that the optimal division scheme of the single-well photodiode is to design the side length l of the small N+ doped region 1 according to the value of the optimal division condition of the doped region 0 The expression of the optimal segmentation condition of the doped region is as follows:
in the above, l 0 A is a value indicating the side length of the divided doped region, a is a light sensation coefficient of the bottom light sensation PN junction 4, b is a light sensation coefficient of the side light sensation PN junction 3, and d is a light sensation coefficient of the side light sensation PN junction 3 0 Representing the spacing of two divided doped regions S 0 The coverage area of the surface metal electrode 5 is shown.
In summary, based on the quantitative division of the n+/P-sub single-well type on-chip solar cell using the model and the formula, the same model and formula are substituted into the triple-well type on-chip solar cell, so as to quantitatively divide the triple-well type on-chip solar cell, which is specifically as follows:
fig. 5 shows a triple-well on-wafer solar cell, in which the n+ doped region 1 is located in the PW doped region 7, the PW doped region 7 is located in the DNW doped region 6, the DNW doped region 6 is located in the substrate P-sub, the surface electrode of n+ is located above the n+ doped region 1, the surface electrode of PW is located above the PW doped region 7, the surface electrode of DNW is located above the DNW doped region 6, and these surface electrodes are all distributed in a ring shape.
The optimization method adopted in the N+/P-sub single-well type on-chip solar cell is extended and expanded to the on-chip solar cell with the triple-well structure,the optimized and segmented triple-well type on-chip solar cell can be obtained. As shown in FIG. 1, L is the total side length of the photodiode, d 1 Represents the distance, d, between the N+ doped region 1 and the N+ doped region 1 2 Represents the spacing, d, between the divided PW doped region 7 and the divided PW doped region 7 3 Representing the spacing, c, of the small DNW doped regions 6 from the small DNW doped regions 6 1 Is the distance from the N+ doped region 1 to the PW edge, c 2 Is the distance from PW doping region 7 to the edge of DNW, c 3 Is the distance from DNW doped region 6 to the edge of P-sub, S 1 Represents the metal electrode area of the N+ doped region 1, S 2 Represents the metal electrode area of PW doped region 7, S 3 The metal electrode area of the DNW doped region 6 is indicated (the surface metal electrode 5 of fig. 1 is not shown, as the pattern is too dense, and the distribution is the same as in fig. 5). l (L) 1 Represents the side length, l, of each small N+ doped region 1 after being divided 2 Representing the side length, l, of each small PW doped region 7 after segmentation 3 Representing the side length of each small DNW doped region 6 after being divided.
The short-circuit current density of the side light sensing areas and the short-circuit current density of the bottom light sensing areas of DNW, PW and N+ are respectively calculated in sequence through a calculation formula of the photocurrent density of the light sensing areas of the photodiodes, namely, the bottom light sensing area coefficients of DNW, PW and N+ are respectively calculated through the calculation formula of the bottom light sensing area coefficients and the side light sensing area coefficients introduced by the invention: a, a 3 、a 2 、a 1 The coefficients of the lateral light-sensitive areas are respectively as follows: b 3 、b 2 、b 1 . The metal coverage areas of DNW, PW and N+ are respectively S 3 、S 2 、S 1 . The photo-generated current I of the solar cell on the triple-well type chip can be obtained by deduction of the optimal segmentation condition formula of the reference doped region SC Can be expressed by the following formula, in particular:
In the above, l 3 、l 2 、l 1 The side lengths of DNW, PW and N+ after being divided are respectively shown,the number of divided DNW, PW and N+ are shown as a 3 、a 2 、a 1 Bottom light-sensitive region coefficients, b, respectively representing DNW, PW, N + 3 、b 2 、b 1 Side light-sensitive region coefficients of DNW, PW and N+ are respectively represented, S 3 、S 2 、S 1 Metal coverage areas of DNW, PW, N+, respectively, +.>The areas of each small doped region after DNW, PW and N+ are divided are respectively shown;
wherein n is 3 、n 2 、n 1 Each of which can be calculated from the following formula:
in the above, d 1 Represents the distance, d, between the N+ doped region 1 and the N+ doped region 1 2 Represents the spacing, d, between the divided PW doped region 7 and the divided PW doped region 7 3 Represents the distance, c, between the segmented DNW doped region 6 and the segmented DNW doped region 6 1 Represents the distance from the N+ doped region 1 to the PW edge, c 2 Represents the distance of PW doped region 7 from the edge of DNW, c 3 Represents the distance l from the DNW doped region 6 to the edge of the P-sub 1 Represents the side length, l, of each small N+ doped region 1 after being divided 2 Representing the side length, l, of each small PW doped region 7 after segmentation 3 Represents the side length, n, of each small DNW doped region 6 after being divided 1 Representing the number of segments of N+ doped region divided on one side，n 2 Represents the number of segments, n, of the PW doped region divided on one side 3 Representing the number of segments the DNW-doped region is divided on one side.
Pair I SC Sequentially find l 3 、l 2 、l 1 Can sequentially determine l 1 、l 2 、l 3 Thereby enabling the photo-generated current I of the on-chip solar cell with the triple-well structure SC1 Has the maximum value. For an area of 0.1mm 2 On-chip solar cell with triple-well structure, which is obtained by calculation, is shown as l 3 The value is 37.72 mu m, l 2 The value is 30.72 mu m, l 1 The value is 14.18 mu m, namely the DNW in the P-sub is divided into 64 blocks, the PW in each DNW is divided into 1 block (i.e. no division is made), the N+ in each PW is divided into 4 blocks, and the photo-generated current I of the on-chip solar cell with the triple-well structure SC1 Has the maximum value.
Therefore, referring to fig. 6, as a result of the division of the triple-well type on-chip solar cell, DNWs in P-sub may be divided into several, PWs in each divided DNW may be divided into several again, and n+ in each PW may be divided into several as well.
The test results show that: the design and optimization method provided by the invention can be used for obtaining 0.1mm 2 The photoelectric conversion efficiency of the optimized solar cell on the split triple-well type chip can reach 10.16 percent. Compared with the common solar cell on the triple-well type chip which is not segmented, the photoelectric efficiency of the solar cell on the novel structure chip is improved by 39.94 percent. The short-circuit current is also increased by 26.51%. The optimized division triple-well type on-chip solar cell provided by the invention has stronger photoelectric conversion capability, and the optimization design method is effective
The content in the method embodiment is applicable to the system embodiment, the functions specifically realized by the system embodiment are the same as those of the method embodiment, and the achieved beneficial effects are the same as those of the method embodiment.
While the preferred embodiment of the present application has been described in detail, the application is not limited to the embodiment, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit of the application, and these equivalent modifications and substitutions are intended to be included in the scope of the present application as defined in the appended claims.
Claims (10)
1. The utility model provides a solar cell on divided triple well type piece which is characterized in that, including doped region, light sense PN junction and surface metal electrode, the edge and the bottom of doped region cover have light sense PN junction, surface metal electrode is for covering in the metal wire of doped region surface, wherein:
the doped region is used for providing dopants with different doping concentrations;
the photoinduced PN junction is used for separating photo-generated electron hole pairs to generate photo-generated current;
the surface metal electrode is used for collecting and conveying photo-generated carriers of the doped region to generate solar cell output current.
2. The segmented triple-well on-wafer solar cell of claim 1, wherein the doped regions comprise an n+ doped region, a P-sub doped region, a DNW doped region and a PW doped region, the P-sub doped region being a substrate of the segmented triple-well on-wafer solar cell, the DNW doped region being wrapped inside the P-sub doped region, the PW doped region being wrapped inside the DNW doped region, the n+ doped region being wrapped inside the PW doped region, the DNW doped region in the P-sub doped region being segmented into a plurality of segmented DNW doped regions, the PW doped region in each of the segmented DNW doped regions being segmented into a plurality of segmented PW doped regions, the n+ doped region in each of the segmented PW doped regions being segmented into a plurality of segmented n+ doped regions, wherein:
the N+ doped region is used for providing high-concentration N-type doping and forms a shallow PN junction with the PW doped region and the P-sub doped region respectively;
the DNW doped region is used for providing low-concentration n-type doping, and respectively forms a sub-deep PN junction with the PW doped region and a deep PN junction with the P-sub doped region;
the PW doped region is used for providing low-concentration P-type doping, and forms the shallow PN junction with the N+ doped region and the sub-deep PN junction with the DNW doped region respectively;
The P-sub doped region is used for forming a substrate of the solar cell on the divided triple-well type wafer through the low-concentration P-type doping.
3. The segmented triple-well on-chip solar cell of claim 2, wherein the photo-induced PN junctions comprise side-side photo-induced PN junctions and bottom-side photo-induced PN junctions, the side-side photo-induced PN junctions being longitudinal PN junctions formed at edges of the doped region, the bottom-side photo-induced PN junctions being longitudinal PN junctions formed at bottoms of the doped region, wherein:
the side light-sensitive PN junction is used for separating photo-generated electron hole pairs of the side light-sensitive PN junction to form photocurrent of the side light-sensitive PN junction;
the bottom light-sensitive PN junction is used for separating photo-generated electron hole pairs of the bottom light-sensitive PN junction to form photocurrent of the bottom light-sensitive PN junction.
4. The segmented triple-well on-wafer solar cell of claim 2, wherein the surface metal electrode comprises an n+ surface metal electrode, a DNW surface metal electrode, a PW surface metal electrode, and a P-sub surface metal electrode, the n+ surface metal electrode is disposed on the upper surface of the n+ doped region, the DNW surface metal electrode is disposed on the upper surface of the DNW doped region, the PW surface metal electrode is disposed on the upper surface of the PW doped region, and the P-sub surface metal electrode is disposed on the upper surface of the P-sub doped region, wherein:
The N+ surface metal electrode is used for collecting and conveying photo-generated carriers generated by the N+ doped region to form an N+ doped region photocurrent;
the DNW surface metal electrode is used for collecting and conveying photo-generated carriers generated by the DNW doped region to form DNW doped region photocurrent;
the PW surface metal electrode is used for collecting and conveying photogenerated carriers generated by the PW doped region to form PW doped region photocurrent;
the P-sub surface metal electrode is used for collecting and conveying photo-generated carriers generated by the P-sub doped region to form a P-sub doped region photocurrent.
5. The segmented triple-well on-chip solar cell of claim 4, further comprising a substrate formed of N-base silicon, wherein for the substrate of the segmented triple-well on-chip solar cell formed of the N-base silicon, the triple-well structure is N-sub, deep P-well DPW, N-well NW, and P-type highly doped region p+ and for the substrate of the segmented triple-well on-chip solar cell formed of the low concentration P-type doping, the triple-well structure is n+ doped region, P-sub doped region, DNW doped region, and PW doped region.
6. The method for optimizing the segmentation of the segmented triple-well on-chip solar cell is characterized by comprising the following steps of:
acquiring the photocurrent density of a photo-induced PN junction through a photocurrent density formula of a photo-induced region of a photo-diode, wherein the photocurrent density of the photo-induced PN junction comprises the photocurrent density of a side photo-induced PN junction and the photocurrent density of a bottom photo-induced PN junction;
introducing an auxiliary coefficient, and determining the area of the side light-sensitive PN junction and the area of the bottom light-sensitive PN junction;
determining a light sensation coefficient of the side light sensation PN junction according to the light current density of the side light sensation PN junction and the area of the side light sensation PN junction;
determining a light sensation coefficient of the bottom light sensation PN junction according to the light current density of the bottom light sensation PN junction and the area of the bottom light sensation PN junction;
determining the coverage area of the surface metal electrode, wherein the coverage area of the surface metal electrode is the sum of the coverage area of the N+ surface metal electrode, the coverage area of the DNW surface metal electrode and the coverage area of the PW surface metal electrode;
dividing a doped region to obtain a divided doped region, wherein the doped region comprises the N+ doped region, the DNW doped region and the PW doped region;
And constructing optimal segmentation conditions of the doped region according to the segmented doped region, the coverage area of the surface metal electrode, the light sensation coefficient of the side light sensation PN junction and the light sensation coefficient of the bottom light sensation PN junction.
7. The method of optimizing split of a split triple-well on-chip solar cell according to claim 6, wherein the step of introducing an auxiliary coefficient to determine the area of the side light-sensitive PN junction and the area of the bottom light-sensitive PN junction specifically comprises:
acquiring the width of an N+ doped region and the width of the P-sub doped region;
setting the size of the photoinduced PN junction to be larger than the size of the doped region by considering the peripheral response of the photoinduced carriers on the doped region;
constructing the auxiliary coefficient according to the ratio of the size of the light-sensitive PN junction to the size of the doped region;
and determining the area of the side light-sensitive PN junction and the area of the bottom light-sensitive PN junction according to the auxiliary coefficient.
8. The method of optimizing the division of a solar cell on a divided triple-well type wafer according to claim 7, wherein the step of constructing the optimal division condition of the doped region based on the divided doped region, the coverage area of the surface metal electrode, the light-sensing coefficient of the side-light-sensing PN junction, and the light-sensing coefficient of the bottom-light-sensing PN junction specifically comprises:
Based on the segmented doped region, acquiring the side length of the N+ doped region, the side length of the PW doped region and the side length of the DNW doped region which are respectively l 1 、l 2 And l 3 The number of divided N+ doped regionsThe number of the divided PW doped regions and the number of the divided DNW doped regions are respectively n 1 、n 2 And n 3 ；
According to the coverage area of the N+ surface metal electrode and the side length l of the N+ doped region after being divided 1 And the number N of divided N+ doped regions 1 Calculating the photo-generated current after the N+ doped region is divided;
according to the coverage area of the PW surface metal electrode and the side length l of the PW doped region after being divided 2 And the number n of divided PW doped regions 2 Calculating the photo-generated current of the PW doped region after being divided;
according to the coverage area of the DNW surface metal electrode and the side length l of the DNW doped region after being divided 3 And the number n of divided DNW doped regions 3 Calculating photo-generated current after the DNW doped region is segmented;
accumulating the photo-generated current after the N+ doped region is divided to obtain the photo-generated current of the N+ doped region;
accumulating the photo-generated current of the DNW doped region after being divided to obtain the photo-generated current of the DNW doped region;
Accumulating the divided photogenerated currents of the PW doped region to obtain the photogenerated currents of the PW doped region;
integrating the photo-generated current of the N+ doped region, the photo-generated current of the DNW doped region and the photo-generated current of the PW doped region to obtain the photo-generated current of the solar cell on the divided triple-well type sheet;
deriving the photo-generated current of the solar cell on the divided triple-well type wafer to obtain the value of the side length of the N+ doped region after division, the value of the side length of the DNW doped region after division and the value of the side length of the PW doped region after division;
and constructing the optimal segmentation condition of the doped region according to the segmented side length value of the N+ doped region, the segmented side length value of the DNW doped region and the segmented side length value of the PW doped region by combining the light sensation coefficient of the side light sensation PN junction, the light sensation coefficient of the bottom light sensation PN junction and the coverage area of the surface metal electrode.
9. The method for optimizing the division of a solar cell on a divided triple-well type wafer according to claim 8, wherein the expression of the optimal division condition of the doped region is:
in the above, l 0 A represents the light sensation coefficient of the bottom light sensation PN junction, b represents the light sensation coefficient of the side light sensation PN junction, d 0 Representing the spacing of two divided doped regions S 0 The coverage area of the surface metal electrode is shown.
10. The method for optimizing the division of the solar cell on the divided triple-well type wafer according to claim 9, wherein the solar cell on the triple-well type wafer is divided by an optimal division condition, the DNW doped region in the P-sub doped region is divided into a plurality of divided DNW doped regions, the PW doped region in each of the divided DNW doped regions is divided into a plurality of divided PW doped regions, and the n+ doped region in each of the divided PW doped regions is divided into a plurality of divided n+ doped regions.
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