CN117080190A - Chip, chip assembly and chip manufacturing method - Google Patents

Chip, chip assembly and chip manufacturing method Download PDF

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Publication number
CN117080190A
CN117080190A CN202210482157.7A CN202210482157A CN117080190A CN 117080190 A CN117080190 A CN 117080190A CN 202210482157 A CN202210482157 A CN 202210482157A CN 117080190 A CN117080190 A CN 117080190A
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CN
China
Prior art keywords
chip
circuit layer
connection
bottom plate
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210482157.7A
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Chinese (zh)
Inventor
陈中山
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Zhongshan Longsys Electronics Co ltd
Original Assignee
Zhongshan Longsys Electronics Co ltd
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Filing date
Publication date
Application filed by Zhongshan Longsys Electronics Co ltd filed Critical Zhongshan Longsys Electronics Co ltd
Priority to CN202210482157.7A priority Critical patent/CN117080190A/en
Publication of CN117080190A publication Critical patent/CN117080190A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices

Abstract

The application provides a chip, which comprises a bottom plate and a circuit layer, wherein the bottom plate is provided with a first surface and a second surface which are opposite, and the circuit layer is formed on the first surface and is provided with an I/O port; the chip further comprises an interface connection part, wherein the interface connection part comprises a first connection piece and a second connection piece, the first connection piece is formed inside the bottom plate before the circuit layer is formed on the bottom plate, one end of the first connection piece is electrically connected with the I/O port of the circuit layer, and the other end of the first connection piece penetrates through the bottom plate and is exposed from the second surface; the second connecting piece is formed on the circuit layer and is electrically connected with the I/O port of the circuit layer. The application also provides a chip assembly formed by the chip and a chip manufacturing method for manufacturing the chip.

Description

Chip, chip assembly and chip manufacturing method
Technical Field
The application relates to the technical field of chip manufacturing, in particular to a chip, a chip assembly and a chip manufacturing method.
Background
The basic structure of most integrated circuit chips is to form a circuit layer on the bottom plate of the integrated circuit, and the circuit layer is provided with an Input/Output interface (I/O port). When a plurality of chips are stacked to form a chip vertical stack package structure, the I/O ports on each chip are easily blocked by other chips and are difficult to directly connect with other components, so that it is necessary to form connections between the I/O ports and between them and external circuits using a specific connection scheme.
In the conventional vertical stack package structure of a chip, a manner for connecting an I/O port is mainly two manners, namely a Wire Bonding (WB) process and a through silicon via (through silicon) process, but the two manners have own drawbacks. The WB process uses leads to establish connection between I/O ports of a plurality of chips and connect them with external circuits, and this process requires adding a lot of external leads, and also requires arranging the plurality of chips offset from each other to a certain extent so as to expose the I/O ports for easy lead access, thus requiring more space occupation and reducing space utilization inside the electronic device. The silicon through hole process is to drill a through hole extending to the control circuit on the silicon substrate of the chip, then fill the through hole with conductive material and connect with the I/O port, so that the I/O port forms an electric connection path on the other surface of the silicon substrate through the conductive material in the through hole; this approach can eliminate excessive leads, but the specific process is complicated and costly.
Therefore, it is necessary to provide a chip and a method for manufacturing the same, which can realize the interconnection and external connection of the I/O ports of the chip in a space-saving, simpler operation and lower cost manner, thereby realizing a vertically stacked package structure of the chip with high space utilization and lower cost in the chip assembly.
Disclosure of Invention
In order to solve the above technical problem, an aspect of the present application provides a chip including a base plate having opposite first and second surfaces, and a circuit layer formed on the first surface and having an I/O port formed therein; the method is characterized in that: the chip further comprises an interface connection part, wherein the interface connection part comprises a first connection piece and a second connection piece, the first connection piece is formed inside the bottom plate before the circuit layer is formed on the bottom plate, one end of the first connection piece is electrically connected with the I/O port of the circuit layer, and the other end of the first connection piece penetrates through the bottom plate and is exposed from the second surface; the second connecting piece is formed on the circuit layer and is electrically connected with the I/O port of the circuit layer.
In some embodiments, the chip further includes a structure fixing portion formed on the second surface and electrically connected to the first connecting member, for fixing the chip and the external component to each other and providing external electrical connection to the first connecting member.
In some embodiments, the structural securing portion includes at least one of a pad, a wire, a conductive terminal, a conductive post, a via.
In some embodiments, the first and second connectors include at least one of pads, wires, conductive terminals, conductive posts, vias.
In some embodiments, the substrate comprises at least one of a silicon-based substrate, a gallium nitride substrate, a diamond substrate.
Another aspect of the present application provides a chip assembly including a circuit board and at least one chip including a base plate having opposing first and second surfaces and a circuit layer formed on the first surface and having an I/O port formed therein; the method is characterized in that: the chip further comprises an interface connection part, wherein the interface connection part comprises a first connection piece and a second connection piece, the first connection piece is formed inside the bottom plate before the circuit layer is formed on the bottom plate, one end of the first connection piece is electrically connected with the I/O port of the circuit layer, and the other end of the first connection piece penetrates through the bottom plate and is exposed from the second surface; the second connecting piece is formed on the circuit layer and is electrically connected with the I/O port of the circuit layer; the chip is fixed on the circuit board and is electrically connected with the circuit board.
In some embodiments, the chip further includes a structure fixing portion formed on the second surface and electrically connected to the first connecting member, for fixing the chip and the external component to each other and providing external electrical connection to the first connecting member.
In some embodiments, the number of chips is a plurality, and the plurality of chips form a stacked structure, wherein adjacent chips are fixed to each other and electrically connected by a structure fixing portion of one of the chips.
In some embodiments, the structure fixing portion of one of the plurality of chips is fixed to the circuit board and establishes electrical connection with the circuit board.
Another aspect of the present application provides a chip manufacturing method, comprising the steps of: forming a base plate having opposed first and second surfaces; forming a first connecting piece for electric connection inside the bottom plate; after the first connecting piece is formed, forming a circuit layer with an I/O port on the first surface, and enabling the I/O port of the circuit layer to be electrically connected with the first connecting piece; forming a second connecting piece which is electrically connected with the I/O port of the circuit layer on the circuit layer; and thinning the bottom plate to expose the other end of the first connecting piece from the second surface.
In some embodiments, the method further comprises the steps of: forming a structure fixing part on the second surface, and electrically connecting the structure fixing part with the first connecting piece; the chip and the external component are mutually fixed through the structure fixing part, and external electric connection is provided for the first connecting piece.
In some embodiments, the step of forming a first connection member for electrical connection inside the base plate includes: pre-positioning the conductive member at a predetermined position in the molded container; the base plate is formed in the molding container such that the pre-placed conductive member forms the first connection inside the base plate.
In some embodiments, the step of forming a first connection member for electrical connection inside the base plate includes: forming a recess portion not penetrating through the bottom plate at a predetermined position on the first surface; and filling conductive material into the concave part to form the first connecting piece.
In some embodiments, the thinning process includes at least one of grinding, cutting, and etching.
In contrast to the prior art, in the chip and the chip assembly formed by the chip according to the embodiments of the present application, the first connection member penetrating through the bottom board in each chip is formed in advance inside the bottom board before the circuit layer is formed on the bottom board, so that the I/O signal channels are provided for the circuit layer below the circuit layer, and the second connection member provides the I/O signal channels for the circuit layer above the circuit layer, so that each chip is provided with two I/O signal channels respectively located on the upper and lower surfaces of the bottom board, and the stacked package structure of the multi-layer chip can be realized in the chip assembly through the stacked connection of the I/O signal channels. In the corresponding method for manufacturing the chip package assembly, before the circuit layer is formed on the bottom plate in the initial stage of manufacturing the chip, the first connecting piece is formed in the bottom plate in advance by means of pre-placement, etching and carving and is exposed out of the upper surface, then the bottom plate is thinned by means of grinding or etching, one end of the first connecting piece embedded in the bottom plate is exposed out of the lower surface of the thinned bottom plate, so that an I/O signal channel is provided for the circuit layer below the circuit layer, and the second connecting piece is provided for the circuit layer above the circuit layer, so that each chip can be provided with two I/O signal channels respectively positioned on the upper surface and the lower surface of the bottom plate, and the stacked package structure of the multi-layer chip can be realized through stacked connection of the I/O signal channels. Compared with the prior art, the chip assembly and the corresponding manufacturing method thereof do not need to stagger a plurality of chips and use more external leads for connection like a WB process, and do not need to precisely drill holes on the manufactured silicon substrate like a through silicon via process, so that higher space utilization rate can be realized, the structure is simpler, and the cost is low.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a chip according to an embodiment of the present application.
Fig. 2 is a schematic structural diagram of a chip assembly according to an embodiment of the present application.
Fig. 3 is a schematic diagram of a method for manufacturing a chip, in which a bottom plate, a circuit layer, a first connector and a second connector of the chip are formed, according to an embodiment of the present application.
Fig. 4 is a schematic diagram of a chip manufacturing method according to an embodiment of the present application, in which a base plate is thinned.
Fig. 5 is a schematic diagram of a method for manufacturing a chip, in which a structure connection portion is formed on the chip, according to an embodiment of the present application.
Fig. 6 is a schematic diagram of a chip manufacturing method according to an embodiment of the present application, in which two chips are connected by a structural connection portion.
Detailed Description
The application is described in further detail below with reference to the drawings and examples. It is specifically noted that the following examples are only for illustrating the present application, but do not limit the scope of the present application. Likewise, the following examples are only some, but not all, of the examples of the present application, and all other examples, which a person of ordinary skill in the art would obtain without making any inventive effort, are within the scope of the present application.
As shown in fig. 1, one embodiment of the present application provides a chip 10, where the chip 10 includes a base plate 11, a circuit layer 12, and an interface connection 13.
The substrate 11 may be any of various semiconductor material substrates for integrated circuits, such as silicon substrate, gallium nitride substrate, diamond substrate, etc., and in this embodiment, a silicon substrate is preferably used. The base plate 11 has opposed first and second surfaces 111, 112.
The circuit layer 12 is formed on the first surface 111 of the base plate 11, and may include various existing circuit structures for integrated circuits, and is provided with an Input/Output interface (I/O interface) in a conventional manner, which is not specifically shown in the figure.
The interface connection portion 13 includes a first connection member 131 and a second connection member 132, where the first connection member 131 and the second connection member 132 are electrical connection devices, for example, may be pads, wires, conductive terminals, conductive columns, vias, and the like, and in this embodiment, the first connection member 131 is preferably a conductive column, and the second connection member 132 is preferably a pad. The first connection member 131 is formed inside the base plate 11 before the circuit layer 12 is formed on the base plate 11 by, for example, pre-placement, etching, engraving, etc., and has one end connected to the I/O port on the circuit layer 12 and the other end penetrating through the base plate 11 and exposed from the second surface 112 of the base plate 11, thereby providing an external electrical connection path for the I/O port of the circuit layer 12 through the base plate 11. The second connection member 132 is formed on the outer surface (shown as the upper surface in the drawing) of the circuit layer 12 and is electrically connected to the I/O port of the circuit layer 12, and may be completely integrated with the I/O port, so as to provide an external electrical connection path directly facing the outside for the I/O port of the circuit layer 12.
In other embodiments, for example, as shown in fig. 2 and 4, the chip 10 may further include a structure fixing portion 14. The structure fixing portion 14 may be, for example, a pad, a wire, a conductive terminal, a conductive post, a via hole, or the like, and the structure fixing portion 14 in this embodiment is preferably a pad formed by a solder ball-plating process, and is formed on the second surface 112 of the base plate 11, and contacts an end portion of the first connecting member 131 exposed from the second surface 112 to establish an electrical connection, and preferably also completely covers the end portion to protect it. The structure fixing portion 14 may be used to form a fixed connection between the chip 10 and other components, for example, by soldering, and may also be used to form an electrical connection between the first connector 11 and other components by its own conductivity.
In the chip 10 according to the above embodiment, the first connection member 131 penetrating the substrate 11 is formed in advance inside the substrate 11 before the circuit layer 12 is formed on the substrate 11, so that the circuit layer 12 can be provided with the I/O signal path below the circuit layer 12, and the second connection member 132 can be provided with the I/O signal path above the circuit layer 12 for the circuit layer 12. In contrast to the prior art, the chip 10 is provided with two I/O signal channels on the upper and lower surfaces of the base plate 11, respectively, and a stacked package structure of the multi-layered chip 10 can be realized by stacked connection of these I/O signal channels. Therefore, the plurality of chips are not required to be staggered and connected by using external leads like a WB (wire bonding) process, and precise drilling is not required to be carried out on the manufactured silicon substrate like a through silicon (through silicon) process, so that higher space utilization rate can be realized, the structure is simpler, and the cost is low.
As shown in fig. 2, another embodiment of the present application provides a chip package assembly 100, and as shown in fig. 1, the chip package assembly 100 has a chip vertical stack package structure including the chip 10 and the circuit board 20 as described above. The number of the chips 10 may be one or more, and preferably four in the present embodiment, although other embodiments are not limited thereto.
In the chip package assembly 100, a plurality of chips 10 are arranged in parallel and aligned with each other, forming a stacked structure to improve space utilization. The chips 10 can be fixed and electrically connected to each other in various ways, and in this embodiment, the chips are fixed and electrically connected to each other by the fixing portions 14. The specific manner in which any two adjacent chips 10 are fixed to each other by the structure fixing portion 14 and electrically connected is to fixedly connect the structure fixing portion 14 of the preceding chip 10 (the upper one of each two adjacent chips 10 shown in fig. 2) to the second connecting member 132 of the succeeding chip 10 (the lower one of each two adjacent chips 10 shown in fig. 2) by welding and electrically connect the two chips 10 to each other, so that the two chips 10 are structurally and fixedly connected to each other, and simultaneously, the first connecting member 131 of the preceding chip 10 is electrically connected to the second connecting member 132 of the succeeding chip 10 by the structure fixing portion 14, so that the I/O ports of the circuit layers 12 of the two chips 10 can be electrically connected to each other, and the parallel connection of the circuit layers 12 of the two chips 10 can be realized. According to such a connection manner, the plurality of chips 10 may be sequentially stacked and connected to form a chip vertical stack package structure. Wherein the I/O ports of the circuit layers 12 of all chips 10 can be electrically connected together by the above-described connection means. In this way, when an external circuit is electrically connected to the I/O ports of the circuit layer 12 of any one of the chips 10, the external circuit is also electrically connected to all the I/O ports of the chips 10 at the same time, so that the circuit layers 12 of the chips 10 are all connected to the external circuit in parallel.
The circuit board 20 may be a conventional circuit board for a chip package assembly, for example, a printed circuit board (Printed Circuit Board, PCB) based on ceramic, resin, etc., preferably a rigid PCB. In this embodiment, the last chip 10 (the lowermost chip 10 shown in fig. 2) among the plurality of chips 10 connected together in the above manner may be fixed to the circuit board 20 and electrically connected to the circuit board 20 in various manners, and in this embodiment, the structure fixing portion 14 of the chip 10 is fixedly connected to the circuit board 20 and electrically connected to the circuit board 20 in a soldering manner, so that the first connecting member 131 of the chip 10 is electrically connected to the circuit board 20 through the structure fixing portion 14. As described above, since the I/O ports of the circuit layers 12 of the plurality of chips 10 are all electrically connected together, the circuit board 20 is simultaneously electrically connected to all the I/O ports of the plurality of chips 10, so that the circuit layers 12 of the plurality of chips 10 are all connected to the circuit board 20 in parallel, and can be connected to other functional devices through the circuit board 20, respectively. It should be further understood that in the embodiment including only one chip 10, only the structure fixing portion 14 of the chip 10 needs to be directly fixed to the circuit board 20 by soldering and establish electrical connection; for such an embodiment, the second connection member 132 on the chip 10 may be omitted, and the necessary external electrical connection may be implemented for the circuit layer 12 only by the first connection member 131.
In the chip package assembly 100 according to the above embodiment, the plurality of chips 10 may be mechanically and electrically connected by the above connection method, and the first connection member 131 penetrating the bottom board 11 is formed inside the bottom board 11 before the circuit layer 12 is formed on the bottom board 11, so as to provide the I/O signal path for the circuit layer 12 below the circuit layer 12, and the second connection member 132 provides the I/O signal path for the circuit layer 12 above the circuit layer 12. In contrast to the prior art, each chip 10 of the chip package assembly 100 is provided with two I/O signal channels respectively located on the upper and lower surfaces of the bottom plate 11, and a stacked package structure of the multi-layer chip 10 can be realized by stacked connection of the I/O signal channels. Therefore, the plurality of chips are not required to be staggered and connected by using external leads like a WB (wire bonding) process, and precise drilling is not required to be carried out on the manufactured silicon substrate like a through silicon (through silicon) process, so that higher space utilization rate can be realized, the structure is simpler, and the cost is low.
Another embodiment of the present application provides a chip manufacturing method that can be used to manufacture the chip 10 provided in the previous embodiment. As shown in fig. 3 and 4, the method for manufacturing the chip package assembly may include the following specific steps.
S1, manufacturing a bottom plate of a chip, such as the bottom plate 11 of the chip 10, wherein the bottom plate is provided with a first surface and a second surface which are opposite.
The sub-step S11 may be implemented by using an existing substrate manufacturing technique, for example, a semiconductor material such as a silicon-based material, a gallium nitride material, a diamond material, etc. may be used as the material of the substrate 11, and the substrate 11 may be manufactured by using a crystal growth process.
S2, forming a first connecting piece for electric connection, such as the first connecting piece 131 of the chip 10, in the bottom plate, and exposing one end of the first connecting piece from the first surface of the bottom plate.
This step S2 may be implemented in various ways, for example: the conductive members such as pins, wires, conductive columns, vias, etc. made of conductive materials such as metal materials may be previously placed at predetermined positions in a molding container, such as a mold, for forming the base plate 11, and then the above-mentioned step S1, such as the aforementioned crystal growth process, is performed in the molding container, so that the base plate 11 is formed around the previously placed conductive members, which are formed as the first connection members embedded inside the base plate 11 after the base plate 11 is manufactured. By adjusting the placement position of the conductive member, it is ensured that one end of the first connecting member 131 is exposed from the first surface 111 of the base plate 11. It is also possible to form a recess (not shown) for accommodating the first connector 131 at a predetermined position on the first surface 111 by a processing means such as etching or carving after the above step S1 is completed, the recess not necessarily penetrating the bottom plate 11; then, the conductive material is filled into the recess by a process such as fitting, bonding, plating, etc., to form the first connection member 131 embedded in the recess, so that the tip of the first connection member 131 is exposed from the opening of the recess, that is, from the first surface 111. No matter the mode of pre-placement or the mode of processing the concave part, the precise drilling holes penetrating through the two side surfaces of the bottom plate are required to be formed on the bottom plate 11, and the processing technology is simpler.
S3, after the first connecting piece is formed, a circuit layer of a chip, such as the circuit layer 12 of the chip 10, is formed on the first surface of the bottom plate, and the I/O port of the circuit layer is electrically connected with the first connecting piece.
Specifically, in this step S3, the circuit layer 12 may be formed on the first surface 111 of the base plate 11 by various existing methods, such as printing, plating, lamination, 3D printing, and the like. The circuit layer 12 may be used as a control circuit of the chip 10, and the I/O port of the circuit layer 12 is positioned to correspond to the first connection member 131 exposed on the surface of the base plate 11, preferably to contact the first connection member 131, and to establish electrical connection with the first connection member 131.
S4, forming a second connecting piece for electric connection, such as the second connecting piece 132, on the outer side surface of the circuit layer, and enabling the second connecting piece to establish electric connection with the I/O port of the circuit layer.
Specifically, in this substep S14, after the circuit layer 12 is formed, the second connection member 132 may be formed on the outer side surface of the circuit layer 12 (the upper surface of the circuit layer 12 is shown in the drawing of the present application), and the second connection member 132 may be electrically connected to the I/O port of the circuit layer 12. Preferably, the second connectors 132 are each corresponding in number, shape and size to the first connectors 131 and are also aligned with the first connectors 131.
S5, thinning the chip to enable the other end of the first connecting piece to be exposed out of the second surface of the bottom plate.
Specifically, in this step S5, the second surface 112 of the base plate 11 may be processed by, for example, conventional grinding, cutting or etching, and a portion of the base plate material is gradually removed from the second surface 112, so as to uniformly thin the thickness of the base plate 11 until an end (a lower end is shown in the drawing) of the first connection member 131 opposite to the circuit layer 12 is exposed from the second surface 112, as shown in fig. 4.
Through the above steps S1 to S5, the chip 10 as described above can be manufactured.
In other embodiments, as shown in fig. 5, the method may further comprise the steps of:
s6, forming a structure fixing part for connecting the chip and the external component, such as the structure fixing part 14 of the chip 10, on the second surface, and electrically connecting the structure fixing part and the first connecting piece.
Specifically in this step S6, the structure fixing portion 14 may be formed at a position where the first connection member 131 is exposed on the second surface 112 of the base plate 11, as shown in fig. 5. The structure fixing portion 14 may be formed by, for example, ball mounting according to a conventional solder ball mounting process. The structure fixing portion 14 is formed to contact with an end portion of the first connection member 131 exposed from the second surface 112 to establish electrical connection, for example, the structure fixing portion 14 may be formed to directly contact an end portion of the first connection member 131 exposed from the second surface 112 to establish electrical connection, and the structure fixing portion 14 is preferably also formed to entirely cover the end portion of the first connection member 131 to protect it.
The method may further include the step of fixing the chip 10 and the external component to each other by the structure fixing portion 14, and providing the first connection member 131 with external electrical connection. For example, as shown in fig. 6 and 2, the method may further include the following steps:
s7, fixedly connecting the chips together and establishing electrical connection.
This step S7 may specifically be performed by arranging a plurality of chips 10 in parallel and aligned with each other in the aforementioned assembly manner of the chip assembly 100, forming a laminated structure to improve space utilization, and preferably fixedly coupled together by the structure fixing portion 14 thereof. As shown in fig. 6, the specific connection manner of any two adjacent chips 10 through the structure fixing portion 14 is to fixedly connect the structure fixing portion 14 of the previous chip 10 (the upper one of the two adjacent chips 10 shown in fig. 6) with the second connecting member 132 of the next chip 10 (the lower one of the two adjacent chips 10 shown in fig. 6) through welding and establish electrical connection, so as to fixedly connect the two chips 10 to each other structurally, and simultaneously establish electrical connection between the first connecting member 131 of the previous chip 10 and the second connecting member 132 of the next chip 10 through the structure fixing portion 14, so that the I/O ports of the circuit layers 12 of the two chips 10 can be electrically connected to each other, and further, the parallel connection of the circuit layers 12 of the two chips 10 can be realized. According to such a connection manner, the plurality of chips 10 are sequentially stacked and connected to form a chip vertical stack package structure. Wherein the I/O ports of the circuit layers 12 of all chips 10 can be electrically connected together by the above-described connection means.
S8, the chip 10 and a circuit board, such as the circuit board 20, are assembled together and electrical connection is established.
Referring back to fig. 2, in step S8, the last chip 10 (the lowest chip 10 shown in fig. 2) among the plurality of chips 10 fixedly connected together is fixedly connected to the circuit board 20 and electrically connected to the circuit board 20, and in this embodiment, the structure fixing portion 14 of the chip 10 is preferably fixedly connected to the circuit board 20 and electrically connected to the circuit board 20 by soldering, so that the first connecting member 131 of the chip 10 is electrically connected to the circuit board 20 through the structure fixing portion 14. As described above, since the I/O ports of the circuit layers 12 of the plurality of chips 10 are electrically connected together, the circuit board 20 is electrically connected to all the I/O ports of the plurality of chips 10 at the same time, so that the circuit layers 12 of the plurality of chips 10 are connected to the circuit board 20 in parallel, and can be connected to other functional devices through the circuit board 20, respectively, thereby realizing the fabrication of the chip package assembly 100 using the chips 10.
In the method for manufacturing the chip package assembly according to the above embodiment, before the circuit layer 12 is formed on the base plate 11 in the initial stage of manufacturing the chip 10, the first connection member 131 is formed in advance inside the base plate 11 by being placed in advance or etched and engraved so as to be exposed from the upper surface, and then the base plate 11 is thinned by grinding or etching so that one end of the first connection member 131 embedded inside the base plate 11 is exposed from the lower surface of the thinned base plate 11, thereby providing the circuit layer 12 with the I/O signal channels below the circuit layer 12, and the second connection member 132 provides the circuit layer 12 with the I/O signal channels above the circuit layer 12, so that each chip 10 can be provided with two I/O signal channels respectively located on the upper and lower surfaces of the base plate 11, and a stacked package structure of the multi-layer chip 10 can be realized by stacked connection of these I/O signal channels. Compared with the prior art, the manufacturing method does not need to stagger a plurality of chips and connect the chips by using external leads like a WB process, and does not need to precisely drill holes on the manufactured silicon substrate like a through silicon via process, so that higher space utilization rate can be realized, the structure is simpler, and the cost is low.
The foregoing description is only a partial embodiment of the present application, and is not intended to limit the scope of the present application, and all equivalent devices or equivalent processes using the descriptions and the drawings of the present application or directly or indirectly applied to other related technical fields are included in the scope of the present application.

Claims (14)

1. A chip comprising a substrate having opposing first and second surfaces and a circuit layer formed on the first surface and having an I/O port formed therein; the method is characterized in that: the chip further comprises an interface connection part, wherein the interface connection part comprises a first connection piece and a second connection piece, the first connection piece is formed inside the bottom plate before the circuit layer is formed on the bottom plate, one end of the first connection piece is electrically connected with the I/O port of the circuit layer, and the other end of the first connection piece penetrates through the bottom plate and is exposed from the second surface; the second connecting piece is formed on the circuit layer and is electrically connected with the I/O port of the circuit layer.
2. The chip of claim 1, further comprising a structural securing portion formed on the second surface and electrically connected to the first connector for securing the chip to an external component and providing an external electrical connection to the first connector.
3. The chip of claim 2, wherein the structural securing portion comprises at least one of a pad, a wire, a conductive terminal, a conductive post, a via.
4. The chip of claim 1, wherein the first and second connectors comprise at least one of pads, wires, conductive terminals, conductive pillars, vias.
5. The chip of claim 1, wherein the substrate comprises at least one of a silicon-based substrate, a gallium nitride substrate, and a diamond substrate.
6. A chip assembly, characterized in that: the chip assembly comprises a circuit board and at least one chip, wherein the chip comprises a bottom plate and a circuit layer, the bottom plate is provided with a first surface and a second surface which are opposite, and the circuit layer is formed on the first surface and is provided with an I/O port; the method is characterized in that: the chip further comprises an interface connection part, wherein the interface connection part comprises a first connection piece and a second connection piece, the first connection piece is formed inside the bottom plate before the circuit layer is formed on the bottom plate, one end of the first connection piece is electrically connected with the I/O port of the circuit layer, and the other end of the first connection piece penetrates through the bottom plate and is exposed from the second surface; the second connecting piece is formed on the circuit layer and is electrically connected with the I/O port of the circuit layer; the chip is fixed on the circuit board and is electrically connected with the circuit board.
7. The chip assembly of claim 6, wherein: the chip further comprises a structure fixing part, wherein the structure fixing part is formed on the second surface and is electrically connected with the first connecting piece, and the structure fixing part is used for fixing the chip and an external component to each other and providing external electrical connection for the first connecting piece.
8. The chip package assembly of claim 7, wherein the number of chips is plural, the plural chips forming a stacked structure in which adjacent chips are fixed to each other and electrically connected by a structure fixing portion of one of the chips.
9. The chip package assembly of claim 8, wherein the structural securing portion of one of the plurality of chips is secured to the circuit board and establishes electrical connection therewith.
10. A method of manufacturing a chip, the method comprising the steps of:
forming a base plate having opposed first and second surfaces;
forming a first connecting piece for electric connection inside the bottom plate;
after the first connecting piece is formed, forming a circuit layer with an I/O port on the first surface, and enabling the I/O port of the circuit layer to be electrically connected with the first connecting piece;
forming a second connecting piece which is electrically connected with the I/O port of the circuit layer on the circuit layer;
and thinning the bottom plate to expose the other end of the first connecting piece from the second surface.
11. The method of claim 10, further comprising the step of:
forming a structure fixing part on the second surface, and electrically connecting the structure fixing part with the first connecting piece;
the chip and the external component are mutually fixed through the structure fixing part, and external electric connection is provided for the first connecting piece.
12. The method of claim 10, wherein the step of forming a first connection member for electrical connection inside the base plate comprises:
pre-positioning the conductive member at a predetermined position in the molded container;
the base plate is formed in the molding container such that the pre-placed conductive member forms the first connection inside the base plate.
13. The method of claim 10, wherein the step of forming a first connection member for electrical connection inside the base plate comprises:
forming a recess portion not penetrating through the bottom plate at a predetermined position on the first surface;
and filling conductive material into the concave part to form the first connecting piece.
14. The method of claim 10, wherein the thinning process comprises at least one of grinding, cutting, and etching.
CN202210482157.7A 2022-05-05 2022-05-05 Chip, chip assembly and chip manufacturing method Pending CN117080190A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210482157.7A CN117080190A (en) 2022-05-05 2022-05-05 Chip, chip assembly and chip manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210482157.7A CN117080190A (en) 2022-05-05 2022-05-05 Chip, chip assembly and chip manufacturing method

Publications (1)

Publication Number Publication Date
CN117080190A true CN117080190A (en) 2023-11-17

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210482157.7A Pending CN117080190A (en) 2022-05-05 2022-05-05 Chip, chip assembly and chip manufacturing method

Country Status (1)

Country Link
CN (1) CN117080190A (en)

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