CN117080042A - Semiconductor etching equipment - Google Patents
Semiconductor etching equipment Download PDFInfo
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- CN117080042A CN117080042A CN202311325926.3A CN202311325926A CN117080042A CN 117080042 A CN117080042 A CN 117080042A CN 202311325926 A CN202311325926 A CN 202311325926A CN 117080042 A CN117080042 A CN 117080042A
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- radio frequency
- shielding ring
- electrostatic chuck
- frequency shielding
- ring
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- 238000005530 etching Methods 0.000 title claims abstract description 84
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 238000000034 method Methods 0.000 claims abstract description 41
- 238000002955 isolation Methods 0.000 claims abstract description 10
- 238000001816 cooling Methods 0.000 claims description 28
- 239000007789 gas Substances 0.000 claims description 13
- 239000010453 quartz Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 239000000919 ceramic Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 239000000112 cooling gas Substances 0.000 claims description 9
- DMFGNRRURHSENX-UHFFFAOYSA-N beryllium copper Chemical compound [Be].[Cu] DMFGNRRURHSENX-UHFFFAOYSA-N 0.000 claims description 8
- 238000007789 sealing Methods 0.000 claims description 7
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 239000013049 sediment Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000004308 accommodation Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000001311 chemical methods and process Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32623—Mechanical discharge control means
- H01J37/32651—Shields, e.g. dark space shields, Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32458—Vessel
- H01J37/32477—Vessel characterised by the means for protecting vessels or internal parts, e.g. coatings
- H01J37/32504—Means for preventing sputtering of the vessel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention relates to the technical field of semiconductor etching processing and discloses semiconductor etching equipment. The semiconductor etching equipment comprises a shell component, an upper electrode, an electrostatic chuck and a first radio frequency shielding ring. The shell assembly comprises an upper cover and a bottom shell which are connected with each other, and is provided with a process cavity; the upper electrode is arranged in the process cavity and is connected with the upper cover; the electrostatic chuck is arranged in the process cavity, is positioned below the upper electrode, and is provided with a supporting part for adsorbing a wafer; the upper cover is provided with an air inlet hole, etching gas can be conveyed between the upper electrode and the electrostatic chuck through the air inlet hole, the electrostatic chuck is electrically connected with a radio frequency power supply, so that the electrostatic chuck can generate radio frequency, the radio frequency ionizes the etching gas and generates plasma, and the plasma is used for etching a wafer; the first radio frequency shielding ring is arranged on the electrostatic chuck in a surrounding mode and covers the circumferential side wall of the electrostatic chuck, and radio frequency isolation can be carried out on the first radio frequency shielding ring.
Description
Technical Field
The invention relates to the technical field of semiconductor etching processing, in particular to semiconductor etching equipment.
Background
CCP (Capacitively Coupled Plasma ) etching apparatus is a new type of special device, which is formed by capacitive and circuit coupling, and can form a highly efficient ion body use technology. In principle, it fully utilizes circuit characteristics and ion chemical processes to act on gas to form a capacitively coupled plasma field, thereby realizing the effect of ions. The CCP process has good uniformity, simple structure and easy adjustment of ionization energy, so the CCP process is widely applied to oxide etching and is used for processing semiconductors.
In the prior art, glow discharge carried out by the electrostatic chuck is more dispersed, on one hand, plasma is locked in the process chamber, and the process chamber is filled with reaction sediment generated by the plasma, so that the process chamber needs to be cleaned frequently, and the production efficiency is reduced; on the other hand, glow discharge is more dispersed, and the etching rate of the semiconductor is reduced.
Based on this, a semiconductor etching apparatus is demanded to solve the above-mentioned problems.
Disclosure of Invention
Based on the foregoing, an object of the present invention is to provide a semiconductor etching apparatus, where the first rf shielding ring performs energy focusing, enhances energy density, and increases etching rate; and can effectively reduce the deposition of particles on the inner wall of the process chamber and reduce the cleaning times of the open chamber.
In order to achieve the above purpose, the invention adopts the following technical scheme:
a semiconductor etching apparatus, comprising:
a housing assembly comprising an upper cover and a bottom case connected to each other, the housing assembly being provided with a process chamber;
the upper electrode is arranged in the process cavity and is connected with the upper cover;
the electrostatic chuck is arranged in the process cavity, is positioned below the upper electrode and is provided with a supporting part, and the supporting part is used for adsorbing a wafer;
the upper cover is provided with an air inlet hole, etching gas can be conveyed between the upper electrode and the electrostatic chuck through the air inlet hole, the electrostatic chuck is electrically connected with a radio frequency power supply, so that the electrostatic chuck can generate radio frequency, the radio frequency ionizes the etching gas and generates plasma, and the plasma is used for etching the wafer;
the first radio frequency shielding ring is arranged on the electrostatic chuck in a surrounding mode and covers the circumferential side wall of the electrostatic chuck, and the first radio frequency shielding ring can conduct radio frequency isolation.
As a preferred technical scheme of the semiconductor etching equipment, the semiconductor etching equipment further comprises a second radio frequency shielding ring, wherein the second radio frequency shielding ring is connected to the bottom wall of the process cavity, the bottom end of the first radio frequency shielding ring stretches into the second radio frequency shielding ring, and a beryllium copper shielding ring is arranged between the inner wall of the second radio frequency shielding ring and the outer wall of the first radio frequency shielding ring.
As a preferable technical scheme of the semiconductor etching equipment, the semiconductor etching equipment further comprises an adjusting screw, wherein a plurality of threaded holes are formed in the top wall ring of the second radio frequency shielding ring, and the adjusting screw is in threaded connection with the threaded holes;
the outer wall of the first radio frequency shielding ring is in a ladder shape, the outer wall of the first radio frequency shielding ring comprises a large-diameter section, a small-diameter section and a ladder surface, the small-diameter section is connected to the inner wall of the second radio frequency shielding ring in a sliding manner, and the ladder surface is positioned above the second radio frequency shielding ring;
the stepped surface is annularly provided with a plurality of limit grooves, and the head of the adjusting screw is abutted to the bottoms of the limit grooves.
As a preferable technical scheme of the semiconductor etching equipment, the bottom of the limiting groove is provided with a penetrating operation hole, and the adjusting screw is an inner angle screw.
As a preferred technical scheme of the semiconductor etching equipment, the semiconductor etching equipment further comprises an adjusting ring, wherein the adjusting ring is arranged on the upper electrode, the adjusting ring is arranged on the upper cover and is positioned above the first radio frequency shielding ring, and a gap between the adjusting ring and the first radio frequency shielding ring is smaller than 3mm.
As a preferable technical scheme of the semiconductor etching equipment, the top wall of the first radio frequency shielding ring is higher than the top wall of the electrostatic chuck by not less than 3mm.
As a preferable technical scheme of the semiconductor etching equipment, the first radio frequency shielding ring and/or the second radio frequency shielding ring are/is aluminum rings;
and carrying out hard anodic oxidation treatment on the first radio frequency shielding ring and/or the second radio frequency shielding ring.
As a preferable technical scheme of the semiconductor etching device, the semiconductor etching device further comprises a silicon ring, wherein the silicon ring is arranged on the supporting part.
As a preferred technical scheme of the semiconductor etching equipment, the semiconductor etching equipment further comprises a ceramic insulating layer and a quartz insulating layer, wherein the ceramic insulating layer is provided with a mounting groove, the bottom of the mounting groove is provided with a containing hole, the top of the electrostatic chuck is embedded in the mounting groove, and the supporting part extends into the containing hole;
the bottom end of the quartz insulating layer is connected with the bottom wall of the process cavity in a sealing mode, and the top end of the quartz insulating layer is connected with the top of the electrostatic chuck in a sealing mode.
As a preferable technical scheme of the semiconductor etching equipment, a cooling groove is formed in the periphery of the top wall of the supporting portion in a surrounding mode, a plurality of first cooling holes are formed in the bottom of the cooling groove at intervals, a plurality of second cooling holes are formed in the center of the supporting portion, and the first cooling holes and the second cooling holes are communicated with the cooling gas supply device.
The beneficial effects of the invention are as follows:
the invention provides a semiconductor etching device, when a wafer is processed, a supporting part adsorbs the wafer, etching gas is conveyed between an upper electrode and an electrostatic chuck through an air inlet, a radio frequency power supply applies voltage to the electrostatic chuck, so that the electrostatic chuck can generate radio frequency, the radio frequency ionizes the etching gas and generates plasma, the plasma is used for etching the wafer, and the wafer is etched. In the process of generating radio frequency by the electrostatic chuck, as the first radio frequency shielding ring is annularly arranged on the electrostatic chuck and covers the circumferential side wall of the electrostatic chuck, the first radio frequency shielding ring can isolate radio frequency in an etching processing area, on one hand, the first radio frequency shielding ring gathers energy, so that the radio frequency density of the etching processing area is increased, the plasma gathering area can be locked, the energy density is enhanced, and the etching rate is improved; on the other hand, the method can prevent radio frequency from entering the process cavity except the first radio frequency shielding ring, can effectively reduce the deposition of particles on the inner wall of the process cavity, reduce the cleaning times of the open cavity, improve the effective utilization rate of the semiconductor etching equipment, improve the working efficiency and reduce the labor cost.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following description will briefly explain the drawings needed in the description of the embodiments of the present invention, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the contents of the embodiments of the present invention and these drawings without inventive effort for those skilled in the art.
Fig. 1 is a schematic structural diagram of a semiconductor etching apparatus according to an embodiment of the present invention;
fig. 2 is a cross-sectional view of a semiconductor etching apparatus provided in an embodiment of the present invention;
fig. 3 is an enlarged view of fig. 2 at a;
FIG. 4 is a schematic view of a portion of a semiconductor etching apparatus according to an embodiment of the present invention;
fig. 5 is an exploded view of a part of the structure of a semiconductor etching apparatus according to an embodiment of the present invention.
The figures are labeled as follows:
1. a housing assembly; 11. an upper cover; 12. a bottom case; 13. a process chamber;
2. an upper electrode;
3. an electrostatic chuck; 31. a support part; 32. a cooling tank; 33. a second cooling hole;
4. a first radio frequency shielding ring; 41. a large diameter section; 42. a small diameter section; 43. a step surface; 44. an operation hole; 45. a limit groove;
5. a second radio frequency shielding ring; 6. beryllium copper shielding ring; 7. an adjusting screw; 8. an adjusting ring; 9. a silicon ring; 10. a ceramic insulating layer; 20. a quartz insulating layer; 30. a base; 40. and lifting the cylinder.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
In the description of the present invention, unless explicitly stated and limited otherwise, the terms "connected," "connected," and "fixed" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In the present invention, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.
In the description of the present embodiment, the terms "upper", "lower", "left", "right", and the like are orientation or positional relationships based on those shown in the drawings, merely for convenience of description and simplicity of operation, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the invention. Furthermore, the terms "first," "second," and the like, are used merely for distinguishing between descriptions and not for distinguishing between them.
As shown in fig. 1 to 3, the present embodiment provides a semiconductor etching apparatus including a housing assembly 1, an upper electrode 2, an electrostatic chuck 3, and a first radio frequency shielding ring 4.
Specifically, the housing assembly 1 comprises an upper cover 11 and a bottom shell 12 connected to each other, the housing assembly 1 being provided with a process chamber 13; the upper electrode 2 is arranged in the process chamber 13 and is connected with the upper cover 11; the electrostatic chuck 3 is arranged in the process chamber 13, the electrostatic chuck 3 is positioned below the upper electrode 2, the electrostatic chuck 3 is provided with a supporting part 31, and the supporting part 31 is used for adsorbing a wafer; the upper cover 11 is provided with an air inlet hole, etching gas can be conveyed between the upper electrode 2 and the electrostatic chuck 3 through the air inlet hole, the electrostatic chuck 3 is electrically connected with a radio frequency power supply, so that the electrostatic chuck 3 can generate radio frequency, the radio frequency ionizes the etching gas and generates plasma, and the plasma is used for etching a wafer; the first rf shielding ring 4 is disposed around the electrostatic chuck 3 and covers a circumferential sidewall of the electrostatic chuck 3, and the first rf shielding ring 4 can perform rf isolation. The etching gas may be argon.
During wafer processing, the supporting part 31 of the electrostatic chuck 3 adsorbs a wafer, etching gas is conveyed between the upper electrode 2 and the electrostatic chuck 3 through the air inlet holes, and a radio frequency power supply applies voltage to the electrostatic chuck 3, so that the electrostatic chuck 3 can generate radio frequency, the radio frequency ionizes the etching gas and generates plasma, the plasma is used for etching the wafer, and the wafer is etched. In the process of generating radio frequency by the electrostatic chuck 3, as the first radio frequency shielding ring 4 is annularly arranged on the electrostatic chuck 3 and covers the circumferential side wall of the electrostatic chuck 3, the first radio frequency shielding ring 4 can isolate radio frequency in an etching processing area, on one hand, the first radio frequency shielding ring 4 gathers energy, so that the radio frequency density of the etching processing area is increased, the plasma gathering area can be locked, the energy density is enhanced, and the etching rate is improved; on the other hand, the method can prevent radio frequency from entering the process cavity 13 except the first radio frequency shielding ring 4, can effectively reduce the deposition of particles on the inner wall of the process cavity 13, reduce the cleaning times of the open cavity, improve the effective utilization rate of the semiconductor etching equipment, improve the working efficiency and reduce the labor cost.
Preferably, as shown in fig. 2 and 3, the semiconductor etching apparatus further includes a second rf shielding ring 5, the second rf shielding ring 5 is connected to the bottom wall of the process chamber 13, the bottom end of the first rf shielding ring 4 extends into the second rf shielding ring 5, and a beryllium copper shielding ring 6 is disposed between the inner wall of the second rf shielding ring 5 and the outer wall of the first rf shielding ring 4. The beryllium copper shielding ring 6 has the function of radio frequency isolation, and the beryllium copper shielding ring 6 is soft, so that the gap between the beryllium copper shielding ring 6 and the first radio frequency shielding ring 4 is effectively reduced, the gap between the beryllium copper shielding ring 6 and the second radio frequency shielding ring 5 is reduced, shielding treatment between the bottom of the first radio frequency shielding ring 4 and the process cavity 13 is realized, radio frequency is prevented from penetrating to the outer side of the first radio frequency shielding ring 4 through the bottom of the first radio frequency shielding ring 4, and the effect of radio frequency isolation is improved.
Preferably, the first radio frequency shielding ring 4 and/or the second radio frequency shielding ring 5 are subjected to hard anodic oxidation treatment, so that the corrosion resistance of the first radio frequency shielding ring 4 and the second radio frequency shielding ring 5 is improved, and the service life is prolonged. In this embodiment, the first rf shielding ring 4 and/or the second rf shielding ring 5 are aluminum rings, so that the rf isolation effect is significant and the production cost is low.
Preferably, as shown in fig. 4 and 5, the semiconductor etching apparatus further includes an adjusting screw 7, the top wall of the second rf shielding ring 5 is provided with a plurality of threaded holes in a ring, and the adjusting screw 7 is connected to the threaded holes in a threaded manner; the outer wall of the first radio frequency shielding ring 4 is in a ladder shape, the outer wall of the first radio frequency shielding ring 4 comprises a large-diameter section 41, a small-diameter section 42 and a ladder surface 43, the small-diameter section 42 is connected to the inner wall of the second radio frequency shielding ring 5 in a sliding manner, and the ladder surface 43 is positioned above the second radio frequency shielding ring 5; the step surface 43 is provided with a plurality of limit grooves 45 in a surrounding manner, and the head of the adjusting screw 7 is abutted against the bottom of the limit grooves 45. The screwing depth of the adjusting screw 7 is adjusted, so that the first radio frequency shielding ring 4 is adjusted in height, different process requirements are met by the height of the first radio frequency shielding ring 4 relative to the electrostatic chuck 3, universality is improved, the head of the adjusting screw 7 can be prevented from being separated from the stepped surface 43 by the groove wall of the limiting groove 45, and equipment reliability is improved.
In this embodiment, the top wall of the first rf shielding ring 4 is higher than the top wall of the electrostatic chuck 3 by not less than 3mm, so as to improve the rf isolation effect of the first rf shielding ring 4 on the electrostatic chuck 3 and meet the production requirement.
Further preferably, the groove bottom of the limit groove 45 is provided with a through operation hole 44, and the adjusting screw 7 is an inside angle screw. The first radio frequency shielding ring 4 is in press connection with the plurality of adjusting screws 7, if the height of the first radio frequency shielding ring 4 needs to be adjusted, an operator can wear the operating hole 44 above the first radio frequency shielding ring 4 by using a tool, so that the internal angle screw screwing is realized, the operation is convenient, and the adjusting efficiency is improved.
In this embodiment, as shown in fig. 2 and 3, the semiconductor etching apparatus further includes an adjusting ring 8, the adjusting ring 8 is disposed on the upper electrode 2, the adjusting ring 8 is mounted on the upper cover 11, the adjusting ring 8 is located above the first radio frequency shielding ring 4, and a gap between the adjusting ring 8 and the first radio frequency shielding ring 4 is smaller than 3mm. The gap between the adjusting ring 8 and the first radio frequency shielding ring 4 is used for circulating etching gas, the gap between the adjusting ring 8 and the first radio frequency shielding ring 4 is controlled to be smaller than 3mm, plasma can be reduced as much as possible and enters the process cavity 13 through the gap, the plasma is concentrated in an etching area, and the etching rate is improved. Preferably, the adjusting ring 8 is made of a radio frequency isolation material, and the adjusting ring 8 can perform radio frequency isolation to further prevent radio frequency from entering the process chamber 13, so as to reduce sediment generated on the inner wall of the process chamber 13.
Further, the semiconductor etching device further comprises a ceramic insulating layer 10 and a quartz insulating layer 20, wherein the ceramic insulating layer 10 is provided with a mounting groove, the bottom of the mounting groove is provided with a containing hole, the top of the electrostatic chuck 3 is embedded in the mounting groove, and the supporting part 31 extends into the containing hole; the bottom end of the quartz insulating layer 20 is hermetically connected to the bottom wall of the process chamber 13, and the top end of the quartz insulating layer 20 is hermetically connected to the top of the electrostatic chuck 3. Wherein, can adopt the sealing washer to realize the sealed connection, the ceramic insulating layer 10 can insulate top and lateral part of the electrostatic chuck 3, the ceramic insulating layer 10 has corrosion-resistant characteristic, raise the life time of the ceramic insulating layer 10; the quartz insulating layer 20 can insulate the bottom of the electrostatic chuck 3.
In order to solve the above problem, in this embodiment, the semiconductor etching apparatus further includes a silicon ring 9, and the silicon ring 9 is disposed around the supporting portion 31. During the etching process of the wafer, the silicon ring 9 can be etched at the same time, the silicon ring 9 absorbs the energy of the edge of the wafer in the etching process and binds the plasma, so that the edge etching rate of the wafer is reduced, the uniformity of the wafer processing is ensured, and the product quality is improved. In the present embodiment, the support portion 31 and the silicon ring 9 are both disposed in the accommodation hole of the ceramic insulating layer 10.
Further, a cooling groove 32 is formed around the outer periphery of the top wall of the supporting portion 31, a plurality of first cooling holes are formed at intervals at the bottom of the cooling groove 32, a plurality of second cooling holes 33 are formed in the center of the supporting portion 31, and the first cooling holes and the second cooling holes 33 are both communicated with the cooling gas supply device. In operation, the cooling gas generated by the cooling gas supply device enters the cooling groove 32 through the plurality of first cooling holes to cool the outer periphery of the wafer, and the cooling gas cools the middle of the wafer through the plurality of second cooling holes 33. In this embodiment, the cooling gas is helium.
In this embodiment, the semiconductor etching apparatus further includes a jacking cylinder 40 and a plurality of pins, the jacking cylinder 40 is in driving connection with the plurality of pins, the jacking cylinder 40 can drive the plurality of pins to penetrate through the second cooling holes 33, the wafer is placed above the plurality of pins, the jacking cylinder 40 drives the plurality of pins to retract, the wafer can be placed on the electrostatic chuck 3 in the retracting process, the pins continue to retract until the pins are separated from the second cooling holes 33, the second cooling holes 33 are used for circulation of cooling gas, and the second cooling holes 33 have multiple purposes. In this embodiment, the number of the second cooling holes 33 and the number of the ejector pins are four.
The electrostatic chuck 3 is further electrically connected with an electrostatic power supply, the electrostatic power supply is used for enabling the electrostatic chuck 3 to generate static electricity, and the electrostatic chuck 3 adsorbs a wafer through the static electricity, so that the stability of the wafer is improved.
Further, the semiconductor etching apparatus further comprises a base 30, the electrostatic chuck 3 is connected above the base 30 in a sealing manner, the quartz insulating layer 20 is connected below the base 30 in a sealing manner, and the base 30 is used for fixing structures such as a cooling gas supply device, a jacking cylinder 40, an electrode of an electrostatic power supply, an electrode of a radio frequency power supply and the like.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (10)
1. A semiconductor etching apparatus, comprising:
a housing assembly (1) comprising an upper cover (11) and a bottom shell (12) connected to each other, the housing assembly (1) being provided with a process chamber (13);
an upper electrode (2) disposed within the process chamber (13) and connected to the upper cover (11);
an electrostatic chuck (3) disposed in the process chamber (13), the electrostatic chuck (3) being located below the upper electrode (2), the electrostatic chuck (3) being provided with a support portion (31), the support portion (31) being for adsorbing a wafer;
the upper cover (11) is provided with an air inlet hole, etching gas can be conveyed between the upper electrode (2) and the electrostatic chuck (3) through the air inlet hole, the electrostatic chuck (3) is electrically connected to a radio frequency power supply, so that the electrostatic chuck (3) can generate radio frequency, the radio frequency ionizes the etching gas and generates plasma, and the plasma is used for etching the wafer;
the first radio frequency shielding ring (4) is arranged on the electrostatic chuck (3) in a surrounding mode and covers the circumferential side wall of the electrostatic chuck (3), and the first radio frequency shielding ring (4) can conduct radio frequency isolation.
2. The semiconductor etching apparatus according to claim 1, further comprising a second radio frequency shielding ring (5), wherein the second radio frequency shielding ring (5) is connected to a bottom wall of the process chamber (13), a bottom end of the first radio frequency shielding ring (4) extends into the second radio frequency shielding ring (5), and a beryllium copper shielding ring (6) is disposed between an inner wall of the second radio frequency shielding ring (5) and an outer wall of the first radio frequency shielding ring (4).
3. The semiconductor etching apparatus according to claim 2, further comprising an adjusting screw (7), a top wall ring of the second radio frequency shielding ring (5) being provided with a plurality of threaded holes, the adjusting screw (7) being threadedly connected to the threaded holes;
the outer wall of the first radio frequency shielding ring (4) is in a ladder shape, the outer wall of the first radio frequency shielding ring (4) comprises a large-diameter section (41), a small-diameter section (42) and a ladder surface (43), the small-diameter section (42) is connected to the inner wall of the second radio frequency shielding ring (5) in a sliding mode, and the ladder surface (43) is located above the second radio frequency shielding ring (5);
the stepped surface (43) is annularly provided with a plurality of limit grooves (45), and the head of the adjusting screw (7) is abutted to the groove bottoms of the limit grooves (45).
4. A semiconductor etching apparatus according to claim 3, wherein the groove bottom of the limit groove (45) is provided with a through operation hole (44), and the adjusting screw (7) is an inside angle screw.
5. The semiconductor etching apparatus according to claim 1, further comprising an adjusting ring (8), the adjusting ring (8) being provided to the upper electrode (2), the adjusting ring (8) being mounted to the upper cover (11), the adjusting ring (8) being located above the first radio frequency shielding ring (4), a gap between the adjusting ring (8) and the first radio frequency shielding ring (4) being smaller than 3mm.
6. Semiconductor etching apparatus according to claim 1, characterized in that the top wall of the first radio frequency shielding ring (4) is not less than 3mm higher than the top wall of the electrostatic chuck (3).
7. Semiconductor etching apparatus according to claim 2, characterized in that the first radio frequency shielding ring (4) and/or the second radio frequency shielding ring (5) are aluminium rings;
the first radio frequency shielding ring (4) and/or the second radio frequency shielding ring (5) are subjected to hard anodic oxidation treatment.
8. Semiconductor etching apparatus according to claim 1, further comprising a silicon ring (9), the silicon ring (9) being arranged around the support (31).
9. The semiconductor etching apparatus according to any one of claims 1 to 8, further comprising a ceramic insulating layer (10) and a quartz insulating layer (20), the ceramic insulating layer (10) being provided with a mounting groove, a bottom of the mounting groove being provided with a receiving hole, a top of the electrostatic chuck (3) being fitted into the mounting groove, and the supporting portion (31) extending into the receiving hole;
the bottom end of the quartz insulating layer (20) is connected with the bottom wall of the process chamber (13) in a sealing mode, and the top end of the quartz insulating layer (20) is connected with the top of the electrostatic chuck (3) in a sealing mode.
10. Semiconductor etching apparatus according to any one of claims 1 to 8, wherein a cooling groove (32) is provided around the outer periphery of the top wall of the support portion (31), a plurality of first cooling holes are provided at intervals at the bottom of the cooling groove (32), a plurality of second cooling holes (33) are provided at the center of the support portion (31), and both the first cooling holes and the second cooling holes (33) are communicated with a cooling gas supply device.
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| US6284093B1 (en) * | 1996-11-29 | 2001-09-04 | Applied Materials, Inc. | Shield or ring surrounding semiconductor workpiece in plasma chamber |
| US20040072426A1 (en) * | 2002-08-02 | 2004-04-15 | Soon-Jong Jung | Process chamber for manufacturing a smiconductor device |
| KR20040075550A (en) * | 2003-02-21 | 2004-08-30 | 삼성전자주식회사 | Dry etching equipment having improved shadow ring structure |
| KR100849394B1 (en) * | 2007-03-06 | 2008-07-31 | (주)아이씨디 | Plasma processing apparatus having isolator capable of adjusting height |
| CN101235482A (en) * | 2007-01-29 | 2008-08-06 | 应用材料股份有限公司 | Process kit for substrate processing chamber |
| CN112614769A (en) * | 2020-12-11 | 2021-04-06 | 无锡邑文电子科技有限公司 | Silicon carbide etching process cavity device and using method |
| KR20220092161A (en) * | 2020-12-24 | 2022-07-01 | 세메스 주식회사 | Apparatus for processing a substrate |
| US20230002894A1 (en) * | 2021-07-01 | 2023-01-05 | Applied Materials, Inc. | Shadow ring lift to improve wafer edge performance |
-
2023
- 2023-10-13 CN CN202311325926.3A patent/CN117080042B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6284093B1 (en) * | 1996-11-29 | 2001-09-04 | Applied Materials, Inc. | Shield or ring surrounding semiconductor workpiece in plasma chamber |
| US20040072426A1 (en) * | 2002-08-02 | 2004-04-15 | Soon-Jong Jung | Process chamber for manufacturing a smiconductor device |
| KR20040075550A (en) * | 2003-02-21 | 2004-08-30 | 삼성전자주식회사 | Dry etching equipment having improved shadow ring structure |
| CN101235482A (en) * | 2007-01-29 | 2008-08-06 | 应用材料股份有限公司 | Process kit for substrate processing chamber |
| KR100849394B1 (en) * | 2007-03-06 | 2008-07-31 | (주)아이씨디 | Plasma processing apparatus having isolator capable of adjusting height |
| CN112614769A (en) * | 2020-12-11 | 2021-04-06 | 无锡邑文电子科技有限公司 | Silicon carbide etching process cavity device and using method |
| KR20220092161A (en) * | 2020-12-24 | 2022-07-01 | 세메스 주식회사 | Apparatus for processing a substrate |
| US20230002894A1 (en) * | 2021-07-01 | 2023-01-05 | Applied Materials, Inc. | Shadow ring lift to improve wafer edge performance |
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| CN117080042B (en) | 2023-12-26 |
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