CN117079598A

CN117079598A - Pixel circuit, driving method thereof, display panel and display device

Info

Publication number: CN117079598A
Application number: CN202311168083.0A
Authority: CN
Inventors: 樊聪; 都蒙蒙; 王琦伟; 董向丹; 黄耀; 王蓉
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2023-09-11
Filing date: 2023-09-11
Publication date: 2023-11-17

Abstract

A pixel circuit, a driving method thereof, a display panel and a display device are provided, and belong to the technical field of display. The pixel circuit includes a light emission control circuit, a potential adjusting circuit, and a light emission driving circuit. The light-emitting control circuit, the potential regulating circuit and the light-emitting driving circuit can be mutually matched under the driving of a gate driving signal provided by a gate signal end, a reset signal provided by a reset signal end and a light-emitting control signal provided by a light-emitting control end so as to drive the light-emitting element to emit light. In the pixel circuit, the driving transistor included in the light-emitting driving circuit is an N-type transistor; the light-emitting control circuit comprises a plurality of control transistors, and at least one target transistor is a P-type transistor. That is, the pixel circuit has a hybrid circuit structure. Therefore, the pixel circuit can be driven to work by using the mature low-level output type display driving circuit with good working stability, the pixel circuit is ensured to reliably drive the light-emitting element to emit light, and the display effect is good.

Description

Pixel circuit, driving method thereof, display panel and display device

Technical Field

The disclosure relates to the technical field of display, and in particular relates to a pixel circuit, a driving method thereof, a display panel and a display device.

Background

An active-matrix organic light-emitting diode (AM OLED) display panel is used as a novel display product, and has the advantages of rich colors, high response speed and the like.

In the related art, an AMOLED display panel generally includes: a substrate, and a plurality of pixels located on the substrate. The pixel comprises a pixel circuit and a light-emitting element, wherein the pixel circuit is respectively coupled with the display driving circuit and the light-emitting element and is used for driving the light-emitting element to emit light based on a driving signal provided by the display driving circuit. In addition, the pixel circuit includes a plurality of transistors, and N-type transistors made of oxide materials are often used in consideration of poor uniformity of P-type transistor characteristics made of low-temperature polysilicon materials.

However, the current display driving circuit capable of providing the required driving signal to the N-type transistor has poor operation stability, so that the pixel circuit cannot reliably drive the light emitting element to emit light, resulting in poor display effect.

Disclosure of Invention

A pixel circuit, a driving method thereof, a display panel and a display device are provided, which can solve the problem that the pixel circuit can not reliably drive a light emitting element to emit light in the related art, so that the display effect is poor. The technical scheme is as follows:

In one aspect, there is provided a pixel circuit including:

the light-emitting control circuit is respectively coupled with a grid signal end, a reset signal end, a light-emitting control end, a data signal end, a reset power end, a driving power end, a first node, a second node, a third node, a fourth node and a fifth node, and is used for controlling the on-off of the data signal end and the fifth node in response to a grid driving signal provided by the grid signal end, controlling the on-off of the reset power end and the first node, the third node and the fourth node in response to a reset signal provided by the reset signal end, and controlling the on-off of the fifth node and the first node in response to a light-emitting control signal provided by the light-emitting control end, and controlling the on-off of the driving power end and the second node;

a potential adjusting circuit coupled to the third node, the fourth node, and the fifth node, respectively, and configured to adjust a potential of the third node, a potential of the fourth node, and a potential of the fifth node;

a light emission driving circuit coupled to the first node, the second node, and the third node, respectively, and configured to control on-off of the second node and the third node in response to a potential of the first node, and transmit a light emission driving signal to the third node based on the potential of the first node and the potential of the second node, the third node being coupled to the light emitting element;

Wherein, the drive transistor included in the light-emitting drive circuit is an N-type transistor; the light-emitting control circuit comprises a plurality of control transistors, wherein at least one target transistor is a P-type transistor.

Optionally, among the plurality of control transistors, the influence of the transistor characteristics of the target transistor on the light emission driving signal is smaller than the influence of the transistor characteristics of the other transistors except the target transistor on the light emission driving signal;

wherein the transistor characteristics include at least one of the following characteristics: threshold voltage, mobility, and off-current.

Optionally, the P-type transistor and the N-type transistor each include: an active layer, a gate metal layer and a source drain metal layer stacked;

wherein, the material of the active layer in the P-type transistor comprises: a low temperature polysilicon material; the material of the active layer in the N-type transistor comprises the following components: an oxide material.

Optionally, the reset signal terminal includes: a first reset signal terminal and a second reset signal terminal; the light emission control terminal includes: a first light emission control end and a second light emission control end; the reset power supply terminal comprises: a first reset power supply terminal and a second reset power supply terminal; the light emission control circuit is used for:

Controlling the on-off of the second reset power supply end and the third node in response to a first reset signal provided by the first reset signal end; the second reset signal provided by the second reset signal end is responded, the on-off of the first reset power end and the first node is controlled, and the on-off of the first reset power end and the fourth node is controlled; controlling the on-off of the driving power supply end and the second node in response to a first light emitting control signal provided by the first light emitting control end; the on-off of the fifth node and the first node is controlled in response to a second light-emitting control signal provided by the second light-emitting control end;

wherein the target transistor includes at least one of the following control transistors: a control transistor coupled to the first reset signal terminal; a control transistor coupled to the second reset signal terminal; a control transistor coupled to the first light emitting control terminal; a control transistor coupled to the second light emission control terminal; and a control transistor coupled to the gate signal terminal.

Optionally, the plurality of control transistors in the light emission control circuit include: a first reset transistor, a second reset transistor, a data writing transistor, a first light emission control transistor, a second light emission control transistor, and a third reset transistor;

Wherein the gate of the first reset transistor and the gate of the second reset transistor are both coupled to the second reset signal terminal, the first pole of the first reset transistor and the first pole of the second reset transistor are both coupled to the first reset power terminal, the second pole of the first reset transistor is coupled to the first node, and the second pole of the second reset transistor is coupled to the fourth node;

the grid electrode of the data writing transistor is coupled with the grid electrode signal end, the first electrode of the data writing transistor is coupled with the data signal end, and the second electrode of the data writing transistor is coupled with the fifth node;

the grid electrode of the first light-emitting control transistor is coupled with the first light-emitting control end, the first electrode of the first light-emitting control transistor is coupled with the driving power supply end, and the second electrode of the first light-emitting control transistor is coupled with the second node;

the grid electrode of the second light-emitting control transistor is coupled with the second light-emitting control end, the first electrode of the second light-emitting control transistor is coupled with the fifth node, and the second electrode of the second light-emitting control transistor is coupled with the first node;

The gate of the third reset transistor is coupled to the first reset signal terminal, the first pole of the third reset transistor is coupled to the second reset power terminal, and the second pole of the third reset transistor is coupled to the third node.

Optionally, the potential adjusting circuit includes: a first capacitor and a second capacitor; the light emission driving circuit includes: the driving transistor;

one end of the first capacitor is coupled with the fourth node, and the other end of the first capacitor is coupled with the third node;

one end of the second capacitor is coupled with the fifth node, and the other end of the second capacitor is coupled with the fourth node;

the gate of the driving transistor is coupled to the first node, the first pole of the driving transistor is coupled to the second node, and the second pole of the driving transistor is coupled to the third node.

In another aspect, there is provided a driving method of a pixel circuit, which is applied to the pixel circuit as described in the above aspect; the method comprises the following steps:

in the first stage, a reset signal end provides a reset signal of an effective potential, a light-emitting control circuit responds to the reset signal and controls a reset power end to be conducted with a first node, a third node and a fourth node, and the reset power end transmits the reset power signal to the first node, the third node and the fourth node;

The second stage, the gate signal end provides the gate driving signal of the effective potential, the said luminescent control circuit responds to the said gate driving signal, control the data signal end to turn on with the fifth node, the said data signal end transmits the data signal to the said fifth node;

the third stage, the light-emitting control end provides a light-emitting control signal of an effective potential, the light-emitting control circuit responds to the light-emitting control signal and controls the fifth node to be conducted with the first node and controls the driving power end to be conducted with the second node, and the driving power end transmits a driving power signal to the second node; the light-emitting driving circuit controls the second node to be conducted with the third node based on the potential of the first node, and transmits a light-emitting driving signal to the third node based on the potential of the first node and the potential of the second node so as to drive a light-emitting element coupled with the third node to emit light;

and, in the first stage, the second stage, and the third stage, the potential adjustment circuit adjusts the potential of the third node, the potential of the fourth node, and the potential of the fifth node.

In still another aspect, there is provided a display panel including: a substrate, and a plurality of pixels located at one side of the substrate;

Wherein the pixel includes: a light emitting element, and a pixel circuit as described in the above aspect, the pixel circuit being coupled to the light emitting element and configured to drive the light emitting element to emit light.

Optionally, the substrate has a display area and a non-display area adjacent to each other, the pixel is located in the display area, and the display panel further includes:

at least one display driving circuit in the non-display region, the display driving circuit being coupled to a pixel circuit included in the pixel and configured to provide a driving signal to the pixel circuit so that the pixel circuit drives the light emitting element to emit light based on the driving signal;

the display driving circuit comprises a transistor which is a P-type transistor, and the material of an active layer in the P-type transistor comprises a low-temperature polysilicon material.

In still another aspect, there is provided a display device including: a power supply assembly and a display panel as described in the above further aspect;

the power supply assembly is coupled with the display panel and is used for supplying power to the display panel.

In summary, the beneficial effects brought by the technical scheme provided by the disclosure at least may include:

A pixel circuit, a driving method thereof, a display panel and a display device are provided. The pixel circuit includes a light emission control circuit, a potential adjusting circuit, and a light emission driving circuit. The light-emitting control circuit, the potential regulating circuit and the light-emitting driving circuit can be mutually matched under the driving of a gate driving signal provided by the gate signal end, a reset signal provided by the reset signal end and a light-emitting control signal provided by the light-emitting control end so as to transmit the light-emitting driving signal to the light-emitting element to drive the light-emitting element to emit light. In the pixel circuit, the driving transistor included in the light-emitting driving circuit is an N-type transistor; the light-emitting control circuit comprises a plurality of control transistors, and at least one target transistor is a P-type transistor. That is, the pixel circuit has a hybrid circuit structure. Therefore, the pixel circuit can be driven to work by using the mature low-level output type display driving circuit with good working stability, the pixel circuit is ensured to reliably drive the light-emitting element to emit light, and the display effect is good.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.

Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of another pixel circuit provided in an embodiment of the disclosure;

fig. 3 is a circuit configuration diagram of a pixel circuit provided in an embodiment of the present disclosure;

FIG. 4 is a signal simulation diagram of a pixel circuit provided in an embodiment of the present disclosure;

fig. 5 is a structural layout corresponding to the pixel circuit shown in fig. 3 according to an embodiment of the present disclosure;

FIG. 6 is another structural layout corresponding to the pixel circuit shown in FIG. 3 according to an embodiment of the present disclosure;

FIG. 7 is a layout corresponding to the pixel circuit shown in FIG. 3 according to an embodiment of the present disclosure;

fig. 8 is a circuit configuration diagram of another pixel circuit provided by an embodiment of the present disclosure;

fig. 9 is a circuit configuration diagram of still another pixel circuit provided by an embodiment of the present disclosure;

fig. 10 is a circuit configuration diagram of still another pixel circuit provided in an embodiment of the present disclosure;

fig. 11 is a circuit configuration diagram of still another pixel circuit provided in an embodiment of the present disclosure;

fig. 12 is a circuit configuration diagram of still another pixel circuit provided in an embodiment of the present disclosure;

fig. 13 is a circuit configuration diagram of still another pixel circuit provided in an embodiment of the present disclosure;

Fig. 14 is a flowchart of a driving method of a pixel circuit according to an embodiment of the present disclosure;

FIG. 15 is a signal timing diagram corresponding to the pixel circuit shown in FIG. 3 according to an embodiment of the present disclosure;

FIG. 16 is a signal timing diagram corresponding to the pixel circuit shown in FIG. 8 according to an embodiment of the present disclosure;

FIG. 17 is a signal timing diagram corresponding to the pixel circuit shown in FIG. 9 according to an embodiment of the present disclosure;

FIG. 18 is a signal timing diagram corresponding to the pixel circuit shown in FIG. 10 according to an embodiment of the present disclosure;

FIG. 19 is a signal timing diagram corresponding to the pixel circuit shown in FIG. 11 according to an embodiment of the present disclosure;

FIG. 20 is a signal timing diagram corresponding to the pixel circuit shown in FIG. 12 according to an embodiment of the present disclosure;

FIG. 21 is a signal timing diagram corresponding to the pixel circuit shown in FIG. 13 according to an embodiment of the present disclosure;

fig. 22 is a schematic structural view of a display panel according to an embodiment of the present disclosure;

fig. 23 is a schematic structural view of another display panel according to an embodiment of the present disclosure;

fig. 24 is a schematic structural view of yet another display panel provided in an embodiment of the present disclosure;

fig. 25 is a circuit configuration diagram of a gate driving circuit provided in an embodiment of the present disclosure;

Fig. 26 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.

Detailed Description

For the purposes of clarity, technical solutions and advantages of the present disclosure, the following further details the embodiments of the present disclosure with reference to the accompanying drawings.

It should be noted that, the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics, and the transistors used in the embodiments of the present disclosure are mainly switching transistors according to the functions in the circuit. Since the source and drain of the switching transistor employed herein are symmetrical, the source and drain are interchangeable. In the embodiments of the present disclosure, the source is referred to as a first pole and the drain is referred to as a second pole. The middle terminal of the transistor is defined as a control electrode according to the form in the figure, and may be called a gate electrode, a signal input terminal as a source electrode, and a signal output terminal as a drain electrode. In addition, the switching transistor used in the embodiments of the present disclosure may include any one of a P-type switching transistor that is turned on when the gate is at a low level, turned off when the gate is at a high level, and an N-type switching transistor that is turned on when the gate is at a high level, and turned off when the gate is at a low level. Further, the plurality of signals in the various embodiments of the present disclosure each correspond to a first potential and a second potential. The first potential and the second potential only represent that the potential of the signal has 2 state quantities, and do not represent that the first potential or the second potential has a specific value in the whole text.

Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the disclosure. As shown in fig. 1, the pixel circuit includes: a light emission control circuit 01, a potential adjustment circuit 02, and a light emission drive circuit 03.

The light emission control circuit 01 is coupled to the Gate signal terminal Gate1, the Reset signal terminal Reset, the light emission control terminal EM, the Data signal terminal Data, the Reset power terminal Vinit, the driving power terminal VDD, the first node N1, the second node N2, the third node N3, the fourth node N4, and the fifth node N5, respectively. The light emission control circuit 01 is configured to control on/off of the Data signal terminal Data and the fifth node N5 in response to a Gate driving signal provided by the Gate signal terminal Gate1, control on/off of the Reset power terminal Vinit and the first node N1, the third node N3 and the fourth node N4 in response to a Reset signal provided by the Reset signal terminal Reset, and control on/off of the fifth node N5 and the first node N1 in response to a light emission control signal provided by the light emission control terminal EM, and control on/off of the driving power terminal VDD and the second node N2.

For example, when the potential of the Gate driving signal provided by the Gate signal terminal Gate1 is the first potential, the light emission control circuit 01 may control the Data signal terminal Data to be conducted with the fifth node N5, so that the Data signal provided by the Data signal terminal Data may be transmitted to the fifth node N5 to charge the fifth node N5. And, the light emission control circuit 01 may control the Data signal terminal Data to be decoupled from the fifth node N5 when the potential of the Gate driving signal provided by the Gate signal terminal Gate1 is the second potential.

Similarly, when the potential of the Reset signal provided by the Reset signal terminal Reset is the first potential, the light-emitting control circuit 01 may control the Reset power terminal Vinit to be conducted with the first node N1, the third node N3 and the fourth node N4, so that the Reset power terminal provided by the Reset power terminal Vinit may be transmitted to the first node N1, the third node N3 and the fourth node N4, respectively, so as to Reset the first node N1, the third node N3 and the fourth node N4. And, the light emission control circuit 01 may control the Reset power supply terminal Vinit to be decoupled from the first node N1, the third node N3, and the fourth node N4 when the potential of the Reset signal provided by the Reset signal terminal Reset is the second potential.

The light emission control circuit 01 may control the fifth node N5 to be connected to the first node N1 when the potential of the light emission control signal provided by the light emission control terminal EM is the first potential, so that the signal transmitted to the fifth node N5 may be further transmitted to the first node N1, and control the driving power terminal VDD to be connected to the second node N2, so that the driving power signal provided by the driving power terminal VDD may be transmitted to the second node N2. And, the light emission control circuit 01 may control the fifth node N5 to be decoupled from the first node N1 and control the driving power source terminal VDD to be decoupled from the second node N2 when the potential of the light emission control signal provided by the light emission control terminal EM is the second potential.

Alternatively, in an embodiment of the present disclosure, the first potential may be an active potential and the second potential may be an inactive potential. For a P-type transistor in a circuit, the first potential may be low relative to the second potential; for an N-type transistor in a circuit, the first potential may be high relative to the second potential.

The potential adjusting circuit 02 is coupled to the third node N3, the fourth node N4, and the fifth node N5, respectively. The potential adjusting circuit 02 is configured to adjust the potential of the third node N3, the potential of the fourth node N4, and the potential of the fifth node N5.

For example, the potential adjusting circuit 02 may adjust the potential of the third node N3, the potential of the fourth node N4, and the potential of the fifth node N5 by coupling.

The light emitting driving circuit 03 is coupled to the first node N1, the second node N2, and the third node N3, respectively. The light-emitting driving circuit 03 is configured to control on/off of the second node N2 and the third node N3 in response to the potential of the first node N1, and transmit a light-emitting driving signal to the third node N3 based on the potential of the first node N1 and the potential of the second node N2, and the third node N3 is coupled to the light-emitting element L1.

For example, when the potential of the first node N1 is the first potential, the light-emitting driving circuit 03 may control the second node N2 to be turned on with the third node N3, and simultaneously transmit a light-emitting driving signal (e.g., a driving current) to the third node N3 based on the potential of the first node N1 and the potential of the second node N2, so as to drive the light-emitting element L1 coupled to the third node N3 to emit light. And, the light emitting driving circuit 03 may control the second node N2 to be decoupled from the third node N3 when the potential of the first node N1 is the second potential.

Alternatively, referring to fig. 1, in the embodiment of the present disclosure, the third node N3 may be coupled to the first pole of the light emitting element L1, and further, the second pole of the light emitting element L1 may be coupled to the pull-down power supply terminal Vss. The light emitting element L1 may emit light under the voltage difference between the light emitting driving signal received by the first pole and the pull-down power signal provided by the pull-down power terminal Vss received by the second pole. As shown in fig. 1, the first electrode of the light-emitting element L1 may be an anode, and the second electrode of the light-emitting element L1 may be a cathode. Of course, in some other embodiments, the first pole of the light emitting element L1 may be a cathode and the second pole of the light emitting element L1 may be an anode.

Also, in the embodiment of the present disclosure, the driving transistor included in the light-emitting driving circuit 03 is an N-type transistor. The light emission control circuit 01 includes a plurality of control transistors, and at least one target transistor is a P-type transistor. That is, the pixel circuit described in the embodiments of the present disclosure is a Hybrid (Hybrid) structure pixel circuit including an N-type transistor and a P-type transistor, and is not an all-N-type or all-P-type single structure pixel circuit.

It should be noted that, the control terminals (including the Gate signal terminal Gate1, the Reset signal terminal Reset and the light emission control terminal EM) of the control transistors in the light emission control circuit 01 are coupled to the display driving circuit, and receive the signals provided by the display driving circuit. For example, for the Gate signal terminal Gate1, a Gate driving circuit may be used as a display driving circuit, and the Gate driving circuit is coupled to the Gate signal terminal Gate1 and is used for transmitting a required Gate driving signal to the Gate signal terminal Gate 1. For the Reset signal terminal Reset, a Reset driving circuit may be used as a display driving circuit, which is coupled to the Reset signal terminal Reset and is used to transmit a required Reset signal to the Reset signal terminal Reset. For the light emission control terminal EM, a light emission control driving circuit may be used as a display driving circuit, and the light emission control driving circuit is coupled to the light emission control terminal EM and is used for transmitting a required light emission control signal to the light emission control terminal EM.

Alternatively, in some embodiments, the display driver circuitry may be integrated into the non-display area of the display substrate using substrate row driving (gate drive on array, GOA) techniques to facilitate narrow bezel designs. Correspondingly, the GOA circuit is also called. For distinction, the Gate drive circuit may be referred to as Gate GOA circuit; the Reset driving circuit may be referred to as a Reset GOA circuit; the emission control driving circuit may be referred to as an EM GOA circuit.

Currently, a more sophisticated GOA circuit architecture is a low-level (i.e., potential) output type architecture including a plurality of P-type transistors. On this basis, the current GOA circuit architecture is contrary to the design of the N-type transistors in the pixel circuit for turning on the required high level signals. In addition, although the high-level output type GOA circuit structure is continuously developed, the mass production feasibility of the high-level output type GOA circuit structure is still to be researched, and the working stability and the reliability of the existing high-level output type GOA circuit structure are poor.

In the embodiment of the disclosure, by setting at least one target transistor of the plurality of control transistors included in the light-emitting control circuit 01 as a P-type transistor, a mature low-level output type GOA circuit with better working stability can be directly used to ensure that the pixel circuit is reliably driven to work, so that the pixel circuit can reliably drive the light-emitting element L1 to emit light, and display uniformity and better image quality of the display panel are ensured. In addition, due to the influence of the preparation process and materials, the design area of the N-type transistor is larger than that of the P-type transistor, so that by setting a plurality of control transistors included in the light-emitting control circuit 01, at least one target transistor is the P-type transistor, the pixel space can be optimized, and the product design of high PPI is facilitated, wherein PPI refers to: the number of pixels per inch included in a display panel, english full scale: pixels PerInch for indicating resolution. And the low-level output GOA circuit structure comprising a plurality of P-type transistors is matched, so that the space of a non-display area can be optimized in the same way, and the narrow frame design is further facilitated.

That is, the scheme provided by the embodiments of the present disclosure may be considered as a design combining a low-level output type GOA circuit architecture that facilitates a narrow frame design with a hybrid type pixel circuit that can ensure a better display image quality, and is considered as one of the main technologies for future product technology development.

In summary, the embodiments of the present disclosure provide a pixel circuit. The pixel circuit includes a light emission control circuit, a potential adjusting circuit, and a light emission driving circuit. The light-emitting control circuit, the potential regulating circuit and the light-emitting driving circuit can be mutually matched under the driving of a gate driving signal provided by the gate signal end, a reset signal provided by the reset signal end and a light-emitting control signal provided by the light-emitting control end so as to transmit the light-emitting driving signal to the light-emitting element to drive the light-emitting element to emit light. In the pixel circuit, the driving transistor included in the light-emitting driving circuit is an N-type transistor; the light-emitting control circuit comprises a plurality of control transistors, and at least one target transistor is a P-type transistor. That is, the pixel circuit has a hybrid circuit structure. Therefore, the pixel circuit can be driven to work by using the mature low-level output type display driving circuit with good working stability, the pixel circuit is ensured to reliably drive the light-emitting element to emit light, and the display effect is good.

Alternatively, among the plurality of control transistors included in the light emission control circuit 01 according to the embodiment of the present disclosure, the influence of the transistor characteristics of the target transistor on the light emission driving signal may be smaller than the influence of the transistor characteristics of the other transistors than the target transistor on the light emission driving signal. Wherein the transistor characteristics include at least one of the following characteristics: threshold voltage Vth, mobility (mob.) and off-current Ioff.

Therefore, on the basis of ensuring reliable driving of the pixel circuit to work and optimizing the space, the GOA circuit with a mature low-level output type framework with good working stability is used, the influence on the luminous brightness of the luminous element, namely the influence on the display gray scale, is avoided, and the display effect is further ensured to be good.

Optionally, the P-type transistor and the N-type transistor provided in the embodiments of the present disclosure may each include: an active layer, a gate metal layer and a source drain metal layer are stacked.

The material of the active layer in the P-type transistor may include: low temperature polysilicon (low temperature poly-silico, LTPS) material. The material of the active layer in the N-type transistor may include: oxide (Oxide) material. For example, indium gallium zinc oxide (indium gallium zinc oxide, IGZO) may be used. Thus, the pixel circuit provided by the embodiments of the present disclosure may also be referred to as a Hybrid type pixel circuit of LTPO; the GOA circuits of the low-level output architecture that are used in the past may also be referred to as GOA circuits of LTPS.

Optionally, fig. 2 is a schematic structural diagram of another pixel circuit provided in an embodiment of the disclosure. As shown in fig. 2, the Reset signal terminal Reset may include: a first Reset signal terminal Reset1 and a second Reset signal terminal Reset2. The light emission control terminal EM may include: a first light emission control terminal EM1 and a second light emission control terminal EM2. The reset power supply terminal Vinit may include: a first reset power supply terminal Vinit1 and a second reset power supply terminal Vinit2.

The light emission control circuit 01 may be configured to: and responding to a first Reset signal provided by the first Reset signal terminal Reset1, and controlling the on-off of the second Reset power supply terminal Vinit2 and the third node N3. And responding to a second Reset signal provided by a second Reset signal end Reset2, controlling the on-off of the first Reset power end Vinit1 and the first node N1, and controlling the on-off of the first Reset power end Vinit1 and the fourth node N4. In response to the first light emitting control signal provided by the first light emitting control terminal EM1, the driving power terminal VDD is controlled to be turned on or off with the second node N2. And the on-off of the fifth node N5 and the first node N1 is controlled in response to a second light-emitting control signal provided by the second light-emitting control end EM2.

For example, when the potential of the first Reset signal provided by the first Reset signal terminal Reset1 is the first potential, the light emission control circuit 01 may control the second Reset power terminal Vinit2 to be turned on with the third node N3, so that the second Reset power signal provided by the second Reset power terminal Vinit2 may be transmitted to the third node N3. And, the light emission control circuit 01 may control the second Reset power supply terminal Vinit2 to be decoupled from the third node N3 when the potential of the first Reset signal provided by the first Reset signal terminal Reset1 is the second potential.

Similarly, when the potential of the second Reset signal provided by the second Reset signal terminal Reset2 is the first potential, the light-emitting control circuit 01 may control the first Reset power terminal Vinit1 to be turned on with the first node N1 and the fourth node N4, so that the second Reset power signal provided by the first Reset power terminal Vinit1 is transmitted to the first node N1 and the fourth node N4 respectively. And, the light emission control circuit 01 may control the first Reset power supply terminal Vinit1 to be decoupled from both the first node N1 and the fourth node N4 when the potential of the second Reset signal provided by the second Reset signal terminal Reset2 is the second potential.

Similarly, when the potential of the first light emitting control signal provided by the first light emitting control terminal EM1 is the first potential, the light emitting control circuit 01 may control the driving power terminal VDD to be turned on with the second node N2, so that the driving power signal provided by the driving power terminal VDD is transmitted to the second node N2. And, the light emission control circuit 01 may control the driving power supply terminal VDD to be decoupled from the second node N2 when the potential of the first light emission control signal provided by the first light emission control terminal EM1 is the second potential.

Similarly, when the potential of the second light emission control signal provided by the second light emission control terminal EM2 is the first potential, the light emission control circuit 01 may control the fifth node N5 to be turned on with the first node N1, so that the signal transmitted to the fifth node N5 may be further transmitted to the first node N1. And, the light emission control circuit 01 may control the fifth node N5 to be decoupled from the first node N1 when the potential of the second light emission control signal provided by the second light emission control terminal EM2 is the second potential.

By dividing the Reset signal terminal Reset to include the first Reset signal terminal Reset1 and the second Reset signal terminal Reset2, the light emission control terminal EM includes the first light emission control terminal EM1 and the second light emission control terminal EM2, it is possible to improve flexibility in resetting different nodes in response to different Reset signals, and flexibility in controlling the electric potentials of different nodes in response to different light emission control signals. Namely, the pixel circuit is enabled to work more flexibly.

Wherein the target transistor that is P-type (i.e., the target transistor of LTPS) may include at least one of the following control transistors:

a control transistor coupled to the first Reset signal terminal Reset 1.

A control transistor coupled to the second Reset signal terminal Reset 2.

A control transistor coupled to the first light emitting control terminal EM 1.

And a control transistor coupled to the second emission control terminal EM 2.

And a control transistor coupled to the Gate signal terminal Gate 1.

Alternatively, fig. 3 shows a circuit configuration diagram of a pixel circuit on the basis of fig. 2. As can be seen with reference to fig. 3, the light emission control circuit 01 may include: a first reset transistor T1, a second reset transistor T2, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, and a third reset transistor T7. The potential adjusting circuit 02 may include: a first capacitor C1 and a second capacitor C2. The light emission driving circuit 03 may include: and a driving transistor T3.

The gate of the first Reset transistor T1 and the gate of the second Reset transistor T2 may be coupled to the second Reset signal terminal Reset2, the first pole of the first Reset transistor T1 and the first pole of the second Reset transistor T2 may be coupled to the first Reset power terminal Vinit1, the second pole of the first Reset transistor T1 may be coupled to the first node N1, and the second pole of the second Reset transistor T2 may be coupled to the fourth node N4.

The Gate of the Data writing transistor T4 may be coupled to the Gate signal terminal Gate1, the first pole of the Data writing transistor T4 may be coupled to the Data signal terminal Data, and the second pole of the Data writing transistor T4 may be coupled to the fifth node N5.

The gate electrode of the first light emitting control transistor T5 may be coupled to the first light emitting control terminal EM1, the first pole of the first light emitting control transistor T5 may be coupled to the driving power terminal VDD, and the second pole of the first light emitting control transistor T5 may be coupled to the second node N2.

The gate of the second light-emitting control transistor T6 may be coupled to the second light-emitting control terminal EM2, the first pole of the second light-emitting control transistor T6 may be coupled to the fifth node N5, and the second pole of the second light-emitting control transistor T6 may be coupled to the first node N1.

The gate of the third Reset transistor T7 may be coupled to the first Reset signal terminal Reset1, the first pole of the third Reset transistor T7 may be coupled to the second Reset power terminal Vinit2, and the second pole of the third Reset transistor T7 may be coupled to the third node N3.

One end of the first capacitor C1 may be coupled to the fourth node N4, and the other end of the first capacitor C1 may be coupled to the third node N3. That is, the first capacitor C1 may be connected in series between the fourth node N4 and the third node N3.

One end of the second capacitor C2 may be coupled to the fifth node N5, and the other end of the second capacitor C2 may be coupled to the fourth node N4. That is, the second capacitor C2 may be connected in series between the fifth node N5 and the fourth node N4.

The gate of the driving transistor T3 may be coupled to the first node N1, the first pole of the driving transistor T3 may be coupled to the second node N2, and the second pole of the driving transistor T3 may be coupled to the third node N3.

It should be noted that the pixel circuit shown in fig. 3 is of a 7T2C structure (i.e., includes 7 transistors and 2 capacitors). In some other embodiments, the pixel circuit may have other structures, such as 6T1C.

Alternatively, in the pixel circuit described in the embodiments of the present disclosure, the transistors may be metal-oxide-semiconductor (MOS) transistors, which are also referred to as MOS transistors. Correspondingly, the P-type transistor is also called a PMOS tube; n-type transistors are also known as NMOS transistors.

Based on fig. 3, in combination with the above description, at least one of the following transistors included in the light emission control circuit 01 in the embodiment of the present disclosure may be PMOS transistors of LTPS:

(1) A first reset transistor T1 and a second reset transistor T2;

(2) A data writing transistor T4;

(3) A first light emitting control transistor T5;

(4) A second light emission control transistor T6;

(5) And a third reset transistor T7.

For example, based on the above description, fig. 4 shows a schematic diagram of an analog simulation of a P-type transistor. The abscissa is used to characterize the threshold voltage Vth and the mobility mob, and the ordinate is used to characterize the luminance. And fig. 4 shows the brightness of Red (Red, R), green (G) and blue (blue, B) pixels at three different gray scales of L8, L32 and L255, respectively. The pixel includes a pixel circuit and a light emitting element. As can be seen with reference to fig. 4, the difference in the threshold voltage Vth and mobility mob of the third reset transistor T7 has the smallest influence on the brightness. On this basis, different pixel circuit designs are given by taking the following schemes as examples:

scheme 1: referring to fig. 3, in the light emission control circuit 01, a data writing transistor T4 coupled to a Gate signal terminal Gate1 is a PMOS transistor of LTPS, and is identified as T4-P; the rest of transistors except the data writing transistor T4 are NMOS transistors of Oxide. Fig. 5 to 7 also show the structural Layout (Layout) of the pixel circuit shown in fig. 3, respectively, on the basis of fig. 3. The layout shown in FIG. 5 includes an active layer, three gate metal layers gate1, gate2 and gate3, and transfer layers CNT-L and CNT-O. The material of the active layer of the data writing transistor T4 comprises low-temperature polysilicon LTPS, also called polysilicon p-si, and the material of the active layer of the rest transistors comprises Oxide, and the transfer layer CNT-L is used for transferring the active layer and other layers of the low-temperature polysilicon LTPS; the switching layer CNT-O is used to switch the active layer and other layers of Oxide material. The layout shown in fig. 6 further includes a source drain metal layer SD1. The layout shown in fig. 7 further comprises a further source drain metal layer SD2. Of course, the layout structure is only schematically illustrated here. The design advantages of scheme 1 include: the Gate GOA circuit can be used along with a mature Gate GOA circuit of LTPS, NMOS tubes of Oxide in the pixel circuit can still ensure the advantages of good uniformity, small leakage current and the like for improving the uniformity of display gray-scale image quality, meanwhile, the Gate GOA circuit of LTPS in a non-display area can reliably control low-level output signals to data signals, and can optimize space and facilitate realization of high PPI and narrow frames.

Scheme 2: referring to fig. 8, in the light emission control circuit 01, a third Reset transistor T7 coupled to the first Reset signal terminal Reset1 is a PMOS transistor of LTPS, and is identified as T7-P; the rest of transistors except the third reset transistor T7 are NMOS transistors of Oxide. The design advantages of scheme 2 include: the Reset GOA circuit can adopt a mature LTPS Reset GOA circuit, the driving stability is good, the NMOS tube of Oxide in the pixel circuit can still ensure good uniformity, the leakage current is small, and the like, the uniformity of the display gray-scale image quality is improved, meanwhile, with reference to fig. 4, the effect of uniformity difference on brightness is small due to the fact that the difference of the threshold voltage Vth and the mobility mob of the third Reset transistor T7 is small, the display effect can be further ensured, the space can be optimized, and the realization of high PPI and a narrow frame is facilitated.

Scheme 3: referring to fig. 9, in the light emission control circuit 01, a first Reset transistor T1 and a second Reset transistor T2 coupled to a second Reset signal terminal Reset2 are PMOS transistors of LTPS, respectively identified as T1-P and T2-P; the rest of transistors except the first reset transistor T1 and the second reset transistor T2 are NMOS transistors of Oxide. The design advantages of scheme 3 include: the Reset GOA circuit can follow a mature Reset GOA circuit of LTPS, namely, the first node N1 and the fourth node N4 can be reliably Reset by adopting low-level control of the output of the Reset GOA circuit of LTPS, the NMOS tube of Oxide in the pixel circuit can still ensure the advantages of better uniformity, smaller leakage current and the like on improving the uniformity of the display gray-scale image quality, and the space can be optimized, so that the realization of high PPI and a narrow frame is facilitated.

Scheme 4: referring to fig. 10, in the light emission control circuit 01, a second light emission control transistor T6 coupled to the second light emission control terminal EM2 is a PMOS transistor of LTPS, denoted as T6-P; the rest of the transistors except the second light emission control transistor T6 are NMOS transistors of Oxide. The design advantages of scheme 4 include: the EM GOA circuit can be used along with an EM GOA circuit of mature LTPS, NMOS tubes of oxides in the pixel circuits can still ensure the advantages of good uniformity, small leakage current and the like for improving the uniformity of display gray-scale image quality, and the space can be optimized, so that the realization of high PPI and narrow frames is facilitated.

Scheme 5: referring to fig. 11, in the light emission control circuit 01, a first light emission control transistor T5 coupled to a first light emission control terminal EM1 is a PMOS transistor of LTPS, denoted as T5-P; the rest of transistors except the first light emitting control transistor T5 are NMOS transistors of Oxide. The design advantages of scheme 5 include: the EM GOA circuit can be used along with an EM GOA circuit of mature LTPS, NMOS tubes of oxides in the pixel circuits can still ensure the advantages of good uniformity, small leakage current and the like for improving the uniformity of display gray-scale image quality, and the space can be optimized, so that the realization of high PPI and narrow frames is facilitated.

Scheme 6: referring to fig. 12, in the light emission control circuit 01, a second light emission control transistor T6 coupled to the second light emission control terminal EM2 and a first light emission control transistor T5 coupled to the first light emission control terminal EM1 are PMOS transistors of LTPS, respectively identified as T5-P and T6-P; the rest of transistors except the first light emission control transistor T5 and the second light emission control transistor T6 are NMOS transistors of Oxide. The design advantage of the solution 6 can be referred to the descriptions of the above solutions 4 and 5, and will not be repeated here.

Scheme 7: referring to fig. 13, in the light emission control circuit 01, the data writing transistor T4 coupled to the Gate signal terminal Gate1 and the third Reset transistor T7 coupled to the first Reset signal terminal Reset1 are PMOS transistors of LTPS, respectively identified as T4-P and T7-P; the rest of transistors except the data writing transistor T4 and the third reset transistor T7 are NMOS transistors of Oxide. The design advantage of the embodiment 7 can be referred to the descriptions of the embodiments 1 and 2, and will not be repeated here.

It should be noted that the above embodiments are merely illustrative, and do not limit the embodiments of the disclosure. And, for the various schemes described above, the NMOS tubes are all identified as "-N" to distinguish them from the PMOS tubes.

Fig. 14 is a flowchart of a driving method of a pixel circuit according to an embodiment of the present disclosure, where the method is applied to the pixel circuit described in the above embodiment. As shown in fig. 14, the method includes:

In step 1401, in the first stage, the reset signal terminal provides a reset signal of an effective potential, and the light-emitting control circuit responds to the reset signal and controls the reset power terminal to be conducted with the first node, the third node and the fourth node, and the reset power terminal transmits the reset power signal to the first node, the third node and the fourth node.

In step 1402, in the second stage, the gate signal terminal provides a gate driving signal with an effective potential, and the light emission control circuit controls the data signal terminal to be conducted with the fifth node in response to the gate driving signal, and the data signal terminal transmits the data signal to the fifth node.

In step 1403 and in the third stage, the light-emitting control terminal provides a light-emitting control signal with an effective potential, and the light-emitting control circuit responds to the light-emitting control signal to control the fifth node to be conducted with the first node, and controls the driving power terminal to be conducted with the second node, and the driving power terminal transmits a driving power signal to the second node. The light-emitting driving circuit controls the second node to be conducted with the third node based on the potential of the first node, and transmits a light-emitting driving signal to the third node based on the potential of the first node and the potential of the second node so as to drive the light-emitting element coupled with the third node to emit light.

And, in the first stage, the second stage, and the third stage, the potential adjusting circuit adjusts the potential of the third node, the potential of the fourth node, and the potential of the fifth node.

Alternatively, taking the pixel circuit structure shown in fig. 3 (i.e., scheme 1) as an example, fig. 15 shows a timing chart of signal terminals in the pixel circuit. Taking the structure shown in fig. 15 as an example, the operation principle of the pixel circuit (including the stages 1 to 10) is described as follows:

in the stage 1, the first light emitting control terminal EM1 provides a first light emitting control signal with an effective potential and the second light emitting control terminal EM2 provides a second light emitting control signal with an effective potential, so that both the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on, and the light emitting element L1 is driven to emit light. The light emission here refers to a light emission phase of a previous frame adjacent to the current frame. It should be noted that, as for the first light emitting control transistor T5-N and the second light emitting control transistor T6-N of the N type in the structure shown in fig. 3, as can be seen from fig. 15, the effective potential of the first light emitting control signal and the effective potential of the second light emitting control signal may be both high.

In phase 2, the light emission of the previous frame is ended, and the driving of the next frame (i.e., the current frame) is entered. This phase reserves a gap (margin) of Tr/Tf between two frames, tr being the rise time from the falling edge to the rising edge; tf refers to the falling time from the rising edge to the falling edge, thereby ensuring stable driving into the current frame.

In stage 3, the second Reset signal terminal Reset2 provides a second Reset signal of an active potential, so that the first Reset transistor T1 and the second Reset transistor T2 are turned on, and further, the second Reset power signal provided by the first Reset power terminal Vinit1 may be transmitted to the first node N1 and the fourth node N4 through the turned-on first Reset transistor T1 and the second Reset transistor T2, respectively, to Reset (also referred to as initializing) the first node N1 and the fourth node N4. That is, assuming that the potential of the second reset power supply signal is Vinit10, in phase 3, the potential V-n1=vinit 10 of the first node N1, and the potential V-n4=vinit 10 of the fourth node N4. It should be noted that, for the first reset transistor T1-N and the second reset transistor T2-N of the N type in the structure shown in fig. 3, as can be seen in conjunction with fig. 15, the effective potential of the second reset signal may be a high potential.

In stage 4, the first Reset signal terminal Reset1 provides a first Reset signal with an active potential, so that the third Reset transistor T7 is turned on, and further, the second Reset power signal provided by the second Reset power terminal Vinit2 may be transmitted to the third node N3 through the turned-on third Reset transistor T7, so as to Reset the third node N3. That is, assuming that the potential of the second reset power supply signal is Vinit20, in the stage 4, the potential V-n3=vinit 20 of the third node N3 needs to be explained that, for the N-type third reset transistor T7-N in the structure shown in fig. 3, as can be seen in conjunction with fig. 15, the effective potential of the first reset signal may be a high potential.

In stage 5, the second Reset signal terminal Reset2 still provides the second Reset signal of the active potential to continue to Reset the first node N1 and the fourth node N4.

In stage 6, the first light emitting control terminal EM1 provides the first light emitting control signal with an effective potential (i.e., a high potential), so that the first light emitting control transistor T5 is turned on, and the driving power signal provided by the driving power terminal VDD is transmitted to the second node N2 through the turned-on first light emitting control transistor T5-N. The threshold voltage Vth of the driving transistor T3 can be compensated at this time. As described in the stage 3, in the stage t6, the potential V-n4=vinit 10 of the fourth node N4, and the potential V-n3=vinit 10-Vth of the third node N3.

In stage 7, the Gate signal terminal Gate1 provides a Gate driving signal with an effective potential, so that the Data writing transistor T4 is turned on, and the Data signal provided by the Data signal terminal Data is transmitted to the fifth node N5 through the turned-on Data writing transistor T4. That is, assuming that the potential of the data signal is Vdata, in phase 7, the potential v—n5=vdata of the fifth node N5. It should be noted that, for the P-type data writing transistors T4-P in the structure shown in fig. 3, it can be seen in conjunction with fig. 15 that the effective potential of the gate driving signal may be a low potential.

In stage 8, the first light emitting control terminal EM1 still provides the first light emitting control signal with the effective potential, i.e. the compensation operation of stage 6 is continuously performed.

In phase 9, the second Reset signal terminal Reset2 stops the second Reset signal supplying the active potential (i.e., supplying the inactive potential), so that both the first Reset transistor T1 and the second Reset transistor T2 are turned off. This stage reserves margin for the second emission control signal that provides an effective potential for the second emission control terminal EM 2.

In stage 10, the second light emitting control terminal EM2 starts to provide the second light emitting control signal with the active potential, so that the second light emitting control transistor T6 is turned on, and the signal transmitted to the fifth node N5 (i.e. the data signal transmitted in stage 7) is further transmitted to the first node N1 via the turned-on second light emitting control transistor T6. That is, in phase 10, the potential V-n1=v-n5=vdata of the first node N1. Further, the driving transistor T3 may be turned on, and may transmit a light emission driving signal (i.e., a driving current) to the third node N3 based on the potential of the first node N1 and the potential of the second node N2, thereby driving the light emitting element L1 coupled to the third node N3 to emit light.

In the phase 6, the potential V-n3=vinit 10-Vth of the third node N3 is controlled. Therefore, in combination with the current saturation formula, the driving current i_oled finally transmitted to the light emitting element L1 satisfies the following conditions: i_oled=kx (Vgs-Vth) ≡2=kx [ Vdata- (Vinit 10-Vth) ]ζζ 2=kx (Vdata-Vinit 10) ≡2;

In the above formula, vgs refers to the gate-source voltage difference of the driving transistor T3, vth refers to the threshold voltage of the driving transistor T3, and Kx may be determined according to the process parameters of the driving transistor T3, and belongs to a fixed value. As can be seen, the driving current i_oled transmitted to the light emitting element L1 is related to only the potential Vdata of the data signal and the potential Vref0 of the second reset power signal, and is unrelated to the threshold voltage Vth of the driving transistor T3. In this way, the threshold voltage Vth of the driving transistor T3 is prevented from being shifted to affect the driving current.

In addition, referring to fig. 15, it can be further seen that the stages 3 to 5 can be divided into the first stage t1 described in the step 1401, the stages 6 to 8 can be divided into the second stage t2 described in the step 1402, and the stages 9 to 10 can be divided into the second stage t3 described in the step 1403.

Alternatively, on the basis of the description of the above operation principle, fig. 16 shows an operation timing chart corresponding to the pixel circuit structure of the scheme 2. As can be seen from comparing fig. 15 and 16, since the scheme 2 is designed to design the third reset transistor T7 in the pixel circuit to be a P-type transistor (T7-P) and the rest of the control transistors except the third reset transistor T7 are all N-type transistors, compared with the scheme 1, the timing difference is that: first, the effective potential of the first Reset signal provided by the first Reset signal terminal Reset1 is a low potential. Second, the effective potential of the Gate driving signal provided by the Gate signal terminal Gate1 is high.

Optionally, on the basis of the description of the above working principle, fig. 17 shows a working timing chart corresponding to the pixel circuit structure of the scheme 3. As can be seen from comparing fig. 15 and 17, since the scheme 3 is designed to design the first reset transistor T1 and the second reset transistor T2 in the pixel circuit to be P-type transistors (T1-P and T2-P) and the rest of the control transistors except the first reset transistor T1 and the second reset transistor T2 are N-type transistors with respect to the scheme 1, the timing difference is that: first, the effective potential of the second Reset signal provided by the second Reset signal terminal Reset2 is a low potential. Second, the effective potential of the Gate driving signal provided by the Gate signal terminal Gate1 is high.

Alternatively, on the basis of the description of the above operation principle, fig. 18 shows an operation timing chart corresponding to the pixel circuit structure of the scheme 4. As can be seen from comparing fig. 15 and fig. 18, since the scheme 4 is designed to design the second light emission control transistor T6 in the pixel circuit to be a P-type transistor (T6-P) and the rest of the control transistors except the second light emission control transistor T6 are all N-type transistors, the timing difference is that: first, the effective potential of the second light emission control signal provided by the second light emission control terminal EM2 is low. Second, the effective potential of the Gate driving signal provided by the Gate signal terminal Gate1 is high.

Optionally, on the basis of the description of the above operation principle, fig. 19 shows an operation timing chart corresponding to the pixel circuit structure of the scheme 5. As can be seen from comparing fig. 15 and 19, since the scheme 5 is designed to design the first light emitting control transistor T5 in the pixel circuit to be a P-type transistor (T5-P) with respect to the scheme 1, the remaining control transistors except for the first light emitting control transistor T5 are all N-type transistors, so the timing difference is that: first, the effective potential of the first light control signal provided by the first light emitting control terminal EM1 is low. Second, the effective potential of the Gate driving signal provided by the Gate signal terminal Gate1 is high.

Alternatively, on the basis of the description of the above operation principle, fig. 20 shows an operation timing chart corresponding to the pixel circuit structure of the scheme 6. As can be seen from comparing fig. 15 and 20, since the scheme 6 is designed to design the first light emission control transistor T5 and the second light emission control transistor T6 in the pixel circuit to be P-type transistors (T5-P and T6-P) with respect to the scheme 1, the remaining control transistors except for the first light emission control transistor T5 and the second light emission control transistor T6 are N-type transistors, so the timing difference is that: first, the effective potential of the first light control signal provided by the first light emitting control terminal EM1 and the effective potential of the second light emitting control signal provided by the second light emitting control terminal EM2 are both low. Second, the effective potential of the Gate driving signal provided by the Gate signal terminal Gate1 is high.

Alternatively, on the basis of the description of the above operation principle, fig. 21 shows an operation timing chart corresponding to the pixel circuit structure of the scheme 7. As can be seen from comparing fig. 15 and 21, since the scheme 7 is that the data writing transistor T4 and the third reset transistor T7 in the pixel circuit are P-type transistors (T4-P and T7-P) compared with the scheme 1, the rest of the control transistors except the data writing transistor T4 and the third reset transistor T7 are N-type transistors, so the timing difference is that: in addition to the effective potential of the Gate driving signal provided by the Gate signal terminal Gate1 being a low potential, the effective potential of the first Reset signal provided by the first Reset signal terminal Reset1 is also a low potential.

Since the driving method of the pixel circuit may have substantially the same technical effects as those of the pixel circuit described in the previous embodiments, the technical effects of the driving method are not repeated here for the sake of brevity.

Fig. 22 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. As shown in fig. 22, the display panel includes: a substrate 10, and a plurality of pixels P1 located at one side of the substrate 10.

Wherein the pixel P1 includes: the light emitting element L1, and the pixel circuit 00 described in the above embodiment, the pixel circuit 00 is coupled to the light emitting element L1, and is used to drive the light emitting element L1 to emit light.

Alternatively, fig. 23 is a schematic structural diagram of another display panel according to an embodiment of the disclosure. As shown in fig. 23, the substrate 10 may have a display area A1 and a non-display area B1 adjacent to each other, the pixel P1 may be located in the display area A1, and the display panel may further include:

at least one display driving circuit 20 located in the non-display area B1, the display driving circuit 20 is coupled to the pixel circuit 00 included in the pixel P1, and is configured to provide a driving signal to the pixel circuit 00, so that the pixel circuit 00 drives the light emitting element L1 to emit light based on the driving signal. As described in the above embodiments, the display driving circuit 20 may be coupled to a control terminal (including the Gate signal terminal Gate1, the Reset signal terminal Reset, and the light emission control terminal EM) or the like coupled to the pixel circuit 00, and configured to supply a desired control signal to the control terminal.

Alternatively, the transistors included in the display driving circuit 20 are P-type transistors, and the material of the active layer in the P-type transistors includes low temperature polysilicon LTPS material. That is, as described in the above embodiment, the display driving circuit 20 may be provided as a GOA circuit of LTPS which is mature and has high operation stability.

By way of example, taking the display driving circuit 20 as an example, which includes the Gate GOA circuit, the Reset GOA circuit, and the EM GOA circuit described in the above embodiments, and the GOA circuit is a GOA circuit of LTPS, fig. 24 shows a schematic configuration of another display panel. Referring to fig. 24, it can be seen that one Gate GOA circuit, one Reset GOA circuit, and one EM GOA circuit may be respectively disposed at the left and right sides of the display area A1, so that it is possible to ensure reliable and timely driving of the pixels at the left and right sides of each row of the pixels P1 when the display panel is large in size and the number of the pixels P1 is large. For example, a left GOA circuit may be coupled to a left plurality of pixels and a right GOA circuit may be coupled to a right plurality of pixels. Of course, this is also only a schematic illustration.

Alternatively, taking the Gate GOA circuit of LTPS as an example, fig. 25 also shows a schematic structure of a GOA unit included therein. Referring to fig. 25, it can be seen that the GOA unit shown is of a 9T3C structure (i.e., includes 9 transistors and 3 capacitors), and is coupled to the power supply terminal VGH/VGL, the clock terminal CK/CB, and the start signal terminal STV, respectively, and is coupled to the Gate signal terminal Gate1 through the output terminal OUT, for transmitting a desired Gate driving signal to the Gate signal terminal Gate1 based on signals provided from the coupled terminals. The coupling relationship between each transistor and each capacitor is shown in fig. 25, and will not be described herein.

Since the display panel can have substantially the same technical effects as the pixel circuits described in the previous embodiments, the technical effects of the display panel are not repeated here for the sake of brevity.

Fig. 26 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. As shown in fig. 26, the display device includes: the power supply assembly J1, and the display panel 100 described in the above embodiment.

The power supply assembly J1 is coupled to the display panel 100 and is used for supplying power to the display panel 100.

Alternatively, the display device may be: AMOLED display devices, OLED display devices, liquid crystal display devices, and the like.

The AMOLED display device has the advantages of small power consumption, wide operating temperature range, low cost, high contrast, wide viewing angle, wide color gamut and thinner display panel, and can realize flexible display so as to gradually become a next-generation display 'imperial crown'. The OLED display device can meet the requirements of most of the current information age on high performance and large capacity of display equipment, can be used for indoor and outdoor illumination, can be used as wallpaper ornaments, can be made into folded electronic newspapers, and can also be applied to portable electronic products such as mobile phones, tablet computers, wearable electronic equipment and the like.

Since the display device may have substantially the same technical effects as the display panel described in the previous embodiments, the technical effects of the display device are not repeated here for the sake of brevity.

It is to be understood that the terminology used in the description of the embodiments of the disclosure is for the purpose of describing the embodiments only, and is not intended to be limiting of the disclosure. Unless defined otherwise, technical or scientific terms used in the embodiments of the present disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure belongs.

As used in the specification and claims of this application, the terms "first," "second," or "third," and the like, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. "connected" or "coupled" refers to electrical connections.

Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

The word "comprising" or "comprises", and the like, is intended to mean that elements or items that are present in front of "comprising" or "comprising" are included in the word "comprising" or "comprising", and equivalents thereof, without excluding other elements or items.

"upper", "lower", "left" or "right" etc. are only used to indicate relative positional relationships, which may also be changed accordingly when the absolute position of the object to be described is changed.

The foregoing description of the preferred embodiments of the present disclosure is provided for the purpose of illustration only, and is not intended to limit the disclosure to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, alternatives, and alternatives falling within the spirit and principles of the disclosure.

Claims

1. A pixel circuit, the pixel circuit comprising:

2. The pixel circuit according to claim 1, wherein among the plurality of control transistors, an influence of a transistor characteristic of a target transistor on the light emission drive signal is smaller than an influence of transistor characteristics of other transistors than the target transistor on the light emission drive signal;

3. The pixel circuit of claim 1, wherein the P-type transistor and the N-type transistor each comprise: an active layer, a gate metal layer and a source drain metal layer stacked;

4. A pixel circuit according to any one of claims 1 to 3, wherein the reset signal terminal comprises: a first reset signal terminal and a second reset signal terminal; the light emission control terminal includes: a first light emission control end and a second light emission control end; the reset power supply terminal comprises: a first reset power supply terminal and a second reset power supply terminal; the light emission control circuit is used for:

5. The pixel circuit according to claim 4, wherein the plurality of control transistors in the light emission control circuit include: a first reset transistor, a second reset transistor, a data writing transistor, a first light emission control transistor, a second light emission control transistor, and a third reset transistor;

6. A pixel circuit according to any one of claims 1 to 3, wherein the potential adjusting circuit includes: a first capacitor and a second capacitor; the light emission driving circuit includes: the driving transistor;

7. A driving method of a pixel circuit, characterized by being applied to the pixel circuit according to any one of claims 1 to 6; the method comprises the following steps:

8. A display panel, the display panel comprising: a substrate, and a plurality of pixels located at one side of the substrate;

wherein the pixel includes: a light emitting element, and a pixel circuit as claimed in any one of claims 1 to 6, coupled to the light emitting element, for driving the light emitting element to emit light.

9. The display panel of claim 8, wherein the substrate has a display region and a non-display region adjacent to each other, the pixel being located in the display region, the display panel further comprising:

10. A display device, characterized in that the display device comprises: a power supply assembly as claimed in claim 8 or 9;