CN117076349B - High-speed storage method and high-speed storage device for separating data stream from control stream - Google Patents

High-speed storage method and high-speed storage device for separating data stream from control stream Download PDF

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CN117076349B
CN117076349B CN202311323251.9A CN202311323251A CN117076349B CN 117076349 B CN117076349 B CN 117076349B CN 202311323251 A CN202311323251 A CN 202311323251A CN 117076349 B CN117076349 B CN 117076349B
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storage
file system
fpga
storage address
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CN117076349A (en
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刘宇洋
谭德辉
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Hunan Bojiang Information Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/781—On-chip cache; Off-chip memory
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention discloses a high-speed storage method and a high-speed storage device for separating a data stream from a control stream, wherein the high-speed storage device comprises a CPU (Central processing Unit) and an FPGA (field programmable gate array); the FPGA is provided with a first data interface and is connected with a first storage module; the CPU is connected with a second storage module; the CPU comprises an application layer, a file system layer and a device driving layer; the application layer comprises a record management application; the file system layer comprises a file system and a file system monitoring plug-in; the device driving layer comprises an FPGA communication driver and a combined block device driver; the record management application, the FPGA communication driver and the FPGA are sequentially in communication connection; the record management application, the file system and the combined block device driver are sequentially in communication connection with the FPGA; the file system monitoring plug-in is respectively in driving communication connection with the file system and the combined block device; the technical scheme provided by the invention is beneficial to solving the defect that the file storage delay cannot be reduced by utilizing the self file system under the high-speed storage scene.

Description

High-speed storage method and high-speed storage device for separating data stream from control stream
Technical Field
The invention relates to the technical field of high-speed storage, in particular to a high-speed storage device and a high-speed storage method for separating data flow from control flow.
Background
In a high-speed storage scenario, for example, a scenario in which a data recorder performs high-speed storage, a conventional technical solution is to perform data receiving, data storage and a file system under an operating system, so as to provide services such as a network hard disk for the outside. However, in the application scenario where the high-capacity and high-speed writing load occupies most of the application scenarios, for example, the data recorders of facilities such as vehicles, ships, aircrafts, etc., in order to provide more data interfaces, a RAID card is often selected to manage storage, but the RAID card cannot be autonomously controllable at present, if the demand for the high-speed interface becomes more, the conventional CPU cannot meet the abundant data interface demand, and only can be customized by using the FPGA, so the improvement can also be made from the following schemes:
firstly, realizing RAID card function by using domestic FPGA logic; the scheme has the advantages of small change and incapability of meeting rich data interface requirements, and the RAID card of logic realization has poorer performance compared with the RAID card.
Secondly, using the FPGA as a data interface, and placing a data storage and file system on an operating system; compared with the traditional scheme, the scheme has the advantages that the design of the storage part is completely the same, the problem that the data interface is inconvenient to expand is solved, but because the high-speed bandwidth still passes through the operating system, the requirements on the connection interface between the memory (DDR) chip and the FPGA and the CPU are higher, meanwhile, the pressure ratio on the file system is higher, the write amplification influence of the file system and the solid state disk is easily received in the high-speed continuous writing process, the influence is the superimposed influence, and the time delay of the file system and the time delay of the solid state disk can all influence the performance.
Thirdly, the FPGA is used as a data interface, the data storage is not placed in the operating system, but placed in the FPGA, so that the control flow passes through the operating system, and the data flow passes through the FPGA, therefore, the delay of file storage can be effectively reduced due to separation of the control flow and the data flow, but the file system under the operating system cannot be directly used due to separation of the storage and the file system, a simple file system is required to be designed by oneself or the file system of an operating system kernel is transplanted, and meanwhile, software middleware connection is designed so as to use network storage services. When the file system is designed by oneself, the file system needs to be specially designed according to specific situations, has low universality and is far less robust than a mature file system; in the file system designed by oneself, advanced functions such as data recovery and snapshot can not be realized. The workload of the file system for transplanting the kernel of the operating system is large and complex, and it is difficult to achieve complete transplanting, and when the file system needs to be replaced, for example, from ext4 to xfs, the file system needs to be transplanted again, so that the research and development cost is high and the practical effect is difficult to predict.
Therefore, the technical scheme has the following defects: in a high-speed storage scene, the delay of file storage cannot be reduced by utilizing a self file system.
Disclosure of Invention
The invention mainly aims to provide a high-speed storage device and a high-speed storage method for separating data flow from control flow, and aims to solve the defect that the delay of file storage cannot be reduced by utilizing a self file system under a high-speed storage scene.
In order to achieve the above object, the present invention proposes a high-speed storage device including a CPU and an FPGA; the FPGA is provided with a first data interface and is connected with a first storage module; the CPU is connected with a second storage module; the CPU comprises an application layer, a file system layer and a device driving layer;
the application layer comprises a record management application; the file system layer comprises a file system and a file system monitoring plug-in; the device driving layer comprises an FPGA communication driver and a combined block device driver;
the record management application and the FPGA communication drive are sequentially in communication connection with the FPGA; the record management application, the file system and the combined block device driver are sequentially in communication connection with the FPGA; the file system monitoring plug-in is respectively in drive communication connection with the file system and the combined block device; the combined block device driver is in communication connection with the second storage module;
The record management application is used for generating a first file operation request according to data to be stored received by the first data interface connected with the FPGA;
the file system is used for converting the first file operation request into a first block device read-write request;
the file system monitoring plug-in is used for distributing a first storage address for data and a second storage address for metadata according to the read-write request of the first block of equipment;
the combined block device driver is used for remapping the first storage address to the storage address of the first storage module, remapping the second storage address to the storage address of the second storage module, and storing metadata distributed to the second storage address to the second storage module;
the FPGA is used for remapping the first storage address to the storage address of the first storage module and storing the cached data to be stored into the first storage module.
Preferably, the record management application is further configured to:
when the FPGA receives external data through the first data interface, the FPGA is subjected to memory space management through the FPGA communication drive so as to cache the data to be stored in the FPGA.
Preferably, the file system monitoring plug-in is specifically configured to:
after receiving the read-write request of the first block device, judging a file system request type of the read-write request of the first block device in the file system, distributing a storage address according to the file request type, and sending the distributed storage address to the combined block device driver, wherein when the file system request type is data, the file system monitoring plug-in distributes a first storage address, and when the file system request type is metadata, the file system monitoring plug-in distributes a second storage address.
Preferably, the CPU is provided with a second data interface;
the record management application is further for: judging whether a receiving interface of data to be stored is the first data interface or the second data interface, and generating a second file operation request when the receiving interface of the data to be stored is the second data interface;
the file system is used for converting the second file operation request into a second block device read-write request;
the file system monitoring plug-in is used for distributing a third storage address for data and a fourth storage address for metadata according to the read-write request of the second block device;
The combined block device driver is used for remapping the third storage address to the storage address of the first storage module, remapping the fourth storage address to the storage address of the second storage module, and storing metadata distributed to the fourth storage address to the second storage module;
the FPGA is used for remapping the third storage address to the storage address of the first storage module and storing the cached data to be stored into the first storage module.
Preferably, the file system monitoring plug-in is applicable to various file systems, and the file system monitoring plug-in is further used for:
acquiring data organization logic, a data distribution strategy and a data structure from a block device read-write request, wherein the block device read-write request comprises a first block device read-write request and a second block device read-write request;
and obtaining a file system type corresponding to the read-write request of the block equipment and a data type corresponding to the file system type according to the data organization logic, the data distribution strategy and the data structure, wherein the data type comprises metadata and data.
In addition, in order to achieve the above object, the present invention further provides a high-speed storage method for separating a data stream from a control stream, which is applied to the high-speed storage device, and the method includes:
The record management application generates a first file operation request according to data to be stored received by the first data interface connected with the FPGA;
the file system converts the first file operation request into a first block of equipment read-write request;
the file system monitoring plug-in allocates a first storage address for data and a second storage address for metadata according to the read-write request of the first block of equipment;
the combined block device driver remaps the first storage address to a storage address of a first storage module, remaps the second storage address to a storage address of a second storage module, and stores metadata allocated to the second storage address to the second storage module;
and the FPGA remaps the first storage address to the storage address of the first storage module, and stores the cached data to be stored into the first storage module.
Preferably, the CPU is provided with a second data interface;
the method further comprises the steps of:
the record management application judges whether a receiving interface of the data to be stored is the first data interface or the second data interface, and generates a second file operation request when the receiving interface of the data to be stored is the second data interface;
The file system converts the second file operation request into a second block device read-write request;
the file system monitoring plug-in allocates a third storage address for data and a fourth storage address for metadata according to the read-write request of the second block device;
the combined block device driver remaps the third storage address to the storage address of the first storage module, remaps the fourth storage address to the storage address of the second storage module, and stores metadata allocated to the fourth storage address to the second storage module;
and the FPGA remaps the storage address of the first storage module according to the third storage address, and stores the cached data to be stored into the first storage module.
Preferably, the file system monitoring plug-in is applicable to multiple file systems, and the method further comprises:
the file system monitoring plug-in acquires data organization logic, a data distribution strategy and a data structure from a block device read-write request, wherein the block device read-write request comprises a first block device read-write request and a second block device read-write request;
and obtaining a file system type corresponding to the read-write request of the block equipment and a data type corresponding to the file system type according to the data organization logic, the data distribution strategy and the data structure, wherein the data type comprises metadata and data.
Preferably, the method further comprises:
generating a rapid storage address sequence table through the file system monitoring plug-in, and sending the rapid storage address sequence table to the FPGA through the combined block equipment drive;
detecting the occupation of a memory space in the FPGA and the transmission rate of a first data interface;
judging whether the memory space occupation and the transmission rate trigger a quick storage instruction or not, and determining the acting period of the quick storage instruction;
and storing the data to be stored received by the FPGA in the action period in a first storage module according to an address sequence formed in a rapid storage address sequence table, and feeding back storage address information to the file system monitoring plug-in.
Preferably, the period of action of the fast store instruction is determined in the following manner:
when (when)；
Wherein,represents the instant i>For i time FPGA used memory space, +.>For the set memory space occupation threshold value, +.>Less than the memory space capacity; />The transmission rate of the first data interface at the moment i; />The storage time length from the moment of starting storage to the moment i; />Is a preset rate, is a constant, +.>The method comprises the steps of carrying out a first treatment on the surface of the For fast storing instructionsIs a period of action start time;
；
；
；
When (when)；
Then；
Wherein,for the used memory space of the FPGA at the moment j, the moment j is later than +.>Time of day (I)>For j+1 time FPGA used memory space, </i >>For j+2 time FPGA used memory space, </i >>The used memory space of the FPGA at the moment j+3; />For the increment of the used memory space of the FPGA at the moment j+1 compared with the moment j,/for the FPGA at the moment j>The increment of the used memory space of the FPGA is shown as j+2 compared with j+1, and the increment is shown as +.>The increment of the used memory space of the FPGA is the increment of j+3 time compared with the increment of j+2 time; />For the transmission rate average value of the first data interface from the moment j to the moment j+3,/for the moment j>The storage time length from the moment of starting storage to the moment of j is set;
；
wherein,for the transmission rate of the first data interface corresponding to time j,/for the time j>For the transmission rate of the first data interface corresponding to time j+1, < >>For the transmission rate of the first data interface corresponding to time j+2, < >>The transmission rate of the first data interface corresponding to the j+3 moment;
end time of active period for fast store instruction, < >>Represents the moment j+3;
each storage area in the rapid storage address sequence table is generated by adopting the following mode:
；
wherein,the size of the storage space occupied by the data stored in the y-th storage area in the rapid storage address sequence table is k, which is the number of data buffered in the memory space, +. >，/>For the occupied storage space size of the buffered kth data in memory space,/for the buffered kth data>Floating parameters for a predetermined memory space experience, < >>；
And taking the next address of the storage address end point of the y-1 storage area as a storage address starting point, determining the size of a storage space by using the size of the storage space occupied by the data stored in the y storage area in the rapid storage address sequence table, and determining the y storage area in the rapid storage address sequence table.
The technical scheme of the invention designs an application layer, a file system layer and a device driving layer of the CPU so that the data stream is managed by the FPGA and the control stream is managed by the CPU on the premise of applying the original file system of the CPU, thereby realizing the separation of the data stream and the control stream. Specifically, after the first data interface of the FPGA receives the high-speed data, the record management application of the CPU starts the control flow at the end of the CPU, specifically: when the first data interface connected with the FPGA receives data to be stored, the record management application of the CPU generates a first file operation request, the first file operation request is converted into a first block equipment read-write request through a file system of the CPU, and the file system monitoring plug-in is used for distributing a first storage address for the data and a second storage address for the metadata according to the first block equipment read-write request; the combined block device driver of the CPU remaps the first storage address to the storage address of the first storage module and returns the first storage address to the FPGA so that the FPGA remaps the first storage address to the storage address of the first storage module according to the first storage address, the data to be stored is stored in the first storage module connected with the PFGA, and the combined block device driver of the CPU also remaps the first storage address to the storage address of the second storage module according to the second storage address, and the metadata is stored in the second storage module connected with the CPU. Compared with the high-speed data stream, the metadata occupies very small space, so that when the metadata is managed and stored by the CPU, the metadata occupies very small performance of the CPU, and the high-speed data occupying large storage space is controlled and stored by the FPGA in the whole course without passing through the CPU, so that compared with the mode of adopting the CPU to manage the control stream and the high-speed data stream at the same time, the occupation condition of the CPU is greatly reduced; therefore, the write-in delay phenomenon caused by the condition that the metadata and the high-speed data are simultaneously managed and stored by the CPU is avoided;
Furthermore, the technical scheme of the invention ensures that the whole control process is still finished through the file system of the CPU operating system, a new file system is not required to be designed by self, and an operating system at the side of the CPU is not required to be transplanted, so that the control of running away the CPU can be realized by directly utilizing a mature operating system, and the data is running away the FPGA.
Therefore, the method and the device are beneficial to solving the defect that the file storage delay cannot be reduced by utilizing the self file system under the high-speed storage scene.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a functional block diagram of one embodiment of a high-speed memory device of the present invention;
FIG. 2 is a flow chart of an embodiment of a method for high-speed storage with data stream and control stream separation according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The description as it relates to "first", "second", etc. in the present invention is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In addition, the technical solutions of the embodiments of the present invention may be combined with each other, but it is necessary to be based on the fact that those skilled in the art can implement the technical solutions, and when the technical solutions are contradictory or cannot be implemented, the combination of the technical solutions should be considered as not existing, and not falling within the scope of protection claimed by the present invention.
Referring to fig. 1 to 2, in order to achieve the above objective, the present invention provides a high-speed memory device, including a CPU and an FPGA; the FPGA is provided with a first data interface and is connected with a first storage module; the CPU is connected with a second storage module; the CPU comprises an application layer, a file system layer and a device driving layer;
the application layer comprises a record management application; the file system layer comprises a file system and a file system monitoring plug-in; the device driving layer comprises an FPGA communication driver and a combined block device driver;
the record management application and the FPGA communication drive are sequentially in communication connection with the FPGA; the record management application, the file system and the combined block device driver are sequentially in communication connection with the FPGA; the file system monitoring plug-in is respectively in drive communication connection with the file system and the combined block device; the combined block device driver is in communication connection with the second storage module;
the record management application is used for generating a first file operation request according to data to be stored received by the first data interface connected with the FPGA;
the file system is used for converting the first file operation request into a first block device read-write request;
The file system monitoring plug-in is used for distributing a first storage address for data and a second storage address for metadata according to the read-write request of the first block of equipment;
the combined block device driver is used for remapping the first storage address to the storage address of the first storage module, remapping the second storage address to the storage address of the second storage module, and storing metadata distributed to the second storage address to the second storage module;
the FPGA is used for remapping the first storage address to the storage address of the first storage module and storing the cached data to be stored into the first storage module.
The technical scheme of the invention designs an application layer, a file system layer and a device driving layer of the CPU so that the data stream is managed by the FPGA and the control stream is managed by the CPU on the premise of applying the original file system of the CPU, thereby realizing the separation of the data stream and the control stream. Specifically, after the first data interface of the FPGA receives the high-speed data, the record management application of the CPU starts the control flow at the end of the CPU, specifically: when the first data interface connected with the FPGA receives data to be stored, the record management application of the CPU generates a first file operation request, the first file operation request is converted into a first block equipment read-write request through a file system of the CPU, and the file system monitoring plug-in is used for distributing a first storage address for the data and a second storage address for the metadata according to the first block equipment read-write request; the combined block device driver of the CPU remaps the first storage address to the storage address of the first storage module and returns the first storage address to the FPGA so that the FPGA remaps the first storage address to the storage address of the first storage module according to the first storage address, the data to be stored is stored in the first storage module connected with the PFGA, and the combined block device driver of the CPU also remaps the first storage address to the storage address of the second storage module according to the second storage address, and the metadata is stored in the second storage module connected with the CPU. Compared with the high-speed data stream, the metadata occupies very small space, so that when the metadata is managed and stored by the CPU, the metadata occupies very small performance of the CPU, and the high-speed data occupying large storage space is controlled and stored by the FPGA in the whole course without passing through the CPU, so that compared with the mode of adopting the CPU to manage the control stream and the high-speed data stream at the same time, the occupation condition of the CPU is greatly reduced; therefore, the write-in delay phenomenon caused by the condition that the metadata and the high-speed data are simultaneously managed and stored by the CPU is avoided;
Furthermore, the technical scheme of the invention ensures that the whole control process is still finished through the file system of the CPU operating system, a new file system is not required to be designed by self, and an operating system at the side of the CPU is not required to be transplanted, so that the control of running away the CPU can be realized by directly utilizing a mature operating system, and the data is running away the FPGA.
Therefore, the method and the device are beneficial to solving the defect that the file storage delay cannot be reduced by utilizing the self file system under the high-speed storage scene.
The recording management application plays a role of a control signal initiator in the whole process. Is responsible for managing external data and performing file operations on the data.
And the FPGA is used for communication driving, so that the record management application and the FPGA are communicated.
The file system monitoring plug-in is responsible for monitoring file system read-write requests, distinguishing whether the requests are metadata or data, and transmitting the information to the combined block device driver for analysis.
The file system can be various self-contained file systems in the linux kernel, and is used in a normal manner without modification.
A combined block device driver for receiving requests from the file system, and making different treatments according to data type (data type is metadata or data): if the metadata is the metadata, after remapping, the metadata is written into the corresponding position of the second storage module; if the data is the data, the file request is sent to the FPGA, and the FPGA writes the data into the first storage module.
The FPGA is used for receiving external data into the memory and storing the data into the first storage module according to a data read-write request sent by the CPU.
The first storage module can be a high-capacity solid-state storage array, is a physical storage medium used for independently storing data, and is controlled by the FPGA to read and write the high-capacity solid-state storage array.
The second storage module is a physical storage medium for separately storing metadata, and may be a storage disk managed by an operating system according to its size. The second storage module has low actual read-write bandwidth and small data volume, and does not need to use an independent storage medium, so the second storage module can be an independent partition in the existing storage medium under the operating system, and can also use a file in the operating system, thereby effectively saving the storage cost, and in addition, the independent metadata storage module can be subjected to high-reliability design backup.
Preferably, the record management application is further configured to: when the FPGA receives external data through the first data interface, the FPGA is subjected to memory space management through the FPGA communication drive so as to cache the data to be stored in the FPGA.
At this time, the FPGA communication driver is a driver for the record management application to manage the cache on the FPGA.
Specifically, after the FPGA receives the high-speed data through the first data interface, the record management application initiates two management operations:
the first aspect is to control the FPGA to cache the high-speed data in the memory module of the FPGA.
The second aspect is that the record management application starts a file system, a file system monitoring plug-in unit, an FPGA communication driver and a combined block device driver, a storage address is allocated to the cached data to be stored in the first storage module, the cached data to be stored is controlled to be stored in the first storage module through the FPGA, a storage address is allocated to the metadata in the second storage module, and the metadata is controlled to be stored in the second storage module through the CPU.
The memory capacity of the FPGA is relatively small, and may be only a few G, so in the scenario of high-speed continuous storage, the memory of the FPGA will be full in a short time, resulting in that subsequent high-speed data cannot be cached, and thus data loss is caused. Therefore, if the data storage of the high-speed data and the file system are both placed in the operating system, the write-in amplification phenomenon of the file system and the solid state disk is caused, the delay of the file system and the delay of the solid state disk are caused, and the data is easy to lose, so that the high-speed storage performance is obviously affected. According to the invention, only metadata occupying small CPU resources and control information of the FPGA are stored in the CPU, and file system delay and solid state disk write-in amplification are avoided, so that the storage response speed is faster, the high-speed data cached in the FPGA can be stored in the first storage module rapidly, and the high-speed data loss caused by insufficient memory capacity is avoided.
The high-speed storage device may be a data recorder, for example, a data recorder applied to facilities such as vehicles, ships, airplanes, and the like. The first data interface provided by the FPGA may be plural.
The invention aims to provide a technical scheme of a data recorder under a high-speed continuous writing scene, which can combine the advantages of various schemes, better solve the problems of multi-path high-speed data interface access, high-performance high-bandwidth recording, provide stable and reliable file management by using a mature file system, and simultaneously can conveniently provide various network storage services of a standard operating system under the condition of no loss of performance.
In the invention, the metadata and the data are respectively stored in independent storage, and the remapping function is that the addresses of the metadata and the data on the disk in the original file system are not overlapped with each other, and a great amount of space is wasted when the requests are directly stored in the corresponding addresses, so that the metadata and the data are concentrated by remapping, and the capacity requirement on the metadata storage disk is greatly reduced. The operation changes the storage of the metadata and the data into independent asynchronous operation, effectively reduces the time delay of file operation, and simultaneously decouples fragments generated on the solid state disk by the metadata and the data respectively, so that the write-in amplification on the independent storage media can be further reduced.
Preferably, the file system monitoring plug-in is specifically configured to:
after receiving the read-write request of the first block device, judging a file system request type of the read-write request of the first block device in the file system, distributing a storage address according to the file request type, and sending the distributed storage address to the combined block device driver, wherein when the file system request type is data, the file system monitoring plug-in distributes a first storage address, and when the file system request type is metadata, the file system monitoring plug-in distributes a second storage address.
In particular, the file system monitoring plug-in also has a compressed storage function to avoid data and metadata scatter storage. In the present invention, the first storage module and the second storage module are mapped to one complete storage medium, and the mapped complete storage medium is partitioned to avoid scatter storage, for example, the mapped complete storage medium is partitioned according to a set storage address, a storage area higher than the storage address is used for storing one of data and metadata, and a storage area lower than the storage address is used for storing the other of data and metadata. Thus, partitioned storage of data and metadata is achieved. Therefore, when the file system request type is data, the file system monitoring plug-in allocates a first storage address from one of the storage areas for storing the data (the storage area storing the data corresponds to the first storage medium); when the file system request type is metadata, the file system monitoring plug-in allocates a second storage address from another storage area for storing metadata (the storage area storing metadata corresponds to a second storage medium).
In a preferred embodiment, the CPU is provided with a second data interface; the first data interface is a high-speed data interface, and the second data interface is a low-speed data interface;
the record management application is further for: judging whether a receiving interface of data to be stored is the first data interface or the second data interface, and generating a second file operation request when the receiving interface of the data to be stored is the second data interface;
the file system is used for converting the second file operation request into a second block device read-write request;
the file system monitoring plug-in is used for distributing a third storage address for data and a fourth storage address for metadata according to the read-write request of the second block device;
the combined block device driver is used for remapping the third storage address to the storage address of the first storage module, remapping the fourth storage address to the storage address of the second storage module, and storing metadata distributed to the fourth storage address to the second storage module;
the FPGA is used for remapping the third storage address to the storage address of the first storage module and storing the cached data to be stored into the first storage module.
Specifically, in the invention, a first data interface is set in the FPGA as a high-speed data interface, and the high-speed data is managed and cached by a CPU and stored in the FPGA; and the second data interface is set as a low-speed data interface in the CPU, and the data received by the low-speed data interface is stored in the first storage module connected with the FPGA and the metadata is stored in the second storage module connected with the CPU in the same processing mode of the high-speed data under the management of the CPU. Therefore, the invention can realize the receiving of the high-speed data and the low-speed data at the same time, and the high-speed data is received by the FPGA, the low-speed data is received by the CPU, and the high-speed data and the low-speed data adopt different receiving paths, which has the advantages that: the high-speed data is usually big data, the low-speed data is usually small data, fragments are easy to generate on a storage medium when the big data and the small data are stored in a mixed mode, garbage collection is required to be frequently performed when fragments are frequently generated, CPU (central processing unit) expenses are frequently generated in the process of frequent garbage collection, and therefore the response speed of the high-speed storage device is slowed down. When the high-speed data, namely the big data and the low-speed data, are stored separately, the storage of the same magnitude data on each side is realized, the high-speed data and the low-speed data can be further stored in different storage sections of the first storage module, and metadata corresponding to the high-speed data and the low-speed data are also stored in different storage sections of the second storage module, so that the reduction of data storage fragments and the reduction of garbage recycling frequency are facilitated, the CPU overhead generated by the garbage recycling frequency is reduced, and the improvement of storage response performance is facilitated.
The combined block device driver is configured to remap a storage address allocated by the file system monitoring plug-in for the data store to a real storage address of the first storage module and to remap a storage address allocated by the file system monitoring plug-in for the metadata store to a real storage address of the second storage module.
Further, the file system monitoring plug-in is applicable to various file systems, and the file system monitoring plug-in is further used for:
acquiring data organization logic, a data distribution strategy and a data structure from a block device read-write request, wherein the block device read-write request comprises a first block device read-write request and a second block device read-write request;
and obtaining a file system type corresponding to the read-write request of the block equipment and a data type corresponding to the file system type according to the data organization logic, the data distribution strategy and the data structure, wherein the data type comprises metadata and data.
Specifically, the file system monitoring plug-in the invention can manage data type identification of various file systems at the same time, for example, a file system suitable for a Windows operating system or a file system suitable for a Linux operating system. A plurality of data type identification units can be arranged in the file system monitoring plug-in, and each data type identification unit identifies the data type of one file system, so that the high-speed storage device can be suitable for the file systems of different operating systems.
Furthermore, the file system monitoring plug-in can be set as a public module, a plurality of CPUs provided with different file systems are respectively in communication connection with the file system monitoring plug-in, specifically, the file system and the combined block device driver of each CPU are respectively in communication connection with the file system monitoring plug-in, so that the high-speed storage device can simultaneously identify data and metadata under various file systems, store the data into the first storage module connected with the FPGA, and store the metadata into the second storage module connected with the CPU.
At this time, the number of FPGAs in the high-speed storage device may be not limited to one but may be extended to a plurality.
Referring to fig. 1, in order to achieve the above objective, the present invention further provides a high-speed storage method for separating a data stream from a control stream, which is applied to the high-speed storage device, and the method includes:
step S10, the record management application generates a first file operation request according to data to be stored received by the first data interface connected with the FPGA;
step S20, the file system converts the first file operation request into a first block device read-write request;
step S30, the file system monitoring plug-in allocates a first storage address for data and a second storage address for metadata according to the read-write request of the first block of equipment;
Step S40, the combined block device driver remaps the first storage address to the storage address of the first storage module, remaps the second storage address to the storage address of the second storage module, and stores metadata allocated to the second storage address to the second storage module;
and step S50, the FPGA remaps the storage address of the first storage module according to the first storage address, and stores the cached data to be stored into the first storage module.
The method can realize the same functions and the same beneficial effects of the high-speed storage device, and is not described herein.
In a second embodiment of the present invention, based on the first embodiment of the present invention, the CPU is provided with a second data interface; the first data interface is a high-speed data interface, and the second data interface is a low-speed data interface;
the method further comprises the steps of:
step S60, the record management application judges whether a receiving interface of the data to be stored is the first data interface or the second data interface, and generates a second file operation request when the receiving interface of the data to be stored is the second data interface;
step S70, the file system converts the second file operation request into a second block device read-write request;
Step S80, the file system monitoring plug-in allocates a third storage address for data and a fourth storage address for metadata according to the read-write request of the second block device;
step S90, the combined block device driver remaps the third storage address to the storage address of the first storage module, remaps the fourth storage address to the storage address of the second storage module, and stores metadata allocated to the fourth storage address to the second storage module;
and step S100, the FPGA remaps the storage address of the first storage module according to the third storage address, and stores the cached data to be stored into the first storage module.
Based on the second embodiment of the present invention, the file system monitoring plug-in the third embodiment of the present invention is applicable to a plurality of file systems, and the method further includes:
step S110, the file system monitoring plug-in acquires data organization logic, a data distribution strategy and a data structure from a read-write request of block equipment, wherein the read-write request of the block equipment comprises a read-write request of a first block equipment and a read-write request of a second block equipment;
step S120, according to the data organization logic, the data distribution strategy and the data structure, obtaining the file system type corresponding to the read-write request of the block device and the data type corresponding to the file system type, wherein the data type comprises metadata and data.
In a fourth embodiment of the present invention, based on the first to third embodiments of the present invention, the method further includes:
step S130, generating a rapid storage address sequence table through the file system monitoring plug-in, and sending the rapid storage address sequence table to the FPGA through the combined block device driver;
step S140, detecting the occupation of the memory space in the FPGA and the transmission rate of the first data interface;
step S150, judging whether the memory space occupation and the transmission rate trigger a quick storage instruction or not, and determining the acting period of the quick storage instruction;
and step 160, storing the data to be stored received by the FPGA in the action period in a first storage module according to an address sequence formed in a rapid storage address sequence table, and feeding back storage address information to the file system monitoring plug-in.
Specifically, the storage addresses in the first storage module are ordered according to the sequence from front to back, and when the file system monitoring plug-in allocates the first storage addresses, the data to be stored are allocated to the first storage addresses according to the sequence from front to back of the storage addresses according to the sequence to be stored of the high-speed data.
And distributing the data to be stored with the storage addresses according to the rapid storage address sequence table, and storing the data according to the sequence from back to front of the storage addresses. The file system monitoring plug-in sequentially distributes all storage areas in the rapid storage address sequence table to all data to be stored, wherein the storage areas are reserved for the data to be stored, the storage addresses of all the storage areas are not overlapped, and the file system monitoring plug-in sequentially distributes all the storage areas in the rapid storage address sequence table to all the data to be stored, wherein the data to be stored are at risk of data loss.
The FPGA detects the occupation of the memory space and the transmission rate of the first data interface, predicts whether the memory space is possibly full according to the occupation of the memory space and the transmission rate of the first data interface, if so, predicts that the memory space has data loss risk, triggers the quick storage instruction when the data loss risk exists, and determines the time period with the data loss risk as the acting time period of the quick storage instruction;
and storing the data to be stored received by the FPGA in the action period from back to front in the storage address of the first storage module according to an address sequence formed in the rapid storage address sequence table, and feeding back the storage address information to the file system monitoring plug-in.
The technical scheme has the advantages that: the normal stored high-speed data is stored in the front end address of the first storage module, and the data which can be lost is stored in the tail end address of the first storage module, so that the normal stored high-speed data can be stored in sequence, and scattered storage space and excessive occupied storage space caused by scattered storage are avoided; meanwhile, the data which can be lost can be directly stored to the tail end address of the first storage module according to the rapid storage address sequence table to rapidly release the occupied memory space when the memory space cannot be emptied in time, so that a series of analysis and forwarding of modules such as a record management application, a file system monitoring plug-in unit, a combined block device driver and the like are not needed when the memory space is insufficient, the storage efficiency is improved, and the risk of data loss is reduced;
and the data stored at the tail end of the first storage module is strictly distinguished from the data stored at the front end of the first storage module according to whether the storage address is positioned at the front end or the tail end, so that the high-speed storage device can easily distinguish normally stored data, and the data which is rapidly stored by utilizing the rapid storage address sequence table is convenient for identifying the storage time and the occupied storage space of the data which is rapidly stored by utilizing the rapid storage address sequence table, thereby analyzing whether the FPGA memory is matched with the high-speed data transmission rate or not and adjusting the size of the FPGA memory.
Meanwhile, when the high-speed storage device is idle, the data stored at the tail end of the first storage module can be migrated to the front end of the first storage module, so that convenience in data migration is realized, and the tail end storage address of the first storage module can be conveniently emptied.
Furthermore, when the fast memory address sequence table is formed, an empirical floating parameter can be added, so that more sufficient memory space is reserved for the easy-to-lose high-speed data, namely, redundant memory space can be reserved between each easy-to-lose high-speed data, and therefore, when defragmentation is performed, defragmentation and memory space recovery can be performed specifically for the terminal memory address of the first memory module.
Specifically, the period of action of the fast store instruction is determined as follows:
when (when)And->When (I)>；
Wherein,represents the instant i>For i time FPGA used memory space, +.>For the set memory space occupation threshold value, +.>Less than the memory space capacity; />The transmission rate of the first data interface at the moment i; />The storage time length from the moment of starting storage to the moment i; />Is a preset rate, is a constant, +.>；/>A time period start time of action for the fast store instruction;
；
；
；
When (when)And->；
Then；
Wherein,for the used memory space of the FPGA at the moment j, the moment j is later than +.>Time of day (I)>For j+1 time FPGA used memory space, </i >>For j+2 time FPGA used memory space, </i >>The used memory space of the FPGA at the moment j+3; />For the increment of the used memory space of the FPGA at the moment j+1 compared with the moment j,/for the FPGA at the moment j>The increment of the used memory space of the FPGA is shown as j+2 compared with j+1, and the increment is shown as +.>The increment of the used memory space of the FPGA is the increment of j+3 time compared with the increment of j+2 time; />For the transmission rate average value of the first data interface from the moment j to the moment j+3,/for the moment j>The storage time length from the moment of starting storage to the moment of j is set;
；
wherein,for the transmission rate of the first data interface corresponding to time j,/for the time j>For the transmission rate of the first data interface corresponding to time j+1, < >>For the transmission rate of the first data interface corresponding to time j+2, < >>The transmission rate of the first data interface corresponding to the j+3 moment; />
End time of active period for fast store instruction, < >>Represents the moment j+3;
each storage area in the rapid storage address sequence table is generated by adopting the following mode:
；
wherein,the size of the storage space occupied by the data stored in the y-th storage area in the rapid storage address sequence table is k, which is the number of data buffered in the memory space, +. >，/>For the occupied storage space size of the buffered kth data in memory space,/for the buffered kth data>Floating parameters for a predetermined memory space experience, < >>；
And taking the next address of the storage address end point of the y-1 storage area as a storage address starting point, determining the size of a storage space by using the size of the storage space occupied by the data stored in the y storage area in the rapid storage address sequence table, and determining the y storage area in the rapid storage address sequence table.
The invention designs a special combined block device driver, the module can respectively store metadata and data on different storage media connected with a CPU and an FPGA by remapping read-write requests generated by a file system, the storage media do not limit positions, and the storage media are very suitable for discrete management, so that the file system is prevented from being changed in a third scheme in the background technology, the research and development efficiency is improved, and the development time is saved.
In addition, the invention designs a file system monitoring plug-in which can analyze the read-write request of the file system, and the plug-in content of different file systems is different and is suitable for various file systems, so the file system monitoring plug-in is used as an independent module, and the development cost brought by replacing the file system can be reduced as much as possible.
Furthermore, the metadata and the data of the file system adopt an asynchronous operation mode, and the operations of the metadata and the data are not mutually interfered and blocked, and compared with the traditional mode, the asynchronous mode can more easily cope with the write-in performance fluctuation caused by the solid state disk.
The foregoing description of the preferred embodiments of the present invention should not be construed as limiting the scope of the invention, but rather utilizing equivalent structural changes made in the present invention description and drawings or directly/indirectly applied to other related technical fields are included in the scope of the present invention.

Claims (10)

1. The high-speed storage device is characterized by comprising a CPU and an FPGA; the FPGA is provided with a first data interface and is connected with a first storage module; the CPU is connected with a second storage module; the CPU comprises an application layer, a file system layer and a device driving layer;
the application layer comprises a record management application; the file system layer comprises a file system and a file system monitoring plug-in; the device driving layer comprises an FPGA communication driver and a combined block device driver;
the record management application and the FPGA communication drive are sequentially in communication connection with the FPGA; the record management application, the file system and the combined block device driver are sequentially in communication connection with the FPGA; the file system monitoring plug-in is respectively in drive communication connection with the file system and the combined block device; the combined block device driver is in communication connection with the second storage module;
The record management application is used for generating a first file operation request according to data to be stored received by the first data interface connected with the FPGA;
the file system is used for converting the first file operation request into a first block device read-write request;
the file system monitoring plug-in is used for distributing a first storage address for data and a second storage address for metadata according to the read-write request of the first block of equipment;
the combined block device driver is used for remapping the first storage address to the storage address of the first storage module, remapping the second storage address to the storage address of the second storage module, and storing metadata distributed to the second storage address to the second storage module;
the FPGA is used for remapping the first storage address to the storage address of the first storage module and storing the cached data to be stored into the first storage module.
2. The high-speed storage device of claim 1, wherein the record management application is further to:
when the FPGA receives external data through the first data interface, the FPGA is subjected to memory space management through the FPGA communication drive so as to cache the data to be stored in the FPGA.
3. The high-speed storage device according to claim 1, wherein the file system monitoring plug-in is specifically configured to:
after receiving the read-write request of the first block device, judging a file system request type of the read-write request of the first block device in the file system, distributing a storage address according to the file request type, and sending the distributed storage address to the combined block device driver, wherein when the file system request type is data, the file system monitoring plug-in distributes a first storage address, and when the file system request type is metadata, the file system monitoring plug-in distributes a second storage address.
4. A high-speed storage device according to any one of claims 1 to 3, characterized in that: the CPU is provided with a second data interface;
the record management application is further for: judging whether a receiving interface of data to be stored is the first data interface or the second data interface, and generating a second file operation request when the receiving interface of the data to be stored is the second data interface;
the file system is used for converting the second file operation request into a second block device read-write request;
The file system monitoring plug-in is used for distributing a third storage address for data and a fourth storage address for metadata according to the read-write request of the second block device;
the combined block device driver is used for remapping the third storage address to the storage address of the first storage module, remapping the fourth storage address to the storage address of the second storage module, and storing metadata distributed to the fourth storage address to the second storage module;
the FPGA is used for remapping the third storage address to the storage address of the first storage module and storing the cached data to be stored into the first storage module.
5. The high-speed storage device of claim 4, wherein the file system monitoring plug-in is adapted for use with a plurality of file systems, the file system monitoring plug-in further adapted to:
acquiring data organization logic, a data distribution strategy and a data structure from a block device read-write request, wherein the block device read-write request comprises a first block device read-write request and a second block device read-write request;
and obtaining a file system type corresponding to the read-write request of the block equipment and a data type corresponding to the file system type according to the data organization logic, the data distribution strategy and the data structure, wherein the data type comprises metadata and data.
6. A high-speed storage method of separating a data stream from a control stream, applied to the high-speed storage device of any one of claims 1 to 5, the method comprising:
the record management application generates a first file operation request according to data to be stored received by the first data interface connected with the FPGA;
the file system converts the first file operation request into a first block of equipment read-write request;
the file system monitoring plug-in allocates a first storage address for data and a second storage address for metadata according to the read-write request of the first block of equipment;
the combined block device driver remaps the first storage address to a storage address of a first storage module, remaps the second storage address to a storage address of a second storage module, and stores metadata allocated to the second storage address to the second storage module;
and the FPGA remaps the first storage address to the storage address of the first storage module, and stores the cached data to be stored into the first storage module.
7. The high-speed storage method of separating data stream from control stream according to claim 6, wherein the CPU is provided with a second data interface;
The method further comprises the steps of:
the record management application judges whether a receiving interface of the data to be stored is the first data interface or the second data interface, and generates a second file operation request when the receiving interface of the data to be stored is the second data interface;
the file system converts the second file operation request into a second block device read-write request;
the file system monitoring plug-in allocates a third storage address for data and a fourth storage address for metadata according to the read-write request of the second block device;
the combined block device driver remaps the third storage address to the storage address of the first storage module, remaps the fourth storage address to the storage address of the second storage module, and stores metadata allocated to the fourth storage address to the second storage module;
and the FPGA remaps the storage address of the first storage module according to the third storage address, and stores the cached data to be stored into the first storage module.
8. The method of claim 7, wherein the file system monitoring plug-in is adapted for use with a plurality of file systems, the method further comprising:
The file system monitoring plug-in acquires data organization logic, a data distribution strategy and a data structure from a block device read-write request, wherein the block device read-write request comprises a first block device read-write request and a second block device read-write request;
and obtaining a file system type corresponding to the read-write request of the block equipment and a data type corresponding to the file system type according to the data organization logic, the data distribution strategy and the data structure, wherein the data type comprises metadata and data.
9. A method of high-speed storage of data streams separated from control streams according to any one of claims 6 to 8, characterized in that the method further comprises:
generating a rapid storage address sequence table through the file system monitoring plug-in, and sending the rapid storage address sequence table to the FPGA through the combined block equipment drive;
detecting the occupation of a memory space in the FPGA and the transmission rate of a first data interface;
judging whether the memory space occupation and the transmission rate trigger a quick storage instruction or not, and determining the acting period of the quick storage instruction;
and storing the data to be stored received by the FPGA in the action period in a first storage module according to an address sequence formed in a rapid storage address sequence table, and feeding back storage address information to the file system monitoring plug-in.
10. The method of claim 9, wherein the period of time of action of the fast store instruction is determined by:
when (when)And->When (I)>；
Wherein,represents the instant i>For i time FPGA used memory space, +.>For a set memory space occupation threshold value,less than the memory space capacity; />The transmission rate of the first data interface at the moment i; />The storage time length from the moment of starting storage to the moment i; />Is a preset rate, is a constant, +.>；/>A time period start time of action for the fast store instruction;
；
；
；
when (when)；
Then；
Wherein,for the used memory space of the FPGA at the moment j, the moment j is later than +.>Time of day (I)>For j+1 time FPGA used memory space, </i >>For j+2 time FPGA used memory space, </i >>Time j+3 FPGA is used memory space; />For the increment of the used memory space of the FPGA at the moment j+1 compared with the moment j,/for the FPGA at the moment j>The increment of the used memory space of the FPGA is shown as j+2 compared with j+1, and the increment is shown as +.>The increment of the used memory space of the FPGA is the increment of j+3 time compared with the increment of j+2 time; />For the transmission rate average value of the first data interface from the moment j to the moment j+3,/for the moment j>The storage time length from the moment of starting storage to the moment of j is set;
；
wherein,for the transmission rate of the first data interface corresponding to time j,/for the time j >For the transmission rate of the first data interface corresponding to time j+1, < >>For the transmission rate of the first data interface corresponding to time j+2, < >>The transmission rate of the first data interface corresponding to the j+3 moment;
end time of active period for fast store instruction, < >>Represents the moment j+3;
each storage area in the rapid storage address sequence table is generated by adopting the following mode:
；
wherein,the size of the storage space occupied by the data stored in the y-th storage area in the rapid storage address sequence table is k, which is the number of data buffered in the memory space, +.>，/>For the occupied storage space size of the buffered kth data in memory space,/for the buffered kth data>Floating parameters for a predetermined memory space experience, < >>；
And taking the next address of the storage address end point of the y-1 storage area as a storage address starting point, determining the size of a storage space by using the size of the storage space occupied by the data stored in the y storage area in the rapid storage address sequence table, and determining the y storage area in the rapid storage address sequence table.
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