CN117076228A - Chip testing method and related assembly - Google Patents
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- CN117076228A CN117076228A CN202311118032.7A CN202311118032A CN117076228A CN 117076228 A CN117076228 A CN 117076228A CN 202311118032 A CN202311118032 A CN 202311118032A CN 117076228 A CN117076228 A CN 117076228A
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
- G06F11/2733—Test interface between tester and unit under test
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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Abstract
The application discloses a method for testing a chip and related components, and relates to the field of testing, wherein the method comprises the steps of obtaining port information of network connectors of all layers in the chip, wherein the port information comprises modules connected with uplink ports and downlink ports of the network connectors of all layers; determining a network connection link between the processor and the functional module according to port information of each layer of network connectors; determining a target functional module according to the network connection link, and transmitting excitation to the target functional module; and determining whether the target functional module passes the test according to the value of the excitation output by the target functional module. The processor is connected with each functional module through the multi-layer network connector, a network connection link from the processor to the network connector to each functional module can be formed after the uplink port and the downlink port of the network connector are determined, excitation is sent to the target functional module through the network connection link, whether the chip passes the test is determined according to the value output by the target module, and the test process is simpler.
Description
Technical Field
The present application relates to the field of testing, and in particular, to a method for testing a chip and related components.
Background
The system on a chip includes a processor, an interconnect bus, and functional modules for implementing various functions. The system level verification of the chip is to send a value to the input end of the chip, the sent value is called excitation to the chip, the value output by the functional module of the chip is collected, and whether the chip realizes the correct function is judged according to the value output by the functional module. The processor is connected with the functional modules through the multi-layer network connectors, the first layer network connector is connected with the processor, the last layer network connector is connected with the functional modules, because the connection between the network connectors of all layers in the middle is complex, the address space allocated by each functional module on the chip may need to be changed, the transmitted excitation also changes along with the address of the functional module when the system level verification is carried out, when the address space allocated by the functional module changes, the address can be wrong when accessing the target functional module, and a great amount of time is consumed for compiling simulation when the excitation is revised. Determining the network connection links between the individual network connectors and the functional modules on the chip is important for system level verification of the chip.
Disclosure of Invention
The application aims to provide a chip testing method and related components, wherein after an uplink port and a downlink port of a network connector are determined, a network connection link from a processor to the network connector to each functional module can be formed, excitation can be directly sent to a target functional module through the network connection link, whether a chip passes the test or not is determined according to a value output by the target module, and the testing process is more concise.
In order to solve the above technical problems, the present application provides a method for testing a chip, including:
acquiring port information of each layer of network connector in a chip, wherein the port information comprises a module connected with an uplink port and a downlink port of each layer of network connector, the module comprises a processor in the chip, the network connector and a functional module in the chip, the uplink port of the first layer of network connector is connected with the processor, and the downlink port of the last layer of network connector is connected with the functional module;
determining a network connection link between the processor and the functional module according to port information of each layer of network connectors;
determining a target functional module according to the network connection link, and sending excitation to the target functional module;
and determining whether the target functional module passes the test according to the value of the excitation output by the target functional module.
On the other hand, obtaining port information of each layer of network connectors in the chip includes:
acquiring the identification of each network connector in a chip, the connection relation between an uplink port and a downlink port of the network connector, and the address, the identification, the protocol and the bit width of a module connected with the uplink port and a module connected with the downlink port of the network connector;
and converting the identifiers of the network connectors, the connection relation between the uplink ports and the downlink ports of the network connectors, and the addresses, identifiers, protocols and bit widths of the modules connected with the uplink ports and the modules connected with the downlink ports of the network connectors into data types of dictionaries.
In another aspect, determining a network connection link between the processor and the functional module according to port information of each layer of network connectors includes:
taking a downlink port of the network connector of the first layer as a father node;
determining an uplink port of a network connector of a next layer connected with the father node according to port information of the network connectors of each layer;
adding an uplink port of the network connector of the next layer connected with the father node as a child node to a network connection link;
updating the downlink port of the network connector corresponding to the child node into a parent node, and determining whether an uplink port of the network connector connected with the updated parent node exists or not according to the port information of the network connectors of each layer;
if the uplink port of the network connector connected with the updated father node exists, entering a step of adding the uplink port of the network connector of the next layer connected with the father node as a child node to a network connection link;
if the uplink port of the network connector connected with the updated father node does not exist, determining that the network connector is the network connector of the last layer, and taking the path from the network connector of the first layer connected with the processor to the network connector of the last layer as the network connection link.
On the other hand, determining a target functional module according to the network connection link, and sending an incentive to the target functional module, including:
determining a starting address and a terminating address of a target functional module according to addresses of a module connected with an uplink port and a module connected with a downlink port of the network connector;
and determining a target functional module according to the network connection link, and sending excitation to a target address range of the target functional module so as to realize read-write operation of the target address range.
On the other hand, determining a target functional module according to the network connection link, and sending an incentive to the target functional module, including:
determining a value of expected output of the target functional module corresponding to excitation set according to actual requirements;
determining the value actually output by the target functional module;
and when the expected output value is the same as the actual output value, determining that the target functional module passes the test.
On the other hand, when the network connector is provided with m uplink ports and n downlink ports, and the port information comprises a types, the port information is a+n rows by a+m columns, and m, n and a are positive integers;
after obtaining the port information of each layer of network connector in the chip, the method further comprises the following steps:
extracting data from a+1st row to a+n th row, wherein the port information comprises a connection relation between an uplink port and a downlink port of the network connector, and an address, an identifier, a protocol, a clock domain and a bit width of a module connected with the uplink port or the downlink port of the network connector;
extracting data of a+1th column to a+m column;
the data of the a+1th column to the a+m column are subjected to column-row exchange;
determining a network connection link between the network connector and the functional module in the chip according to the identification of the uplink port and the downlink port of the network connector connected with the module, including:
and determining a network connection link between the network connector and the functional module in the chip according to the data from the a+1 row to the a+n row and the data from the a+1 column to the a+m column after row-column exchange.
In order to solve the technical problem, the application also provides a system for testing a chip, which comprises:
the port information acquisition unit is used for acquiring port information of each layer of network connector in the chip, wherein the port information comprises modules connected with an uplink port and a downlink port of each layer of network connector, the modules comprise a processor in the chip, the network connector and a functional module in the chip, the uplink port of the first layer of network connector is connected with the processor, and the downlink port of the last layer of network connector is connected with the functional module;
a network connection link determining unit, configured to determine a network connection link between the processor and the functional module according to port information of each layer of network connectors;
the target function module determining unit is used for determining a target function module according to the network connection link and sending excitation to the target function module;
and the test unit is used for determining whether the target functional module passes the test according to the target functional module and the value of the excitation output.
In order to solve the technical problem, the application also provides a device for testing a chip, which comprises:
a memory for storing a computer program;
and the processor is used for realizing the steps of the method for testing the chip when executing the computer program.
In order to solve the technical problems, the application also provides a chip, which comprises the device for testing the chip.
To solve the above technical problem, the present application further provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements the steps of the method for chip testing described above.
The application provides a method for testing a chip and a related component, relating to the field of testing, comprising the steps of obtaining port information of network connectors of each layer in the chip, wherein the port information comprises a module connected with an uplink port and a downlink port of the network connectors of each layer; determining a network connection link between the processor and the functional module according to port information of each layer of network connectors; determining a target functional module according to the network connection link, and transmitting excitation to the target functional module; and determining whether the target functional module passes the test according to the value of the excitation output by the target functional module. The processor is connected with each functional module through the multi-layer network connector, a network connection link from the processor to the network connector to each functional module can be formed after the uplink port and the downlink port of the network connector are determined, excitation can be directly sent to the target functional module through the network connection link, whether the chip passes the test or not is further determined according to the value output by the target functional module, and the test process is more concise.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the prior art and the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for testing a chip according to the present application;
FIG. 2 is a diagram showing a distribution of port information according to the present application;
FIG. 3 is a diagram showing another port information distribution diagram according to the present application;
FIG. 4 is a schematic diagram of a system for testing chips according to the present application;
fig. 5 is a schematic structural diagram of a device for testing chips according to the present application.
Detailed Description
The core of the application is to provide a chip testing method and related components, after the uplink port and the downlink port of the network connector are determined, a network connection link from the processor to the network connector to each functional module can be formed, and excitation can be directly sent to a target functional module through the network connection link, so that whether the chip passes the test or not is determined according to the value output by the target module, and the testing process is more concise.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Fig. 1 is a flowchart of a method for testing a chip according to the present application, where the method for testing a chip includes:
s11: the method comprises the steps that port information of each layer of network connectors in a chip is obtained, the port information comprises a module connected with an uplink port and a downlink port of each layer of network connectors, the module comprises a processor in the chip, the network connectors and a functional module in the chip, the uplink port of a first layer of network connectors is connected with the processor, and the downlink port of a last layer of network connectors is connected with the functional module;
a multi-layer network connector is arranged between the processor and the functional module, taking three layers of network connectors as an example, an uplink port of the first layer of network connector is connected with the processor, a downlink port of the first layer of network connector is connected with an uplink port of the second layer of network connector, a downlink port of the second layer of network connector is connected with an uplink port of the third layer of network connector, a downlink port of the third layer of network connector is connected with the functional module, and the functional module can be a flash memory and other functional modules. Considering that the connection between the upstream port and the downstream port between the multi-layer network connectors is complex, and when the address space allocated by the functional module is changed, the address is changed back to be wrong when the target functional module is accessed, so that the test on the chip in the related technology is complex.
The port information of each network connector is predetermined, the network connector can be a first layer network connector, a last layer network connector or an intermediate layer network connector, so that the module connected with the network connector can be a processor in a chip, other network connectors or a functional module in the chip, and the uplink port and the downlink port of each network connector are determined to be connected with which module, so that the network link can be determined conveniently later.
S12: determining a network connection link between the processor and the functional module according to port information of each layer of network connectors;
the connection relation of the uplink port and the connection relation of the downlink port of each network connector are determined, the network connection link of the processor-network connector-functional module can be determined according to the connection relation, after the network connection link is determined, even if the address of the functional module is modified, the functional module can be determined through the network connection link, and meanwhile, the complex connection relation of the internal network connector can be unnecessary to be determined in the testing process.
S13: determining a target functional module according to the network connection link, and transmitting excitation to the target functional module;
after determining the target function module to be tested, the processor may access the target function module according to the network connection link determined previously, and the processor sends an excitation to the target function module through the network connection link, where the excitation may be a preset program or test value, and the excitation is set according to the actual requirement.
S14: and determining whether the target functional module passes the test according to the value of the excitation output by the target functional module.
The target functional module outputs a corresponding value after receiving the excitation, and whether the operation of the target functional module is normal or not can be determined according to the value output by the target functional module, and meanwhile, whether a network connection link of the chip fails or not can be determined, so that the chip is tested.
The application provides a chip testing method, which relates to the testing field, and comprises the steps of obtaining port information of network connectors of each layer in a chip, wherein the port information comprises a module connected with an uplink port and a downlink port of the network connectors of each layer; determining a network connection link between the processor and the functional module according to port information of each layer of network connectors; determining a target functional module according to the network connection link, and transmitting excitation to the target functional module; and determining whether the target functional module passes the test according to the value of the excitation output by the target functional module. The processor is connected with each functional module through the multi-layer network connector, a network connection link from the processor to the network connector to each functional module can be formed after the uplink port and the downlink port of the network connector are determined, excitation can be directly sent to the target functional module through the network connection link, whether the chip passes the test or not is further determined according to the value output by the target functional module, and the test process is more concise.
Based on the above embodiments:
FIG. 2 is a diagram showing a distribution of port information according to the present application;
the network connector includes 2 upstream ports and 3 downstream ports. The eighth column, the ninth column and the tenth column are port information of three downstream ports of the network connector, respectively.
In some embodiments, obtaining port information for network connectors of each layer in a chip includes:
acquiring the identification of each network connector in the chip, the connection relation between an uplink port and a downlink port of the network connector, and the addresses, the identifications, the protocols and the bit widths of a module connected with the uplink port and a module connected with the downlink port of the network connector;
and converting the identification of each network connector, the connection relation between the uplink port and the downlink port of the network connector, and the addresses, the identification, the protocol and the bit width of the module connected with the uplink port and the module connected with the downlink port of the network connector into the data type of the dictionary.
The port information comprises more data types, including the distributed address of the functional module, the bus type of the network connector connected with the functional module, the data bit width of the bus between the network connector and the functional module capable of transmitting, and the data bit width required by the functional module. In addition, the method also comprises the steps that the bit width, the ID identification bit, the protocol, the data bit width and the wr of the uplink port in the figure 2 are written, namely write, and are write strobe signal output ends; rd is read, namely read, is an output end of a read strobe signal, wr/rd is a bit width of data read-write, mst is a master host, which can be understood as an upstream port, slv is a slave, which can be understood as a downstream port.
Converting the data into the data type of the dictionary can facilitate subsequent data acquisition.
In some embodiments, determining a network connection link between a processor and a functional module from port information of each layer of network connectors includes:
taking a downlink port of the network connector of the first layer as a father node;
determining an uplink port of a network connector of a next layer connected with a father node according to port information of the network connectors of each layer;
adding an uplink port of a network connector of a next layer connected with a father node as a child node to a network connection link;
updating the downlink port of the network connector corresponding to the child node into a parent node, and determining whether an uplink port of the network connector connected with the updated parent node exists according to the port information of each layer of network connectors;
if the uplink port of the network connector connected with the updated father node exists, the step of adding the uplink port of the network connector of the next layer connected with the father node as a child node to a network connection link is entered;
if the uplink port of the network connector connected with the updated father node does not exist, the network connector is determined to be the network connector of the last layer, and the path from the network connector of the first layer connected with the processor to the network connector of the last layer is used as a network connection link.
When determining the path, firstly, the network connector of the first layer is found, the uplink port of the network connector of the first layer is connected with the processor, if the downlink port of the network connector of the first layer is used as a father node, the uplink port of the network connector of the second layer connected with the downlink port of the network connector of the first layer is found, and the uplink port is used as a child node to be added into the path, thus the network connection link of the processor-the network connector of the first layer-the network connector of the second layer can be determined. And then the downlink port of the network connector of the second layer is used as a father node, the uplink port of the network connector of the third layer connected with the father node is found to be used as a child node, and the network connection link from the processor to the network connector of each layer can be determined by cycling step by step. The downstream port of the network connector of the last layer is not connected with the upstream ports of other network connectors but connected with the functional module, if the downstream port of the network connector is determined to be not connected with the upstream port of the other network connectors, the network connector is determined to be the network connector of the last layer, and the path from the network connector of the first layer to the network connector is the network connection link.
After each network connection link is determined, the processor can be accurately positioned to the target functional module, so that subsequent chip testing is realized.
The function find_dsp_port is used to find the downstream port: the input is a list of incoming uplink ports, each uplink port on all network connectors is traversed, a downlink port under each uplink port is added to a path_list path, a downlink port name is used as a father node, and an uplink port of a next-stage network connector is searched to be used as an initial path_list of the layer. The function find_usp_subject returns information corresponding to the upstream port according to the imported USP name, and the information type is dictionary type. The function find_dsp_subject returns information corresponding to the downlink port according to the input downlink port name, wherein the information type is a dictionary type.
The function find_usp_port is used to find the upstream port: the input is a name set of the parent node which is input, uplink ports corresponding to all the parent node names are found in the dictionary, if the uplink ports are found, the uplink ports are added to a path_list, the path_list is obtained by calling find_dsp_port, and the found usp_list is input.
The function gen_access_path is used for searching a root node root port of the network connector, calling find_dsp_port to acquire a path_list, adding the found root port to the path_list, and finally outputting a complete path_list, wherein each element in the path_list is a list, and indicating a complete path.
The master functions dsp_key_list and usp_key_list are used to identify coordinates of the upstream port and the downstream port and to identify list keys.
In some embodiments, determining a target functional module from a network connection link and sending a stimulus to the target functional module includes:
determining a starting address and a terminating address of a target functional module according to addresses of a module connected with an uplink port and a module connected with a downlink port of the network connector;
and determining a target functional module according to the network connection link, and sending excitation to a target address range of the target functional module to realize read-write operation of the target address range.
The testing process can test the initial address of the target functional module and also can test the boundary address or the randomly set address in a read-write way. It is necessary to determine the address of the connected functional module of the network connector before testing. The port information can determine the starting address, the boundary address and the random address of the target functional module, further determine the address to be tested, and send the stimulus to the address to be tested.
Specifically, the function find_type_int returns a digital part test case extraction function according to the input character string, and each type of test case can extract effective information from port information according to requirements and output the effective information, and the effective information comprises a boundary_test_gen function used for generating a memory boundary test case, including a write-read test for detecting a starting address, a boundary address and a random address of a target module.
In some embodiments, determining a target functional module from a network connection link and sending a stimulus to the target functional module includes:
determining a value of expected output of a target functional module corresponding to excitation set according to actual requirements;
determining the value actually output by the target functional module;
and when the expected output value is the same as the actual output value, determining that the target functional module passes the test.
Before testing, the testing requirement is determined in advance, corresponding excitation is sent to the target functional module after the testing requirement is determined, and after the excitation is sent, the value of how the target functional module should output is determined in advance to represent that the chip passes the testing, namely the expected output value of the target functional module is preset. After the output excitation is transmitted to the target functional module, the actual output value of the target functional module is received, if the actual output value is the same as the expected output value, the target functional module is proved to work normally, the network transmission link is normal, and the chip passes the test. If the actual output value is different from the expected output value, the target functional module is proved to work abnormally and/or the network transmission link is abnormal, the chip fails the test, and the fault cause is required to be checked later.
FIG. 2 is a diagram showing a distribution of port information according to the present application;
FIG. 3 is a diagram showing another port information distribution diagram according to the present application;
the relevant values in fig. 2 and 3 may be filled in according to actual requirements, and specific values are not given here in the present application.
In some embodiments, when the network connector has m upstream ports and n downstream ports, the port information includes a types, the port information is a+n rows by a+m columns, and m, n and a are positive integers;
after obtaining the port information of each layer of network connector in the chip, the method further comprises the following steps:
extracting data from the a+1 line to the a+n line, wherein the port information comprises the connection relation between an uplink port and a downlink port of the network connector and the address, the identifier, the protocol, the clock domain and the bit width of a module connected with the uplink port or the downlink port of the network connector;
extracting data of a+1th column to a+m column;
the data from the a+1th column to the a+m column are subjected to column-row exchange;
determining a network connection link between the network connector and the functional module in the chip according to the identifiers of the uplink port and the downlink port of the network connector connected with the module, including:
and determining a network connection link between the network connector in the chip and the functional module according to the data from the a+1 row to the a+n row and the data from the a+1 column to the a+m column after the row-column exchange.
As shown in fig. 2, taking a network connector of a=7, m=2, and n=3 as an example, there are 7 kinds of data, 2 upstream ports, and 3 downstream ports. The eighth column, the ninth column and the tenth column are port information of three downlink ports of the network connector, the three downlink ports are respectively a BOOT xore fg and an LDCFG, the eighth row and the ninth row are port information of two uplink ports of the network connector, and the two uplink ports are respectively a55 and M33.
It can be seen that the arrangement of fig. 2 is inconvenient for extracting the uplink port and the downlink port of the network connector, so the present application provides a way to facilitate extracting the information of the uplink port and the information of the downlink port. Specifically, since the downstream ports are distributed in a column manner and the upstream ports are distributed in a row manner, the data of the (a+1) -th column to the (a+m) -th column are extracted, and the table in fig. 2 is specifically that the data of the eighth column, the ninth column and the tenth column are extracted, so that the data can be subjected to column-row conversion for facilitating the subsequent processing. In addition, the data of the (a+1) -th row to the (a+n) -th row are extracted, and the table in fig. 2 is the data of the eighth row and the ninth row, and the data of the extracted uplink port and the data of the extracted downlink port are integrated, so that the pattern in fig. 3 is obtained.
the test_name is the name of the network connector, the root_port_name is the name of the network connector connected with the uplink port, the root_port_width is the address bit width of the uplink port, the root_port_width is the identification bit width of the uplink port, the root_port_width is the data bit width of the uplink port, the access_base_addr is the address of each downlink port, the access_address_addr is the range of each downlink port, the end_port_protocol is the protocol of the downlink port, and the end_port_width is the bit width of the downlink port.
The way to extract the column data is: the table has a plurality of columns, the boundary column number is the last column, the boundary column number of the effective information in the list is calculated, column processing is called when the effective information boundary line number is extracted, the effective information of the column before the boundary column is extracted after the boundary column is found, and the port information of the uplink port and the downlink port of the network connector is obtained.
By integrating the uplink port with the downlink port, the port data of the network connector can be separately sorted out for subsequent processing.
Fig. 4 is a schematic structural diagram of a system for testing a chip according to the present application, where the system for testing a chip includes:
a port information obtaining unit 21, configured to obtain port information of each layer of network connectors in the chip, where the port information includes a module connected to an uplink port and a downlink port of each layer of network connectors, the module includes a processor in the chip, a network connector, and a functional module in the chip, the uplink port of the first layer of network connectors is connected to the processor, and the downlink port of the last layer of network connectors is connected to the functional module;
a network connection link determining unit 22 for determining a network connection link between the processor and the functional module according to port information of each layer of network connectors;
a target function module determining unit 23 for determining a target function module according to the network connection link and transmitting an excitation to the target function module;
and a test unit 24 for determining whether the target function module passes the test according to the value of the stimulus output according to the target function module.
Based on the above embodiments:
further comprises:
the port information obtaining unit 21 is specifically configured to obtain an identifier of each network connector in the chip, a connection relationship between an uplink port and a downlink port of the network connector, and an address, an identifier, a protocol, and a bit width of a module connected to the uplink port and a module connected to the downlink port of the network connector;
the dictionary conversion unit is used for converting the identification of each network connector, the connection relation between the uplink port and the downlink port of the network connector, and the address, the identification, the protocol and the bit width of the module connected with the uplink port and the module connected with the downlink port of the network connector into the data type of the dictionary.
The father node determining unit is used for taking a downlink port of the network connector of the first layer as a father node;
the parent node connection determining unit is used for determining an uplink port of a network connector of a next layer connected with the parent node according to the port information of the network connectors of each layer;
a child node determining unit for adding an uplink port of a network connector of a next layer connected with the parent node as a child node to the network connection link;
the parent node updating unit is used for updating the downlink port of the network connector corresponding to the child node into the parent node, and determining whether an uplink port of the network connector connected with the updated parent node exists or not according to the port information of the network connectors of each layer; if yes, triggering a child node determining unit; if not, triggering a last layer determining unit;
and the last layer determining unit is used for determining that the network connector is the network connector of the last layer, and the path from the network connector of the first layer connected with the processor to the network connector of the last layer is used as a network connection link.
The target function module address determining unit is used for determining the starting address and the ending address of the target function module according to the addresses of the module connected with the uplink port and the module connected with the downlink port of the network connector;
the target function module determining unit 23 is specifically configured to determine a target function module according to the network connection link, and send an excitation to a target address range of the target function module, so as to implement a read-write operation on the target address range.
The excitation determining unit is used for determining a value of expected output of a target functional module corresponding to excitation set according to actual requirements;
an output value determining unit for determining a value actually output by the target function module;
and the test passing unit is used for determining that the target functional module passes the test when the expected output value is the same as the actual output value.
When the network connector is provided with m uplink ports and n downlink ports, the port information comprises a type a, the port information is a+n row by a+m column table, and m, n and a are positive integers;
the uplink port extraction unit is used for extracting the data from the (a+1) th row to the (a+n) th row, and the port information comprises the connection relation between the uplink port and the downlink port of the network connector and the address, the identifier, the protocol, the clock domain and the bit width of a module connected with the uplink port or the downlink port of the network connector;
a downstream port extraction unit for extracting data of a+1st column to a+m column;
the row-column conversion unit is used for exchanging the data from the (a+1) th column to the (a+m) th column;
the network connection link determining unit 22 is specifically configured to determine a network connection link between the network connector and the functional module in the chip according to the data from the a+1 row to the a+n row and the data from the a+1 column to the a+m column after the row-column interchange.
Fig. 5 is a schematic structural diagram of a device for testing a chip according to the present application, where the device for testing a chip includes:
a memory 31 for storing a computer program;
a processor 32 for implementing the steps of the method of chip testing described above when executing a computer program.
The application also provides a chip, which comprises the device for testing the chip.
The chip provided by the present application is described with reference to the above embodiments, and will not be described herein.
The application also provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program realizes the steps of the method for testing the chip when being executed by a processor.
The description of the computer readable storage medium provided by the present application refers to the above embodiments, and is not repeated here.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method of chip testing, comprising:
acquiring port information of each layer of network connector in a chip, wherein the port information comprises a module connected with an uplink port and a downlink port of each layer of network connector, the module comprises a processor in the chip, the network connector and a functional module in the chip, the uplink port of the first layer of network connector is connected with the processor, and the downlink port of the last layer of network connector is connected with the functional module;
determining a network connection link between the processor and the functional module according to port information of each layer of network connectors;
determining a target functional module according to the network connection link, and sending excitation to the target functional module;
and determining whether the target functional module passes the test according to the value of the excitation output by the target functional module.
2. The method of chip testing according to claim 1, wherein obtaining port information of network connectors of each layer in a chip comprises:
acquiring the identification of each network connector in a chip, the connection relation between an uplink port and a downlink port of the network connector, and the address, the identification, the protocol and the bit width of a module connected with the uplink port and a module connected with the downlink port of the network connector;
and converting the identifiers of the network connectors, the connection relation between the uplink ports and the downlink ports of the network connectors, and the addresses, identifiers, protocols and bit widths of the modules connected with the uplink ports and the modules connected with the downlink ports of the network connectors into data types of dictionaries.
3. The method of chip testing according to claim 2, wherein determining a network connection link between the processor and the functional module according to port information of each layer of network connectors comprises:
taking a downlink port of the network connector of the first layer as a father node;
determining an uplink port of a network connector of a next layer connected with the father node according to port information of the network connectors of each layer;
adding an uplink port of the network connector of the next layer connected with the father node as a child node to a network connection link;
updating the downlink port of the network connector corresponding to the child node into a parent node, and determining whether an uplink port of the network connector connected with the updated parent node exists or not according to the port information of the network connectors of each layer;
if the uplink port of the network connector connected with the updated father node exists, entering a step of adding the uplink port of the network connector of the next layer connected with the father node as a child node to a network connection link;
if the uplink port of the network connector connected with the updated father node does not exist, determining that the network connector is the network connector of the last layer, and taking the path from the network connector of the first layer connected with the processor to the network connector of the last layer as the network connection link.
4. The method of chip testing according to claim 2, wherein determining a target functional module from the network connection link and transmitting a stimulus to the target functional module, comprises:
determining a starting address and a terminating address of a target functional module according to addresses of a module connected with an uplink port and a module connected with a downlink port of the network connector;
and determining a target functional module according to the network connection link, and sending excitation to a target address range of the target functional module so as to realize read-write operation of the target address range.
5. The method of chip testing according to claim 1, wherein determining a target functional module from the network connection link and transmitting a stimulus to the target functional module, comprises:
determining a value of expected output of the target functional module corresponding to excitation set according to actual requirements;
determining the value actually output by the target functional module;
and when the expected output value is the same as the actual output value, determining that the target functional module passes the test.
6. The method of chip testing according to any one of claims 1 to 5, wherein when the network connector has m upstream ports and n downstream ports, the port information includes a, the port information is a+n rows by a+m columns of tables, and m, n and a are positive integers;
after obtaining the port information of each layer of network connector in the chip, the method further comprises the following steps:
extracting data from a+1st row to a+n th row, wherein the port information comprises a connection relation between an uplink port and a downlink port of the network connector, and an address, an identifier, a protocol, a clock domain and a bit width of a module connected with the uplink port or the downlink port of the network connector;
extracting data of a+1th column to a+m column;
the data of the a+1th column to the a+m column are subjected to column-row exchange;
determining a network connection link between the network connector and the functional module in the chip according to the identification of the uplink port and the downlink port of the network connector connected with the module, including:
and determining a network connection link between the network connector and the functional module in the chip according to the data from the a+1 row to the a+n row and the data from the a+1 column to the a+m column after row-column exchange.
7. A system for chip testing, comprising:
the port information acquisition unit is used for acquiring port information of each layer of network connector in the chip, wherein the port information comprises modules connected with an uplink port and a downlink port of each layer of network connector, the modules comprise a processor in the chip, the network connector and a functional module in the chip, the uplink port of the first layer of network connector is connected with the processor, and the downlink port of the last layer of network connector is connected with the functional module;
a network connection link determining unit, configured to determine a network connection link between the processor and the functional module according to port information of each layer of network connectors;
the target function module determining unit is used for determining a target function module according to the network connection link and sending excitation to the target function module;
and the test unit is used for determining whether the target functional module passes the test according to the target functional module and the value of the excitation output.
8. An apparatus for chip testing, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the method of chip testing according to any one of claims 1 to 6 when executing said computer program.
9. A chip comprising the apparatus for chip testing of claim 8.
10. A computer readable storage medium, characterized in that it has stored thereon a computer program which, when executed by a processor, implements the steps of the method of chip testing according to any of claims 1 to 6.
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| CN117910401A (en) * | 2024-03-19 | 2024-04-19 | 英诺达(成都)电子科技有限公司 | Method, apparatus, device, storage medium and program product for configuring operation mode |
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| CN117910401A (en) * | 2024-03-19 | 2024-04-19 | 英诺达(成都)电子科技有限公司 | Method, apparatus, device, storage medium and program product for configuring operation mode |
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