CN117075909B - Compiling method, electronic device and medium for realizing parallel programming - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/41—Compilation
- G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F8/40—Transformation of program code
- G06F8/41—Compilation
- G06F8/42—Syntactic analysis
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- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to a compiling method, electronic equipment and medium for realizing parallel programming, wherein the method comprises the following steps of S1, acquiring an original abstract syntax tree; s2, traversing an original abstract syntax tree; s3, if the current traversed node has a source code with parallel programming instruction attribute, executing S4, otherwise, returning to S2; s4, checking whether the parallel programming instruction grammar is met, if so, executing S5, otherwise, ending; s5, if the host end is compiled, executing S6, and if the equipment end is compiled, executing S7; s6, converting the currently traversed node into an abstract syntax tree structure of a host-side calling equipment segment code, and executing S8; s7, converting the currently traversed node into an abstract syntax tree structure of an execution code of the equipment end; s8, returning to S2 if the nodes which are not traversed exist, otherwise, determining a target abstract syntax tree; s9, generating a target machine language. The invention has universality, can reduce the cost and improve the efficiency.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a compiling method, an electronic device, and a medium for implementing parallel programming.
Background
The parallel programming model provides a unified parallel programming application programming interface (Application Programming Interface, API for short), and the compiler needs to implement support for the parallel programming API. Some existing mainstream compilers can support parallel programming APIs, and are usually realized by providing a whole set of compiling flow, which has no universality and is complex and tedious. For non-mainstream compilers, support for parallel programming APIs cannot be achieved directly based on mainstream compilation flows. And the corresponding run-time dynamic and instruction conversion logic and the like are required to be added for different heterogeneous devices, so that high cost is required, and the implementation efficiency is low. Therefore, how to provide a general compiling technology for implementing parallel programming, reduce the compiling cost for implementing parallel programming, and improve the compiling efficiency for implementing parallel programming is a technical problem to be solved.
Disclosure of Invention
The invention aims to provide a compiling method, electronic equipment and medium for realizing parallel programming, which have universality, can reduce the compiling cost for realizing parallel programming and improve the compiling efficiency for realizing parallel programming.
According to a first aspect of the present invention, there is provided a compiling method for implementing parallel programming, comprising:
s1, acquiring an original abstract syntax tree, wherein the original abstract syntax tree comprises a plurality of nodes, and each node corresponds to at least one line of source codes;
step S2, traversing nodes which are not traversed in the original abstract syntax tree in sequence;
step S3, if source codes with preset parallel programming instruction attributes exist in source codes corresponding to the nodes traversed currently, executing step S4, otherwise, returning to execute step S2;
step S4, checking whether source codes with preset parallel programming instruction attributes corresponding to the currently traversed nodes accord with preset parallel programming instruction grammar, if so, executing step S5, otherwise, generating grammar error prompt information, and ending the flow;
step S5, acquiring current compiling attribute information, if compiling is performed for a host end, executing step S6, and if compiling is performed for a device end, executing step S7;
step S6, converting the currently traversed node into an abstract syntax tree structure of a host-side calling equipment segment code according to the preset parallel programming instruction type, and executing the step S8;
step S7, converting the currently traversed node into an abstract syntax tree structure of an execution code of the equipment end according to the preset parallel programming instruction type, and executing the step S8;
step S8, returning to the step S2 if the original abstract syntax tree has non-traversed nodes, otherwise, determining the original abstract syntax tree after current processing as a target abstract syntax tree;
and S9, generating a target machine language based on the target abstract syntax tree.
According to a second aspect of the present invention, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method according to the first aspect of the invention.
According to a third aspect of the present invention there is provided a computer readable storage medium storing computer executable instructions for performing the method of the first aspect of the present invention.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the compiling method, the electronic equipment and the medium for realizing parallel programming can achieve quite technical progress and practicality, and have wide industrial utilization value, and the compiling method, the electronic equipment and the medium have at least the following beneficial effects:
the method only needs to convert the original abstract syntax tree into the target abstract syntax tree which can be directly identified in the parallel programming process of the heterogeneous equipment, does not need to add additional processing in compiling other processes, and has universality for the heterogeneous equipment based on the same design concept. The invention reduces the dependence on the environment in the running process, and no additional dynamic library is needed to be arranged in the execution environment, thereby greatly reducing the cost of supporting parallel programming and improving the compiling efficiency of realizing parallel programming.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a compiling method for implementing parallel programming according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
An embodiment of the present invention provides a compiling method for implementing parallel programming, as shown in fig. 1, including:
step S1, an original abstract syntax tree is obtained, wherein the original abstract syntax tree (abstract syntax code, AST for short) comprises a plurality of nodes, and each node corresponds to at least one line of source codes.
And step S2, traversing the nodes which are not traversed in the original abstract syntax tree in sequence.
It will be appreciated that each node in the original abstract syntax tree needs to be traversed and only once.
And step S3, if the source code corresponding to the currently traversed node has the source code with the preset parallel programming instruction attribute, executing the step S4, otherwise, returning to the step S2.
And S4, checking whether source codes with preset parallel programming instruction attributes corresponding to the currently traversed nodes accord with preset parallel programming instruction grammar, if so, executing the step S5, otherwise, generating grammar error prompt information, and ending the flow.
It can be understood that before the abstract syntax tree conversion is executed, whether the source code of the original abstract syntax tree node with the preset parallel programming instruction attribute accords with the preset parallel programming instruction syntax or not needs to be judged, if not, a syntax error reminder is directly generated, the process is ended, and useless calculation is avoided.
Step S5, obtaining the current compiling attribute information, if the compiling is performed for the host side, executing step S6, and if the compiling is performed for the equipment side, executing step S7.
It should be noted that, the current compiling attribute information refers to information identified as compiling at the host side or compiling at the device segment, and this information may be directly obtained when the compiling process is executed. By way of example, the host side refers to the central processor (Central Processing Unit) side, and the device side refers to the graphics processor (English: graphics Processing Unit; GPU) side.
And S6, converting the currently traversed node into an abstract syntax tree structure of a host-side calling equipment segment code according to the preset parallel programming instruction type, and executing the step S8.
And S7, converting the currently traversed node into an abstract syntax tree structure of an execution code of the equipment end according to the preset parallel programming instruction type, and executing the step S8.
And S8, returning to the step S2 if the original abstract syntax tree has non-traversed nodes, otherwise, determining the original abstract syntax tree after current processing as a target abstract syntax tree.
It should be noted that, through the conversion from step S1 to step S8, the original abstract syntax tree can be converted into a target abstract syntax tree which can be directly identified in the parallel programming process of the heterogeneous device.
And S9, generating a target machine language based on the target abstract syntax tree.
According to the method provided by the embodiment of the invention, the original abstract syntax tree is only required to be converted into the target abstract syntax tree which can be directly identified in the parallel programming process of the heterogeneous equipment, no additional processing is required to be added in other compiling processes, dependence of a runtime environment is reduced, no additional dynamic library is required in an execution environment, and the compiled executable file is supported to be quickly migrated. For heterogeneous devices based on the same design concept, the conversion of the abstract syntax tree is universal, and there is little cost for the compiler to add new device support. And because the abstract syntax tree is directly converted and no dependency exists in the running process, more optimization processing can be performed in the compiling process, and the final program performance is better.
As an embodiment, the step S1 includes:
and S11, acquiring a source code character stream for lexical analysis to generate a symbol stream.
The input of the compiler is the text of the source code, the source code text is read to obtain the source code character stream, a certain symbol can be generated by the character stream according to a certain rule through lexical analysis, and the generated symbols are combined together to generate the symbol stream.
And S12, carrying out grammar analysis on the symbol stream to generate the original abstract grammar tree.
It should be noted that, after the original abstract syntax operation, the specification corresponding to the syntax analysis needs to be satisfied, if the specification is not satisfied, the whole process will fail to exit and cannot be continued.
As an embodiment, the step S3 includes:
and S31, judging whether a code sentence or a code block in the source code corresponding to the currently traversed node comprises a preset parallel programming instruction fixed text or not, and if so, determining the code sentence or the code block as the source code with the preset parallel programming instruction attribute.
It should be noted that, step S31 needs to be performed in combination with the source code. The preset parallel programming may specifically be OpenMP programming, and the preset parallel programming instruction fixed text is "#pragmaomp". OpenMP programming is an existing parallel programming method, and is not described herein.
As an embodiment, the step S4 includes:
step S41, checking whether the instruction name in the source code with the preset parallel programming instruction attribute corresponding to the currently traversed node accords with the preset parallel programming instruction setting specification, if so, executing step S4, otherwise, returning to execute step S22, otherwise, executing step S44.
Step S42, checking whether the associated statement, statement or code block of the source code with the preset parallel programming instruction attribute corresponding to the currently traversed node accords with the preset parallel programming instruction setting specification, if so, executing step S4, otherwise, returning to execute step S23, and otherwise, executing step S44.
Step S43, checking whether the following clause and parameter format of the source code with the preset parallel programming instruction attribute corresponding to the currently traversed node meet the preset parallel programming instruction setting specification, if so, executing step S5, otherwise, executing step S44.
And S44, generating grammar error prompt information and ending the flow.
Through the steps S41-S44, whether the source code with the preset parallel programming instruction attribute corresponding to the currently traversed node accords with the preset parallel programming instruction grammar or not can be rapidly and comprehensively checked, if not, grammar error prompt information is generated, the process is ended, and useless calculation is avoided.
As an embodiment, the step S6 includes:
step S61, determining a preset parallel programming instruction type to which the source code with a preset parallel programming instruction attribute corresponding to the currently traversed node belongs, if the source code is a declaration instruction, executing step S62, if the source code is an independent instruction, executing step S63, if the source code is a composite instruction, executing step S64, if the source code is a composite instruction, executing step S65, and if the source code is a combined instruction, executing step S66.
And step S62, according to the declaration instruction and the corresponding clause, adopting a preset host-side characteristic record table to record the characteristic information of the associated statement, declaration or code block of the declaration instruction, and if the declaration instruction simultaneously belongs to an independent instruction, predicting the corresponding characteristic information from the clause and recording the corresponding characteristic information in the preset host-side characteristic record table.
It should be noted that, the preset host-side feature record table is initially empty, and as the flow is executed, feature information is added to the preset host-side feature record table according to the requirement.
And step S63, inserting AST nodes corresponding to meaning codes indicated by the independent instructions and the corresponding clauses into the original abstract syntax tree according to the independent instructions and the corresponding clauses.
Step S64, according to the generated instruction, the corresponding clause and the preset host-side characteristic record table, predicting the thread distribution mode of the related statement or code structure executed at the equipment side, deducing parameter dependence by combining the related statement or code structure, and replacing an AST node corresponding to the generated instruction in the original abstract syntax tree with an AST node corresponding to the calling equipment code based on the thread distribution mode and the parameter dependence executed at the equipment side.
Step S65, splitting the instructions contained in the compound instruction, and returning the split instructions to the execution step S61 one by one according to the sequence relation of the compound instruction;
step S66, splitting the instructions contained in the combined instruction, and returning the split instructions to execute step S61 one by one according to the sequence of the positions in the combined instruction.
The instructions generated in step S65 and step S66 are split, and the source code with the preset parallel programming instruction attribute corresponding to the node currently traversed in step S61 is returned to be processed one by one.
As an embodiment, the step S7 includes:
step S71, judging the type of the preset parallel programming instruction to which the source code with the preset parallel programming instruction attribute corresponding to the currently traversed node belongs, if the source code is the declaration instruction, executing step S72, if the source code is the independent instruction, executing step S73, if the source code is the independent instruction, executing step S74, if the source code is the compound instruction, executing step S75, and if the source code is the combined instruction, executing step S76.
And step S72, according to the declaration instruction and the corresponding clause, adopting a preset equipment-side characteristic record table to record the characteristic information of the associated statement, declaration or code block of the declaration instruction, and if the declaration instruction simultaneously belongs to an independent instruction, predicting the corresponding characteristic information from the clause and recording the corresponding characteristic information in the preset equipment-side characteristic record table.
It should be noted that, the preset device-side feature record table is initially empty, and as the process is executed, feature information is added to the preset device-side feature record table according to the requirement.
And step 73, inserting AST nodes corresponding to meaning codes indicated by the independent instructions and the corresponding clauses into the original abstract syntax tree according to the independent instructions and the corresponding clauses.
Step S74, converting the associated codes corresponding to the generated codes or the sentences in the circulation in sequence according to a preset equipment end characteristic record table, and if an instruction with a preset parallel programming instruction attribute appears, returning to the step S71.
And step S75, splitting the instructions contained in the compound instruction, and returning the split instructions to the execution step S71 one by one according to the precedence relationship of the compound instruction.
Step S76, splitting the instructions contained in the combined instruction, and returning the split instructions to execute step S71 one by one according to the sequence of the positions in the combined instruction.
It should be noted that, the instruction with the preset parallel programming instruction attribute appearing in the step S74, the generated instruction is split in the step S65 and the step S66, and the generated instruction is returned to the step S71 to be used as the source code with the preset parallel programming instruction attribute corresponding to the node traversed at present, and is processed one by one.
As an embodiment, the step S9 includes:
step S91, inputting the target abstract syntax tree into an intermediate code generator to generate target intermediate codes.
And step S92, inputting the target intermediate code into a machine-independent code optimizer for optimization, and generating an optimized target intermediate code.
And step S93, inputting the optimized target intermediate code into a code generator to generate a target machine language to be optimized.
And step S94, inputting the target machine language to be optimized into a machine-related code optimizer for optimization, and generating a target machine language.
The intermediate code generator, the machine-independent code optimizer, the code generator, and the related code optimizer in step S91 to step S94 may be implemented directly by using an existing intermediate code generator, machine-independent code optimizer, code generator, and related code optimizer, and will not be described here.
It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The embodiment of the invention also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the methods of embodiments of the present invention.
The embodiment of the invention also provides a computer readable storage medium, which stores computer executable instructions for executing the method according to the embodiment of the invention.
The embodiment of the invention only needs to convert the original abstract syntax tree into the target abstract syntax tree which can be directly identified in the parallel programming process of the heterogeneous equipment, does not need to add additional processing in other compiling processes, and has universality for the heterogeneous equipment based on the same design concept. The invention reduces the dependence on the environment in the running process, and no additional dynamic library is needed to be arranged in the execution environment, thereby greatly reducing the cost of supporting parallel programming and improving the compiling efficiency of realizing parallel programming.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.
Claims (10)
1. A compilation method for implementing parallel programming, comprising:
s1, acquiring an original abstract syntax tree, wherein the original abstract syntax tree comprises a plurality of nodes, and each node corresponds to at least one line of source codes;
step S2, traversing nodes which are not traversed in the original abstract syntax tree in sequence;
step S3, if source codes with preset parallel programming instruction attributes exist in source codes corresponding to the nodes traversed currently, executing step S4, otherwise, returning to execute step S2;
step S4, checking whether source codes with preset parallel programming instruction attributes corresponding to the currently traversed nodes accord with preset parallel programming instruction grammar, if so, executing step S5, otherwise, generating grammar error prompt information, and ending the flow;
step S5, acquiring current compiling attribute information, if compiling is performed for a host end, executing step S6, and if compiling is performed for a device end, executing step S7;
step S6, converting the currently traversed node into an abstract syntax tree structure of a host-side calling equipment-side code according to the preset parallel programming instruction type, and executing the step S8;
step S7, converting the currently traversed node into an abstract syntax tree structure of an execution code of the equipment end according to the preset parallel programming instruction type, and executing the step S8;
step S8, returning to the step S2 if the original abstract syntax tree has non-traversed nodes, otherwise, determining the original abstract syntax tree after current processing as a target abstract syntax tree, wherein the target abstract syntax tree is an abstract syntax tree which can be directly identified in the parallel programming process of heterogeneous equipment;
and S9, generating a target machine language based on the target abstract syntax tree.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the step S1 includes:
s11, acquiring a source code character stream for lexical analysis to generate a symbol stream;
and S12, carrying out grammar analysis on the symbol stream to generate the original abstract grammar tree.
3. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the step S3 includes:
and S31, judging whether a code sentence or a code block in the source code corresponding to the currently traversed node comprises a preset parallel programming instruction fixed text or not, and if so, determining the code sentence or the code block as the source code with the preset parallel programming instruction attribute.
4. The method of claim 3, wherein the step of,
the preset parallel programming is OpenMP programming, and the fixed text of the preset parallel programming instruction is "#pragma omp".
5. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the step S4 includes:
step S41, checking whether the instruction name in the source code with the preset parallel programming instruction attribute corresponding to the currently traversed node accords with the preset parallel programming instruction setting specification, if so, executing step S4, otherwise, returning to execute step S22, otherwise, executing step S44;
step S42, checking whether the associated statement, statement or code block of the source code with the preset parallel programming instruction attribute corresponding to the currently traversed node accords with the preset parallel programming instruction setting specification, if so, executing step S4, otherwise, returning to execute step S23, otherwise, executing step S44;
step S43, checking whether the following clause and parameter format of the source code with the preset parallel programming instruction attribute corresponding to the currently traversed node meet the preset parallel programming instruction setting specification, if so, executing step S5, otherwise, executing step S44;
and S44, generating grammar error prompt information and ending the flow.
6. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the step S6 includes:
step S61, judging the type of the preset parallel programming instruction which belongs to the source code with the preset parallel programming instruction attribute and corresponds to the node which is currently traversed, if the source code is a declaration instruction, executing step S62, if the source code is an independent instruction, executing step S63, if the source code is a composite instruction, executing step S64, if the source code is a composite instruction, executing step S65, and if the source code is a combined instruction, executing step S66;
step S62, according to the statement instruction and the corresponding clause, adopting a preset host-side feature record table to record the feature information of the associated statement, statement or code block of the statement instruction, and if the statement instruction simultaneously belongs to an independent instruction, predicting the corresponding feature information from the clause and recording the feature information in the preset host-side feature record table;
step S63, according to the independent instruction and the corresponding clause, inserting an AST node corresponding to the meaning code indicated by the independent instruction and the corresponding clause into the original abstract syntax tree;
step S64, according to the generated instruction, the corresponding clause and a preset host-side characteristic record table, predicting a thread distribution mode of the execution of the associated statement or the code structure at the equipment side, deducing parameter dependence by combining the associated statement or the code structure, and replacing an AST node corresponding to the generated instruction in the original abstract syntax tree with an AST node corresponding to the calling equipment code based on the thread distribution mode and the parameter dependence of the execution at the equipment side;
step S65, splitting the instructions contained in the compound instruction, and returning the split instructions to the execution step S61 one by one according to the sequence relation of the compound instruction;
step S66, splitting the instructions contained in the combined instruction, and returning the split instructions to execute step S61 one by one according to the sequence of the positions in the combined instruction.
7. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the step S7 includes:
step S71, judging the type of the preset parallel programming instruction which belongs to the source code with the preset parallel programming instruction attribute and corresponds to the node which is currently traversed, if the source code is a declaration instruction, executing step S72, if the source code is an independent instruction, executing step S73, if the source code is a generating instruction, executing step S74, if the source code is a compound instruction, executing step S75, and if the source code is a combined instruction, executing step S76;
step S72, according to the declaration instruction and the corresponding clause, adopting a preset equipment end characteristic record table to record the characteristic information of the associated statement, declaration or code block of the declaration instruction, and if the declaration instruction simultaneously belongs to an independent instruction, predicting the corresponding characteristic information from the clause and recording the corresponding characteristic information in the preset equipment end characteristic record table;
step 73, according to the independent instruction and the corresponding clause, inserting an AST node corresponding to the meaning code indicated by the independent instruction and the corresponding clause into the original abstract syntax tree;
step S74, converting the associated codes corresponding to the generated codes or sentences in the circulation in sequence according to a preset equipment end characteristic record table, and returning to the execution step S71 if an instruction with a preset parallel programming instruction attribute appears;
step S75, splitting the instructions contained in the compound instruction, and returning the split instructions to the execution step S71 one by one according to the sequence relation of the compound instruction;
step S76, splitting the instructions contained in the combined instruction, and returning the split instructions to execute step S71 one by one according to the sequence of the positions in the combined instruction.
8. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the step S9 includes:
s91, inputting the target abstract syntax tree into an intermediate code generator to generate a target intermediate code;
step S92, inputting the target intermediate code into a machine-independent code optimizer for optimization, and generating an optimized target intermediate code;
step S93, inputting the optimized target intermediate code into a code generator to generate a target machine language to be optimized;
and step S94, inputting the target machine language to be optimized into a machine-related code optimizer for optimization, and generating a target machine language.
9. An electronic device, comprising:
at least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-8.
10. A computer readable storage medium, characterized in that computer executable instructions are stored for performing the method of any of the preceding claims 1-8.
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