CN117074906A - Integrated circuit testing method, testing device and storage medium - Google Patents
Integrated circuit testing method, testing device and storage medium Download PDFInfo
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- 238000012360 testing method Methods 0.000 title claims abstract description 119
- 238000012795 verification Methods 0.000 claims abstract description 172
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- 238000000034 method Methods 0.000 claims abstract description 18
- 238000010200 validation analysis Methods 0.000 claims abstract description 9
- 238000004590 computer program Methods 0.000 claims description 12
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2894—Aspects of quality control [QC]
Abstract
A test method, test apparatus and storage medium for an integrated circuit. The test method comprises the following steps: acquiring a circuit diagram and a layout of an integrated circuit, acquiring a device truth table of the integrated circuit based on the layout, and acquiring a device level list of each device of the integrated circuit based on the device truth table; for each of the devices, automatically constructing a test pattern of the device based on a type of a layer in the device hierarchy list of the device, the test pattern including a validation pattern and a witness pattern; and carrying out consistency verification based on the test pattern and the circuit diagram of each device to obtain a verification result of each device. The method and the device for testing the integrated circuit can automatically construct the test pattern of the device, so that the problems of large dependence on EDA tools, high omission probability, time consumption and the like caused by manually drawing the test pattern can be solved; in addition, since the created test pattern includes the verification pattern and the witness pattern, the reliability of the verification result can be improved.
Description
Technical Field
The present application relates to the field of integrated circuit testing technologies, and in particular, to a testing method, a testing apparatus, and a storage medium for an integrated circuit.
Background
At present, integrated circuits have played a very important role in various fields, and are the foundation of modern information society. In the development and design process of integrated circuits, consistency verification test needs to be performed on the designed layout and circuit diagram, and often hundreds of billions of devices are required. In the existing test method, a developer needs to manually create standard device test patterns, manually run circuit board pattern consistency verification (LVS, layout Versus Schematic) and manually spot check LVS results, so that the verification speed is slow, and meanwhile, the verification coverage rate of layers and optional layers which cannot occur in a layout is low and the verification of a certificate is lacking, so that the accuracy of the verification results is low.
Disclosure of Invention
The present application has been made in order to solve at least one of the above problems. According to an aspect of the present application, there is provided a test method of an integrated circuit, the test method including: acquiring a circuit diagram and a layout of an integrated circuit; acquiring a device truth table of the integrated circuit based on the layout, and acquiring a device level list of each device of the integrated circuit based on the device truth table; for each of the devices, automatically constructing a test pattern of the device based on a type of a layer in the device hierarchy list of the device, the test pattern including a validation pattern and a witness pattern; and carrying out consistency verification based on the test pattern and the circuit diagram of each device to obtain a verification result of each device.
Illustratively, the automatically constructing the test pattern of the device based on the type of layer in the device hierarchy list of the device includes: for optional layers of the device, deleting the optional layers and/or adding the optional layers in the layout to construct the verification pattern; deleting the necessary layers of the device in the layout to construct the witness patterns; and/or adding the non-presentable layer in the layout for the non-presentable layer of the device to construct the witness pattern.
Illustratively, constructing the test patterns is performed based on a pre-set library of parameter units, wherein pattern parameter adjustments based on the library of parameter units result in different ones of the test patterns.
Illustratively, the pattern parameters are customizable.
Illustratively, the performing consistency verification based on the test pattern and the circuit diagram of each device, to obtain a verification result of each device, includes: performing consistency verification based on each test pattern and each circuit diagram to obtain a consistency verification result of each test pattern and each circuit diagram;
illustratively, the automatically aggregating the consistency verification results to obtain a verification result for each of the devices includes: and if the consistency verification result of the verification pattern and the circuit diagram is passing, and the consistency verification result of the verification pattern and the circuit diagram is not passing, the verification result of the device is passing, otherwise, the verification result of the device is not passing.
Illustratively, the method further comprises: and determining a device level verification result of the integrated circuit based on the verification result of each device.
Illustratively, said determining a test result of said integrated circuit based on said verification result of each device comprises: if the verification result of each device is passing, the device level verification result of the integrated circuit is passing, otherwise, the device level verification result of the integrated circuit is not passing.
According to another aspect of the present application, there is also provided an apparatus for testing an integrated circuit, the apparatus comprising a memory and a processor, the memory having stored thereon a computer program for execution by the processor, which when executed by the processor causes the processor to perform the method for testing an integrated circuit as described above.
According to another aspect of the present application, there is also provided a storage medium having stored thereon a computer program to be executed by a processor, which when executed by the processor, causes the processor to execute the above-described test method of an integrated circuit.
The method and the device for testing the integrated circuit firstly acquire a circuit diagram and a layout of the integrated circuit; acquiring a device truth table of the integrated circuit based on the layout, and acquiring a device level list of each device of the integrated circuit based on the device truth table; then for each device, automatically constructing a test pattern of the device based on the type of the layer in the device hierarchy list of the device, the test pattern including a validation pattern and a witness pattern; and further carrying out consistency verification based on the test pattern and the circuit diagram of each device to obtain a verification result of each device. The test patterns of the device can be automatically constructed, so that the problems of large dependence on EDA tools, high omission probability, time consumption and the like caused by manually drawing the test patterns can be solved; in addition, since the created test pattern includes the verification pattern and the witness pattern, the reliability of the verification result can be improved.
Drawings
The above and other objects, features and advantages of the present application will become more apparent by describing embodiments of the present application in more detail with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate the application and together with the embodiments of the application, and not constitute a limitation to the application. In the drawings, like reference numerals generally refer to like parts or steps.
FIG. 1 illustrates a flow chart of a method of testing an integrated circuit according to one embodiment of the application.
Fig. 2 shows a schematic block diagram of a method of testing an integrated circuit according to one embodiment of the application.
Fig. 3 shows a schematic diagram of a test apparatus for an integrated circuit according to one embodiment of the application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, exemplary embodiments according to the present application will be described in detail with reference to the accompanying drawings. It should be apparent that the described embodiments are only some embodiments of the present application and not all embodiments of the present application, and it should be understood that the present application is not limited by the example embodiments described herein. Based on the embodiments of the application described in the present application, all other embodiments that a person skilled in the art would have without inventive effort shall fall within the scope of the application.
The embodiment of the application provides a testing method of an integrated circuit, which comprises the following steps:
step S101, obtaining a circuit diagram and a layout of an integrated circuit;
step S102, acquiring a device truth table of the integrated circuit based on the layout, and acquiring a device level list of each device of the integrated circuit based on the device truth table;
step S103, for each device, automatically constructing a test pattern of the device based on the type of the layer in the device hierarchy list of the device, wherein the test pattern comprises a verification pattern and a witness pattern;
and step S104, carrying out consistency verification based on the test pattern and the circuit diagram of each device to obtain a verification result of each device.
The testing method of the integrated circuit of the embodiment of the application firstly obtains a circuit diagram and a layout of the integrated circuit; acquiring a device truth table of the integrated circuit based on the layout, and acquiring a device level list of each device of the integrated circuit based on the device truth table; then for each device, automatically constructing a test pattern of the device based on the type of the layer in the device hierarchy list of the device, the test pattern including a validation pattern and a witness pattern; and further carrying out consistency verification based on the test pattern and the circuit diagram of each device to obtain a verification result of each device. The test patterns of the device can be automatically constructed, so that the problems of large dependence on EDA tools, high omission probability, time consumption and the like caused by manually drawing the test patterns can be solved; in addition, since the created test pattern includes the verification pattern and the witness pattern, the reliability of the verification result can be improved.
The following describes in detail the testing method of the integrated circuit according to the present application with reference to fig. 1 and 2, and by way of example, the testing method of the integrated circuit according to the present application comprises the following steps:
first, step S101 is performed to acquire a circuit diagram and a layout of an integrated circuit. In one example, a GDS (Graphic Data System, image data System) file of an integrated circuit is first read, with layout information of the chip stored therein. The GDS file contains the geometry of the planes in the integrated circuit layout and other relevant information. In step S101, a CDL (Circuit Description Language ) file of the integrated circuit is read, the circuit description language being used to describe the electronic circuit, the CDL file including a netlist of the integrated circuit, the interconnections of all elements being listed completely.
And then, executing step S102, acquiring a device truth table of the integrated circuit based on the layout, and acquiring a device level list of each device of the integrated circuit based on the device truth table. In one example, a device truth table for an integrated circuit is obtained based on the GDS file for the integrated circuit read in step S101. The GDS file for the integrated circuit contains a device truth table for the integrated circuit from which a device level list for each device of the integrated circuit can be obtained. The device layer list of each device of the integrated circuit further comprises a layer type of each layer, wherein the layer types are divided into three types, namely a necessary layer, an unoccupied layer and an optional layer, as shown in fig. 2, the layer type of the necessary layer is "1", the layer type of the unoccupied layer is "0", and the layer type of the optional layer is "x".
Next, step S103 is performed to automatically construct, for each device, a test pattern of the device based on the type of layer in the device hierarchy list of the device, the test pattern including a validation pattern and a witness pattern.
Illustratively, automatically constructing a test pattern of a device based on a type of layer in a device hierarchy list of the device, comprising: for optional layers of the device, deleting the optional layers and/or adding the optional layers in the layout to construct a verification pattern; deleting the necessary layers of the device in the layout to construct a witness pattern; and/or adding the non-presentable layer in the layout for the non-presentable layer of the device to construct the witness pattern.
As shown in table 1, in one example, for one device of an integrated circuit, the device has four layers in total, layer numbers are layer 1, layer 2, layer 3, layer 4, layer 1 has a layer type of must layer "1", layer 2 has a layer type of cannot occur layer "0", layer 3 has a layer type of must layer "1", and layer 4 has a layer type of optional layer ". Times.. In step S103, first, for optional layer 4, layer 4 is deleted from the layout, and other layers are unchanged, so as to construct verification pattern 1; adding a layer 4 in the layout, keeping other layers unchanged, and constructing a verification pattern 2; then deleting the layer 1 from the layout for the necessary layer 1, and constructing the witness pattern 1 without changing other layers; then deleting the layer 3 from the layout for the necessary layer 3, and constructing the witness pattern 2 without changing other layers; and then adding the layer 2 into the layout for the layer 2 which cannot appear, and constructing the witness pattern 3 without changing other layers.
| Layout layer number | Layer 1 | Layer 2 | Layer 3 | Layer 4 |
| Layout layer type | 1 | 0 | 1 | * |
| Test pattern | Layer 1 | Layer 2 | Layer 3 | Layer 4 |
| Verification Pattern 1 | 1 | 0 | 1 | 0 |
| Verification Pattern 2 | 1 | 0 | 1 | 1 |
| Witness pattern 1 | 0 | 0 | 1 | 0 |
| Witness pattern 2 | 1 | 0 | 0 | 0 |
| Witness mark 3 | 1 | 1 | 1 | 0 |
TABLE 1
Illustratively, building test patterns is performed based on a pre-set library of parameter cells, wherein pattern parameter adjustments based on the library of parameter cells result in different test patterns.
Illustratively, the pattern parameters are customizable.
In one example, the construction of the test pattern is to modify the layout based on the above-described rules, and the generation of the test pattern according to the modified layer type is performed based on a parameter cell library set in advance. The preset parameter cell library (Pcell) can be used for creating test patterns by defining parameters, different values are given to the parameters in the process of calling the Pcell, and different test patterns can be created. In step S103, first, a layer type is changed based on the type of the layer in the device layer list of the device, then corresponding customization parameters are set according to the changed layer type, and a test pattern conforming to the changed layer type is generated through a parameter unit library based on the customization parameters.
And step S104 is executed again, and consistency verification is carried out based on the test pattern and the circuit diagram of each device, so that a verification result of each device is obtained.
Illustratively, performing consistency verification based on the test pattern and the circuit diagram of each device to obtain a verification result of each device, including: performing consistency verification based on each test pattern and each circuit diagram to obtain a consistency verification result of each test pattern and each circuit diagram; and automatically summarizing consistency verification results to obtain verification results of each device.
Illustratively, automatically aggregating the consistency verification results to obtain a verification result for each device, including: if the consistency verification result of the verification pattern and the circuit diagram is passed, and the consistency verification result of the verification pattern and the circuit diagram is not passed, the verification result of the device is passed, otherwise, the verification result of the device is not passed.
In one example, for each layer of the integrated circuit device, performing consistency verification based on the test pattern and the circuit diagram corresponding to the layer generated in step S103, referring to table 2, for layer 4 of the device in table 1, if the LVS result of verification pattern 1 and the LVS result of verification pattern 2 are both device identified, the verification result of layer 4 of the device is pass, otherwise, it is not pass; for layer 1 of the device in table 1, if the LVS result of the witness mark 1 is that the device is not identified, the verification result of layer 1 of the device is that it passes, otherwise, it is that it does not pass; for layer 3 of the device in table 1, if the LVS result of the witness mark 2 is that the device is not identified, the verification result of layer 3 of the device is pass, otherwise, it is not pass; for layer 2 of the device in table 1, if the LVS result of the witness mark 3 is that the device is not identified, the verification result of layer 2 of the device is pass, otherwise, it is not pass. For the devices in table 1, when the test patterns corresponding to the layers of the devices pass through the LVS, the verification results of the layers are automatically summarized to obtain the verification results of the devices.
| Test pattern | LVS results | Pattern verification results |
| Verification Pattern 1 | The device is identified | By passing through |
| Verification Pattern 2 | The device is identified | By passing through |
| Witness pattern 1 | Device failure to identify | By passing through |
| Witness pattern 2 | Device failure to identify | By passing through |
| Witness mark 3 | Device failure to identify | By passing through |
TABLE 2
Illustratively, the method further comprises: a device level verification result of the integrated circuit is determined based on the verification result of each device.
Illustratively, determining the test results of the integrated circuit based on the verification results for each device includes: if the verification result of each device is passing, the device level verification result of the integrated circuit is passing, otherwise, the device level verification result of the integrated circuit is not passing.
In one example, after the above-mentioned test is performed on each device of the integrated circuit, the verification results of each device are automatically summarized, the device level verification result of the integrated circuit is determined based on the verification result of each device, if the verification result of each device of the integrated circuit is passed, the device level verification result of the integrated circuit is passed, otherwise, the device level verification result of the integrated circuit is not passed. In one example, for an integrated circuit whose device level verification results are failed, a verification report is automatically generated, displaying devices in the integrated circuit whose verification results are failed and/or displaying layers in the integrated circuit whose verification results are failed.
Based on the above description, according to the test method of the embodiment of the application, a circuit diagram and a layout of an integrated circuit are firstly obtained; acquiring a device truth table of the integrated circuit based on the layout, and acquiring a device level list of each device of the integrated circuit based on the device truth table; then for each device, automatically constructing a test pattern of the device based on the type of the layer in the device hierarchy list of the device, the test pattern including a validation pattern and a witness pattern; and further carrying out consistency verification based on the test pattern and the circuit diagram of each device to obtain a verification result of each device. The test patterns of the device can be automatically constructed, so that the problems of large dependence on EDA tools, high omission probability, time consumption and the like caused by manually drawing the test patterns can be solved; in addition, since the created test pattern includes the verification pattern and the witness pattern, the reliability of the verification result can be improved.
According to another aspect of the present application, there is provided an apparatus for testing an integrated circuit, the apparatus comprising a memory and a processor, the memory storing a computer program for execution by the processor, the computer program, when executed by the processor, causing the processor to perform the method for testing an integrated circuit as described above.
As shown in fig. 3, the test apparatus 300 for an integrated circuit includes a memory 301 and a processor 302, the memory 301 stores a computer program executed by the processor 302, and the computer program, when executed by the processor 302, causes the processor 302 to execute the above-mentioned test method for an integrated circuit, including:
step S101, obtaining a circuit diagram and a layout of an integrated circuit;
step S102, acquiring a device truth table of the integrated circuit based on the layout, and acquiring a device level list of each device of the integrated circuit based on the device truth table;
step S103, for each device, automatically constructing a test pattern of the device based on the type of the layer in the device hierarchy list of the device, wherein the test pattern comprises a verification pattern and a witness pattern;
and step S104, carrying out consistency verification based on the test pattern and the circuit diagram of each device to obtain a verification result of each device.
First, the processor 302 executes step S101 to acquire a circuit diagram and a layout of an integrated circuit. In one example, the processor 302 first reads a GDS (Graphic Data System, image data System) file of the integrated circuit, in which layout information of the chip is stored. The GDS file contains the geometry of the planes in the integrated circuit layout and other relevant information. In step S101, the processor 302 reads a CDL (Circuit Description Language ) file of the integrated circuit, the circuit description language being used to describe the electronic circuit, the CDL file including a netlist of the integrated circuit, the interconnections of all elements being fully listed.
The processor 302 then performs step S102, where the processor 302 obtains a device truth table for the integrated circuit based on the layout, and obtains a device hierarchy list for each device of the integrated circuit based on the device truth table. In one example, processor 302 obtains a device truth table for each device of the integrated circuit based on the GDS file for the integrated circuit read in step S101, from which a device level list for each device of the integrated circuit can be obtained. The device layer list of each device of the integrated circuit further comprises a layer type of each layer, wherein the layer types are divided into three types, namely a necessary layer, an unoccupied layer and an optional layer, as shown in fig. 2, the layer type of the necessary layer is "1", the layer type of the unoccupied layer is "0", and the layer type of the optional layer is "x".
Next, the processor 302 executes step S103, and for each device, the processor 302 automatically builds a test pattern of the device based on the type of the layer in the device hierarchy list of the device, the test pattern including a validation pattern and a witness pattern.
Illustratively, automatically constructing a test pattern of a device based on a type of layer in a device hierarchy list of the device, comprising: for optional layers of the device, deleting the optional layers and/or adding the optional layers in the layout to construct a verification pattern; deleting the necessary layers of the device in the layout to construct a witness pattern; and/or adding the non-presentable layer in the layout for the non-presentable layer of the device to construct the witness pattern.
As shown in table 1, in one example, for one device of an integrated circuit, the device has four layers in total, layer numbers are layer 1, layer 2, layer 3, layer 4, layer 1 has a layer type of must layer "1", layer 2 has a layer type of cannot occur layer "0", layer 3 has a layer type of must layer "1", and layer 4 has a layer type of optional layer ". Times.. In step S103, the processor 302 deletes layer 4 in the layout for optional layer 4, and other layers are unchanged, so as to construct a verification pattern 1; adding a layer 4 in the layout, keeping other layers unchanged, and constructing a verification pattern 2; then deleting the layer 1 from the layout for the necessary layer 1, and constructing the witness pattern 1 without changing other layers; then deleting the layer 3 from the layout for the necessary layer 3, and constructing the witness pattern 2 without changing other layers; and then adding the layer 2 into the layout for the layer 2 which cannot appear, and constructing the witness pattern 3 without changing other layers.
TABLE 1
Illustratively, building test patterns is performed based on a pre-set library of parameter cells, wherein pattern parameter adjustments based on the library of parameter cells result in different test patterns.
Illustratively, the pattern parameters are customizable.
In one example, the test pattern is constructed by the processor 302 modifying the layout based on the rules described above, and then the processor 302 generating the test pattern according to the modified layer type is performed based on a pre-set library of parameter elements. The preset parameter cell library (Pcell) can be used for creating test patterns by defining parameters, different values are given to the parameters in the process of calling the Pcell, and different test patterns can be created. In step S103, the processor 302 first sets corresponding customization parameters based on the changed layer types of the layers in the device layer list of the device, and then generates test patterns conforming to the changed layer types through the parameter unit library based on the customization parameters.
The processor 302 further executes step S104 to perform consistency verification based on the test pattern and the circuit diagram of each device, thereby obtaining a verification result of each device.
Illustratively, performing consistency verification based on the test pattern and the circuit diagram of each device to obtain a verification result of each device, including: performing consistency verification based on each test pattern and each circuit diagram to obtain a consistency verification result of each test pattern and each circuit diagram; and automatically summarizing consistency verification results to obtain verification results of each device.
Illustratively, automatically aggregating the consistency verification results to obtain a verification result for each device, including: if the consistency verification result of the verification pattern and the circuit diagram is passed, and the consistency verification result of the verification pattern and the circuit diagram is not passed, the verification result of the device is passed, otherwise, the verification result of the device is not passed.
In one example, for each layer of the integrated circuit device, processor 302 performs a consistency verification based on the test pattern and the circuit diagram corresponding to the layer generated in step S103, referring to table 2, for layer 4 of the device in table 1, if the LVS result of verification pattern 1 and the LVS result of verification pattern 2 are both device identified, the verification result of layer 4 of the device is pass, otherwise, it is not pass; for layer 1 of the device in table 1, if the LVS result of the witness mark 1 is that the device is not identified, the verification result of layer 1 of the device is that it passes, otherwise, it is that it does not pass; for layer 3 of the device in table 1, if the LVS result of the witness mark 2 is that the device is not identified, the verification result of layer 3 of the device is pass, otherwise, it is not pass; for layer 2 of the device in table 1, if the LVS result of the witness mark 3 is that the device is not identified, the verification result of layer 2 of the device is pass, otherwise, it is not pass. For the devices in table 1, when the test patterns corresponding to the layers of the devices pass through the LVS, the processor 302 automatically sums the verification results of the layers to obtain the verification results of the devices.
| Test pattern | LVS results | Pattern verification results |
| Verification Pattern 1 | The device is identified | By passing through |
| Verification Pattern 2 | The device is identified | By passing through |
| Witness pattern 1 | Device failure to identify | By passing through |
| Witness pattern 2 | Device failure to identify | By passing through |
| Witness mark 3 | Device failure to identify | By passing through |
TABLE 2
Illustratively, the method further comprises: a device level verification result of the integrated circuit is determined based on the verification result of each device.
Illustratively, determining the test results of the integrated circuit based on the verification results for each device includes: if the verification result of each device is passing, the device level verification result of the integrated circuit is passing, otherwise, the device level verification result of the integrated circuit is not passing.
In one example, the processor 302 automatically aggregates the verification results of the devices after the above-described testing is performed on the devices of the integrated circuit, determines the device level verification result of the integrated circuit based on the verification results of each device, and if the verification results of each device of the integrated circuit are all passed, the device level verification result of the integrated circuit is passed, otherwise, the device level verification result of the integrated circuit is not passed. In one example, for an integrated circuit whose device level verification results are failed, a verification report is automatically generated, displaying devices in the integrated circuit whose verification results are failed and/or displaying layers in the integrated circuit whose verification results are failed.
Based on the above description, the test device according to the embodiment of the present application firstly obtains a circuit diagram and a layout of an integrated circuit; acquiring a device truth table of the integrated circuit based on the layout, and acquiring a device level list of each device of the integrated circuit based on the device truth table; then for each device, automatically constructing a test pattern of the device based on the type of the layer in the device hierarchy list of the device, the test pattern including a validation pattern and a witness pattern; and further carrying out consistency verification based on the test pattern and the circuit diagram of each device to obtain a verification result of each device. The test patterns of the device can be automatically constructed, so that the problems of large dependence on EDA tools, high omission probability, time consumption and the like caused by manually drawing the test patterns can be solved; in addition, since the created test pattern includes the verification pattern and the witness pattern, the reliability of the verification result can be improved.
According to another aspect of the present application there is also provided a storage medium having stored thereon a computer program for execution by a processor, which when executed by the processor causes the processor to perform the method of testing an integrated circuit as described above.
Although the illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the above illustrative embodiments are merely illustrative and are not intended to limit the scope of the present application thereto. Various changes and modifications may be made therein by one of ordinary skill in the art without departing from the scope and spirit of the application. All such changes and modifications are intended to be included within the scope of the present application as set forth in the appended claims.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, e.g., the division of elements is merely a logical function division, and there may be additional divisions of actual implementation, e.g., multiple elements or components may be combined or integrated into another device, or some features may be omitted, or not performed.
In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in order to streamline the application and aid in understanding one or more of the various inventive aspects, various features of the application are sometimes grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of the application. However, the method of the present application should not be construed as reflecting the following intent: i.e., the claimed application requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this application.
It will be understood by those skilled in the art that all of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be combined in any combination, except combinations where the features are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the application and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.
Various component embodiments of the application may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that some or all of the functions of some of the modules according to embodiments of the present application may be implemented in practice using a microprocessor or Digital Signal Processor (DSP). The present application may also be implemented as an in-vehicle system program (e.g., a computer program and a computer program product) for executing a part or all of the methods described herein. Such a program embodying the present application may be stored on a computer readable medium, or may have the form of one or more signals. Such signals may be downloaded from an internet website, provided on a carrier signal, or provided in any other form.
It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means can be embodied by one and the same item of hardware. The use of the words first, second, third, etc. do not denote any order. These words may be interpreted as names.
The above description is merely illustrative of the embodiments of the present application and the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes or substitutions are covered by the protection scope of the present application. The protection scope of the application is subject to the protection scope of the claims.
Claims (10)
1. A method of testing an integrated circuit, the method comprising:
acquiring a circuit diagram and a layout of an integrated circuit;
acquiring a device truth table of the integrated circuit based on the layout, and acquiring a device level list of each device of the integrated circuit based on the device truth table;
for each of the devices, automatically constructing a test pattern of the device based on a type of a layer in the device hierarchy list of the device, the test pattern including a validation pattern and a witness pattern;
and carrying out consistency verification based on the test pattern and the circuit diagram of each device to obtain a verification result of each device.
2. The method of testing of claim 1, wherein the automatically constructing the test pattern of the device based on the type of layer in the device hierarchy list of the device comprises:
for optional layers of the device, deleting the optional layers and/or adding the optional layers in the layout to construct the verification pattern;
deleting the necessary layers of the device in the layout to construct the witness patterns; and/or adding the non-presentable layer in the layout for the non-presentable layer of the device to construct the witness pattern.
3. The test method according to claim 1, wherein the construction of the test patterns is performed based on a pre-set parameter cell library, wherein different ones of the test patterns are obtained by performing pattern parameter adjustment based on the parameter cell library.
4. A test method according to claim 3, wherein the pattern parameters are customizable.
5. The test method according to claim 1 or 2, wherein the performing the consistency verification based on the test pattern and the circuit diagram of each of the devices to obtain the verification result of each of the devices includes:
performing consistency verification based on each test pattern and each circuit diagram to obtain a consistency verification result of each test pattern and each circuit diagram;
and automatically summarizing the consistency verification results to obtain the verification result of each device.
6. The method of testing of claim 5, wherein automatically aggregating the consistency verification results to obtain a verification result for each of the devices comprises:
and if the consistency verification result of the verification pattern and the circuit diagram is passing, and the consistency verification result of the verification pattern and the circuit diagram is not passing, the verification result of the device is passing, otherwise, the verification result of the device is not passing.
7. The method of testing according to claim 1, wherein the method further comprises:
and determining a device level verification result of the integrated circuit based on the verification result of each device.
8. The method of testing of claim 7, wherein said determining the test result of the integrated circuit based on the verification result of each device comprises:
if the verification result of each device is passing, the device level verification result of the integrated circuit is passing, otherwise, the device level verification result of the integrated circuit is not passing.
9. A test apparatus for an integrated circuit, the apparatus comprising a memory and a processor, the memory having stored thereon a computer program for execution by the processor, which when executed by the processor, causes the processor to perform the test method for an integrated circuit as claimed in any one of claims 1 to 8.
10. A storage medium having stored thereon a computer program to be executed by a processor, which computer program, when executed by the processor, causes the processor to perform the method of testing an integrated circuit according to any of claims 1-8.
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