CN117060935A - Antenna tuning circuit - Google Patents

Abstract

An antenna tuning circuit is disclosed. The antenna tuning circuit is configured to estimate an antenna impedance at the antenna port a plurality of times and determine an optimal tuning state for antenna tuning based on the antenna impedance estimate. According to various embodiments of the present disclosure, the antenna tuning circuit may be further configured to minimize impedance estimation errors, reduce amplitude and/or phase disturbances during antenna tuning, and infer antenna impedance estimates for both transmit and receive frequencies. Thus, the antenna tuning circuit can achieve autonomous antenna tuning optimization to thereby improve transmission and reception performance in a wireless communication device.

Description

Antenna tuning circuit

Cross Reference to Related Applications

The present application claims the benefit of U.S. provisional patent application Ser. No. 63/340,991, filed on day 5 and 12 of 2022, and U.S. provisional patent application Ser. No. 63/389,166, filed on day 7 and 14 of 2022, the disclosures of which are hereby incorporated by reference in their entireties.

Technical Field

The technology of the present disclosure relates generally to antenna tuning.

Background

Mobile communication devices have become increasingly popular in the current society for providing wireless communication services. The popularity of these mobile communication devices is driven in part by the many functions that are currently enabled on such devices. The increase in processing power in such devices means that mobile communication devices have evolved from pure communication tools to complex mobile multimedia centers capable of enhancing user experience.

In general, in order to achieve optimal antenna performance in a wireless communication device, the impedance of an antenna is matched to the impedance of a line carrying a signal to be transmitted. As frequencies increase, antennas associated with mobile communication devices become more sensitive. Thus, when the environment changes (e.g., near an organic material (e.g., near a user's hand, head, or body) or is placed on a metal surface), the change in impedance of the antenna due to such an environment change may have a disproportionate impact on performance due to impedance mismatch. Minimizing the effects of such dynamic impedance variations has proven challenging, and there is still room for improving impedance matching in dynamic environments.

Disclosure of Invention

Aspects disclosed in the detailed description include an antenna tuning circuit. The antenna tuning circuit is configured to estimate an antenna impedance at the antenna port a plurality of times and determine an optimal tuning state for antenna tuning based on the antenna impedance estimate. According to various embodiments of the present disclosure, the antenna tuning circuit may be further configured to minimize impedance estimation errors, reduce amplitude and/or phase disturbances during antenna tuning, and infer antenna impedance estimates for both transmit and receive frequencies. Thus, the antenna tuning circuit can achieve autonomous antenna tuning optimization to thereby improve transmission and reception performance in a wireless communication device.

In one aspect, an antenna tuning circuit is provided. The antenna tuning circuit includes an impedance tuner circuit. An impedance tuner circuit is coupled to the antenna port. The antenna tuning circuit also includes a control circuit. The control circuit is configured to receive one or more input impedances measured at an input of the impedance tuner circuit. Each of the one or more measured input impedances corresponds to a respective one of one or more selected tuning states among a plurality of tuning states associated with the impedance tuner circuit. The control circuit is further configured to generate one or more estimates of the antenna impedance presented at the antenna port based on the one or more measured input impedances, respectively. The control circuit is further configured to determine an optimal tuning state among a plurality of tuning states based on one or more estimates of the antenna impedance. The control circuit is further configured to configure the impedance tuner circuit to thereby match the antenna impedance presented at the antenna port based on the determined optimal tuning state.

In another aspect, a method for performing closed loop antenna tuning is provided. The method includes measuring one or more input impedances that each correspond to a respective one of one or more selected tuning states among a plurality of tuning states. The method also includes generating one or more estimates of the antenna impedance based on the one or more measured input impedances, respectively. The method also includes determining an optimal tuning state among a plurality of tuning states based on one or more estimates of antenna impedance. The method also includes matching the antenna impedance based on the determined optimal tuning state.

Those skilled in the art will recognize the scope of the present disclosure and appreciate additional aspects thereof upon reading the following detailed description of the preferred embodiments and the associated drawings.

Drawings

The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure.

FIG. 1 is a graphical diagram providing an exemplary illustration of the well-known Smith Chart;

fig. 2 is a schematic diagram of an exemplary antenna tuning circuit configured to perform closed loop antenna tuning in accordance with an embodiment of the present disclosure;

FIG. 3 is a graphical diagram illustrating an algorithm for estimating antenna impedance based on measured input impedance;

fig. 4 is a flow chart of an exemplary process that may be used by the closed loop antenna tuning circuit of fig. 2 to perform closed loop antenna tuning;

FIG. 5 is a graphical diagram providing exemplary illustrations of some of the steps in the process of FIG. 4 for estimating a plurality of antenna impedances based on a plurality of measured input impedances;

fig. 6 is a block diagram illustrating a tuner model that may be dynamically defined by the antenna tuning circuit of fig. 2 for determining an optimal tuner state;

FIG. 7 is a graphical diagram illustrating an exemplary complex tuner transfer function that may be controlled to reduce amplitude and phase disturbances during tuner state transitions;

FIG. 8 is a schematic diagram of an exemplary circuit modeling antenna impedance for selected transmit and receive bands;

FIG. 9 is a graphical diagram providing an exemplary illustration of a fifth order rational function; and is also provided with

Fig. 10 is a schematic diagram of an exemplary user element in which the antenna tuning circuit of fig. 2 may be provided to perform closed loop antenna tuning.

Detailed Description

The embodiments set forth below represent the information necessary to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "extending" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly extending onto" another element, there are no intervening elements present. Also, it will be understood that when an element such as a layer, region or substrate is referred to as being "over" or "extending over" another element, it can extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

Relative terms, such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Embodiments are described herein with reference to antenna tuning circuits. The antenna tuning circuit is configured to estimate an antenna impedance at the antenna port a plurality of times and determine an optimal tuning state for antenna tuning based on the antenna impedance estimate. According to various embodiments of the present disclosure, the antenna tuning circuit may be further configured to minimize impedance estimation errors, reduce amplitude and/or phase disturbances during antenna tuning, and infer antenna impedance estimates for both transmit and receive frequencies. Thus, the antenna tuning circuit can achieve autonomous antenna tuning optimization to thereby improve transmission and reception performance in a wireless communication device.

Before discussing the antenna tuning circuit of the present disclosure, beginning with fig. 2, a brief discussion of the well-known smith chart is first made with reference to fig. 1 to help define some key terms in the context of the present disclosure.

Fig. 1 is a graphical diagram providing an exemplary illustration of a well-known smith chart. The smith chart may be divided into four quadrants 1, 2, 3, and 4. In this quadrant, quadrants 1 and 2 represent the inductive reactance region, where the impedance Z can be expressed as R+jX. It will be appreciated that R represents the actual resistance and X represents the inductive reactance. In contrast, quadrants 3 and 4 represent capacitive reactance regions, where the impedance Z may be expressed as R+j (-X). It will be appreciated that R represents the actual resistance and-X represents the capacitive reactance.

Furthermore, quadrants 2 and 3 represent high impedance regions because they correspond toExpressed in ratio as center point P _C The actual resistance R is high. In contrast, quadrants 1 and 4 represent low impedance regions because they correspond to the ratio represented as center point P _C The actual resistance R is low as the nominal resistance of (c).

In the context of the present disclosure, the impedance Γ _Z May be a measured impedance or an estimated impedance. Since the measured impedance may be affected by the measurement error and the estimated impedance may be affected by the estimation error, the impedance Γ _Z Appears as an error distribution circle 10 (also known as an error circle) on the smith chart. As shown in fig. 1, the error distribution circle 10 is represented by the measured/estimated impedance Γ _Z Center E of (2) _C And an impedance Γ corresponding to the measurement/estimation _Z The radius r of the Error Vector Magnitude (EVM). As defined herein, the term "error distribution circle" will often be mentioned in the various embodiments of the present disclosure, which are discussed next.

Fig. 2 is a schematic diagram of an exemplary antenna tuning circuit 12 configured to perform closed loop antenna tuning in accordance with an embodiment of the present disclosure. The antenna tuning circuit 12 is coupled to an antenna port 14, which is further coupled to an antenna circuit 16 (e.g., an antenna array). The antenna circuit 16 is configured to transmit a Radio Frequency (RF) transmit signal 18. In an embodiment, the RF transmit signal 18 may be generated by the transceiver circuitry 20 and provided to the antenna tuning circuitry 12 via the RF front-end circuitry 22. In a non-limiting example, RF front-end circuit 22 may include such active/passive circuits as power amplifiers, RF filter circuits, and switching circuits, which are not shown herein for simplicity.

The antenna circuit 16 presents an antenna impedance Γ at the antenna port 14 _ANT . Notably, the antenna impedance Γ is due to modulation bandwidth, RF frequency, and/or power variations of the RF signal 18 _ANT May fluctuate from time to time. Therefore, the antenna impedance Γ at the antenna port 14 must be accurately determined and matched _ANT To avoid potential distortion of the RF signal 18 caused by, for example, signal reflections.

In this regard, the antenna tuning circuit 12 includes an impedance tuner circuit 24. Impedance tuner electricityThe path 24 is coupled to the antenna port 14 and is dynamically tunable to match the antenna impedance Γ at the antenna port 14 _ANT . More specifically, the antenna tuning circuit 12 may generate an antenna impedance Γ _ANT And is based on the antenna impedance Γ _ANT Determines an optimal tuning state for antenna tuning. Accordingly, the antenna tuning circuit 12 may dynamically tune the impedance tuner circuit 24 based on the determined optimal tuner state to thereby provide an antenna impedance Γ presented at the antenna port 14 _ANT Is a good match to the matching pattern.

In a non-limiting example, the impedance tuner circuit 24 may include a combination of tunable capacitors, resistors, and/or inductors. These tunable capacitors, resistors, and/or inductors may be individually or collectively adjusted based on a particular tuning state. In an embodiment, the tuning state may be a digital bitmap having a plurality of binary bits. Each of the tunable capacitor, resistor, and/or inductor may be associated with one or more binary bits in the bitmap. For example, the impedance tuner circuit 24 may include one tunable capacitor, one tunable resistor, and one tunable inductor. In this regard, if the tuning state is a six-bit digital bitmap, each of the tunable capacitor, tunable resistor, and tunable inductor may be associated with respective two binary bits in the digital bitmap. Thus, each of the tunable capacitor, tunable resistor, and tunable inductor may have four tunable values corresponding to binary values "00", "01", "10", and "11". In this example, there may be sixty-four different tuner state combinations for tuning the tunable capacitor, tunable resistor, and tunable inductor. It will be appreciated that the number of tuning states may increase exponentially as more tunable capacitors, resistors and/or inductors are provided in the impedance tuner circuit 24.

The antenna tuning circuit 12 also includes an impedance sensor 26 and a control circuit 28. The impedance sensor 26 is coupled to an input 30 of the impedance tuner circuit 24. On the other hand, the antenna port 14 is coupled to an output 32 of the impedance tuner circuit 24. As an example, the control circuit 28, which may be a Field Programmable Gate Array (FPGA), is coupled to the impedance sensor 26 and the impedance tuner circuit 24 via a single wire bus 34. In a non-limiting example, the control circuit 28 may include a memory (not shown) for storing all tuning states of the impedance tuner circuit 24.

In an embodiment, the impedance sensor 26 is configured to measure an input impedance Γ presented at an input of the impedance tuner circuit 24 _IN . In a non-limiting example, the impedance tuner circuit 24 may be modeled by a transfer function of a well-known 2-port network, with an input impedance Γ presented at the input of the impedance tuner circuit 24 _IN And the antenna impedance Γ presented at the output 32 of the impedance tuner circuit 24 _ANT The relationship between them can be established as in the following equations (equations 1.1 and 1.2).

Given input impedance Γ _IN And antenna impedance Γ _ANT The control circuit 28 may then be based on the input impedance Γ measured at the input 30 of the impedance tuner circuit 24 _IN To estimate the antenna impedance Γ at the output 32 of the impedance tuner circuit 24 _ANT . Fig. 3 is a graph showing an input impedance Γ for measurement based _IN Estimating antenna impedance Γ _ANT Is a graphical diagram of the algorithm of (a).

Since the Mobius transform M (z) = (az+b)/(cz+d) can be written as a matrix m=So equations (equations 1.1 and 1.2) can be rewritten as equations (equations 2.1 and 2.2).

Thus, when the input impedance Γ is performed by the impedance sensor 26 _IN Is expressed as "Γ _IN-MEAS ") the measured input impedance Γ _IN-MEAS Can be shown as Γ _IN A measurement error circle 36 on a plane 38 (e.g., smith chart). Error circle 36 is measured to measure input impedance Γ _IN-MEAS Is centered and has a corresponding input impedance Γ _IN Radius r of EVM of (2) _IN-MEAS . Let it be assumed that the input impedance Γ _IN Evenly dispersed in the measurement error circle 36.

To generate antenna impedance Γ _ANT Is expressed as (denoted as "Γ) _ANT-MEAS ") the measurement error circle 36 can be converted to Γ _ANT An estimated error circle 40 on a plane 42 (e.g., smith chart). Error circle 40 is estimated to estimate antenna impedance Γ _ANT-EST Is centered and has a radius r as expressed in the following equations (equations 3.1, 3.2 and 3.3) _ANT-EST 。

As discussed above, the control circuit 28 may determine the input impedance Γ from the measurement _IN-MEAS Inferring an estimated antenna impedance Γ _ANT-MEAS . Thus, the control circuit 28 may control the impedance tuner circuit 24 to match the estimated antenna impedance Γ _ANT-MEAS . In this regard, the antenna tuning circuit 12 may perform closed loop antenna tuning to match the antenna impedance Γ as closely as possible _ANT To thereby improve transmission and reception performance in a wireless communication apparatus.

In an embodiment, the antenna tuning circuit 12 may be configured to perform closed loop antenna tuning based on a process. In this regard, fig. 4 is a flow chart of an exemplary process 100 that may be used by the antenna tuning circuit 12 of fig. 2 to perform closed loop antenna tuning. The elements in fig. 2 are mentioned in process 100 and will not be described again herein.

According to process 100, impedance sensor 26 is further configured to perform an input impedance Γ at input 30 of impedance tuner circuit 24 _IN Is expressed as "Γ _IN-MEAS1 -Γ _IN-MEASN ") (step 102). By setting the impedance tuner circuit 24 to one or more selected tuner states TS among all tuner states associated with the impedance tuner circuit 24 ₁ -TS _N To measure the input impedance Γ _IN-MEAS1 -Γ _IN-MEASN Each of which is formed by a pair of metal plates. In other words, the input impedance Γ may be measured based on a selected subset of tuner states associated with the impedance tuner circuit 24 _IN-MEAS1 -Γ _IN-MEASN . As previously described in fig. 3, the measured input impedance Γ _IN-MEAS1 -Γ _IN-MEASN Each associated with a respective one of one or more measurement error circles 36 (1) -36 (N), such as measurement error circle 36 in fig. 3.

Next, in a process 100, the control circuit 28 is based on the measured input impedances Γ, respectively _IN-MEAS1 -Γ _IN-MEASN Generating an antenna impedance Γ at the output 32 of the impedance tuner circuit 24 _ANT Is represented as "Γ _ANT-EST1 -Γ _ANT-ESTN ") (hereinafter interchangeably referred to as" estimated antenna impedance ") (step 104). According to the previous discussion in fig. 3, the estimated antenna impedance Γ _ANT-EST1 -Γ _ANT-ESTN Each associated with a respective one of one or more of the estimation error circles 40 (1) -40 (N), such as the estimation error circle 40 in fig. 3.

Fig. 5 is a graphical diagram providing exemplary illustrations of steps 102 and 104 in the process 100 of fig. 4. Common elements between fig. 3, 4 and 5 are shown with common element numbers and will not be described again herein.

Here, the falseLet the impedance sensor 26 perform three measurements Γ of the input impedance _IN To thereby produce three measured input impedances Γ associated with the three measurement error circles 36 (1) -36 (3) _IN-MEAS1 -Γ _IN-MEAS3 And the control circuit 28 makes three estimates Γ of the antenna impedance _ANT To produce three estimated antenna impedances Γ associated with the three estimated error circles 40 (1) -40 (3) _ANT-EST1 -Γ _ANT-EST3 . It will be appreciated that the illustration provided in fig. 5 is merely an example and should not be construed as limiting in any way.

Here, according to the algorithm described in fig. 3, the input impedance Γ is measured from _IN-MEAS1 -Γ _IN-MEAS3 Determines an estimated antenna impedance Γ _ANT-EST1 -Γ _ANT-EST3 Each of which is formed by a pair of metal plates. Thus, the control circuit 28 may be configured to Γ among the estimation error circles 40 (1) -40 (3) _ANT-EST1 -Γ _ANT-EST3 The estimated antenna impedance is averaged when searching for the maximum overlap region. In one embodiment, the control circuit 28 may determine the estimated antenna impedance Γ _ANT-EST1 -Γ _ANT-EST3 Is a weighted average of (c). In another embodiment, the control circuit 28 may select the estimated antenna impedance Γ _ANT-EST1 -Γ _ANT-EST3 Corresponding to an estimated antenna impedance of the maximum likelihood value. At estimated antenna impedance Γ _ANT-EST1 -Γ _ANT-EST3 In case more than one of them has the same maximum likelihood value, these estimated antenna impedances Γ will be used _ANT-EST1 -Γ _ANT-EST3 Average value of (2). By performing an input impedance Γ _IN-MEAS1 -Γ _IN-MEAS3 And for an estimated antenna impedance Γ _ANT-EST1 -Γ _ANT-EST3 Averaging, it is possible to reduce the input impedance Γ to each measurement _IN-MEAS1 -Γ _IN-MEAS3 Associated random noise.

Referring back to fig. 4, the control circuit 28 then bases on the estimated antenna impedance Γ _ANT-EST1 -Γ _ANT-ESTN Determining an optimal tuner state TS among all tuner states associated with the impedance tuner circuit 24 _OPT (step 106). Here, the control circuit28 is configured to be based on the estimated antenna impedance Γ _ANT-EST1 -Γ _ANT-EST3 Selecting an optimal tuner state TS from among all tuner states associated with the impedance tuner circuit 24 _OPT . In an embodiment, the control circuit 28 may use a tuner model (e.g., an s-parameter model) of the transfer function of the impedance tuner circuit 24 to determine the optimal tuner state TS _OPT 。

Notably, the impedance tuner circuit 24 may be associated with thousands of tuner states, which may consume a significant amount of memory space to store these tuner states. Thus, it is desirable that the tuner model can be defined so as to determine an optimal tuner state TS _OPT Without consuming a lot of memory space. In this regard, FIG. 6 is a diagram illustrating a control circuit 28 that may be dynamically defined by the antenna tuning circuit 12 of FIG. 2 for determining an optimal tuner state TS _OPT A block diagram of tuner model 44 of (c).

According to an embodiment of the present disclosure, tuner model 44 includes a static tuner status block 46 and a dynamic tuner status block 48. The dynamic tuner status block 48 may be further divided into a pair of Programmable Automation Controller (PAC) blocks PAC1 and PAC2. In a non-limiting example, the static tuner state block 46 and the dynamic tuner state block 48 may each be modeled by a 5-port network as represented in equations (equations 4.1 and 4.2).

In a non-limiting example, the static tuner status block 46 need only store 15 complex numbers, while PAC blocks PAC1 and PAC2 would store 96 and 48 complex numbers, respectively. Thus, tuner model 44 will store a total of 159 complex numbers. In contrast, a conventional tuner model with 5-bit PAC1 and 4-bit PAC2 would have to store 1536 complex numbers. In this regard, tuner model 44 may save approximately 90% of memory space as compared to conventional tuner models.

Based on the static tuner state model in equation (equation 4.1) and the dynamic tuner state model in equation (equation 4.2), the 2-port tuner state model S of the impedance tuner circuit 24 can be determined as in equation (equation 5) below.

[S]＝S _E ¹¹ +S _E ¹² *(I ₃ -[S _PAC ]*S _E ²² ) ^-1 *[S _PAC ]*S _E ²¹ (equation 5)

Notably, the highest matrix order is 3, which is the same as the number of connections in tuner model 44. The control circuit 28 is then configured to select an optimal tuner state TS among the static and/or dynamic tuner states stored in the tuner model 44 _OPT . In one embodiment, the tuner model 44 may be predetermined and pre-stored in the control circuit 28. Alternatively, the control circuit 28 may dynamically generate the tuner model 44.

Referring back to FIG. 4, in determining the optimal tuner status TS _OPT Thereafter, the control circuit 28 may be based on the determined optimal tuner status TS _OPT The impedance tuner circuit 24 is adjusted to thereby match the antenna impedance (step 108). Notably, changing the impedance tuner circuit 24 to the optimal tuner state TS _OPT Disturbances (e.g., amplitude and/or phase changes) may be introduced in the RF transmit signal 18. Thus, it is desirable to control the amplitude and phase disturbances in the RF transmit signal 18 when changing the impedance tuner circuit 24 from one tuner state to another. In this regard, fig. 7 is a graphical diagram illustrating an exemplary complex tuner transfer function 50 of the impedance tuner circuit 24 of fig. 2 that may be controlled to reduce amplitude and phase disturbances when the impedance tuner circuit 24 transitions from one tuner state to another tuner state.

With respect to transmitting RF transmit signal 18, complex tuner transfer function 50 controls both the amplitude and phase of the antenna radiated power. The complex tuner function 50 may also control the amplitude and phase of the antenna receive power according to the reciprocal principle. For a generic 2-port network, the transfer function can be written as in equation (equation 6).

For the matching source Γ _S =0, the transfer function in equation (equation 6) can be as follows (equation (et al)

And (3) overwriting in formula 7).

For any given antenna impedance Γ _ANT Can be in tuner state TS ₁ -TS _N Lower calculation of possible complex transfer function value G _Tn (1. Ltoreq. N. Ltoreq. N). As an example, when the impedance tuner circuit 24 is from the tuner state TS ₁ Changing to tuner State TS ₂ At the time, complex transfer function value GT ₁ /GT ₂ The ratio between will determine the change in antenna radiated power or antenna received power. Specifically, the amplitude and phase variation of the antenna radiation/reception power can be expressed in the following equations (equations 8.1 and 8.2).

By limiting GT ₂ /GT ₁ And thus the variation of the antenna radiation/reception power can be limited. In an embodiment, the amplitude variation in decibels (dB) and the phase variation in the amplitude of the phase variation may be limited. Notably, when the impedance tuner circuit 24 is in the tuner state TS ₁ Changing to TS ₂ The amplitude variation and absolute phase variation of dB will remain the same when this is the case, and vice versa.

By traversing tuner states TS ₁ -TS _N Can be constructed from all possible combinations of (a)A one-way diagram in which all edges follow the amplitude and phase control limits as represented in equations (equations 9.1 and 9.2).

After constructing the complex tuner transfer function 50 shown in fig. 7, a standard path search algorithm may be used to find the tuner state TS ₁ -TS _N Is provided, the path between any two of the above. Instead of moving one tunable component per step (e.g., tunable capacitor/resistor/inductor), the algorithm considers all the tunable components involved in the impedance tuner circuit 24.

Referring back to fig. 4, after adjusting the impedance tuner circuit 24 to the optimal tuner state, the control circuit 28 then checks to see if the exit criteria has been met (step 110). In a non-limiting example, the exit criteria may correspond to the highest power of the input match at or below a predefined Voltage Standing Wave Ratio (VSWR). If the exit criteria have not been met, the process 100 will return to step 102. Otherwise, the control circuit 28 will check whether the hold criterion is met (step 112). In a non-limiting example, when the estimated antenna impedance Γ _ANT-EST1 -Γ _ANT-ESTN The retention criterion is met when the maximum likelihood value of (c) is above a threshold or remains relatively constant. If the hold criteria is met, the antenna tuning circuit 12 will enter a hold mode (step 114). Otherwise, the process 100 will return to step 102.

Referring back to fig. 2, in an embodiment, the antenna tuning circuit 12 may include a second impedance sensor 52 disposed between the output 32 of the impedance tuner circuit 24 and the antenna port 14. As with the impedance sensor 26, the second impedance sensor 52 may also measure forward and reverse power to enable calculation of losses in the impedance tuner circuit 24. In this regard, the second impedance sensor 52 may also be capable of measuring the amplitude and/or phase of the reflection coefficient.

The second impedance sensor 52 may also be used to help the control circuit 28 improve the antenna impedance Γ by combining these measured expected error regions _ANT-EST1 -Γ _ANT-ESTN Is to be used for the estimation of the input impedance Γ _IN-MEAS1 -Γ _IN-MEASN Is a measurement of (a).

Notably, the antenna impedance Γ _ANT Only at the transmit frequency by the impedance sensor 26 and/or the second impedance sensor 52. However, the antenna impedance Γ is determined at the receiving frequency _ANT It is also important to improve the overall performance of the wireless device. In this regard, FIG. 8 is an antenna impedance Γ for selected transmit and receive bands _ANT Schematic diagram of an exemplary circuit model 54 that is modeled.

For example, the circuit model 54 may be used to determine the antenna impedance Γ for the following transmit and receive bands _ANT Modeling.

Among the transmission and reception frequencies in the above table, the reception frequencies in B13 and B8 are not measurable by the impedance sensor 26 and/or the second impedance sensor 52. Therefore, it is necessary to infer the antenna impedance Γ at the reception frequencies in B13 and B8 _ANT 。

Notably, the antenna impedance Γ _ANT And the reflection coefficient is periodic and infinite with respect to frequency. However, in a limited frequency range, a rational approximation that can be transferred to an L-C-R circuit model similar to circuit model 54 can be achieved by methods such as vector fitting methods, singular Value Decomposition (SVD) methods, levenberg-Marquardt methods, and the like.

When the antenna has a full measurement over the frequency range, the approximation is typically a minimum error fit over the entire frequency range. For a particular type of antenna, there is a minimum order of the rational function to achieve a reasonable minimum error. For example, fig. 9 is a graph showing a five-order rational function of a Planar Inverted F Antenna (PIFA) antenna fitted from 650MHz to 1.2 GHz. Here, the rational function may be expressed in the following equation (equation 10).

Rational function Γ _ANT (s) can be easily transferred to the circuit model 54 of fig. 8. Note that in fig. 8, a negative resistor is present in the circuit model 54. The passivity of the antenna can be ensured only in the frequency range of 650MHz to 1.2 GHz.

The antenna tuning circuit 12 in fig. 2 may be provided in the user element to achieve closed loop antenna tuning in accordance with the embodiments described above. In this regard, fig. 10 is a schematic diagram of an exemplary user element 200 in which the antenna tuning circuit 12 of fig. 2 may be provided.

Herein, the user element 200 may be any type of user element, such as a mobile terminal, a smart watch, a tablet, a computer, a navigation device, an access point, and similar wireless communication devices supporting wireless communication, such as cellular, wireless Local Area Network (WLAN), bluetooth, and near field communication. The user element 200 will typically include a control system 202, a baseband processor 204, transmit circuitry 206, receive circuitry 208, antenna switching circuitry 210, a plurality of antennas 212, and user interface circuitry 214. In a non-limiting example, control system 202 may be a Field Programmable Gate Array (FPGA), as an example. In this regard, the control system 202 may include at least a microprocessor, embedded memory circuitry, and a communication bus interface. Receive circuitry 208 receives radio frequency signals from one or more base stations via antenna 212 and through antenna switching circuitry 210. The low noise amplifier and the filter cooperate to amplify and cancel wideband interference from the received signal for processing. The filtered received signal is then down-converted to an intermediate or baseband frequency signal by down-conversion and digitizing circuitry (not shown), which then digitizes the signal into one or more digital streams using an analog-to-digital converter (ADC).

The baseband processor 204 processes the digitized received signal to extract the information or data bits conveyed in the received signal. Such processing typically includes demodulation, decoding, and error correction operations, which will be discussed in more detail below. The baseband processor 204 is typically implemented in one or more Digital Signal Processors (DSPs) and Application Specific Integrated Circuits (ASICs).

For transmission, the baseband processor 204 receives digitized data, which may represent voice, data, or control information, from the control system 202, which it encodes for transmission. The encoded data is output to transmit circuitry 206 where a digital-to-analog converter (DAC) converts the digitally encoded data to an analog signal and a modulator modulates the analog signal onto a carrier signal at one or more desired transmit frequencies. The power amplifier amplifies the modulated carrier signal to a level suitable for transmission and delivers the modulated carrier signal to antenna 212 through antenna switching circuitry 210. Multiple antennas 212 and replicated transmit circuitry 206 and receive circuitry 208 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims (20)

1. An antenna tuning circuit, comprising:

an impedance tuner circuit coupled to the antenna port; and

a control circuit configured to:

receiving one or more input impedances measured at an input of the impedance tuner circuit, each of the one or more measured input impedances corresponding to a respective one of one or more selected tuning states among a plurality of tuning states associated with the impedance tuner circuit;

generating one or more estimates of antenna impedance presented at the antenna port based on the one or more measured input impedances, respectively;

determining an optimal tuning state among the plurality of tuning states based on the one or more estimates of the antenna impedance; and is also provided with

The impedance tuner circuit is configured based on the determined optimal tuning state to thereby match the antenna impedance presented at the antenna port.

2. The antenna tuning circuit of claim 1, further comprising an impedance sensor coupled to the input of the impedance tuner circuit and configured to measure the one or more input impedances, each corresponding to the respective one of the one or more selected tuning states.

3. The antenna tuning circuit of claim 2, further comprising a second impedance sensor coupled between an output of the impedance tuner circuit and the antenna port, the second impedance sensor configured to measure power loss at the antenna port to thereby enable the control circuit to optimize the determined optimized tuning state.

4. The antenna tuning circuit of claim 2, wherein:

the impedance sensor is further configured to measure the one or more input impedances at one or more transmit frequencies, respectively; and is also provided with

The control circuit is further configured to generate the one or more estimates of the antenna impedance at the one or more transmit frequencies, respectively.

5. The antenna tuning circuit of claim 4, wherein the control circuit is further configured to infer one or more receive impedances at one or more receive frequencies outside of a measurement range of the impedance sensor.

6. The antenna tuning circuit of claim 1, wherein the one or more estimates of the antenna impedance each correspond to a respective one of one or more error distribution circles, each comprising:

a center corresponding to a respective one of the one or more estimates of the antenna impedance; and

radius corresponding to the corresponding Error Vector Magnitude (EVM).

7. The antenna tuning circuit of claim 1, wherein the control circuit is further configured to determine the optimal tuning state among the plurality of tuning states based on an average of the one or more estimates of the antenna impedance.

8. The antenna tuning circuit of claim 1, wherein the control circuit is further configured to control a transfer function of the impedance tuner circuit to limit an amplitude and/or phase variation of a transmit power delivered to the antenna port and/or a receive power received via the antenna port.

9. The antenna tuning circuit of claim 1, wherein the control circuit is further configured to determine the optimal tuning state based on an impedance tuner model comprising a static tuner state block and a dynamic tuner state block, the dynamic tuner state block comprising a pair of Programmable Automation Controller (PAC) blocks.

10. A method for performing closed loop antenna tuning, comprising:

measuring one or more input impedances, each of the one or more input impedances corresponding to a respective one of one or more selected tuning states among a plurality of tuning states;

generating one or more estimates of antenna impedance based on the measured one or more input impedances, respectively;

determining an optimal tuning state among the plurality of tuning states based on the one or more estimates of the antenna impedance; and

the antenna impedance is matched based on the determined optimal tuning state.

11. The method of claim 10, further comprising measuring the one or more input impedances in one or more measurement error circles based on one or more selected tuning states, respectively.

12. The method of claim 11, further comprising generating the one or more estimates of the antenna impedance in one or more estimated error circles based on the measured one or more input impedances, respectively.

13. The method of claim 12, further comprising:

measuring the one or more input impedances at one or more transmit frequencies, respectively; and

the one or more estimates of the antenna impedance are generated at the one or more transmit frequencies, respectively.

14. The method of claim 13, further comprising inferring one or more receive impedances at one or more receive frequencies.

15. The method of claim 12, wherein each of the one or more estimated error circles corresponds to a respective one of one or more error distribution circles, each of the one or more error distribution circles comprising:

a center corresponding to a respective one of the one or more estimates of the antenna impedance; and

radius corresponding to the corresponding Error Vector Magnitude (EVM).

16. The method of claim 12, further comprising averaging the one or more estimates of the antenna impedance to thereby reduce random noise associated with each of the one or more estimates of the antenna impedance.

17. The method of claim 10, further comprising determining the optimal tuning state based on an average of the one or more estimates.

18. The method of claim 10, further comprising determining the optimal tuning state based on a tuner model comprising a static tuner state block and a dynamic tuner state block, the dynamic tuner state block comprising a pair of Programmable Automation Controller (PAC) blocks.

19. The method of claim 10, further comprising optimizing the determined optimized tuning state based on the measured power loss.

20. The method of claim 10, further comprising limiting amplitude and/or phase variations of transmit power and/or receive power.