CN117059590B - Wafer structure and chip - Google Patents

Abstract

The embodiment of the application provides a wafer structure and a chip, wherein the wafer structure comprises a base layer and a plurality of medium layers which are stacked; further comprises: a bonding portion and a plurality of conductive layers; the plurality of dielectric layers and the plurality of conductive layers are located between the base layer and the bonding portion; each dielectric layer corresponds to one conductive layer; a reinforcing piece is further arranged inside the dielectric layer close to the bonding part; the projection of the reinforcement piece in the thickness direction of the wafer structure is at least partially overlapped with the projection of the conductive layer close to the bonding part in the thickness direction of the wafer structure, so that the technical problems that the wafer is easy to be subjected to high strain or high stress in a subsequent packaging process to cause the damage or destruction of an interconnection structure, such as Low-k collapse or interface delamination of copper and Low-k, can be avoided or relieved.

Description

Wafer structure and chip

Technical field

Embodiments of the present application relate to the field of semiconductor technology, and in particular to a wafer structure and a chip.

Background technique

Wafer generally refers to the silicon wafer used in the production of silicon semiconductor integrated circuits. Because its shape is round, it is called a wafer. At this stage, silicon wafers can be processed into various circuit component structures to become semiconductor component products with specific electrical functions.

Currently, conventional interconnect structures for integrated circuits in wafers are typically formed using aluminum as the metal interconnect and silicon dioxide as the dielectric layer. However, as integrated circuits are continuously scaled down, conventional interconnect structures often suffer from interconnect delays due to high resistance and parasitic wiring capacitance, thus limiting the speed of high-performance integrated circuits. Due to these problems, in the related art, copper materials are usually used instead of aluminum materials in interconnect structures, and Low-k materials (k<3.9) are used instead of silicon dioxide. Copper helps reduce the resistance of the interconnect metal and increases the reliability of the interconnect structure, while Low-k materials help reduce parasitic capacitance between interconnect structures by providing a lower dielectric constant.

However, the mechanical strength of Low-k materials decreases, the Young's modulus decreases, and the interlayer adhesion weakens. The wafer is susceptible to high strain or high stress in the subsequent packaging process. Under these strains or stress, it may cause Damage or destruction of the interconnect structure, such as leading to Low-k collapse or interface delamination of copper and Low-k.

Contents of the invention

The present application provides a wafer structure and chip that can avoid or reduce the interconnection structure damage or destruction caused by high strain or high stress caused by the wafer in subsequent packaging processes, such as Low-k collapse or copper and Low- Technical issues with interface layering of k.

In a first aspect, embodiments of the present application provide a wafer structure, which at least includes: a stacked base layer and a plurality of dielectric layers; further includes: a bonding portion and a plurality of conductive layers; the plurality of dielectric layers and the plurality of conductive layers. A conductive layer is located between the base layer and the bonding part; each dielectric layer corresponds to one conductive layer, and a reinforcing member is also provided inside the dielectric layer close to the bonding part; The projection of the reinforcement member in the thickness direction of the wafer structure at least partially overlaps the projection of the conductive layer close to the bonding portion in the thickness direction of the wafer structure.

In the wafer structure provided by the embodiments of the present application, the wafer structure also has reinforcement members inside the dielectric layer close to the bonding part. The reinforcement members can increase the structural strength of the dielectric layer, thereby improving the reliability of the dielectric layer. sex. In addition, by designing the projection of the reinforcing member in the thickness direction of the wafer structure to at least partially overlap with the projection of the conductive layer close to the bonding portion in the thickness direction of the wafer structure, the reinforcing member can affect the conductive layer close to the bonding portion. It plays a certain strength supporting role, which can further improve the interlayer structure strength of the wafer structure. Therefore, embodiments of the present application can avoid or reduce the risk that the wafer is susceptible to high strain or high stress in the subsequent packaging process, causing damage or destruction of the interconnect structure, such as causing Low-k collapse or interface delamination between copper and Low-k. technical issues.

In a possible implementation, a conductive via hole is provided inside each dielectric layer, and the conductive via hole is connected to the corresponding conductive layer; the conductive layer close to the bonding part and The conductive via hole is made of copper.

By using the material of the conductive layer close to the bonding part and the material of the conductive via hole close to the bonding part as copper, compared with the material used in the conductive layer close to the bonding part and the material close to the bonding part in the related art, The conductive vias at the bottom are made of aluminum. The copper metal layer has high strength, which can alleviate the compressive stress introduced by the bonding wire during the bonding process to a large extent, thereby improving the reliability of the dielectric layer. .

In a possible implementation, the projection of the reinforcement in the thickness direction of the wafer structure is all located close to the projection of the conductive layer in the thickness direction of the wafer structure. Inside.

By designing the projection of the reinforcement in the thickness direction of the wafer structure to be entirely within the projection of the conductive layer close to the bonding portion in the thickness direction of the wafer structure, the entire reinforcement can act on the conductive layer close to the bonding portion. It plays a strong supporting role, which can better improve the interlayer structure strength of the wafer structure.

In a possible implementation, the number of the reinforcement members is multiple, and the plurality of reinforcement members are located around the conductive through hole close to the bonding portion.

The greater the number of reinforcements, the stronger the strength support effect on the conductive layer close to the bonding part. By designing the number of reinforcement members to be multiple, with multiple reinforcement members located around the conductive through holes close to the bonding part, it can be ensured that the strength support effect of the multiple reinforcement members on the conductive layer close to the bonding part is more balanced and effective. This can better improve the interlayer structure strength of the wafer structure.

In a possible implementation, the reinforcing member is made of carbon nanotubes.

Carbon nanotubes, also known as Bucky tubes, are one-dimensional nanoscale quantum materials with a special structure (radial dimensions are on the order of nanometers, axial dimensions are on the order of microns, and both ends of the tube are basically sealed) and are lightweight. , the hexagonal structure is perfectly connected and has excellent mechanical, electrical and chemical properties. Carbon nanotubes are mainly coaxial circular tubes composed of several to dozens of layers of carbon atoms arranged in a hexagonal shape. The distance between the layers of carbon nanotubes is fixed, about 0.34nm, and the diameter is generally 2~20nm. Carbon nanotubes can be divided into three types: zigzag carbon nanotubes, armchair carbon nanotubes and spiral carbon nanotubes according to the different orientations of the carbon hexagons along the axial direction. Among them, spiral carbon nanotubes have chirality, while zigzag carbon nanotubes and armchair carbon nanotubes have no chirality.

In a possible implementation, the plurality of dielectric layers include: a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer that are stacked in sequence;

The plurality of conductive layers include: a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer that are stacked in sequence;

The first dielectric layer is located between the base layer and the second dielectric layer, and the fourth dielectric layer is located between the third dielectric layer and the bonding portion;

The first conductive layer is located between the base layer and the second conductive layer, and the fourth conductive layer is located between the third conductive layer and the bonding portion;

The material used in the first dielectric layer, the second dielectric layer and the third dielectric layer is at least Low-k material, and the material used in the fourth dielectric layer is silicon dioxide.

Low-k material is an insulating material, specifically a non-conductive material. Low-k materials refer to silicon dioxide doped with carbon and hydrogen. Low-k materials are beneficial to improving chip performance. By designing the materials used in the first dielectric layer, the second dielectric layer and the third dielectric layer to be at least Low-k materials, the performance of the wafer structure can be improved.

In a possible implementation, the first dielectric layer, the second dielectric layer and the third dielectric layer respectively include: a first part and a second part;

The second part is located on the periphery of the first part;

The material used in the first part is Low-k material, and the material used in the second part is silicon dioxide.

By designing the first dielectric layer, the second dielectric layer and the third dielectric layer to include a first part and a second part respectively, taking the first dielectric layer including a first part and a second part as an example, the material used in the first part is Low -k material, the second part is located on the outer periphery of the first part, and the material used in the second part is silica. Due to the high mechanical strength of silica, it can prevent laser cutting, plastic sealing, dispensing and other processes from damaging the second part. The second part of a dielectric layer (i.e., the cutting edge) has an impact, for example, to avoid delamination of Low-k materials caused by excessive shear stress.

In a possible implementation, a first plating layer is further provided between the conductive layer close to the bonding portion and the bonding portion;

The first plating layer is made of nickel.

The first plating layer is provided between the conductive layer close to the bonding part and the bonding part, that is, the first plating layer is disposed on the side of the conductive layer close to the bonding part facing the bonding part. The material used for the first plating layer is nickel. , Nickel as the first plating layer can avoid or reduce the technical problem that copper metal is prone to oxidation corrosion.

In a possible implementation, a second plating layer is further provided between the first plating layer and the bonding portion;

The second plating layer is made of gold.

By disposing the first plating layer between the first plating layer and the bonding part, that is, disposing the second plating layer on the side of the first plating layer facing the bonding part, the material used for the second plating layer is gold, and gold as the second plating layer can On the basis of the first plating layer, the technical problem of copper metal being prone to oxidative corrosion is further avoided or reduced.

In a possible implementation, at least one passivation layer is further provided on a side of the dielectric layer close to the bonding portion facing the bonding portion;

The passivation layer and the bonding portion avoid each other.

By further disposing at least one passivation layer on the side of the dielectric layer close to the bonding portion and facing the bonding portion, the passivation layer can play a role in protecting the dielectric layer. In addition, the passivation layer and the bonding portion avoid each other, which can prevent the passivation layer from interfering with the bonding portion.

In a second aspect, embodiments of the present application further provide a chip, which at least includes: the wafer structure described in any of the above items.

The chip provided by the embodiment of the present application at least includes a wafer structure. The wafer structure is also provided with reinforcement members inside the dielectric layer close to the bonding part. The reinforcement members can play a role in increasing the structural strength of the dielectric layer, and thus can Improve the reliability of the dielectric layer. In addition, by designing the projection of the reinforcing member in the thickness direction of the wafer structure to at least partially overlap with the projection of the conductive layer close to the bonding portion in the thickness direction of the wafer structure, the reinforcing member can affect the conductive layer close to the bonding portion. It plays a certain strength supporting role, which can further improve the interlayer structure strength of the wafer structure. Therefore, embodiments of the present application can avoid or reduce the risk that the wafer is susceptible to high strain or high stress in the subsequent packaging process, causing damage or destruction of the interconnect structure, such as causing Low-k collapse or interface delamination between copper and Low-k. technical issues.

Description of the drawings

Figure 1 is a schematic diagram of the overall structure of a wafer structure provided by an embodiment of the present application;

Figure 2 is a schematic cross-sectional view of a wafer structure provided by an embodiment of the present application;

Figure 3 is a top view of the fourth conductive layer in the wafer structure provided by an embodiment of the present application;

Figure 4 is a top view of the fourth dielectric layer in the wafer structure provided by an embodiment of the present application;

Figure 5 is a top view of the first dielectric layer, the second dielectric layer or the third dielectric layer in the wafer structure provided by an embodiment of the present application;

Figure 6 is a schematic cross-sectional structural diagram of a wafer structure in the related art;

Figure 7 is a top view of the fourth conductive layer in the wafer structure in the related art;

Figure 8 is a top view of the fourth dielectric layer in the wafer structure in the related art;

FIG. 9 is a top view of a first dielectric layer, a second dielectric layer or a third dielectric layer in a wafer structure in the related art.

Explanation of reference symbols:

100, 100a-wafer structure; 110-base layer;

111-Functional part; 121, 121a-First dielectric layer;

122, 122a - second dielectric layer; 1221, 1221a - second conductive via hole;

123, 123a-the third dielectric layer; 1231, 1231a-the third conductive via hole;

124, 124a-the fourth dielectric layer; 1241, 1241a-the fourth conductive via hole;

125-Part 1; 126-Part 2;

127a-fifth dielectric layer; 1271a-fifth conductive via;

130-bonding part; 141, 141a-first conductive layer;

142, 142a - second conductive layer; 143, 143a - third conductive layer;

144, 144a-the fourth conductive layer; 145a-the fifth conductive layer;

150-reinforcement; 161-first plating layer;

162-Second plating layer; 171-First passivation layer;

172-The second passivation layer; 181-The first etching stop layer;

182-The second etching stop layer; 183-The third etching stop layer;

184-The fourth etching stop layer; 185-The fifth etching stop layer.

Detailed ways

The terms used in the embodiments of the present application are only used to explain the specific embodiments of the present application and are not intended to limit the present application. The implementation of the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

Wafer generally refers to the silicon wafer used in the production of silicon semiconductor integrated circuits. Because its shape is round, it is called a wafer. At this stage, silicon wafers can be processed into various circuit component structures to become semiconductor component products with specific electrical functions.

Currently, conventional interconnect structures for integrated circuits in wafers are typically formed using aluminum as the metal interconnect and silicon dioxide as the dielectric layer. However, when integrated circuits are continuously scaled down, for example, when devices are scaled down from the 90nm node to the 65nm node and further scaled down to smaller nodes, conventional interconnect structures often fail due to high resistance and parasitic wiring capacitance. Suffering from interconnect delays, these issues are major factors limiting the speed of high-performance integrated circuits.

Due to these problems, in the related art, copper is usually used instead of aluminum in the interconnection structure, and Low-k materials (dielectric constant k < 3.9) are used instead of silicon dioxide. It is known that Low-k materials are usually used in Silicon dioxide is doped with carbon and hydrogen. Copper helps reduce the resistance of the interconnect metal and increases the reliability of the interconnect structure, while Low-k materials help reduce parasitic capacitance between interconnect structures by providing a lower dielectric constant.

However, compared with silicon dioxide materials, Low-k materials have lower mechanical strength and lower Young's modulus. Moreover, Low-k materials weaken interlayer adhesion and make the wafer susceptible to high stress in subsequent packaging processes. Strain or high stress, such as shear stress during the cutting process, compressive stress during wire bonding and flip chip mounting, or mismatch in coefficient of thermal expansion (CTE) after molding or dispensing. The resulting shear stress, under these strains or stresses, may cause damage or destruction of the interconnect structure, such as causing Low-k collapse or interface delamination between copper and Low-k materials.

Specifically, shear stress during the cutting process can easily lead to delamination of Low-k materials, compressive stress during wire bonding can easily lead to cracking of Low-k materials, and the shear stress caused by the mismatch of thermal expansion coefficients in dispensing can also lead to low-k material delamination. It is easy to cause delamination of Low-k materials.

Based on this, embodiments of the present application provide a new wafer structure and chip. The wafer structure includes a stacked base layer and a plurality of dielectric layers; it also includes: a bonding portion and a plurality of conductive layers; a plurality of dielectric layers and Multiple conductive layers are located between the base layer and the bonding part; each dielectric layer corresponds to a conductive layer; a reinforcing member is also provided inside the dielectric layer close to the bonding part; the projection of the reinforcing member in the thickness direction of the wafer structure is consistent with The projection of the conductive layer close to the bonding portion in the thickness direction of the wafer structure at least partially overlaps, which can avoid or reduce the risk of the wafer being susceptible to high strain or high stress in subsequent packaging processes, resulting in damage or destruction of the interconnect structure, such as Technical issues leading to Low-k collapse or interface delamination of copper and Low-k.

Taking a specific embodiment as an example, the specific structure of the wafer structure will be introduced below with reference to the accompanying drawings.

Referring to Figures 1 and 2, an embodiment of the present application provides a wafer structure 100. In the embodiment of the present application, the wafer structure 100 may at least include: a stacked base layer 110 and a plurality of dielectric layers, wherein the base layer 110 may include a functional part 111, and the wafer structure 100 may further include a bonding part 130 and a plurality of conductive layers.

Specifically, taking the number of dielectric layers as four as an example, in FIG. 2 , the plurality of dielectric layers may include a first dielectric layer 121 , a second dielectric layer 122 , a third dielectric layer 123 and a fourth dielectric layer that are stacked in sequence. Layer 124 , wherein the first dielectric layer 121 is located between the base layer 110 and the second dielectric layer 122 , and the fourth dielectric layer 124 is located between the third dielectric layer 123 and the bonding portion 130 .

Taking the number of conductive layers as four as an example, in Figure 2, the plurality of conductive layers may include a first conductive layer 141, a second conductive layer 142, a third conductive layer 143 and a fourth conductive layer 144 that are stacked in sequence. The first conductive layer 141 may be located between the base layer 110 and the second conductive layer 142 , and the fourth conductive layer 144 may be located between the third conductive layer 143 and the bonding part 130 .

In this embodiment of the present application, multiple dielectric layers and multiple conductive layers are located between the base layer 110 and the bonding portion 130 , that is to say, the first dielectric layer 121 , the second dielectric layer 122 , and the third dielectric layer 123 The fourth dielectric layer 124, the first conductive layer 141, the second conductive layer 142, the third conductive layer 143 and the fourth conductive layer 144 are all located between the base layer 110 and the bonding part 130, and each dielectric layer corresponds to one conductive layer. , that is, the first dielectric layer 121 corresponds to the first conductive layer 141, the second dielectric layer 122 corresponds to the second conductive layer 142, the third dielectric layer 123 corresponds to the third conductive layer 143, the fourth dielectric layer 124 and The fourth conductive layer 144 corresponds.

Moreover, a conductive via hole may be provided inside each dielectric layer, and the conductive via hole is connected to the corresponding conductive layer. Specifically, the first conductive via hole may or may not be provided inside the first dielectric layer 121 (see FIG. 3 ). Continuing to refer to FIG. 3 , a second conductive via 1221 may be provided inside the second dielectric layer 122 , and the second conductive via 1221 is connected to the corresponding second conductive layer 142 . Similarly, the third dielectric layer 123 A third conductive via 1231 may be provided inside, and the third conductive via 1231 may be connected to the corresponding third conductive layer 143. Similarly, a fourth conductive via 1241 may be provided inside the fourth dielectric layer 124. The conductive vias 1241 are connected to the corresponding fourth conductive layer 144 .

In the embodiment of the present application, as shown in FIGS. 2 and 3 , the conductive layer and conductive vias close to the bonding portion 130 are made of copper. That is to say, the fourth conductive layer 144 and the fourth conductive via 1241 are made of copper.

In the wafer structure 100 , the material of the conductive layer close to the bonding portion 130 and the conductive via hole close to the bonding portion 130 of the wafer structure 100 are made of copper. The material used for the conductive layer of the bonding portion 130 and the material used for the conductive via holes close to the bonding portion 130 is aluminum. The fourth conductive layer 144 and the fourth conductive via hole 1241 using a copper metal layer have high strength and can The compressive stress introduced by the bonding wire during the bonding process is relieved to a large extent, thereby improving the reliability of the dielectric layer.

Therefore, the embodiments of the present application can avoid or reduce the risk that the wafer is susceptible to high strain or high stress in the subsequent packaging process, causing damage or destruction of the interconnect structure, such as causing Low-k collapse or the interface between copper and Low-k materials. Layered technical issues.

It should be noted that in the embodiment of the present application, the metal thickness of the fourth conductive layer 144 may be 1um~3um. For example, the metal thickness of the fourth conductive layer 144 may be 1um, 1.5um, 2um, 2.5um or 3um, etc. , the embodiments of the present application are not limited to this, nor are they limited to the above examples.

It is easy to understand that in some embodiments, a reinforcement 150 may also be provided inside the dielectric layer close to the bonding portion 130 , that is, a reinforcement 150 may also be provided inside the fourth dielectric layer 124 (see FIG. 2 and FIG. 4), by disposing the reinforcing member 150 inside the fourth dielectric layer 124, the reinforcing member 150 can increase the structural strength of the fourth dielectric layer 124.

In addition, the projection of the reinforcement member 150 in the thickness direction of the wafer structure 100 and the projection of the conductive layer close to the bonding portion 130 in the thickness direction of the wafer structure 100 may at least partially overlap. That is, the projection of the reinforcement 150 in the thickness direction of the wafer structure 100 and the projection of the fourth conductive layer 144 in the thickness direction of the wafer structure 100 may at least partially overlap.

By designing the projection of the reinforcement 150 in the thickness direction of the wafer structure 100 to at least partially overlap with the projection of the fourth conductive layer 144 in the thickness direction of the wafer structure 100 , the reinforcement 150 can act on the fourth conductive layer 144 It has a certain strength supporting effect, which can further enhance the interlayer structure strength of the wafer structure 100 .

In one possible implementation, the projection of the reinforcement 150 in the thickness direction of the wafer structure 100 is entirely located within the projection of the conductive layer close to the bonding portion 130 in the thickness direction of the wafer structure 100 , that is, reinforcement The projection of the component 150 in the thickness direction of the wafer structure 100 is entirely within the projection of the fourth conductive layer 144 in the thickness direction of the wafer structure 100 .

By designing the projection of the reinforcement 150 in the thickness direction of the wafer structure 100 to be entirely located within the projection of the fourth conductive layer 144 in the thickness direction of the wafer structure 100 , the entire reinforcement 150 can act on the fourth conductive layer 144 It has a strength supporting effect, thereby better improving the interlayer structure strength of the wafer structure 100 .

It should be noted that in the embodiment of the present application, the number of reinforcement members 150 may be multiple, and the multiple reinforcement members 150 may be located around the conductive through holes close to the bonding portion 130 , that is, the multiple reinforcement members 150 may be evenly spaced. Located around the fourth conductive via 1241.

The greater the number of reinforcing members 150 , the stronger the strength supporting effect close to the fourth conductive layer 144 is. By designing the number of reinforcing members 150 to be multiple, and the multiple reinforcing members 150 being located around the fourth conductive through hole 1241, it is possible to ensure that the strength support effect of the multiple reinforcing members 150 on the fourth conductive layer 144 is more balanced and effective, and thus The interlayer structure strength of the wafer structure 100 can be better improved.

In a possible implementation manner, the material used for the reinforcing member 150 may be a high-strength polymer structure. For example, the material used for the reinforcing member 150 may be carbon nanotube (CNT).

Carbon nanotubes, also known as Bucky tubes, are one-dimensional nanoscale quantum materials with a special structure (radial dimensions are on the order of nanometers, axial dimensions are on the order of microns, and both ends of the tube are basically sealed) and are lightweight. , the hexagonal structure is perfectly connected and has excellent mechanical, electrical and chemical properties. Carbon nanotubes are mainly coaxial circular tubes composed of several to dozens of layers of carbon atoms arranged in a hexagonal shape. The distance between the layers of carbon nanotubes is fixed, about 0.34nm, and the diameter is generally 2~20nm. Carbon nanotubes can be divided into three types: zigzag carbon nanotubes, armchair carbon nanotubes and spiral carbon nanotubes according to the different orientations of the carbon hexagons along the axial direction. Among them, spiral carbon nanotubes have chirality, while zigzag carbon nanotubes and armchair carbon nanotubes have no chirality.

At present, carbon nanotubes have been used in chip front-end device field effect transistors (Field EffectTransistor, FET), that is, CNT-FET. The corresponding chemical vapor deposition (CVD) process is mature and can meet the processing needs in the later stages of wafer structure 100 processing.

In addition, carbon nanotubes have a Young's modulus that far exceeds that of Low-k materials (specifically, the Young's modulus of carbon nanotubes is 1000Gpa, and the Young's modulus of Low-k materials is 5-10Gpa). Carbon nanotubes It also has a k value close to Low-k materials (k value is generally 2-3), which can improve the strength of the interlayer dielectric layer without almost reducing chip performance.

It should be noted that in the embodiment of the present application, the size of the reinforcement 150 can be flexibly selected according to the size of the bonding part 130, the diameter of the bonding wire, and the diameter of the bonding ball. The structural length and width of a single reinforcement 150 They may vary between 15-40 μm respectively, and the height of the reinforcement 150 may be the same as the fourth dielectric layer 124. For example, the heights of the fourth dielectric layer 124 and the reinforcement 150 may be 800-1000 nm respectively. The embodiments of the present application are This is not limiting and is not limited to the above examples.

In some embodiments, the first dielectric layer 121 , the second dielectric layer 122 and the third dielectric layer 123 may be made of at least Low-k materials, and the fourth dielectric layer 124 may be made of silicon dioxide.

Among them, the Chinese name of Low-k material is low dielectric constant material, which is an insulating material. Specifically, it refers to a non-conductive material. Low-k materials refer to silicon dioxide doped with carbon and hydrogen. The mechanical strength of silicon dioxide is higher than that of Low-k materials. Compared with silicon dioxide, Low-k materials are beneficial to improving chip performance. By combining the first dielectric layer 121, the second dielectric layer 122 and the third dielectric layer The material used in 123 is at least designed to be a Low-k material, which can improve the performance of the wafer structure 100 .

Specifically, in the embodiment of the present application, the first dielectric layer 121, the second dielectric layer 122 and the third dielectric layer 123 may respectively include: a first part 125 and a second part 126, wherein, as shown in Figures 2 and 5 , the second part 126 is located on the outer periphery of the first part 125, the first part 125 may be made of Low-k material, and the second part 126 may be made of silicon dioxide.

By designing the first dielectric layer 121 , the second dielectric layer 122 and the third dielectric layer 123 to include the first part 125 and the second part 126 respectively, the first dielectric layer 121 may include the first part 125 and the second part 126 as For example, the first part 125 is made of Low-k material, the second part 126 is located on the outer periphery of the first part 125, and the second part 126 is made of silica, because silica has high mechanical strength. , can prevent laser cutting, plastic sealing, dispensing and other processes from affecting the second part 126 (ie, the cutting edge) of the first dielectric layer 121. For example, it can prevent the Low-k material from delaminating due to excessive shear stress.

It should be noted that in the embodiment of the present application, the structural height of the second part 126 is the same as the structural height of the first part 125 located in the same dielectric layer, and both may be 300 nm-500 nm. For example, the structural height of the second part 126 It can be 300nm, 350nm, 400nm, 450nm or 500nm, etc.

The structural width of the second part 126 may be 2um-3um. For example, the structural width of the second part 126 may be 2um, 2.2um, 2.4um, 2.6um, 2.8um or 3um, etc. This is not considered in the embodiment of the present application. Not limited to the above examples.

It should be noted here that the numerical values and numerical ranges involved in the embodiments of the present invention are approximate values. Affected by the manufacturing process, there may be a certain range of errors. Those skilled in the art can consider these errors to be ignored.

In addition, in a possible implementation, a first plating layer 161 can also be provided between the conductive layer close to the bonding portion 130 and the bonding portion 130 , that is, there can also be a first plating layer 161 between the fourth conductive layer 144 and the bonding portion 130 . A first plating layer 161 is provided, and the material used for the first plating layer 161 may be nickel.

By disposing the first plating layer 161 between the fourth conductive layer 144 and the bonding portion 130 , that is, the first plating layer 161 is disposed on the side of the fourth conductive layer 144 facing the bonding portion 130 . The material used for the first plating layer 161 is: Nickel. Nickel as the first plating layer 161 can avoid or alleviate the technical problem that the copper metal of the fourth conductive layer 144 is prone to oxidative corrosion.

Furthermore, a second plating layer 162 may be disposed between the first plating layer 161 and the bonding part 130, and the material of the second plating layer 162 may be gold.

By disposing the first plating layer 161 between the first plating layer 161 and the bonding part 130, that is, disposing the second plating layer 162 on the side of the first plating layer 161 facing the bonding part 130, and the material of the second plating layer 162 is gold. Using gold as the second plating layer 162 can further avoid or alleviate the technical problem that copper metal is prone to oxidative corrosion on the basis of the first plating layer 161 .

It should be noted that in the embodiment of the present application, the thickness of the first plating layer 161 and the first plating layer 161 can be flexibly selected between 1-100 μm according to actual process requirements, and is not limited here.

In an optional embodiment, at least one passivation layer can be provided on the side of the dielectric layer close to the bonding portion 130 facing the bonding portion 130 , that is, the fourth dielectric layer 124 can be provided on the side facing the bonding portion 130 At least one passivation layer can also be provided.

For example, in FIG. 2 , a first passivation layer 171 and a second passivation layer 172 are provided on the side of the fourth dielectric layer 124 facing the bonding portion 130 .

By further disposing at least one passivation layer on the side of the fourth dielectric layer 124 facing the bonding portion 130 , the passivation layer can play a role in protecting the fourth dielectric layer 124 .

In addition, in the embodiment of the present application, the passivation layer and the bonding portion 130 can avoid each other. The passivation layer and the bonding portion 130 can avoid each other to prevent the passivation layer from interfering with the bonding portion 130 .

It can be understood that in some embodiments, the wafer structure 100 may also include: multiple etching stop layers. Specifically, taking the number of etching stop layers as five as an example, in FIG. 2, multiple etching stop layers The stop layer may include: a first etching stop layer 181, a second etching stop layer 182, a third etching stop layer 183, a fourth etching stop layer 184 and a fifth etching stop layer 185, where the first The etching stop layer 181 is located between the base layer 110 and the first dielectric layer 121 , the second etching stop layer 182 is located between the first dielectric layer 121 and the second dielectric layer 122 , and the third etching stop layer 183 is located between the second dielectric layer 121 and the second dielectric layer 122 . Between the layer 122 and the third dielectric layer 123, the fourth etching stop layer 184 is located between the third dielectric layer 123 and the fourth dielectric layer 124, and the fourth etching stop layer 184 is located between the fourth dielectric layer 124 and the first passivation layer 122. between layers 171.

In the related art, the number of dielectric layers in the wafer structure 100a is five. Referring to Figures 6, 8 and 9, the first dielectric layer 121a, the second dielectric layer 122a, the third dielectric layer 123a, the fourth dielectric layer The layer 124a and the fifth dielectric layer 127a are stacked in sequence. The first dielectric layer 121a, the second dielectric layer 122a and the third dielectric layer 123a are made of Low-k material. The fourth dielectric layer 124a and the fifth dielectric layer 127a The material used is silicon dioxide.

In addition, each dielectric layer corresponds to a conductive layer. Taking the number of conductive layers in the wafer structure 100a as four as an example, in FIG. 6, multiple conductive layers may include a first conductive layer 141a, a second conductive layer 141a, The conductive layer 142a, the third conductive layer 143a, the fourth conductive layer 144a and the fifth conductive layer 145a, wherein the first dielectric layer 121a corresponds to the first conductive layer 141a, and the second dielectric layer 122a and the second conductive layer 142a correspond to each other. Correspondingly, the third dielectric layer 123a corresponds to the third conductive layer 143a, the fourth dielectric layer 124a corresponds to the fourth conductive layer 144a, and the fifth dielectric layer 127a corresponds to the fifth conductive layer 145a.

A conductive via hole is provided inside each dielectric layer, and the conductive via hole is connected with the corresponding conductive layer. Specifically, the first conductive via hole may or may not be provided inside the first dielectric layer 121a (see FIG. 6). Continuing to refer to Figure 6, a second conductive via 1221a may be provided inside the second dielectric layer 122a, and the second conductive via 1221a is connected to the corresponding second conductive layer 142a. Similarly, the third dielectric layer 123a A third conductive via 1231a may be provided inside, and the third conductive via 1231a may be connected to the corresponding third conductive layer 143a. A fourth conductive via 1241a may be provided inside the fourth dielectric layer 124a. The fourth conductive via 1241a is connected to the corresponding fourth conductive layer 144a. A fifth conductive via 1271a may be provided inside the fifth dielectric layer 127a. The fifth conductive via 1271a is connected to the corresponding fifth conductive layer 145a.

In the related art, as shown in FIGS. 6 and 7 , the conductive layer and conductive vias close to the bonding portion 130 are made of aluminum. That is to say, the fifth conductive layer 145a and the fifth conductive via 1271a are made of aluminum.

In the wafer structure 100 provided by the embodiment of the present application, the wafer structure 100 is formed by combining the material used for the conductive layer close to the bonding part 130 and the conductive via hole close to the bonding part 130 (ie, the fourth conductive hole in FIG. 2 The material used for the layer 144a and the fourth conductive via 1241a) is copper. The strength E of copper is generally 120 GPa, and the strength E of aluminum is generally 70 GPa. Compared with the conductive layer close to the bonding portion 130 in the related art, The material used for the conductive via holes close to the bonding portion 130 (ie, the fifth conductive layer 145a and the fifth conductive via hole 1271a in FIG. 6 ) is aluminum, and the fourth conductive layer 144 and the fourth conductive layer 144 are made of copper metal layers. The conductive via 1241 itself has high strength, which can alleviate the compressive stress introduced by the bonding wire during the bonding process to a large extent, thereby improving the reliability of the dielectric layer.

It is easy to understand that compared with related technologies, the embodiment of the present application also saves a dielectric layer (fifth dielectric layer 127a), a conductive layer (fifth conductive layer 145a) and a fifth conductive via 1271a, which can It has the effect of reducing wafer structure processing costs.

In addition, the related art does not provide silicon dioxide with high mechanical strength on the outer periphery or outer edge of the first dielectric layer 121a, the second dielectric layer 122a and the third dielectric layer 123a using Low-k materials, so it cannot prevent laser cutting, Molding, dispensing and other processes affect the outer edges (i.e. cutting edges) of the first dielectric layer 121a, the second dielectric layer 122a and the third dielectric layer 123a. In other words, the wafer structure 100a in the related art cannot avoid Technical problem of delamination of Low-k materials caused by excessive shear stress.

Moreover, in the related art, the reinforcement 150 is not provided inside the dielectric layer close to the bonding portion 130, that is, the reinforcement 150 is not provided inside the fifth dielectric layer 127a (see Figures 6 and 8), and In the embodiment of the present application, the reinforcing member 150 is further disposed inside the fourth dielectric layer 124 , and the reinforcing member 150 can increase the structural strength of the dielectric layer (the fourth dielectric layer 124 ) close to the bonding portion 130 .

In addition, the greater the number of reinforcement members 150 , the stronger the strength supporting effect close to the fourth conductive layer 144 is. In the wafer structure 100 in the embodiment of the present application, the number of reinforcement members 150 is designed to be multiple. The plurality of reinforcement members 150 are located around the fourth conductive through hole 1241, which can ensure that the plurality of reinforcement members 150 are effective against the fourth conductive layer. The strength supporting effect of 144 is more balanced and effective, which can better improve the interlayer structure strength of the wafer structure 100 .

In addition, embodiments of the present application also provide a chip, which may at least include: the wafer structure 100 in any of the above items.

The chip provided by the embodiment of the present application may at least include a wafer structure 100. The wafer structure 100 is made of a material used for the conductive layer close to the bonding part 130 and a material used for the conductive via hole close to the bonding part 130. Copper, compared to the material used in the conductive layer close to the bonding part 130 and the material used in the conductive via hole close to the bonding part 130 in the related art, the copper metal layer has higher strength and can be used in larger To a certain extent, the compressive stress introduced by the bonding wire during the bonding process can be alleviated, thereby improving the reliability of the dielectric layer, thereby improving the overall reliability of the wafer structure 100 .

Therefore, the embodiments of the present application can avoid or reduce the risk that the wafer is susceptible to high strain or high stress in the subsequent packaging process, causing damage or destruction of the interconnect structure, such as causing Low-k collapse or the interface between copper and Low-k. Layered technical issues.

In the description of the embodiments of this application, it should be noted that, unless otherwise clearly stated and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection or a fixed connection. Indirect connection through an intermediary can be the internal connection between two elements or the interaction between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of this application can be understood according to specific circumstances.

The devices or elements mentioned in the embodiments of this application or by implication must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the embodiments of this application. In the description of the embodiments of this application, "plurality" means two or more, unless otherwise precisely and specifically specified.

The terms "first", "second", "third", "fourth", etc. (if present) in the description and claims of the embodiments of this application and the above-mentioned drawings are used to distinguish similar objects, and It is not necessary to describe a specific order or sequence. It is to be understood that data so used are interchangeable under appropriate circumstances such that embodiments of the embodiments of the application described herein can, for example, be practiced in sequences other than those illustrated or described herein. In addition, the terms "may include" and "have" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units and need not be limited to those explicitly listed. may include other steps or elements not expressly listed or inherent to the process, method, product or apparatus.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present application, but not to limit them. Although the embodiments of the present application have been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art It should be understood that the technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features can be equivalently replaced, and these modifications or substitutions do not deviate from the essence of the corresponding technical solutions from the embodiments of the present application. The scope of the technical solutions of each embodiment.

Claims (10)

1. A wafer structure, characterized in that it at least includes: A stacked base layer and a plurality of dielectric layers, the plurality of dielectric layers including a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer stacked in sequence; The first dielectric layer, the second dielectric layer and the third dielectric layer respectively include: a first part and a second part; The second part is located on the periphery of the first part; The material used in the first part is Low-k material, and the material used in the second part is silicon dioxide; It also includes: a bonding portion and a plurality of conductive layers; the plurality of dielectric layers and the plurality of conductive layers are located between the base layer and the bonding portion; Each dielectric layer corresponds to one conductive layer; A reinforcing member is also provided inside the dielectric layer close to the bonding portion; The projection of the reinforcement member in the thickness direction of the wafer structure at least partially overlaps the projection of the conductive layer close to the bonding portion in the thickness direction of the wafer structure. 2. The wafer structure according to claim 1, wherein each dielectric layer is provided with a conductive via hole inside, and the conductive via hole is connected to the corresponding conductive layer; The conductive layer and the conductive via hole close to the bonding part are made of copper. 3. The wafer structure according to claim 2, wherein the projection of the reinforcement member in the thickness direction of the wafer structure is all located near the bonding portion of the conductive layer on the wafer structure. within the projection in the thickness direction of the circular structure. 4. The wafer structure according to claim 3, wherein the number of the reinforcement members is multiple, and the plurality of reinforcement members are located around the conductive via holes close to the bonding portion. 5. The wafer structure according to claim 3, wherein the reinforcing member is made of carbon nanotubes. 6. The wafer structure according to any one of claims 1 to 5, characterized in that the plurality of conductive layers include: a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer that are stacked in sequence. conductive layer; The first dielectric layer is located between the base layer and the second dielectric layer, and the fourth dielectric layer is located between the third dielectric layer and the bonding portion; The first conductive layer is located between the base layer and the second conductive layer, and the fourth conductive layer is located between the third conductive layer and the bonding portion; The material used in the first dielectric layer, the second dielectric layer and the third dielectric layer is at least Low-k material, and the material used in the fourth dielectric layer is silicon dioxide. 7. The wafer structure according to any one of claims 1 to 5, characterized in that a first plating layer is further provided between the conductive layer close to the bonding portion and the bonding portion; The first plating layer is made of nickel. 8. The wafer structure according to claim 7, wherein a second plating layer is further provided between the first plating layer and the bonding portion; The second plating layer is made of gold. 9. The wafer structure according to any one of claims 1 to 5, characterized in that at least one passivation layer is provided on a side of the dielectric layer close to the bonding portion facing the bonding portion; The passivation layer and the bonding portion avoid each other. 10. A chip, characterized in that it at least includes: the wafer structure according to any one of the above claims 1-9.