CN117059590B

CN117059590B - Wafer structure and chip

Info

Publication number: CN117059590B
Application number: CN202311311285.6A
Authority: CN
Inventors: 李洽; 温娟
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2023-10-11
Filing date: 2023-10-11
Publication date: 2024-03-12
Anticipated expiration: 2043-10-11
Also published as: CN117059590A

Abstract

The embodiment of the application provides a wafer structure and a chip, wherein the wafer structure comprises a base layer and a plurality of medium layers which are stacked; further comprises: a bonding portion and a plurality of conductive layers; the plurality of dielectric layers and the plurality of conductive layers are located between the base layer and the bonding portion; each dielectric layer corresponds to one conductive layer; a reinforcing piece is further arranged inside the dielectric layer close to the bonding part; the projection of the reinforcement piece in the thickness direction of the wafer structure is at least partially overlapped with the projection of the conductive layer close to the bonding part in the thickness direction of the wafer structure, so that the technical problems that the wafer is easy to be subjected to high strain or high stress in a subsequent packaging process to cause the damage or destruction of an interconnection structure, such as Low-k collapse or interface delamination of copper and Low-k, can be avoided or relieved.

Description

Wafer structure and chip

Technical Field

Embodiments of the present disclosure relate to the field of semiconductor technologies, and in particular, to a wafer structure and a chip.

Background

A wafer is generally referred to as a wafer because it is a wafer in which silicon chips used for manufacturing a silicon semiconductor integrated circuit are formed in a circular shape. At present, various circuit element structures can be manufactured on a silicon wafer, and the semiconductor element product with specific electrical functions is obtained.

Currently, conventional interconnect structures for integrated circuits in wafers are typically formed using aluminum as the metal interconnect and silicon dioxide as the dielectric layer. However, as integrated circuits are continuously scaled down, conventional interconnect structures often suffer from interconnect delays due to high resistance and parasitic wiring capacitance, thus limiting the speed of high performance integrated circuits. Because of these problems, in the related art, copper material is generally used instead of aluminum material and Low-k material (k < 3.9) is used instead of silicon dioxide in the interconnect structure. Copper helps to reduce the resistance of the interconnect metal and increase the reliability of the interconnect structure, while Low-k materials help to reduce parasitic capacitance between the interconnect structures by providing a lower dielectric constant.

However, the Low-k material has reduced mechanical strength, reduced young's modulus, reduced interlayer adhesion, and the wafer is susceptible to high strain or stress in subsequent packaging processes, which may lead to damage or destruction of the interconnect structure, such as Low-k collapse or interfacial delamination of copper and Low-k.

Disclosure of Invention

The wafer structure and the chip can avoid or relieve the technical problems that the wafer is easy to be subjected to high strain or high stress in the subsequent packaging process to cause the damage or the destruction of an interconnection structure, such as Low-k collapse or interface delamination of copper and Low-k.

In a first aspect, an embodiment of the present application provides a wafer structure, at least including: a base layer and a plurality of dielectric layers which are laminated; further comprises: a bonding portion and a plurality of conductive layers; the plurality of dielectric layers and the plurality of conductive layers are located between the base layer and the bonding portion; each dielectric layer corresponds to one conductive layer, and a reinforcing piece is arranged in the dielectric layer close to the bonding part; the projection of the reinforcement member in the thickness direction of the wafer structure at least partially overlaps with the projection of the conductive layer near the bonding portion in the thickness direction of the wafer structure.

According to the wafer structure provided by the embodiment of the application, the reinforcing piece is further arranged in the medium layer close to the bonding part, the reinforcing piece can play a role in increasing the structural strength of the medium layer, and then the reliability of the medium layer can be improved. In addition, the projection of the reinforcing piece in the thickness direction of the wafer structure is designed to be at least partially overlapped with the projection of the conductive layer close to the bonding part in the thickness direction of the wafer structure, and the reinforcing piece can play a certain strength supporting role on the conductive layer close to the bonding part, so that the interlayer structure strength of the wafer structure can be further improved. Therefore, the embodiment of the application can avoid or relieve the technical problems that the wafer is easy to be subjected to high strain or high stress in the subsequent packaging process, so that the interconnection structure is damaged or destroyed, for example, the Low-k collapse or the interface layering of copper and Low-k is caused.

In one possible implementation manner, each dielectric layer is internally provided with a conductive through hole, and the conductive through holes are communicated with the corresponding conductive layers; the conductive layer and the conductive through hole near the bonding part are made of copper.

The bonding wire is characterized in that the conducting layer close to the bonding part is made of copper, and the conducting through hole close to the bonding part is made of aluminum compared with the conducting layer close to the bonding part and the conducting through hole close to the bonding part in the related art, the strength of the copper metal layer is high, the compressive stress of the bonding wire in the bonding process can be relieved to a greater extent, and then the reliability of the dielectric layer can be improved.

In one possible implementation, the projections of the stiffener in the thickness direction of the wafer structure are all located within the projections of the conductive layer near the bond in the thickness direction of the wafer structure.

Through with the projection design of reinforcement in the thickness direction of wafer structure for all being located in the projection of the conducting layer in the thickness direction of wafer structure that is close to bonding portion, whole reinforcement can play intensity supporting role to the conducting layer that is close to bonding portion, and then the interlaminar structural strength of promotion wafer structure that can be better.

In one possible implementation, the number of the reinforcing members is plural, and plural reinforcing members are located around the conductive through hole near the bonding portion.

The greater the number of stiffeners, the stronger the strength support of the conductive layer near the bond. Through designing the quantity of reinforcement into a plurality ofly, a plurality of reinforcements all are located around being close to the conductive through hole of bonding portion, can ensure that a plurality of reinforcements are more balanced effective to the intensity supporting effect of the conductive layer that is close to bonding portion, and then the interlaminar structural strength of promotion wafer structure that can be better.

In one possible implementation, the reinforcement member is made of carbon nanotubes.

The carbon nanotube is also called as a Baki tube, is a one-dimensional nano quantum material with a special structure (the radial dimension is nano-scale, the axial dimension is micro-scale, and the two ends of the tube are basically sealed), has light weight, perfect connection of a hexagonal structure and excellent mechanical, electrical and chemical properties. Carbon nanotubes mainly consist of layers to tens of layers of coaxial round tubes of carbon atoms arranged in a hexagonal manner. The carbon nanotube layer is kept at a fixed distance from layer to layer, about 0.34nm, and the diameter is generally 2-20 nm. The carbon nanotubes can be divided into three types of zigzag carbon nanotubes, armchair carbon nanotubes and spiral carbon nanotubes according to different orientations of the carbon hexagons in the axial direction. Wherein, the spiral carbon nanotube has chirality, and the zigzag carbon nanotube and the armchair carbon nanotube have no chirality.

In one possible implementation manner, the plurality of dielectric layers include a structure that is stacked in sequence: the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer;

the plurality of conductive layers include the stacked arrangement in proper order: a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer;

the first dielectric layer is positioned between the base layer and the second dielectric layer, and the fourth dielectric layer is positioned between the third dielectric layer and the bonding part;

the first conductive layer is positioned between the base layer and the second conductive layer, and the fourth conductive layer is positioned between the third conductive layer and the bonding portion;

the materials adopted by the first dielectric layer, the second dielectric layer and the third dielectric layer are at least Low-k materials, and the materials adopted by the fourth dielectric layer are silicon dioxide.

The Low-k material is an insulating material, in particular a non-conductive material. Low-k materials refer to the incorporation of carbon and hydrogen into silicon dioxide. The Low-k material is beneficial to improving the performance of the chip, and the performance of the wafer structure can be improved by designing the materials adopted by the first dielectric layer, the second dielectric layer and the third dielectric layer to be at least Low-k materials.

In one possible implementation manner, the first dielectric layer, the second dielectric layer, and the third dielectric layer respectively include: a first portion and a second portion;

the second portion is located at the periphery of the first portion;

the first part is made of Low-k material, and the second part is made of silicon dioxide.

By respectively designing the first dielectric layer, the second dielectric layer and the third dielectric layer to comprise a first part and a second part, taking the first dielectric layer comprising the first part and the second part as an example, the first part adopts a Low-k material, the second part is positioned at the periphery of the first part, and the second part adopts silicon dioxide, so that the second part (namely, a cutting edge) of the first dielectric layer can be prevented from being influenced by processes such as laser cutting, plastic packaging, dispensing and the like, for example, the delamination of the Low-k material caused by overlarge shearing stress can be avoided.

In one possible implementation manner, a first plating layer is further arranged between the conductive layer near the bonding part and the bonding part;

the first coating is made of nickel.

Through setting up first cladding material between the conducting layer that is close to bonding portion and bonding portion, set up first cladding material on the conducting layer that is close to bonding portion towards bonding portion's one side promptly, the material that first cladding material adopted is nickel, and nickel can avoid or alleviate copper metal and take place the technical problem that oxidation corrosion easily as first cladding material.

In one possible implementation manner, a second plating layer is further arranged between the first plating layer and the bonding part;

the second coating is made of gold.

Through setting up first cladding material between first cladding material and bonding portion, set up the second cladding material on the one side of first cladding material towards bonding portion promptly, the material that the second cladding material adopted is gold, and gold can further avoid or alleviate the technical problem that copper metal takes place the oxidation corrosion easily on the basis of first cladding material as the second cladding material.

In one possible implementation manner, at least one passivation layer is further arranged on one surface, facing the bonding portion, of the dielectric layer close to the bonding portion;

the passivation layer and the bonding part are mutually avoided.

The passivation layer can play a role in protecting the dielectric layer by further arranging at least one passivation layer on one surface, close to the bonding part, of the dielectric layer facing the bonding part. In addition, the passivation layer and the bonding part are mutually avoided, and interference or interference of the passivation layer on the bonding part can be avoided.

In a second aspect, embodiments of the present application further provide a chip, where the chip at least includes: a wafer structure as claimed in any preceding claim.

The chip that this application embodiment provided, chip include wafer structure at least, and wafer structure still is provided with the reinforcement through the inside at the dielectric layer that is close to bonding portion, and the reinforcement can play the effect that increases dielectric layer structural strength, and then can improve dielectric layer's reliability. In addition, the projection of the reinforcing piece in the thickness direction of the wafer structure is designed to be at least partially overlapped with the projection of the conductive layer close to the bonding part in the thickness direction of the wafer structure, and the reinforcing piece can play a certain strength supporting role on the conductive layer close to the bonding part, so that the interlayer structure strength of the wafer structure can be further improved. Therefore, the embodiment of the application can avoid or relieve the technical problems that the wafer is easy to be subjected to high strain or high stress in the subsequent packaging process, so that the interconnection structure is damaged or destroyed, for example, the Low-k collapse or the interface layering of copper and Low-k is caused.

Drawings

FIG. 1 is a schematic diagram of an overall structure of a wafer structure according to an embodiment of the present disclosure;

FIG. 2 is a schematic cross-sectional view of a wafer structure according to an embodiment of the present disclosure;

FIG. 3 is a top view of a fourth conductive layer in a wafer structure according to one embodiment of the present disclosure;

FIG. 4 is a top view of a fourth dielectric layer in a wafer structure according to one embodiment of the present disclosure;

fig. 5 is a top view of a first dielectric layer, a second dielectric layer, or a third dielectric layer in a wafer structure according to an embodiment of the present disclosure;

FIG. 6 is a schematic cross-sectional view of a wafer structure according to the related art;

FIG. 7 is a top view of a fourth conductive layer of a related art wafer structure;

FIG. 8 is a top view of a fourth dielectric layer in a related art wafer structure;

fig. 9 is a top view of a first dielectric layer, a second dielectric layer, or a third dielectric layer in a wafer structure according to the related art.

Reference numerals illustrate:

100 100 a-wafer structure; 110-a base layer;

111-a functional part; 121, 121 a-a first dielectric layer;

122 122 a-a second dielectric layer; 1221, 1221 a-second conductive vias;

123 123 a-a third dielectric layer; 1231, 1231 a-third conductive vias;

124 124 a-fourth dielectric layer; 1241, 1241 a-fourth conductive vias;

125-a first part; 126-a second part;

127 a-a fifth dielectric layer; 1271 a-fifth conductive vias;

130-a bond; 141, 141 a-a first conductive layer;

142 142 a-a second conductive layer; 143, 143 a-a third conductive layer;

144 144 a-fourth conductive layers; 145 a-a fifth conductive layer;

150-stiffeners; 161-first plating;

162-second plating; 171-a first passivation layer;

172-a second passivation layer; 181-a first etch stop layer;

182-a second etch stop layer; 183-third etch stop layer;

184-fourth etch stop layer; 185-fifth etch stop layer.

Detailed Description

The terminology used in the description of the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application, as will be described in detail with reference to the accompanying drawings.

Currently, conventional interconnect structures for integrated circuits in wafers are typically formed using aluminum as the metal interconnect and silicon dioxide as the dielectric layer. However, as integrated circuits are continuously scaled down, for example, devices scale down from 90nm nodes to 65nm nodes and further scale down to smaller nodes, conventional interconnect structures often suffer from interconnect delays due to high resistance and parasitic wiring capacitance, which are major factors limiting the speed of high performance integrated circuits.

Because of these problems, in the related art, copper is generally used instead of aluminum in the interconnect structure, and a Low-k material (dielectric constant k < 3.9) is used instead of silicon dioxide, it being understood that the Low-k material is generally doped with carbon and hydrogen in silicon dioxide. Copper helps to reduce the resistance of the interconnect metal and increase the reliability of the interconnect structure, while Low-k materials help to reduce parasitic capacitance between the interconnect structures by providing a lower dielectric constant.

However, low-k materials have reduced mechanical strength and a lower young's modulus compared to silicon dioxide materials, and the Low-k materials have reduced interlayer adhesion, are susceptible to high strain or stress during subsequent packaging processes, such as shear stress during dicing processes, compressive stress during wire bonding and flip-chip mounting processes, and mismatch in coefficient of thermal expansion (coefficient of thermal expansion, CTE) after plastic packaging or dispensing, and may result in damage or destruction of interconnect structures under such strain or stress, such as Low-k collapse or interfacial delamination between copper and Low-k materials.

Specifically, the Low-k material is easily layered due to shearing stress in the cutting process, the Low-k material is easily cracked due to the compressive stress in the wire bonding process, and the Low-k material is easily layered due to the shearing stress caused by mismatch of thermal expansion coefficients of dispensing.

Based on this, the embodiment of the application provides a new wafer structure and a chip, wherein the wafer structure comprises a base layer and a plurality of dielectric layers which are stacked; further comprises: a bonding portion and a plurality of conductive layers; the dielectric layers and the conductive layers are positioned between the base layer and the bonding part; each dielectric layer corresponds to one conductive layer; a reinforcing piece is arranged in the medium layer close to the bonding part; the projection of the reinforcement piece in the thickness direction of the wafer structure is at least partially overlapped with the projection of the conductive layer close to the bonding part in the thickness direction of the wafer structure, so that the technical problems that the wafer is easy to be subjected to high strain or high stress in a subsequent packaging process to cause the damage or destruction of the interconnection structure, such as Low-k collapse or interface layering of copper and Low-k, can be avoided or relieved.

Specific embodiments are described below as examples, with reference to the accompanying drawings.

Referring to fig. 1 and 2, in an embodiment of the present application, a wafer structure 100 is provided, where in an embodiment of the present application, the wafer structure 100 may at least include: the base layer 110 and the plurality of dielectric layers are stacked, wherein the base layer 110 may include a functional portion 111, and the wafer structure 100 may further include: the bonding portion 130 and a plurality of conductive layers.

Specifically, taking the number of dielectric layers as four as an example, in fig. 2, the plurality of dielectric layers may include: the first dielectric layer 121, the second dielectric layer 122, the third dielectric layer 123 and the fourth dielectric layer 124, wherein the first dielectric layer 121 is located between the base layer 110 and the second dielectric layer 122, and the fourth dielectric layer 124 is located between the third dielectric layer 123 and the bonding portion 130.

Taking the number of conductive layers as four as an example, in fig. 2, the plurality of conductive layers may include a structure in which: the first conductive layer 141, the second conductive layer 142, the third conductive layer 143, and the fourth conductive layer 144, wherein the first conductive layer 141 may be located between the base layer 110 and the second conductive layer 142, and the fourth conductive layer 144 may be located between the third conductive layer 143 and the bonding portion 130.

In this embodiment, the plurality of dielectric layers and the plurality of conductive layers are located between the base layer 110 and the bonding portion 130, that is, the first dielectric layer 121, the second dielectric layer 122, the third dielectric layer 123, the fourth dielectric layer 124, the first conductive layer 141, the second conductive layer 142, the third conductive layer 143, and the fourth conductive layer 144 are located between the base layer 110 and the bonding portion 130, each of the dielectric layers corresponds to one conductive layer, that is, the first dielectric layer 121 corresponds to the first conductive layer 141, the second dielectric layer 122 corresponds to the second conductive layer 142, the third dielectric layer 123 corresponds to the third conductive layer 143, and the fourth dielectric layer 124 corresponds to the fourth conductive layer 144.

Furthermore, each dielectric layer may be provided with a conductive via inside, which communicates with the corresponding conductive layer. Specifically, the first dielectric layer 121 may or may not be provided with the first conductive via inside (see fig. 3). With continued reference to fig. 3, the interior of the second dielectric layer 122 may be provided with a second conductive via 1221, the second conductive via 1221 being in communication with the corresponding second conductive layer 142, likewise, the interior of the third dielectric layer 123 may be provided with a third conductive via 1231, the third conductive via 1231 being in communication with the corresponding third conductive layer 143, likewise, the interior of the fourth dielectric layer 124 may be provided with a fourth conductive via 1241, the fourth conductive via 1241 being in communication with the corresponding fourth conductive layer 144.

In the embodiment of the present application, as shown in fig. 2 and 3, the conductive layer and the conductive via near the bonding portion 130 are made of copper. That is, the material used for the fourth conductive layer 144 and the fourth conductive via 1241 is copper.

In the wafer structure 100, the material adopted by the conductive layer close to the bonding portion 130 and the material adopted by the conductive through hole close to the bonding portion 130 are copper, so that the strength of the fourth conductive layer 144 and the fourth conductive through hole 1241 which adopt copper metal layers is higher than those of the material adopted by the conductive layer close to the bonding portion 130 and the material adopted by the conductive through hole close to the bonding portion 130 in the related art, the compressive stress introduced by the bonding wire in the bonding process can be relieved to a greater extent, and the reliability of the dielectric layer can be improved.

Therefore, the embodiment of the application can avoid or relieve the technical problems that the wafer is easy to be subjected to high strain or high stress in the subsequent packaging process, so that the interconnection structure is damaged or destroyed, for example, low-k collapse or interfacial delamination of copper and Low-k materials is caused.

In this embodiment, the metal thickness of the fourth conductive layer 144 may be 1um to 3um, for example, the metal thickness of the fourth conductive layer 144 may be 1um,1.5um,2um,2.5um, or 3um, which is not limited in this embodiment and is not limited in the above example.

It will be readily appreciated that in some embodiments, the inside of the dielectric layer near the bonding portion 130 may also be provided with a reinforcement member 150, i.e., the inside of the fourth dielectric layer 124 may also be provided with a reinforcement member 150 (see fig. 2 and 4), and that the reinforcement member 150 may function to increase the structural strength of the fourth dielectric layer 124 by further providing the reinforcement member 150 inside the fourth dielectric layer 124.

In addition, the projection of the stiffener 150 in the thickness direction of the wafer structure 100 and the projection of the conductive layer near the bonding portion 130 in the thickness direction of the wafer structure 100 may at least partially overlap. That is, the projection of the stiffener 150 in the thickness direction of the wafer structure 100 and the projection of the fourth conductive layer 144 in the thickness direction of the wafer structure 100 may at least partially overlap.

By designing the projection of the stiffener 150 in the thickness direction of the wafer structure 100 to at least partially overlap with the projection of the fourth conductive layer 144 in the thickness direction of the wafer structure 100, the stiffener 150 can play a certain role in supporting the fourth conductive layer 144 in strength, and thus the interlayer structural strength of the wafer structure 100 can be further improved.

In one possible implementation, the projections of the stiffener 150 in the thickness direction of the wafer structure 100 are all located within the projections of the conductive layer near the bonding portion 130 in the thickness direction of the wafer structure 100, i.e., the projections of the stiffener 150 in the thickness direction of the wafer structure 100 are all located within the projections of the fourth conductive layer 144 in the thickness direction of the wafer structure 100.

By designing the projection of the reinforcement member 150 in the thickness direction of the wafer structure 100 to be entirely located in the projection of the fourth conductive layer 144 in the thickness direction of the wafer structure 100, the entire reinforcement member 150 can play a role in supporting the strength of the fourth conductive layer 144, and thus the interlayer structural strength of the wafer structure 100 can be better improved.

It should be noted that, in the embodiment of the present application, the number of the reinforcing members 150 may be plural, and the plurality of reinforcing members 150 may be all located around the conductive through hole near the bonding portion 130, that is, the plurality of reinforcing members 150 may be all located around the fourth conductive through hole 1241.

The greater the number of stiffeners 150, the more strongly supporting the strength near the fourth conductive layer 144. Through designing the quantity of reinforcement 150 to be a plurality of, a plurality of reinforcement 150 all are located around fourth conductive via 1241, can ensure that a plurality of reinforcement 150 are more balanced effective to the intensity supporting effect of fourth conductive layer 144, and then the interlaminar structural strength of promotion wafer structure 100 that can be better.

In one possible implementation, the material used for the reinforcement member 150 may be a high-strength polymer structure, and for example, the material used for the reinforcement member 150 may be Carbon Nanotubes (CNT).

Carbon nanotubes have been used for front-end-of-chip device field effect transistors (Field Effect Transistor, FETs), i.e., CNT-FETs. The corresponding chemical vapor deposition (chemical vapor deposition, CVD) process is well established to meet the processing requirements at the later stages of processing of the wafer structure 100.

In addition, the carbon nanotube has a Young's modulus far exceeding that of the Low-k material (specifically, the Young's modulus of the carbon nanotube is 1000Gpa, and the Young's modulus of the Low-k material is 5-10 Gpa), and also has a k value (k value is generally 2-3) close to that of the Low-k material, so that the strength of the interlayer dielectric layer can be improved on the premise of hardly reducing the performance of the chip.

It should be noted that, in the embodiment of the present application, the size of the stiffener 150 may be flexibly selected according to the size of the bonding portion 130, the diameter of the bonding wire, and the diameter of the bonding ball, the structural length and width of the individual stiffener 150 may be respectively different between 15 μm and 40 μm, and the height of the stiffener 150 may be the same as that of the fourth dielectric layer 124, for example, the heights of the fourth dielectric layer 124 and the stiffener 150 may be respectively 800 nm to 1000nm, which is not limited in the embodiment of the present application.

In some embodiments, the materials used for the first dielectric layer 121, the second dielectric layer 122 and the third dielectric layer 123 may be at least Low-k materials, and the material used for the fourth dielectric layer 124 may be silicon dioxide.

The Low-k material is named as a Low dielectric constant material, is an insulating material, and particularly refers to a non-conductive material. Low-k materials refer to the incorporation of carbon and hydrogen into silicon dioxide. The mechanical strength of the silicon dioxide is higher than that of the Low-k material, which is beneficial to the performance improvement of the chip compared with the silicon dioxide, and the performance of the wafer structure 100 can be improved by designing the materials adopted by the first dielectric layer 121, the second dielectric layer 122 and the third dielectric layer 123 to be at least Low-k materials.

Specifically, in the embodiment of the present application, the first dielectric layer 121, the second dielectric layer 122, and the third dielectric layer 123 may include: the second portion 126 is located at the outer periphery of the first portion 125, as shown in fig. 2 and 5, where the first portion 125 may be made of a Low-k material, and the second portion 126 may be made of silicon dioxide.

By designing the first dielectric layer 121, the second dielectric layer 122 and the third dielectric layer 123 to include the first portion 125 and the second portion 126, for example, the first dielectric layer 121 may include the first portion 125 and the second portion 126, the first portion 125 is made of a Low-k material, the second portion 126 is located on the periphery of the first portion 125, and the second portion 126 is made of silicon dioxide, so that the second portion 126 (i.e., a cutting edge) of the first dielectric layer 121 is prevented from being affected by processes such as laser cutting, plastic packaging and dispensing, for example, delamination of the Low-k material caused by excessive shear stress can be avoided.

It should be noted that, in the embodiment of the present application, the structural height of the second portion 126 is the same as that of the first portion 125 located in the same dielectric layer, and may be 300nm to 500nm, for example, the structural height of the second portion 126 may be 300nm,350nm,400nm,450nm, 500nm, or the like.

The structural width of the second portion 126 may be 2um-3um, for example, the structural width of the second portion 126 may be 2um,2.2um,2.4um,2.6um,2.8um, or 3um, which is not limited in this embodiment and is not limited to the above examples.

It should be noted that, in the embodiments of the present invention, the ranges of values are approximate, and may be affected by the manufacturing process, and some errors may exist in a range, which may be considered to be negligible by those skilled in the art.

In addition, in one possible implementation manner, a first plating layer 161 may be further disposed between the conductive layer near the bonding portion 130 and the bonding portion 130, that is, a first plating layer 161 may be further disposed between the fourth conductive layer 144 and the bonding portion 130, and a material used for the first plating layer 161 may be nickel.

By providing the first plating layer 161 between the fourth conductive layer 144 and the bonding portion 130, that is, providing the first plating layer 161 on the surface of the fourth conductive layer 144 facing the bonding portion 130, the first plating layer 161 is made of nickel, and the nickel as the first plating layer 161 can avoid or reduce the technical problem that the copper metal of the fourth conductive layer 144 is susceptible to oxidation corrosion.

A second plating layer 162 may be further provided between the first plating layer 161 and the bonding portion 130, and the material used for the second plating layer 162 may be gold.

By providing the first plating layer 161 between the first plating layer 161 and the bonding portion 130, that is, providing the second plating layer 162 on the surface of the first plating layer 161 facing the bonding portion 130, the second plating layer 162 is made of gold, and the gold as the second plating layer 162 can further avoid or reduce the technical problem that the copper metal is susceptible to oxidation corrosion on the basis of the first plating layer 161.

It should be noted that, in the embodiment of the present application, the thickness of the first plating layer 161 and the first plating layer 161 may be flexibly selected between 1 μm and 100 μm according to actual process requirements, which is not limited herein.

In an alternative embodiment, at least one passivation layer may be further disposed on a side of the dielectric layer adjacent to the bonding portion 130 facing the bonding portion 130, i.e., at least one passivation layer may be further disposed on a side of the fourth dielectric layer 124 facing the bonding portion 130.

Illustratively, in fig. 2, a first passivation layer 171 and a second passivation layer 172 are disposed on a side of the fourth dielectric layer 124 facing the bonding portion 130.

By further providing at least one passivation layer on the side of the fourth dielectric layer 124 facing the bonding portion 130, the passivation layer can function to protect the fourth dielectric layer 124.

In addition, in the embodiment of the application, the passivation layer and the bonding portion 130 may avoid each other, and the passivation layer and the bonding portion 130 avoid each other, so that interference or disturbance of the passivation layer on the bonding portion 130 may be avoided.

It is appreciated that in some embodiments, the wafer structure 100 may further comprise: the plurality of etch stop layers, specifically, taking the number of etch stop layers as five as an example, in fig. 2, may include: a first etch stop layer 181, a second etch stop layer 182, a third etch stop layer 183, a fourth etch stop layer 184, and a fifth etch stop layer 185, wherein the first etch stop layer 181 is located between the base layer 110 and the first dielectric layer 121, the second etch stop layer 182 is located between the first dielectric layer 121 and the second dielectric layer 122, the third etch stop layer 183 is located between the second dielectric layer 122 and the third dielectric layer 123, the fourth etch stop layer 184 is located between the third dielectric layer 123 and the fourth dielectric layer 124, and the fourth etch stop layer 184 is located between the fourth dielectric layer 124 and the first passivation layer 171.

In the related art, the number of dielectric layers in the wafer structure 100a is five, as shown in fig. 6, 8 and 9, the first dielectric layer 121a, the second dielectric layer 122a, the third dielectric layer 123a, the fourth dielectric layer 124a and the fifth dielectric layer 127a are sequentially stacked, the materials used for the first dielectric layer 121a, the second dielectric layer 122a and the third dielectric layer 123a are Low-k materials, and the materials used for the fourth dielectric layer 124a and the fifth dielectric layer 127a are silicon dioxide.

In addition, each dielectric layer corresponds to one conductive layer, taking the number of conductive layers in the wafer structure 100a as four as an example, in fig. 6, the plurality of conductive layers may include: the first conductive layer 141a, the second conductive layer 142a, the third conductive layer 143a, the fourth conductive layer 144a, and the fifth conductive layer 145a, wherein the first dielectric layer 121a corresponds to the first conductive layer 141a, the second dielectric layer 122a corresponds to the second conductive layer 142a, the third dielectric layer 123a corresponds to the third conductive layer 143a, the fourth dielectric layer 124a corresponds to the fourth conductive layer 144a, and the fifth dielectric layer 127a corresponds to the fifth conductive layer 145 a.

And a conductive through hole is arranged in each dielectric layer and is communicated with the corresponding conductive layer. Specifically, the first dielectric layer 121a may or may not be provided with the first conductive via inside (see fig. 6). With continued reference to fig. 6, the second dielectric layer 122a may be provided with a second conductive via 1221a inside, the second conductive via 1221a may be in communication with the corresponding second conductive layer 142a, and likewise, the third dielectric layer 123a may be provided with a third conductive via 1231a inside, the third conductive via 1231a may be in communication with the corresponding third conductive layer 143a, the fourth dielectric layer 124a may be provided with a fourth conductive via 1241a inside, the fourth conductive via 1241a may be in communication with the corresponding fourth conductive layer 144a, and the fifth dielectric layer 127a may be provided with a fifth conductive via 1271a inside, the fifth conductive via 1271a may be in communication with the corresponding fifth conductive layer 145 a.

In the related art, as shown in fig. 6 and 7, the conductive layer and the conductive via near the bonding portion 130 are made of aluminum. That is, the fifth conductive layer 145a and the fifth conductive via 1271a are made of aluminum.

In the wafer structure 100 provided in this embodiment, the material adopted by the conductive layer close to the bonding portion 130 and the material adopted by the conductive through hole close to the bonding portion 130 (i.e. the fourth conductive layer 144a and the fourth conductive through hole 1241a in fig. 2) are copper, the strength E of copper is generally 120GPa, and the strength E of aluminum is generally 70GPa, compared with the material adopted by the conductive layer close to the bonding portion 130 and the material adopted by the conductive through hole close to the bonding portion 130 (i.e. the fifth conductive layer 145a and the fifth conductive through hole 1271a in fig. 6) in the related art, the strength of the fourth conductive layer 144 and the fourth conductive through hole 1241 themselves adopting the copper metal layer are higher, so that the compressive stress introduced by the bonding wire in the bonding process can be relieved to a greater extent, and the reliability of the dielectric layer can be improved.

It is easy to understand that compared to the related art, the embodiment of the present application further saves one dielectric layer (the fifth dielectric layer 127 a), one conductive layer (the fifth conductive layer 145 a) and the fifth conductive via 1271a, which can reduce the processing cost of the wafer structure.

In addition, the related art does not provide silicon dioxide with high mechanical strength on the outer circumferences or outer edges of the first dielectric layer 121a, the second dielectric layer 122a and the third dielectric layer 123a using the Low-k material, and thus cannot prevent processes such as laser cutting, plastic packaging, dispensing and the like from affecting the outer edges (i.e., cutting edges) of the first dielectric layer 121a, the second dielectric layer 122a and the third dielectric layer 123a, that is, the wafer structure 100a in the related art cannot avoid the technical problem that the Low-k material is delaminated due to excessive shear stress.

Further, the related art does not provide the reinforcement member 150 inside the dielectric layer near the bonding portion 130, that is, the reinforcement member 150 (see fig. 6 and 8) is not provided inside the fifth dielectric layer 127a, but the reinforcement member 150 can function to increase the structural strength of the dielectric layer near the bonding portion 130 (the fourth dielectric layer 124) by further providing the reinforcement member 150 inside the fourth dielectric layer 124 in the embodiment of the present application.

In addition, the greater the number of stiffeners 150, the stronger the support for strength near the fourth conductive layer 144. The wafer structure 100 in this embodiment of the present application is designed to be multiple by the number of the reinforcing members 150, where the multiple reinforcing members 150 are all located around the fourth conductive through hole 1241, so that it can be ensured that the strength supporting effect of the multiple reinforcing members 150 on the fourth conductive layer 144 is more balanced and effective, and then the interlayer structural strength of the wafer structure 100 can be better improved.

In addition, the embodiment of the application also provides a chip, which at least can include: the wafer structure 100 of any of the above.

The chip provided by the embodiment of the application, the chip at least can include the wafer structure 100, the material adopted by the conductive layer close to the bonding portion 130 and the material adopted by the conductive through hole close to the bonding portion 130 are copper, compared with the material adopted by the conductive layer close to the bonding portion 130 and the material adopted by the conductive through hole close to the bonding portion 130 in the related art are aluminum, the self strength of the copper metal layer is higher, the compressive stress introduced by the bonding wire in the bonding process can be relieved to a greater extent, and the reliability of the dielectric layer can be improved, so that the overall reliability of the wafer structure 100 can be improved.

Therefore, the embodiment of the application can avoid or relieve the technical problems that the wafer is easy to be subjected to high strain or high stress in the subsequent packaging process, so that the interconnection structure is damaged or destroyed, for example, low-k collapse is caused, or the interface of copper and Low-k is layered.

In the description of the embodiments of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, indirectly connected through an intermediary, or may be in communication with each other between two elements or in an interaction relationship between two elements. The specific meaning of the above terms in the embodiments of the present application will be understood by those of ordinary skill in the art according to the specific circumstances.

The embodiments or implications herein must have a particular orientation, be constructed and operate in a particular orientation, and therefore should not be construed as limiting the embodiments herein. In the description of the embodiments of the present application, the meaning of "a plurality" is two or more, unless specifically stated otherwise.

The terms first, second, third, fourth and the like in the description and in the claims of embodiments of the application and in the above-described figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application described herein may be capable of implementation in sequences other than those illustrated or described herein, for example. Furthermore, the terms "may include" and "have," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Finally, it should be noted that: the foregoing embodiments are merely for illustrating the technical solutions of the embodiments of the present application, and are not limited thereto, and although the embodiments of the present application have been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may be modified or some or all of the technical features may be replaced equivalently, and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments in this application.

Claims

1. A wafer structure, comprising:

the basic unit and a plurality of medium layer of range upon range of setting, a plurality of medium layers include the range upon range of setting in proper order: the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer;

the first dielectric layer, the second dielectric layer and the third dielectric layer respectively comprise: a first portion and a second portion;

the second portion is located at the periphery of the first portion;

the first part is made of Low-k material, and the second part is made of silicon dioxide;

further comprises: a bonding portion and a plurality of conductive layers; the plurality of dielectric layers and the plurality of conductive layers are located between the base layer and the bonding portion;

each dielectric layer corresponds to one conductive layer;

a reinforcing piece is further arranged inside the dielectric layer close to the bonding part;

the projection of the reinforcement member in the thickness direction of the wafer structure at least partially overlaps with the projection of the conductive layer near the bonding portion in the thickness direction of the wafer structure.

2. The wafer structure of claim 1, wherein each dielectric layer is internally provided with a conductive via in communication with the corresponding conductive layer;

the conductive layer and the conductive through hole near the bonding part are made of copper.

3. The wafer structure according to claim 2, wherein projections of the reinforcement members in a thickness direction of the wafer structure are all located within projections of the conductive layer near the bonding portion in the thickness direction of the wafer structure.

4. The wafer structure of claim 3, wherein the number of the reinforcing members is plural, and the plurality of reinforcing members are located around the conductive via near the bonding portion.

5. The wafer structure of claim 3, wherein the stiffener is made of carbon nanotubes.

6. The wafer structure of any one of claims 1-5, wherein the plurality of conductive layers comprises, in order: a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer;

7. The wafer structure according to any one of claims 1 to 5, wherein a first plating layer is further provided between the conductive layer near the bonding portion and the bonding portion;

the first coating is made of nickel.

8. The wafer structure of claim 7, wherein a second plating layer is further disposed between the first plating layer and the bonding portion;

the second coating is made of gold.

9. The wafer structure according to any one of claims 1-5, wherein at least one passivation layer is further disposed on a side of the dielectric layer adjacent to the bonding portion facing the bonding portion;

the passivation layer and the bonding part are mutually avoided.

10. A chip, comprising at least: a wafer structure as claimed in any one of claims 1 to 9.