CN117042464A

CN117042464A - Memory and forming method thereof

Info

Publication number: CN117042464A
Application number: CN202310987101.1A
Authority: CN
Inventors: 谈亚丽
Original assignee: Changxin Technology Group Co ltd
Current assignee: Changxin Technology Group Co ltd
Priority date: 2023-08-04
Filing date: 2023-08-04
Publication date: 2023-11-10

Abstract

The embodiment of the disclosure discloses a memory and a forming method thereof, wherein the method comprises the following steps: forming a conductive layer; forming a first dielectric layer on the conductive layer, and forming a groove penetrating through the first dielectric layer and extending into the conductive layer in the first dielectric layer; forming a magnetic tunnel junction covering a bottom wall and a part of a side wall of the trench; a transistor structure is formed in the trench in which the magnetic tunnel junction is formed.

Description

Memory and forming method thereof

Technical Field

The disclosure relates to the technical field of semiconductors, and in particular relates to a memory, a forming method thereof and electronic equipment.

Background

Magnetic random access memory (MRAM, magnetic Random Access Memory) is a nonvolatile memory device that has advantages of high-speed reading and writing capability, high integration, and the like, and thus is widely used.

However, there are a number of problems with mram devices that need to be addressed _。

Disclosure of Invention

In view of the above, the embodiments of the present disclosure provide a memory and a forming method thereof.

According to a first aspect of the present disclosure, there is provided a method of forming a memory, including:

forming a conductive layer;

forming a first dielectric layer on the conductive layer, and forming a groove penetrating through the first dielectric layer and extending into the conductive layer in the first dielectric layer;

forming a magnetic tunnel junction covering a bottom wall and a part of a side wall of the trench;

a transistor structure is formed in the trench in which the magnetic tunnel junction is formed.

In some embodiments, the forming a conductive layer includes:

providing a first semiconductor layer;

and doping the first semiconductor layer to form the source electrode layer.

In some embodiments, the forming a magnetic tunnel junction covering a bottom wall and a portion of a side wall of the trench includes:

forming a magnetic tunnel junction material layer on the side wall and the bottom wall of the groove;

and removing part of the magnetic tunnel junction material layer on the side wall to form a first filling region, wherein the rest magnetic tunnel junction material layer forms the magnetic tunnel junction.

In some embodiments, the forming a transistor structure in the trench in which the magnetic tunnel junction is formed includes:

forming a second semiconductor layer covering the magnetic tunnel junction material layer in the groove with the magnetic tunnel junction material layer before removing part of the magnetic tunnel junction material layer on the side wall, wherein the second semiconductor layer comprises a first doping region, a channel region and a second doping region which are sequentially arranged along the thickness direction of the first dielectric layer; the first doped region is connected with the magnetic tunnel junction;

and after removing part of the magnetic tunnel junction material layer on the side wall, sequentially forming a first insulating layer, a gate structure and a second insulating layer along the thickness direction of the first dielectric layer in the first filling region.

In some embodiments, the method further comprises:

forming a first contact structure on the first dielectric layer after forming a transistor structure in the trench in which the magnetic tunnel junction is formed; the first contact structure is connected with the second doped region of the transistor structure;

and forming a conductive wire on the first contact structure, wherein the conductive wire is connected with the first contact structure.

According to a second aspect of the present disclosure, there is provided a memory method comprising:

a conductive layer;

the first dielectric layer is positioned on the conductive layer;

a magnetic tunnel junction located at a bottom wall and a portion of a sidewall of a trench defined in the first dielectric layer, connected to the conductive layer;

and the transistor structure is positioned in the groove and connected with the magnetic tunnel junction.

In some embodiments, the transistor structure includes:

the second semiconductor layer comprises a first doped region, a channel region and a second doped region which are sequentially arranged along the thickness direction of the first dielectric layer;

and the first insulating layer, the grid structure and the second insulating layer are sequentially arranged between the second semiconductor layer and the first dielectric layer along the thickness direction of the first dielectric layer.

In some embodiments, the material of the second semiconductor layer comprises: indium gallium zinc oxide.

In some embodiments, the memory further comprises a first contact structure, a conductive line; the first contact structure is positioned on the first dielectric layer and connected with the second doped region; the conductive wire is positioned on the first contact structure and connected with the first contact structure.

In some embodiments, the magnetic tunnel junction includes a free layer, a tunnel layer, and a fixed layer disposed in a stack along the first dielectric layer thickness direction; the free layer is connected with the conductive layer, and the fixed layer is connected with the first doped region.

The embodiment of the disclosure discloses a memory and a forming method thereof, wherein the method comprises the following steps: forming a conductive layer; forming a first dielectric layer on the conductive layer, and forming a groove penetrating through the first dielectric layer and extending into the conductive layer in the first dielectric layer; forming a magnetic tunnel junction covering a bottom wall and a part of a side wall of the trench; a transistor structure is formed in the trench in which the magnetic tunnel junction is formed. In the embodiment of the disclosure, on one hand, a conductive layer is formed first, a trench is formed on the conductive layer, a magnetic tunnel junction is formed on the bottom wall and part of the side wall in the trench, the magnetic tunnel junction is isolated at the bottom of the trench, and the trench extends into the conductive layer, so that the conductive layer is directly connected with the magnetic tunnel junction, that is, in the embodiment of the disclosure, a contact structure is not required to be formed on the magnetic tunnel junction alone, so that the magnetic tunnel junction is connected with a bit line, and pollution and bridging problems caused by alignment deviation when the contact structure is formed can be avoided; on the other hand, in the embodiment of the disclosure, the magnetic tunnel junction is formed on the partial side wall and the bottom wall of the trench, so that the effective area of the magnetic tunnel junction is increased under the condition that the horizontal dimension is unchanged, and the problem of magnetic property degradation caused by the miniaturization of the memory dimension can be solved to a certain extent.

Drawings

FIG. 1 is a schematic perspective view of a memory according to an embodiment of the disclosure;

FIG. 2 is a schematic cross-sectional view of a memory according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram of a cross-sectional structure of a memory according to an embodiment of the disclosure;

FIG. 4 is a schematic flow chart of a method for manufacturing a memory according to an embodiment of the disclosure;

fig. 5 to 12 are schematic structural views illustrating a manufacturing process of a memory according to an embodiment of the present disclosure;

FIG. 13 is a schematic diagram of a cross-sectional structure of a memory according to an embodiment of the disclosure;

fig. 14 is a schematic top view of a memory according to an embodiment of the disclosure.

Detailed Description

In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The present disclosure is described more specifically in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more fully apparent from the following description and appended claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the disclosure.

It will be understood that the meanings of "on … …", "over … …" and "over … …" in this disclosure should be interpreted in the broadest manner so that "on … …" means not only that it is "on" something with no intervening features or layers therebetween (i.e., directly on something), but also that it is "on" something with intervening features or layers therebetween.

Further, spatially relative terms such as "on … …," "above … …," "above … …," "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated for ease of description. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In the presently disclosed embodiments, the term "substrate" refers to a material upon which subsequent layers of material are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a variety of semiconductor materials, such as silicon, silicon germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

In the presently disclosed embodiments, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entirety of the underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Further, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal facing at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along an inclined surface. The layer may comprise a plurality of sub-layers. For example, the interconnect layer may include one or more conductors and contact sublayers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sublayers.

In the presently disclosed embodiments, the terms "first," "second," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

Magnetic random access memory is one of the new types of nonvolatile random access memory with modulated magnetic resistance as the principle. Magnetic random access memory (mram) achieves a better compromise in terms of speed, area, number of writes, and power consumption than other mainstream memories, and is therefore considered by the industry as one of the potential access devices for the construction of next generation nonvolatile caches and mainframes. The magnetic random access memory is compared with the technical indexes such as durability, reading time, writing time, leakage current and the like of other main stream memories, wherein the other main stream memories comprise dynamic random access memories (DRAM, dynamic Random Access Memory), mechanical Hard disks (HDD), NAND Flash memories (NAND Flash), variable resistance memories (ReRAM, resistive Random Access Memory), phase change memories (PCM, phase Change Memory) and ferroelectric random access memories (FeRAM, ferroelectric Random Access Memory).

The magnetic random access memory is used as a nonvolatile memory, and the read-write speed of the magnetic random access memory is comparable to that of a representative dynamic random access memory of a volatile memory; in addition, the standby power consumption of the magnetic random access memory is far smaller than that of the dynamic random access memory, the magnetic random access memory is more suitable for mobile terminal application, and the magnetic random access memory is excellent in durability (service life), so that the magnetic random access memory has the feasibility of replacing the volatile memory. The magnetic random access memory includes a plurality of memory cells, as shown in fig. 1, each memory cell includes a magnetic tunnel junction and a transistor structure for controlling writing and reading data, the magnetic tunnel junction generally includes a free layer, a tunnel layer and a fixed layer sequentially disposed, the transistor structure includes a source electrode, a gate electrode structure and a drain electrode, wherein the free layer is connected with a bit line corresponding to the memory cell, the fixed layer is connected with the drain electrode, the gate electrode is connected with a word line corresponding to the memory cell, and the source electrode is connected with a source electrode line corresponding to the memory cell.

Fig. 2 is a schematic cross-sectional structure of a magnetic random access memory according to an embodiment of the disclosure. As shown in fig. 2, an upper electrode contact structure (TEC, top Electrode Contact) is formed on the magnetic tunnel junction, through which the magnetic tunnel junction is connected to the bit line. When the upper electrode contact structure is formed, a contact hole needs to be formed in a dielectric layer on the magnetic tunnel junction, and metal pollution and bridging problems may be caused due to alignment deviation when the contact hole is formed, specifically: because the material of the upper electrode contact structure is mainly tungsten (W), the material of the magnetic tunnel junction mainly comprises cobalt (Co), iron (Fe) and boron (B), when a contact hole is formed, if photoresist is aligned to shift, the material of the magnetic tunnel junction can be exposed when the contact hole is formed by etching, and the factory production line cannot simultaneously contact with various elements of Co/Fe/B, so that the pollution control of the factory production line is conflicted, the pollution problem of the factory production line is caused, and the upper electrode contact structure contacts with the magnetic tunnel junction due to the alignment shift to cause bridging, so that the magnetic tunnel junction cannot store data, and the performance of a memory is seriously influenced. And with increasing demands on memory density, the above contamination and bridging problems are more serious with shrinking memory sizes.

In some embodiments, as shown in fig. 3, after the magnetic tunnel junction is formed on the substrate, a layer of silicon nitride may be deposited on the upper electrode of the magnetic tunnel junction to cover the surface of the upper electrode, the sidewalls of the upper electrode, and the sidewalls of the magnetic tunnel junction to serve as a protective layer, where the protective layer needs to ensure complete coverage of the magnetic tunnel junction to avoid contamination and bridging problems due to exposure of the magnetic tunnel junction. In order to detect whether the protection layer completely covers the magnetic tunnel junction, metal ion analysis (VPD, vapor Phase Decomposition) test needs to be performed on the whole wafer, and especially the edge position needs to be subjected to multi-point slicing to check the coverage condition of the protection layer, so that the process is complicated.

Based on this, in order to solve the above-mentioned problem, an embodiment of the present disclosure provides a method for forming a memory, as shown in fig. 4, including:

s1100: forming a conductive layer;

s1200: forming a first dielectric layer on the conductive layer, and forming a groove penetrating through the first dielectric layer and extending into the conductive layer in the first dielectric layer;

s1300: forming a magnetic tunnel junction covering a bottom wall and a part of a side wall of the trench;

s1400: a transistor structure is formed in the trench in which the magnetic tunnel junction is formed.

It should be understood that the steps shown in fig. 4 are not exclusive and that other steps may be performed before, after, or between any of the steps in the illustrated operations. The steps shown in fig. 4 can be sequentially adjusted according to actual requirements.

Fig. 5 to 12 are schematic flow diagrams of a method for manufacturing a memory according to an embodiment of the disclosure. The following describes a specific procedure of a method for manufacturing a memory provided in an embodiment of the present disclosure with reference to fig. 4 to 12.

As shown in fig. 5, step S1100 is performed to form the conductive layer 101. In some embodiments, the forming the conductive layer 101 includes:

providing a first semiconductor layer;

the first semiconductor layer is subjected to doping treatment, thereby forming the conductive layer 101.

In some specific examples, the material of the first semiconductor layer includes, but is not limited to, silicon germanium.

In some specific examples, as shown in fig. 5, the method further comprises: prior to forming the conductive layer 101, a substrate 117 is provided. After the substrate 117 is provided, the conductive layer 101 is formed over the substrate 117.

In some specific examples, the substrate 117 includes a silicon-on-insulator substrate, but is not limited thereto. The substrate 117 may also be a simple semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, etc.), a germanium on insulator (GeOI) substrate, etc.

In some specific examples, a specific process of forming the conductive layer 101 may be: and directly introducing a silicon and germanium gas source on the substrate to form a first semiconductor layer. The conductive layer 101 is selected to be doped with germanium silicide because of the good process compatibility of the doped germanium silicide with the substrate and dielectric layers.

Here, the method of forming the first semiconductor layer includes, but is not limited to, a deposition process. Deposition processes include, but are not limited to, physical vapor deposition (PVD, physical Vapor Deposition) processes, chemical vapor deposition (CVD, chemical Vapor Deposition) processes, atomic layer deposition (ALD, atomic Layer Deposition), and the like.

The conductive layer 101 here may serve as a common source. The conductive lines formed in the subsequent process may be used as bit lines extending in a first direction; the word lines formed in the subsequent process may extend along the second direction, where the first direction and the second direction are perpendicular to each other and are perpendicular to the thickness direction of the first dielectric layer 102. The first direction may be an X direction in the drawings of the present disclosure, the second direction may be a Y direction in the drawings of the present disclosure, and the thickness direction of the first dielectric layer 102 may be a Z direction in the drawings of the present disclosure.

As shown in fig. 6, step S1200 is performed to form a first dielectric layer 102 on the conductive layer 101, and a trench 103 extending into the conductive layer 101 through the first dielectric layer 102 is formed in the first dielectric layer 102.

In some specific examples, the material of the first dielectric layer 102 includes, but is not limited to, silicon oxide. Methods of forming the first dielectric layer 102 include, but are not limited to, a deposition process.

In some specific examples, a mask layer and photoresist may be formed on the first dielectric layer 102 first, and the trench 103 may be formed through photolithography and etching processes.

It should be noted that, in fig. 6, only two grooves 103 are shown by way of example, but the number of grooves 103 in the embodiment of the present disclosure is not limited thereto, and the grooves 103 in the embodiment of the present disclosure may extend in the second direction, and the plurality of grooves 103 may be arranged in the first direction.

Here, as shown in fig. 6, the bottom of the trench 103 exposes the conductive layer 101.

Next, as shown in fig. 7 to 9, step S1300 is performed to form the magnetic tunnel junction 104 covering the bottom wall and part of the side wall of the trench 103.

In some embodiments, the forming the magnetic tunnel junction 104 covering the bottom wall and part of the side wall of the trench 103 includes:

forming a magnetic tunnel junction material layer 105 on the side walls and the bottom wall of the trench 103;

a portion of the magnetic tunnel junction material layer 105 of the sidewall is removed to form a first fill region 106, and the remaining magnetic tunnel junction material layer 105 forms the magnetic tunnel junction 104.

In some embodiments, the forming a transistor structure in the trench 103 formed with the magnetic tunnel junction 104 includes:

forming a second semiconductor layer 108 covering the magnetic tunnel junction material layer 105 in the trench 103 where the magnetic tunnel junction material layer 105 is formed, the second semiconductor layer 108 including a first doped region 109, a channel region 110, and a second doped region 111 sequentially arranged in a thickness direction of the first dielectric layer 102, before removing a portion of the magnetic tunnel junction material layer 105 of the sidewall; the first doped region 109 is connected to the magnetic tunnel junction 104;

after removing a portion of the magnetic tunnel junction material layer 105 of the sidewall, a first insulating layer 112, a gate structure 113, and a second insulating layer 114 are sequentially formed in the first filling region 106 along the thickness direction of the first dielectric layer 102.

As shown in fig. 7, a magnetic tunnel junction material layer 105 may be formed first on both the sidewalls and bottom wall of the trench 103.

In some specific examples, the magnetic tunnel junction material layer 105 is formed on the surface of the first dielectric layer 102 at the same time that the magnetic tunnel junction material layer 105 is formed on the side wall and the bottom wall of the trench 103.

In some specific examples, the magnetic tunnel junction 104 includes a free layer 118, a tunnel layer 119, and a fixed layer 120. The free layer 118 and the fixed layer 120 of the magnetic tunnel junction 104 may be fabricated using ferromagnetic materials, such as Fe, feCo, feCoB. The material of the tunnel layer 119 includes, but is not limited to, magnesium oxide.

In some specific examples, the method of forming the free layer 118, the tunnel layer 119, and the fixed layer 120 includes, but is not limited to, a deposition process.

Next, as shown in fig. 7, a second semiconductor material layer 107 is formed in the trench 103 in which the magnetic tunnel junction material layer 105 is formed, the second semiconductor material layer 107 covering the magnetic tunnel junction material layer 105.

In some specific examples, the material of the second semiconductor material layer 107 includes, but is not limited to, indium gallium zinc oxide.

It can be appreciated that, in the embodiment of the present disclosure, indium gallium zinc oxide is used as the material of the second semiconductor material layer 107, which can effectively solve the influence of high temperature on the magnetic tunnel junction 104, specifically: in the case of forming a transistor structure using a common material (e.g., silicon), a high temperature process is required, and the magnetic performance of the magnetic tunnel junction 104 is affected by the high temperature process, whereas in the case of forming a transistor structure using indium gallium zinc oxide, the high temperature process is not required, so that the formed magnetic tunnel junction 104 is not affected.

Next, as shown in fig. 8, a portion of the second semiconductor material layer 107 is removed, exposing the magnetic tunnel junction material layer 105 on the surface of the first dielectric layer 102, so that the top surface of the second semiconductor layer 108 is flush with the top surface of the magnetic tunnel junction material layer 105.

In some specific examples, portions of the second semiconductor material layer 107 may be removed by a planarization process, such as chemical mechanical polishing (CMP, chemical Mechanical Polishing).

Next, as shown in fig. 9, a portion of the magnetic tunnel junction material layer 105 of the side wall of the trench 103 is removed, forming a first filling region 106, and the magnetic tunnel junction material layer 105 of the bottom and a portion of the side wall of the trench 103 is left, so that a magnetic tunnel junction 104 having a U-shaped cross section is formed.

Here, the magnetic tunnel junction 104 is in contact with the conductive layer 101.

It can be appreciated that by forming the magnetic tunnel junction 104 on a portion of the side wall and the bottom wall of the trench 103 in the embodiments of the present disclosure, the effective area of the magnetic tunnel junction 104 is increased without changing the horizontal dimension, so that the problem of magnetic performance degradation due to the shrinking of the memory size can be solved to some extent.

Here, the height of the magnetic tunnel junction material layer remaining on the side wall of the trench 103 may be set according to the specific case. It should be considered that, the higher the height of the magnetic tunnel junction material layer remained on the sidewall of the trench 103, the larger the effective area of the formed magnetic tunnel junction 104, but the higher the height of the magnetic tunnel junction material layer remained on the sidewall of the trench 103, the limited space for forming the first insulating layer, the gate structure and the second insulating layer in the subsequent process may have a certain influence on the performance of the transistor structure, so the height of the magnetic tunnel junction material layer remained on the sidewall of the trench 103 can be specifically set by comprehensively considering the two factors.

Next, as shown in fig. 10, step S1400 is performed to form a transistor structure in the trench 103.

The second semiconductor layer 108 formed in the precursor process may include a first doped region 109, a channel region 110, and a second doped region 111 sequentially arranged in a thickness direction perpendicular to the first dielectric layer 102. The first doped region 109 may be a source of a transistor structure and the second doped region 111 may be a drain of the transistor structure. The first doped region 109 and the second doped region 111 are doped with impurities, the doping type can be selected according to the specific situation, and when the transistor structure is an N-type transistor, the doping type is N-type doping; when the transistor structure is a P-type transistor, the doping type is P-type doping.

In some specific examples, ion implantation may be performed on both ends of the first semiconductor layer in the thickness direction of the first dielectric layer 102, thereby forming the first doped region 109 and the second doped region 111.

It can be appreciated that the transistor structure in the embodiments of the present disclosure is a vertical transistor, and the first doped region and the second doped region are distributed at two opposite ends of the second semiconductor layer 108 along the thickness direction of the first dielectric layer, so that the density of the memory can be increased, and a high-density magnetic random access memory can be formed.

A first insulating layer 112, a gate structure 113, and a second insulating layer 114 are sequentially formed in the first filling region 106.

In some specific examples, the materials of the first insulating layer 112 and the second insulating layer 114 include, but are not limited to, silicon nitride and silicon oxide. The materials of the first insulating layer 112 and the second insulating layer 114 may be the same or different. The first insulating layer 112 and the second insulating layer 114 may have a single-layer structure or a composite-layer structure.

In some specific examples, gate structure 113 includes a gate 122 and a gate dielectric layer 121 between gate 122 and channel region 110. The material of the gate dielectric layer 121 includes, but is not limited to, silicon oxide, silicon nitride, and the material of the gate 122 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. The gates 122 of the plurality of transistor structures arranged in the second direction are in contact with each other to constitute a word line, which can control the on and off of the transistor structures.

Here, the gate structure 113 may cover both sidewalls of the channel region 110 opposite in the first direction.

It can be appreciated that the gate structure 113 in the embodiment of the disclosure covers two sidewalls of the channel region 110 opposite to each other along the first direction, which may enable the memory to have a higher driving current and a lower current leakage, so that the performance of the memory may be improved.

In some specific examples, the specific process of forming the first insulating layer 112, the gate structure 113, and the second insulating layer 114 may be: forming a first insulating material layer in the first filling region, removing part of the first insulating material layer to form a second filling region, and forming a first insulating layer 112 by the remaining first insulating material layer; forming a gate structure material layer in the second filling region, removing part of the gate structure material layer to form a third filling region, and forming a gate structure 113 by the rest gate structure material layer; a second insulating layer 114 is formed in the third filling region.

Here, when removing a portion of the first insulating material layer, a certain consumption of the first dielectric layer of the sidewall is also caused, so as shown in fig. 10, the dimension of the gate structure 113 along the first direction is greater than the dimension of the first insulating layer 112 along the first direction.

Next, as shown in fig. 11 and 12, a first contact structure 115 and a conductive line 116 are formed.

In some embodiments, the method further comprises:

after forming a transistor structure in the trench 103 in which the magnetic tunnel junction 104 is formed, a first contact structure 115 is formed on the first dielectric layer 102; the first contact structure 115 is connected to the second doped region 111 of the transistor structure;

a conductive line 116 is formed on the first contact structure 115, the conductive line 116 being connected to the first contact structure 115.

In some specific examples, the conductive line 116 may be a bit line, and the material of the conductive line 116 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.

In some specific examples, the material of the first contact structure 115 includes, but is not limited to, tungsten.

Here, the first contact structure 115 and the conductive line 116 may be formed by forming a second dielectric layer on the first dielectric layer 102, forming a via hole in the second dielectric layer, and filling a conductive material in the via hole, thereby forming the first contact structure 115; a third dielectric layer is formed over the second dielectric layer, and a trench is formed in the third dielectric layer, the trench being filled with a conductive material, thereby forming a conductive line 116.

In the embodiment of the disclosure, the conductive layer 101 is formed first, the trench 103 is formed on the conductive layer 101, the magnetic tunnel junction 104 is formed on the bottom wall and part of the side wall in the trench 103, the magnetic tunnel junction 104 is isolated at the bottom of the trench 103, and the trench 103 extends into the conductive layer 101, so that the conductive layer 101 is directly connected with the magnetic tunnel junction 104, that is, in the embodiment of the disclosure, the contact structure is not required to be separately formed on the magnetic tunnel junction 104, so that the magnetic tunnel junction 104 is connected with the bit line, and thus pollution and bridging problems caused by alignment offset when the contact structure is formed can be avoided.

Based on the method for forming the memory, the embodiment of the present disclosure further provides a memory, and fig. 13 is a memory provided by the embodiment of the present disclosure, as shown in fig. 13, including:

a conductive layer 101;

a first dielectric layer 102 on the conductive layer 101;

a magnetic tunnel junction 104 connected to the conductive layer 101 at a bottom wall and a portion of a side wall of the trench defined in the first dielectric layer 102;

a transistor structure is located in the trench and is connected to the magnetic tunnel junction 104.

In some specific examples, the material of the first dielectric layer 102 includes, but is not limited to, silicon oxide. In some specific examples, conductive layer 101 may be a common source. The material of conductive layer 101 includes, but is not limited to, doped germanium silicide.

It will be appreciated that, in one aspect, the magnetic tunnel junction in the embodiments of the present disclosure is isolated at the bottom of the trench defined in the first dielectric layer 102, the magnetic tunnel junction 104 is connected to the conductive layer 101 such that the magnetic tunnel junction 104 is connected to the bit line without separately forming a contact structure on the magnetic tunnel junction 104 when forming the memory, thereby making it possible to avoid contamination and bridging problems due to alignment offset when forming the contact structure; on the other hand, in the embodiment of the present disclosure, the magnetic tunnel junction 104 is located at the bottom wall and part of the side wall of the trench defined in the first dielectric layer 102, so that the effective area of the magnetic tunnel junction 104 is increased without changing the horizontal dimension, thereby making it possible to solve the problem of degradation of magnetic properties due to the shrinking of the memory size to some extent.

In some embodiments, the transistor structure includes:

a second semiconductor layer 108 including a first doped region 109, a channel region 110, and a second doped region 111 sequentially arranged in a thickness direction of the first dielectric layer 102;

a first insulating layer 112, a gate structure 113, and a second insulating layer 114, which are sequentially arranged in the thickness direction of the first dielectric layer 102, between the second semiconductor layer 108 and the first dielectric layer 102.

In some specific examples, the materials of the first insulating layer 112 and the second insulating layer 114 include, but are not limited to, silicon nitride and silicon oxide. The materials of the first insulating layer 112 and the second insulating layer 114 may be the same or different. The first insulating layer 112 and the second insulating layer 114 may have a single-layer structure or a composite-layer structure. In some specific examples, gate structure 113 includes a gate 122 and a gate dielectric layer 121 between gate 122 and channel region 110. The material of the gate dielectric layer 121 includes, but is not limited to, silicon oxide, silicon nitride, and the material of the gate 122 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.

In some embodiments, the material of the second semiconductor layer 108 includes: indium gallium zinc oxide.

In some embodiments, the memory further comprises a first contact structure 115, a conductive line 116; the first contact structure 115 is located on the first dielectric layer 102 and connected to the second doped region 111; the conductive line 116 is located on the first contact structure 115 and connected to the first contact structure 115.

In some embodiments, the magnetic tunnel junction 104 includes a free layer 118, a tunnel layer 119, and a fixed layer 120 stacked along the thickness of the first dielectric layer 102; wherein the free layer 118 is connected to the conductive layer 101, and the fixed layer 120 is connected to the first doped region 109.

Fig. 14 is a schematic top view of a memory according to an embodiment of the disclosure. As can be seen from fig. 14, the plurality of second semiconductor layers 108 are arranged in an array along the first direction and the second direction, and the plurality of magnetic tunnel junctions 104 are also arranged in an array along the first direction and the second direction, respectively, and one magnetic tunnel junction 104 is connected to one second semiconductor layer 108. The plurality of conductive lines 116 are arranged along the second direction, each conductive line 116 extends along the first direction, and one conductive line 116 may be connected to each of the plurality of second semiconductor layers 108 arranged along the first direction. The plurality of word lines 123 are arranged along the first direction, and each word line 123 extends along the second direction, and one word line 123 is connected to the plurality of second semiconductor layers 108 arranged along the second direction. The conductive layer 101 may be connected to a plurality of magnetic tunnel junctions 104 arranged in an array along the first direction and the second direction.

Based on the memory, the embodiment of the disclosure further provides an electronic device, including the memory according to any one of the embodiments.

In some specific examples, an electronic device includes a circuit board and a magnetic random access memory disposed on the circuit board.

In some specific examples, the electronic device includes a computing device (e.g., a server), a network device (e.g., a switch), a storage device (e.g., a storage array), an in-vehicle device (e.g., an in-vehicle speaker, an in-vehicle navigator, etc.), and a terminal device (e.g., a wearable device, a computer, a cell phone, a tablet computer, etc.), etc.

In several embodiments provided by the present disclosure, it should be understood that the disclosed apparatus and methods may be implemented in a non-targeted manner. The above described device embodiments are only illustrative, e.g. the division of the units is only one logical function division, and there may be other divisions in practice, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the components shown or discussed are coupled to each other or directly.

The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.

The present disclosure is not limited to the specific embodiments, and any person skilled in the art, who is within the technical scope of the present disclosure, can easily conceive of changes or substitutions, which are included in the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method of forming a memory, comprising:

forming a conductive layer;

2. The method of forming of claim 1, wherein the forming of the conductive layer comprises:

providing a first semiconductor layer;

and doping the first semiconductor layer to form the conductive layer.

3. The method of forming of claim 1, wherein forming a magnetic tunnel junction covering a bottom wall and a portion of a side wall of the trench comprises:

4. The method of forming of claim 3, wherein forming a transistor structure in the trench in which the magnetic tunnel junction is formed comprises:

5. The method according to claim 4, wherein the method further comprises:

6. A memory, comprising:

a conductive layer;

the first dielectric layer is positioned on the conductive layer;

7. The memory of claim 6, wherein the transistor structure comprises:

8. The memory of claim 7, wherein the material of the second semiconductor layer comprises: indium gallium zinc oxide.

9. The memory of claim 7, further comprising a first contact structure, a conductive line; the first contact structure is positioned on the first dielectric layer and connected with the second doped region; the conductive wire is positioned on the first contact structure and connected with the first contact structure.

10. The memory of claim 7 wherein the magnetic tunnel junction comprises a free layer, a tunnel layer, and a fixed layer stacked along the first dielectric layer thickness direction; the free layer is connected with the conductive layer, and the fixed layer is connected with the first doped region.