CN117042462A - Ferroelectric random access memory cell and nonvolatile memory - Google Patents
Ferroelectric random access memory cell and nonvolatile memory Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/40—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the peripheral circuit region
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application relates to a ferroelectric random access memory cell and a nonvolatile memory, the cell designs a required cell structure by utilizing a silicon-based MOSFET element and a bottom electrode, a dielectric layer and a top electrode which are sequentially stacked in a first direction, wherein the dielectric layer adopts a common dielectric layer which is a metal oxide material layer to separate two hafnium-based ferroelectric material layers, thus, the size of a ferroelectric phase after annealing is effectively reduced by inserting the common dielectric layer to separate the two hafnium-based ferroelectric material layers, and meanwhile, the number of ferroelectric phase grains of the whole device is improved by combining the regulation and control of a thermal expansion coefficient, thereby effectively improving the multi-value regulation and control capability of the device and easily controlling the fine structure of the dielectric layer in the device, realizing the multi-value storage of information by utilizing the polarization state in a ferroelectric capacitor, and effectively meeting the requirements of multi-value nonvolatile storage and calculation integrated technology.
Description
Technical Field
The application relates to the technical field of semiconductor devices, in particular to a ferroelectric random access memory unit and a nonvolatile memory.
Background
In recent years, with the rapid development of technologies such as internet of things, big data and cloud computing, the data volume required to be stored and processed generated by a terminal is larger and larger, and higher requirements are put on the storage density of a storage device and the computing energy efficiency of a processing device. Developing a multi-value nonvolatile memory technology and developing a memory integrated processing system architecture on the basis of the multi-value nonvolatile memory technology are effective methods for coping with the rapid increase of data quantity.
Hafnium-based ferroelectric materials are materials that can form a non-centrosymmetric ferroelectric phase after heat treatment by doping a fixed proportion of impurities in a hafnium oxide film, wherein the doped impurities generally include zirconium, aluminum, silicon, yttrium, strontium, lanthanum, gadolinium, and the like. The ferroelectric material is nonvolatile through the inversion of the internal polarization state, has the characteristics of high operation speed, low power consumption, long retention time, excellent durability and the like, and has important application prospects in the nonvolatile storage field and the calculation field. Currently, the multi-value regulation capability of the traditional hafnium-based ferroelectric device cannot meet the requirements of multi-value nonvolatile storage and calculation integrated technology.
Disclosure of Invention
Embodiments of the inventive concept provide a ferroelectric random access memory cell and a nonvolatile memory, the device having excellent multi-value modulation capability and being capable of easily controlling a fine structure of a dielectric layer in the device.
In order to achieve the above object, the embodiment of the present application adopts the following technical scheme:
in one aspect, a ferroelectric random access memory cell is provided, comprising a silicon-based MOSFET device, and a bottom electrode, a dielectric layer, and a top electrode sequentially stacked in a first direction, the first direction being perpendicular to an interface between the bottom electrode and the dielectric layer, the bottom electrode being connected to a drain of the silicon-based MOSFET device through an integrated circuit interconnect, a source of the silicon-based MOSFET device being for connection to a memory bit line, a gate of the silicon-based MOSFET device being for connection to a memory word line; the top electrode of the ferroelectric random access memory unit is grounded;
the dielectric layer comprises a first dielectric layer, a second dielectric layer and a third dielectric layer, wherein the first dielectric layer is a hafnium-based ferroelectric material layer, the second dielectric layer is a metal oxide material layer, the third dielectric layer is a hafnium-based ferroelectric material layer, the thermal expansion coefficient of the second dielectric layer is smaller than that of the first dielectric layer and the third dielectric layer, and the first dielectric layer, the second dielectric layer and the third dielectric layer are sequentially stacked in the first direction and are arranged between the bottom electrode and the top electrode.
In one embodiment, the second dielectric layer is SiO 2 、Ti 2 O 5 、Al 2 O 3 、ZnO 2 And/or Ta 2 O 5 A material layer, a first dielectric layer made of HfZrO 2 、HfAlO 2 、HfSiO 2 、HfLaO 2 、HfYO 2 、HfGdO 2 And/or HfSrO 2 A material layer, a third dielectric layer of HfZrO 2 、HfAlO 2 、HfSiO 2 、HfLaO 2 、HfYO 2 、HfGdO 2 And/or HfSrO 2 A material layer.
In one embodiment, the difference between the coefficients of thermal expansion of the first dielectric layer and the second dielectric layer is greater than or equal to 4.0X10 -6 The difference between the thermal expansion coefficients of the third dielectric layer and the second dielectric layer is greater than or equal to 4.0X10 -6 /K。
In one embodiment, the crystalline phase of the first dielectric layer includes an orthorhombic phase having ferroelectric properties and a monoclinic phase having cis properties, and the crystalline phase of the third dielectric layer includes an orthorhombic phase having ferroelectric properties and a monoclinic phase having cis properties.
In one embodiment, the first dielectric layer and the third dielectric layer have the same thickness in the first direction, and the third dielectric layer has a thickness in the first direction that is greater than the thickness of the second dielectric layer in the first direction.
In one embodiment, the total thickness of the dielectric layer in the first direction is less than or equal to 15nm.
In one embodiment, the bottom electrode is an electrode of titanium nitride, tungsten, aluminum, and/or copper material.
In one embodiment, the top electrode is an electrode of titanium nitride, tungsten, aluminum, and/or copper material.
In one embodiment, the silicon-based MOSFET device is an N-type silicon-based MOSFET device.
In another aspect, a nonvolatile memory is provided, including a plurality of ferroelectric random access memory cells as described above.
One of the above technical solutions has the following advantages and beneficial effects:
the ferroelectric random access memory cell and the nonvolatile memory adopt a silicon-based MOSFET element, and a bottom electrode, a dielectric layer and a top electrode which are sequentially stacked in a first direction to design a required cell structure, wherein the common dielectric layer of a metal oxide material layer is adopted in the dielectric layer to separate two hafnium-based ferroelectric material layers, so that smaller grains are formed in the first dielectric layer and a third dielectric layer during annealing, and the size of a ferroelectric phase after annealing is reduced; meanwhile, the thermal expansion coefficient of the second dielectric layer is designed to be smaller than that of the first dielectric layer and the third dielectric layer, and the regulation and control of the thermal expansion coefficient can form internal stress in the annealing process so as to form more ferroelectric phase grains in the first dielectric layer and the third dielectric layer, thereby maintaining or improving the overall residual polarization of the device. In this way, the two hafnium-based ferroelectric material layers are separated by inserting the common dielectric layer, so that the size of the annealed ferroelectric phase is reduced more effectively, and meanwhile, the number of ferroelectric phase grains of the whole device is improved by combining the regulation and control of the thermal expansion coefficient, thereby effectively improving the multi-value regulation and control capability of the device, easily controlling the fine structure of the dielectric layer in the device, realizing the multi-value storage of information by utilizing the polarization state in the ferroelectric capacitor, and effectively meeting the requirements of the multi-value nonvolatile storage and calculation integrated technology.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a cross-sectional view of a ferroelectric random access memory cell in one embodiment;
FIG. 2 is a cross-sectional view of a ferroelectric capacitor structure CAP in one embodiment;
fig. 3 is a hysteresis loop diagram of a ferroelectric capacitor structure CAP in one embodiment.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It is noted that reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.
Those skilled in the art will appreciate that the embodiments described herein may be combined with other embodiments. The term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
In the conventional art in the field, the intercalation method is a method effective for improving the polymorphism of the device, but sacrifices the amount of remnant polarization of the ferroelectric device. While research is being conducted on maintaining the residual polarization of a hafnium-based ferroelectric device, enhancing the multi-value regulation capability of the device is a key technology in the current field.
The ferroelectric device realizes the physical principle of nonvolatile storage and memory calculation integration as follows: the electric field regulates the polarization direction of the ferroelectric phase in the ferroelectric film, and the storage states represented by different polarization directions are different. In the traditional ferroelectric memory, only the polarization direction of the whole film is generally distinguished to be upward or downward, so that data 0 and 1 are represented, and 1bit data storage is realized. However, with the development and progress of technology, there is a higher demand for the capacity and storage density of memories, which leads to multi-valued storage capability.
The application reduces the size of ferroelectric phase after annealing by inserting a common dielectric layer with non-ferroelectricity or non-antiferroelectricity between two adjacent hafnium-based ferroelectric material layers in the research and realization process, overcomes the defect of reduced overall residual polarization of the device caused by inserting a separated common dielectric layer by regulating and controlling the thermal expansion coefficient, can maintain or promote the overall residual polarization of the device while realizing the reduction of the size of the ferroelectric phase, and is more beneficial to meeting the requirements of the current multi-value nonvolatile storage and calculation integrated technology.
Embodiments of the present application will be described in detail below with reference to the attached drawings in the drawings of the embodiments of the present application.
In one embodiment, as shown in FIG. 1, a ferroelectric random access memory cell 100 is provided that includes a silicon-based MOSFET element 12, and a bottom electrode BE, a dielectric layer 14, and a top electrode TE sequentially stacked in a first direction. The first direction is perpendicular to the interface between the bottom electrode BE and the dielectric layer 14, the bottom electrode BE being connected to the drain of the silicon-based MOSFET element through the integrated circuit interconnect line, the source of the silicon-based MOSFET element being used to connect the memory bit line, the gate of the silicon-based MOSFET element being used to connect the memory word line. The top electrode TE of the ferroelectric random access memory cell 100 is grounded. The dielectric layer 14 includes a first dielectric layer 141, a second dielectric layer 143, and a third dielectric layer 145. The first dielectric layer 141 is a hafnium-based ferroelectric material layer, the second dielectric layer 143 is a metal oxide material layer, the third dielectric layer 145 is a hafnium-based ferroelectric material layer, and the thermal expansion coefficient of the second dielectric layer 143 is smaller than the thermal expansion coefficients of the first dielectric layer 141 and the third dielectric layer 145. The first dielectric layer 141, the second dielectric layer 143, and the third dielectric layer 145 are sequentially stacked in the first direction and interposed between the bottom electrode BE and the top electrode TE.
It will BE appreciated that as shown in fig. 2, the bottom electrode BE, the dielectric layer and the top electrode TE, which are sequentially stacked in the first direction, may constitute a ferroelectric capacitor structure CAP, the bottom electrode BE of which is connected to the drain of the silicon-based MOSFET element through an integrated circuit interconnect, and multi-valued storage of information is achieved using polarization states in the ferroelectric capacitor.
Specifically, the first dielectric layer 141 and the third dielectric layer 145 are both hafnium-based ferroelectric material layers, and the common dielectric layer, i.e. the metal oxide material layer, is interposed between the two layers to isolate, and since the second dielectric layer 143 is neither a ferroelectric layer nor an antiferroelectric layer, but is a common dielectric layer, the size of the ferroelectric phase after annealing of the device can BE reduced by isolating the two hafnium-based ferroelectric material layers, but this also brings about the disadvantage of decreasing the overall remnant polarization of the device, so that the thermal expansion coefficient of the second dielectric layer 143 is set to BE smaller than that of the first dielectric layer 141 and the third dielectric layer 145, so that the stress in the layer formed in the annealing process of the device is realized by utilizing the regulation mode of the thermal expansion coefficient, so that more ferroelectric phase grains are formed in the first dielectric layer 141 and the third dielectric layer 145, thereby maintaining or improving the overall remnant polarization of the device, and finally realizing the regulation of the size and number of the ferroelectric phase in the ferroelectric film, so that the multi-valued state capability of the ferroelectric capacitor structure CAP is improved, and the multi-valued state capability of the ferroelectric capacitor structure CAP can BE realized by connecting the bottom electrode BE connected with the drain electrode of the silicon-based MOSFET element through the interconnection line to form a random memory cell through the integrated circuit, and the multi-valued state capacitor structure of the ferroelectric capacitor structure can BE realized by utilizing the ferroelectric information in the CAP.
The ferroelectric random access memory cell 100 is designed by using a silicon-based MOSFET device, and a bottom electrode BE, a dielectric layer and a top electrode TE sequentially stacked in a first direction, wherein the common dielectric layer, which is a metal oxide material layer, is used to separate two hafnium-based ferroelectric material layers, so as to form smaller grains in the first dielectric layer 141 and the third dielectric layer 145 during annealing, and reduce the size of ferroelectric phase after annealing; meanwhile, the thermal expansion coefficient of the second dielectric layer 143 is smaller than that of the first dielectric layer 141 and the third dielectric layer 145, and the thermal expansion coefficient can be controlled to form internal stress in the annealing process so as to form more ferroelectric phase grains in the first dielectric layer 141 and the third dielectric layer 145, thereby maintaining or improving the overall remnant polarization of the device. In this way, the two hafnium-based ferroelectric material layers are separated by inserting the common dielectric layer, so that the size of the annealed ferroelectric phase is reduced more effectively, and meanwhile, the number of ferroelectric phase grains of the whole device is improved by combining the regulation and control of the thermal expansion coefficient, thereby effectively improving the multi-value regulation and control capability of the device, easily controlling the fine structure of the dielectric layer in the device, realizing the multi-value storage of information by utilizing the polarization state in the ferroelectric capacitor, and effectively meeting the requirements of the multi-value nonvolatile storage and calculation integrated technology.
In one embodiment, the second dielectric layer 143 is SiO 2 、Ti 2 O 5 、Al 2 O 3 、ZnO 2 And/or Ta 2 O 5 A material layer. The first dielectric layer 141 is HfZrO 2 、HfAlO 2 、HfSiO 2 、HfLaO 2 、HfYO 2 、HfGdO 2 And/or HfSrO 2 A material layer. The third dielectric layer 145 is HfZrO 2 、HfAlO 2 、HfSiO 2 、HfLaO 2 、HfYO 2 、HfGdO 2 And/or HfSrO 2 A material layer.
It is understood that the first dielectric layer 141 may be composed of at least one hafnium-based ferroelectric material. In the present embodiment, the first dielectric layer 141 may be made of HfZrO 2 、HfAlO 2 、HfSiO 2 、HfLaO 2 、HfYO 2 、HfGdO 2 And HfSrO 2 At least one of the materials may be formed of a hafnium-based ferroelectric material, or may be composed of a mixture of two or more of these hafnium-based ferroelectric materials. The third dielectric layer 145 may be formed of at least one hafnium-based ferroelectric material, and the specific material layer may or may not be the same as the first dielectric layer 141, so long as the desired hafnium-based ferroelectric material layer can be formed. In the present embodiment, the third dielectric layer 145 may also be made of HfZrO 2 、HfAlO 2 、HfSiO 2 、HfLaO 2 、HfYO 2 、HfGdO 2 And HfSrO 2 At least one hafnium-based ferroelectric material of the materials may be formed of, or may be formed ofTwo or more of these hafnium-based ferroelectric materials are mixed. The first dielectric layer 141 and the third dielectric layer 145 are both hafnium-based ferroelectric material layers, so that grains of ferroelectric phase can be formed inside the thin film when the device is annealed, and the polarization direction thereof can be controlled by an externally applied voltage.
The second dielectric layer 143 may be composed of at least one or more metal oxide materials for isolating the first and third dielectric layers 141 and 145 so as to form smaller grains in the first and third dielectric layers 141 and 145 upon subsequent annealing. In the present embodiment, the second dielectric layer 143 is SiO 2 、Ti 2 O 5 、Al 2 O 3 、ZnO 2 And Ta 2 O 5 Any one of the material layers may be SiO 2 、Ti 2 O 5 、Al 2 O 3 、ZnO 2 And Ta 2 O 5 Two or more material layers in the material layers are mixed. Since the second dielectric layer 143 separates the first dielectric layer 141 and the third dielectric layer 145, grain growth in the first dielectric layer 141 and the third dielectric layer 145 may be independent of each other.
By the design of the second dielectric layer 143, on the one hand, it can be used to insulate the first dielectric layer 141 and the third dielectric layer 145 in order to form smaller grains in the first dielectric layer 141 and the third dielectric layer 145 upon a subsequent anneal; on the other hand, the thermal expansion coefficient of the second dielectric layer 143 is smaller than that of the first dielectric layer 141 and the third dielectric layer 145, so that the stress in the layers is formed in the annealing process, more ferroelectric phase grains are formed in the first dielectric layer 141 and the third dielectric layer 145, and the defect that the overall residual polarization of the device is reduced when the second dielectric layer 143 is inserted is overcome.
In one embodiment, further, the difference between the coefficients of thermal expansion of the first dielectric layer 141 and the second dielectric layer 143 is greater than or equal to 4.0X10 -6 and/K. The difference between the coefficients of thermal expansion of the third dielectric layer 145 and the second dielectric layer 143 is greater than or equal to 4.0x10 -6 /K。
It will be appreciated that the first and third dielectric layers 141, 145 have different coefficients of thermal expansionThere is no dependency on the thermal expansion coefficient of the second dielectric layer 143, the thermal expansion coefficient of the first dielectric layer 141 and the thermal expansion coefficient of the third dielectric layer 145. The thermal expansion coefficients of the first dielectric layer 141 and the third dielectric layer 145 are larger than the thermal expansion coefficient of the second dielectric layer 143. For example, the first dielectric layer 141 and the third dielectric layer 145 each have a coefficient of thermal expansion greater than or equal to 8.0X10 -6 And the second dielectric layer 143 has a coefficient of thermal expansion of less than or equal to 4.0X10 -6 and/K. For example, the difference between the coefficients of thermal expansion of the first dielectric layer 141 and the second dielectric layer 143 is greater than or equal to 4.0X10 -6 The difference between the coefficients of thermal expansion of the third dielectric layer 145 and the second dielectric layer 143 is greater than or equal to 4.0X10 -6 /K。
Since the first dielectric layer 141 and the second dielectric layer 143 have different coefficients of thermal expansion, a large in-plane compressive stress is generated at the interface between the first dielectric layer 141 and the second dielectric layer 143, and the crystal phase and the grain size in the first dielectric layer 141 can be controlled, increasing the ratio of the ferroelectric phase. Also, since the third dielectric layer 145 and the second dielectric layer 143 have different coefficients of thermal expansion, a large in-plane compressive stress is generated at the interface between the third dielectric layer 145 and the second dielectric layer 143, and the crystal phase and the grain size in the third dielectric layer 145 can be controlled, increasing the ratio of the ferroelectric phase. In this embodiment, the above-mentioned design of difference in thermal expansion coefficient between layers is adopted, so that the effect of improving the proportion of ferroelectric phases is optimal, and the effect of controlling the crystal phases and the crystal grain sizes is also optimal.
In one embodiment, the crystalline phase of the first dielectric layer 141 includes an orthorhombic phase having ferroelectric properties and a monoclinic phase having cis-electric properties. The crystal phase of the third dielectric layer 145 includes an orthorhombic crystal phase having ferroelectricity and a monoclinic crystal phase having cis-electricity.
It is understood that the first dielectric layer 141 includes an orthorhombic phase having ferroelectricity. The first dielectric layer 141 also includes a paraelectric monoclinic phase. Due to the interfacial stress between the first dielectric layer 141 and the second dielectric layer 143, the formation of the orthorhombic phase in the first dielectric layer 141 is increased, and the formation of the monoclinic phase is suppressed. In the embodiment of the present application, by adjusting the difference between the thermal expansion coefficients of the first dielectric layer 141 and the second dielectric layer 143, the first dielectric layer 141 can be controlled to increase the proportion of the orthorhombic phase and decrease the proportion of the monoclinic phase.
The third dielectric layer 145 includes an orthorhombic phase having ferroelectricity. The third dielectric layer 145 also includes a paraelectric monoclinic phase. Due to the interfacial stress between the third dielectric layer 145 and the second dielectric layer 143, the formation of the orthorhombic phase in the third dielectric layer 145 is increased, and the formation of the monoclinic phase is suppressed. In the embodiment of the present application, by adjusting the difference between the thermal expansion coefficients of the third dielectric layer 145 and the second dielectric layer 143, the third dielectric layer 145 can be controlled to increase the proportion of the orthorhombic phase and decrease the proportion of the monoclinic phase.
In one embodiment, the thicknesses of the first dielectric layer 141 and the third dielectric layer 145 in the first direction are the same. The thickness of the third dielectric layer 145 in the first direction is greater than the thickness of the second dielectric layer 143 in the first direction.
It is understood that the thicknesses of the first dielectric layer 141 and the third dielectric layer 145 are generally set to 5 to 8nm, and the thickness of the second dielectric layer 143 is generally set to 1 to 3nm. The first dielectric layer 141 needs to have a sufficient thickness (e.g., above 5 nm) to ensure ferroelectricity, and the second dielectric layer 143 needs to be as thin as possible, e.g., the thickness of the second dielectric layer 143 may be set in a range of 0.5 to 5nm, so that the influence on the electric field intensity inside the first dielectric layer 141 and the third dielectric layer 145 is reduced while the regulation of the first dielectric layer 141 and the third dielectric layer 145 is achieved.
In one embodiment, further, the total thickness of the dielectric layer in the first direction is less than or equal to 15nm. It can be appreciated that by designing the total thickness of the dielectric layer, the ferroelectric transistor can be ensured to have an operating voltage of less than or equal to 5V, so as to be compatible with the existing CMOS production process, thereby reducing the production cost.
In one embodiment, the bottom electrode BE is an electrode of titanium nitride, tungsten, aluminum, and/or copper material.
It is understood that the bottom electrode BE is formed of, or comprises at least one of, a metal nitride (e.g., titanium nitride) or a metal (e.g., tungsten, aluminum, or copper). Specifically, the bottom electrode BE may BE any one of titanium nitride, tungsten, aluminum and copper materials, or may BE an alloy electrode formed by mixing these materials, and since these materials have a low thermal expansion coefficient, they can form a large clamping stress on the first dielectric layer 141 and the third dielectric layer 145 during annealing, thereby contributing to the formation of a ferroelectric phase.
In one embodiment, the top electrode TE is an electrode of titanium nitride, tungsten, aluminum, and/or copper material.
It is understood that the top electrode TE is formed of, or comprises at least one of, a metal nitride (e.g., titanium nitride) or a metal (e.g., tungsten, aluminum, or copper). Specifically, the top electrode TE may be any one of titanium nitride, tungsten, aluminum and copper materials, or may be an alloy electrode formed by mixing these materials, and since these materials have a low thermal expansion coefficient, they can form a large clamping stress on the first dielectric layer 141 and the third dielectric layer 145 during annealing, thereby contributing to the formation of the ferroelectric phase.
In some embodiments, the bottom electrode BE and the top electrode TE may BE deposited by chemical vapor deposition or physical vapor deposition. Whereas dielectric layers can be generally prepared by atomic layer deposition at a temperature below 300 ℃. After the CAP structure is prepared, the CAP integral structure is subjected to an annealing process, and the temperature of the annealing process is selected to be in the range of 300-600 ℃ so as to obtain the optimal device performance.
In other embodiments, when designing and producing the ferroelectric capacitor structure CAP, the ratio of ferroelectric orthogonal phases in the first dielectric layer 141 and the second dielectric layer 143 may be controlled, so that the second dielectric layer 143 can realize grain refinement in the first dielectric layer 141 and the third dielectric layer 145, and at the same time, ensure that the overall residual polarization of the ferroelectric capacitor structure CAP is not reduced, as shown in fig. 3, which is a hysteresis loop diagram of the ferroelectric capacitor structure CAP.
In one embodiment, the silicon-based MOSFET device is an N-type silicon-based MOSFET device. It will be appreciated that N-type transistors are commonly used in the current research as silicon-based MOSFET devices because NMOS devices perform better than PMOS devices in most CMOS processes. The majority carrier of the NMOS device is electron, the majority carrier of the PMOS device is hole, and the mobility of the electron is higher than that of the hole, so that the NMOS device has higher operation speed, higher current driving capability and lower on-resistance, the area of the NMOS device is smaller under the same condition, and the NMOS device is easier to regulate and control by constraint charge generated by ferroelectric capacitor polarization. Therefore, in the above embodiments, P-type silicon-based MOSFET devices may also be used when the device performance sought is not a primary factor.
In one embodiment, a nonvolatile memory is also provided, including a plurality of ferroelectric random access memory cells 100 as described above.
It will be appreciated that, regarding the specific explanation of the ferroelectric random access memory cell 100 in this embodiment, the same explanation as that of the above embodiments of the ferroelectric random access memory cell 100 may be referred to, and the detailed description thereof will not be repeated here. The specific implementation manner of the ferroelectric random access memory 100 connected to each other to form the nonvolatile memory may be understood by referring to the same manner as that of the ferroelectric random access memory in the similar nonvolatile memory in the art, and will not be described in detail in this specification.
The nonvolatile memory designs a desired cell structure by using the ferroelectric random access memory cell 100 in which a silicon-based MOSFET element, and a bottom electrode BE, a dielectric layer, and a top electrode TE sequentially stacked in a first direction, and in which a metal oxide material layer, which is a common dielectric layer, is used to separate two hafnium-based ferroelectric material layers so as to form smaller grains in the first dielectric layer 141 and the third dielectric layer 145 upon annealing, thereby reducing the size of a ferroelectric phase after annealing; meanwhile, the thermal expansion coefficient of the second dielectric layer 143 is smaller than that of the first dielectric layer 141 and the third dielectric layer 145, and the thermal expansion coefficient can be controlled to form internal stress in the annealing process so as to form more ferroelectric phase grains in the first dielectric layer 141 and the third dielectric layer 145, thereby maintaining or improving the overall remnant polarization of the device. In this way, the two hafnium-based ferroelectric material layers are separated by inserting the common dielectric layer, so that the size of the annealed ferroelectric phase is reduced more effectively, and meanwhile, the number of ferroelectric phase grains of the whole device is improved by combining the regulation and control of the thermal expansion coefficient, thereby effectively improving the multi-value regulation and control capability of the device, easily controlling the fine structure of the dielectric layer in the device, realizing the multi-value storage of information by utilizing the polarization state in the ferroelectric capacitor, and effectively meeting the requirements of the multi-value nonvolatile storage and calculation integrated technology.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it is possible for those skilled in the art to make several variations and modifications without departing from the spirit of the present application, which fall within the protection scope of the present application. The scope of the application is therefore intended to be covered by the appended claims.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present application, unless explicitly specified and limited otherwise, the terms "connected" and the like are to be construed broadly, and may be, for example, mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
Claims (10)
1. A ferroelectric random access memory cell comprising a silicon-based MOSFET device, and a bottom electrode, a dielectric layer, and a top electrode sequentially stacked in a first direction, the first direction being perpendicular to an interface between the bottom electrode and the dielectric layer, the bottom electrode being connected to a drain of the silicon-based MOSFET device by an integrated circuit interconnect, a source of the silicon-based MOSFET device being for connection to a memory bit line, a gate of the silicon-based MOSFET device being for connection to a memory word line; the top electrode of the ferroelectric random access memory unit is grounded;
the dielectric layer comprises a first dielectric layer, a second dielectric layer and a third dielectric layer, wherein the first dielectric layer is a hafnium-based ferroelectric material layer, the second dielectric layer is a metal oxide material layer, the third dielectric layer is a hafnium-based ferroelectric material layer, the thermal expansion coefficient of the second dielectric layer is smaller than that of the first dielectric layer and the third dielectric layer, and the first dielectric layer, the second dielectric layer and the third dielectric layer are sequentially stacked in the first direction and are between the bottom electrode and the top electrode.
2. The ferroelectric random access memory cell of claim 1, wherein the second dielectric layer is SiO 2 、Ti 2 O 5 、Al 2 O 3 、ZnO 2 And/or Ta 2 O 5 A material layer, the first dielectric layer is HfZrO 2 、HfAlO 2 、HfSiO 2 、HfLaO 2 、HfYO 2 、HfGdO 2 And/or HfSrO 2 A material layer, the third dielectric layer is HfZrO 2 、HfAlO 2 、HfSiO 2 、HfLaO 2 、HfYO 2 、HfGdO 2 And/or HfSrO 2 A material layer.
3. The ferroelectric random access memory cell of claim 2, whereinThe difference between the coefficients of thermal expansion of the first dielectric layer and the second dielectric layer is greater than or equal to 4.0X10 -6 and/K, the difference between the coefficients of thermal expansion of the third dielectric layer and the second dielectric layer being greater than or equal to 4.0X10 -6 /K。
4. The ferroelectric random access memory cell of any one of claims 1 to 3, wherein the crystalline phase of the first dielectric layer comprises an orthorhombic phase having ferroelectric properties and a monoclinic phase having cis-electric properties, and the crystalline phase of the third dielectric layer comprises an orthorhombic phase having ferroelectric properties and a monoclinic phase having cis-electric properties.
5. The ferroelectric random access memory cell of claim 4, wherein the thickness of the first dielectric layer and the third dielectric layer in the first direction are the same, and the thickness of the third dielectric layer in the first direction is greater than the thickness of the second dielectric layer in the first direction.
6. The ferroelectric random access memory cell of claim 5, wherein a total thickness of the dielectric layer in the first direction is less than or equal to 15nm.
7. The ferroelectric random access memory cell of claim 4, wherein the bottom electrode is an electrode of titanium nitride, tungsten, aluminum, and/or copper material.
8. The ferroelectric random access memory cell of claim 7, wherein the top electrode is an electrode of titanium nitride, tungsten, aluminum, and/or copper material.
9. The ferroelectric random access memory cell of claim 1, wherein the silicon-based MOSFET device is an N-type silicon-based MOSFET device.
10. A nonvolatile memory comprising a plurality of ferroelectric random access memory cells according to any one of claims 1 to 9.
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