CN117042444A

CN117042444A - Memory device having vertical transistor and method of manufacturing the same

Info

Publication number: CN117042444A
Application number: CN202310524576.7A
Authority: CN
Inventors: 陈赫; 华子群; 王言虹; 刘威
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-05-10
Filing date: 2023-05-08
Publication date: 2023-11-10
Also published as: CN117042443A

Abstract

A three-dimensional (3D) memory device and a method of manufacturing the same are disclosed. The 3D memory device may include an array of memory cells. Each memory cell may include a capacitor and a vertical transistor. The vertical transistor may include: a semiconductor body extending in a vertical direction and contacting the capacitor; and a tri-gate structure surrounding the semiconductor body from three lateral directions. The 3D memory device may further include a memory controller configured to control the array of memory cells.

Description

Memory device having vertical transistor and method of manufacturing the same

Cross Reference to Related Applications

The present application claims the benefit of priority from U.S. provisional application No.63/340,150 filed on 5.10 of 2022 and U.S. provisional application No.63/343,840 filed on 19 of 5.2022, both of which are incorporated herein by reference in their entireties.

Technical Field

The present disclosure relates generally to the field of semiconductor technology, and more particularly, to memory devices and methods of manufacturing the same.

Background

Planar memory cells are scaled down to smaller dimensions by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cells approaches the lower limit, planar processing and fabrication techniques become challenging and costly. As a result, the storage density for the planar memory cell approaches the upper limit.

A three-dimensional (3D) memory architecture may address density limitations in planar memory cells. The 3D memory architecture includes a memory array and peripheral circuitry for facilitating operation of the memory array.

Disclosure of Invention

In some embodiments, a semiconductor device includes: an array of memory cells, each memory cell comprising: a capacitor; and a vertical transistor. The vertical transistor includes: a semiconductor body extending in a vertical direction and contacting the capacitor; and a tri-gate structure surrounding the semiconductor body from three lateral directions.

In some embodiments, the tri-gate structure surrounds curved sidewalls of the semiconductor body.

In some embodiments, the three-sided gate structures of a row of vertical transistors along a first lateral direction are connected to each other to form a word line extending along the first lateral direction, and the three lateral directions include at least two opposing lateral directions along the first lateral direction.

In some embodiments, the semiconductor device further includes: a plurality of first spacers and second spacers, each extending in a first lateral direction between rows of vertical transistors.

In some embodiments, the plurality of first spacers and the second spacers are alternately arranged along a second lateral direction perpendicular to the first lateral direction.

In some embodiments, a semiconductor body of a vertical transistor includes curved sidewalls and planar sidewalls.

In some embodiments, each first spacer is located between curved sidewalls of semiconductor bodies of vertical transistors of adjacent two rows.

In some embodiments, each second spacer is located between planar sidewalls of semiconductor bodies of vertical transistors of adjacent two rows.

In some embodiments, the semiconductor body is aligned along a second lateral direction.

In some embodiments, the semiconductor body is aligned along a third lateral direction having a non-zero angle relative to the first lateral direction.

In some embodiments, the semiconductor device further includes: a gate dielectric layer between the tri-sided gate structure and the curved sidewalls of the semiconductor body.

In some embodiments, the semiconductor device further includes a plurality of bit lines arranged in parallel along the second lateral direction. The capacitor is connected to a first end of the semiconductor body and the bit line is connected to a second end of the semiconductor body opposite the first end.

In some embodiments, a method of forming a semiconductor device includes: forming an array of semiconductor pillars; forming a conductive structure laterally surrounding each semiconductor pillar in the array of semiconductor pillars; forming a plurality of first spacers, each of the first spacers extending in a first lateral direction to separate adjacent rows of the array of semiconductor pillars; and forming a plurality of second spacers, each of the second spacers extending in the first lateral direction to separate each semiconductor pillar in a corresponding row of the array of semiconductor pillars into two semiconductor bodies, wherein the conductive structure is divided into a plurality of word lines by the plurality of first and second spacers, each word line extending in the first lateral direction and comprising a plurality of three-sided gate structures, each of the three-sided gate structures surrounding three sides of the corresponding semiconductor body.

In some embodiments, forming an array of semiconductor pillars comprises: forming a plurality of first trenches in the semiconductor layer, each of the first trenches extending in a first lateral direction; and forming a plurality of second trenches in the semiconductor layer, each of the second trenches extending in a second lateral direction different from the first lateral direction; and removing portions of the upper portion of the semiconductor layer to form an array of semiconductor pillars, wherein each semiconductor pillar has a curved sidewall, rows of the array of semiconductor pillars are separated by a plurality of first trenches, and columns of the array of semiconductor pillars are separated by a plurality of second trenches.

In some embodiments, the first lateral direction is perpendicular to the second lateral direction.

In some embodiments, the first lateral direction is not perpendicular to the second lateral direction.

In some embodiments, forming the conductive structure includes: forming a base dielectric structure in the plurality of first trenches and second trenches to laterally surround each semiconductor pillar in the array of semiconductor pillars; removing an upper portion of the base dielectric structure to expose an upper portion of each semiconductor pillar in the array of semiconductor pillars; forming a gate dielectric layer on exposed sidewalls of each semiconductor pillar in the array of semiconductor pillars; and forming a conductive structure to laterally surround the gate dielectric layer of each semiconductor pillar in the array of semiconductor pillars.

In some embodiments, forming the plurality of first spacers and the second spacers includes: forming a plurality of third trenches in the conductive structure, each of the third trenches extending along the first lateral direction and between adjacent rows of the array of semiconductor pillars; forming a plurality of fourth trenches in the array of conductive structures and semiconductor pillars, each of the fourth trenches extending in a first lateral direction to divide each semiconductor pillar in a corresponding row of the array of semiconductor pillars into two semiconductor bodies; forming a plurality of first spacers in the plurality of third trenches; and forming a plurality of second spacers in the plurality of fourth trenches.

In some embodiments, the method further comprises: forming a first doped region at a first end of each semiconductor body; forming a capacitor electrically connected to the first doped region; forming a second doped region at a second end of each semiconductor body opposite the first end; and forming a bit line electrically connected to the second doped region.

In some implementations, a memory system includes: an array of memory cells, each memory cell comprising: a capacitor, and a vertical transistor, the vertical transistor comprising: a semiconductor body extending in a vertical direction and in contact with the capacitor, and a three-sided gate structure surrounding the semiconductor body from three lateral directions including at least two opposite lateral directions; and a memory controller configured to control the array of memory cells.

Drawings

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the pertinent art to make and use the disclosure.

Fig. 1 shows a schematic circuit diagram of an exemplary memory device including an array of memory cells, each memory cell having a vertical transistor, according to some embodiments of the present disclosure.

Fig. 2A illustrates a schematic plan view of an array of memory cells in an exemplary memory device, each including a vertical transistor, according to some embodiments of the present disclosure.

Fig. 2B illustrates a schematic plan view of an array of memory cells in another example memory device, each including a vertical transistor, according to some other embodiments of the present disclosure.

Fig. 3A and 3B illustrate schematic side views of cross sections of memory cells including vertical transistors in an exemplary 3D memory device according to some embodiments of the present disclosure.

Fig. 4 illustrates a flowchart of an exemplary fabrication method for forming a 3D memory device including vertical transistors, according to some embodiments of the present disclosure.

Fig. 5A illustrates a schematic plan view of an exemplary 3D memory device at a certain stage of fabrication of the method illustrated in fig. 4, in accordance with various embodiments of the present disclosure.

Fig. 5B illustrates a schematic side cross-sectional view of an exemplary 3D memory device at a stage of fabrication of the method illustrated in fig. 4, in accordance with various embodiments of the present disclosure.

Fig. 6A illustrates a schematic plan view of an exemplary 3D memory device at a certain stage of fabrication of the method illustrated in fig. 4, in accordance with various embodiments of the present disclosure.

Fig. 6B illustrates a schematic side cross-sectional view of an exemplary 3D memory device at a stage of fabrication of the method illustrated in fig. 4, in accordance with various embodiments of the present disclosure.

Fig. 7A illustrates a schematic plan view of an exemplary 3D memory device at a certain stage of fabrication of the method illustrated in fig. 4, in accordance with various embodiments of the present disclosure.

Fig. 7B illustrates a schematic side cross-sectional view of an exemplary 3D memory device at a stage of fabrication of the method illustrated in fig. 4, in accordance with various embodiments of the present disclosure.

Fig. 8A illustrates a schematic plan view of an exemplary 3D memory device at a certain stage of fabrication of the method illustrated in fig. 4, in accordance with various embodiments of the present disclosure.

Fig. 8B illustrates a schematic side cross-sectional view of an exemplary 3D memory device at a certain stage of fabrication of the method illustrated in fig. 4, in accordance with various embodiments of the present disclosure.

Fig. 9A illustrates a schematic plan view of an exemplary 3D memory device at a certain stage of fabrication of the method illustrated in fig. 4, in accordance with various embodiments of the present disclosure.

Fig. 9B illustrates a schematic side cross-sectional view of an exemplary 3D memory device at a stage of fabrication of the method illustrated in fig. 4, in accordance with various embodiments of the present disclosure.

Fig. 10A illustrates a schematic plan view of an exemplary 3D memory device at a certain stage of fabrication of the method illustrated in fig. 4, in accordance with various embodiments of the present disclosure.

Fig. 10B illustrates a schematic side cross-sectional view of an exemplary 3D memory device at a stage of fabrication of the method illustrated in fig. 4, in accordance with various embodiments of the present disclosure.

Fig. 11 illustrates a block diagram of an exemplary system having a memory device, according to some embodiments of the present disclosure.

The present disclosure will be described with reference to the accompanying drawings.

Detailed Description

Although specific constructions and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Accordingly, other configurations and arrangements may be used without departing from the scope of this disclosure. Moreover, the present disclosure may also be used in a variety of other applications. The functional and structural features as described in the present disclosure may be combined, adjusted, and modified with each other and in a manner not explicitly shown in the drawings so that such combinations, adjustments, and modifications are within the scope of the present disclosure.

Generally, the terms may be understood, at least in part, from the usage in the context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" may also be construed to convey a singular usage or a plural usage, depending at least in part on the context. In addition, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, but rather may allow for the presence of additional factors not necessarily explicitly described, again depending at least in part on the context.

It should be readily understood that the meanings of "on … …", "over … …" and "over … …" in this disclosure should be interpreted in the broadest manner so that "on … …" means not only "directly on something" but also includes the meaning of "on something" with intermediate features or layers therebetween, and "over … …" or "over … …" means not only the meaning of "over something" or "over something" but also may include the meaning of "over something" or "over something" with no intermediate features or layers therebetween (i.e., directly on something).

Further, spatially relative terms, such as "under … …," "under … …," "lower," "above … …," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element (or elements) or feature as illustrated in the figures. In addition to the orientations shown in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "substrate" refers to a material upon which subsequent layers of material are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

As used herein, the term "layer" refers to a portion of material that includes regions having a thickness. The layer may extend over the entire underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Furthermore, the layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes at the top and bottom surfaces. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, and/or thereunder. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers in which interconnect lines and/or vertical interconnect channel (via) contacts are formed, and one or more dielectric layers.

Transistors are used as switching or selecting devices in memory cells of some memory devices, such as DRAM, PCM, and ferroelectric DRAM (FRAM). However, planar transistors commonly used in existing memory cells typically have a horizontal structure with buried word lines in the substrate and bit lines above the substrate. Since the source and drain of the planar transistor are laterally disposed at different locations, this increases the area occupied by the transistor. The design of planar transistors also complicates the placement of interconnect structures (e.g., word lines and bit lines) coupled to memory cells, e.g., limiting the pitch of word lines and/or bit lines, thereby increasing manufacturing complexity and reducing product yield. Further, because the bit line and the memory cell (e.g., capacitor or PCM element) are disposed on the same side of the planar transistor (above the transistor and substrate), the bit line process margin is limited by the memory cell and the coupling capacitance between the bit line and the memory cell (e.g., capacitor) increases. As saturated drain currents continue to increase, planar transistors may also suffer from high leakage currents, which is undesirable for the performance of the memory device.

To address one or more of the foregoing problems, the present disclosure introduces a solution in which vertical transistors replace conventional planar transistors as switching and selection devices in memory cell arrays of memory devices (e.g., DRAM, PCM, and FRAM). In the following description, DRAM is used as a non-exclusive example of the present disclosure. Vertically arranged transistors (i.e., drain and source are overlapped in plan view) can reduce the area of the transistor and simplify the layout of interconnect structures, such as metal wiring of word lines and bit lines, as compared to planar transistors, which can reduce manufacturing complexity and improve yield. For example, the pitch of the word lines and/or bit lines may be reduced for ease of fabrication. The vertical structure of the transistor also allows the bit line and the memory cell (e.g., capacitor) to be arranged on opposite sides of the transistor in the vertical direction (e.g., one above the transistor and one below the transistor), so that the process margin of the bit line can be increased and the coupling capacitance between the bit line and the memory cell can be reduced.

Consistent with the scope of the present disclosure, in accordance with some embodiments of the present disclosure, a memory cell array has vertical transistors, each including a semiconductor structure extending in a vertical direction and a tri-gate structure surrounding the semiconductor structure from three lateral directions. The tri-gate structure may have a larger gate control area to achieve better channel control with a smaller subthreshold swing. During the off state, leakage current of the multi-gate transistor can also be significantly reduced because the channel is fully depleted. Thus, using a tri-gate vertical transistor instead of a planar transistor can achieve much better speed (saturated drain current)/leakage current performance.

In some embodiments, the word lines and bit lines are disposed proximate to the bonding interface due to vertically disposed transistors that can be coupled to peripheral circuitry through a large number (e.g., millions) of parallel bonding contacts across the bonding interface, and can form a direct short-distance (e.g., micron-sized) electrical connection between the memory cell array and the peripheral circuitry to improve throughput and input/output (I/O) speed of the memory device. In some embodiments, the memory cell array and the peripheral circuit may be formed on different wafers, respectively, so that the manufacturing processes of the memory cell array and the peripheral circuit do not affect each other, and the area efficiency of the memory may be improved.

In some embodiments, the tri-gate vertical transistors disclosed herein are formed by separating full-gate transistors using trench isolation extending in the word line direction. Thus, the memory cell density in the bit line direction can be significantly increased (e.g., doubled) compared to using a process such as self-aligned double patterning (self-aligned double patterning, SADP) without unduly complicating the manufacturing process. In addition, the tri-gate vertical transistor has a larger process window for reducing word line, bit line, and transistor spacing compared to conventional planar transistors.

Fig. 1 illustrates a schematic diagram of an exemplary memory device 100 having an array of memory cells, each memory cell having a vertical transistor, according to some embodiments of the present disclosure. Memory device 100 may include an array of memory cells, where each memory cell 110 includes a vertical transistor 120 and a memory cell coupled to vertical transistor 120. In some embodiments as shown in fig. 1, the memory cell array is a DRAM cell array and the memory cells are capacitors 130 for storing charge as binary information stored by the respective DRAM cells. In some other embodiments not shown in the figures, the memory cell array is a PCM cell array, and the memory cells may be PCM elements (e.g., comprising chalcogenide alloys) for storing binary information of the respective PCM cells based on different resistivities of the PCM elements in amorphous and crystalline phases. In some embodiments, not shown in the drawings, the memory cell array is a FRAM cell array, and the memory cells may be ferroelectric capacitors for storing binary information of the respective FRAM cells based on switching between two polarization states of the ferroelectric material under an external electric field.

As shown in fig. 1, memory cells 110 may be arranged in a two-dimensional (2D) array having rows and columns. The memory device 100 may include: a word line 150 coupling the memory cell array to peripheral circuitry to control switching of the vertical transistors 120 in the memory cells 110 located in a row; and bit lines 160 coupling the memory cell array to peripheral circuitry to send data to memory cells 110 located in a column and/or to receive data from memory cells 110 located in a column. That is, each word line 150 is coupled to a respective row of memory cells 110, and each bit line 160 is coupled to a respective column of memory cells 110. In some embodiments, the gate of vertical transistor 120 is coupled to word line 150, one of the source and drain of vertical transistor 120 is coupled to bit line 160, the other of the source and drain of vertical transistor 120 is coupled to one electrode of capacitor 130, and the other electrode of capacitor 130 is coupled to ground.

Consistent with the scope of the present disclosure, as described in detail below, vertical transistor 120 (e.g., a vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET)) may replace a conventional planar transistor as a pass transistor of memory cell 110 to reduce the area occupied by the pass transistor, coupling capacitance, and complexity of interconnect routing. Fig. 2A illustrates a schematic plan view of an array of memory cells in an exemplary memory device, each including a vertical transistor, according to some embodiments of the present disclosure. Fig. 2B illustrates a schematic plan view of an array of memory cells in another example memory device, each including a vertical transistor, according to some other embodiments of the present disclosure.

As shown in fig. 2A and 2B, the memory device 200A/200B may include a plurality of word lines 250, each word line 250 extending in a first lateral direction (x-direction, referred to as a word line direction). The memory device 200A/200B may also include a plurality of bit lines 260, each bit line 260 extending in a second lateral direction (y-direction, referred to as a bit line direction) perpendicular to the first lateral direction. It should be appreciated that fig. 2A and 2B do not show a cross-sectional view of memory device 200A/200B in the same lateral plane, and that word line 250 and bit line 260 may be formed in different lateral planes to facilitate routing as described in detail below.

Memory cells 210/210' may be formed at intersections of word lines 250 and bit lines 260. In some implementations, each memory cell 210/210' includes a vertical transistor having a semiconductor body 222 and a gate structure 225. Fig. 3A and 3B illustrate schematic side views of cross sections of memory cells including vertical transistors in an exemplary 3D memory device, according to some embodiments of the present disclosure. Note that fig. 3A shows a cross-sectional side view along line AA 'of the memory cell 210 in fig. 2A or the memory cell 210' in fig. 2B, and fig. 3B shows a cross-sectional side view along line BB 'of the memory cell 210 in fig. 2A or the memory cell 210' in fig. 2B.

Referring to fig. 2A-2B and 3A-3B, the semiconductor body 222 may extend in a vertical direction (z-direction, not shown) perpendicular to the first and second lateral directions. Unlike planar transistors, which form active regions in the substrate, vertical transistor 120 includes a semiconductor body 222 that extends vertically (in the z-direction). It should be appreciated that the semiconductor body 222 may have any suitable 3D shape, such as a polyhedral shape or a cylindrical shape. That is, the cross-section of the semiconductor body 222 in plan view (e.g., in the x-y plane) may have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape, a partially circular shape, an elliptical shape, a partially elliptical shape, or any other suitable shape. In the following description, a cross section of the semiconductor body 222 having a partially elliptical shape as shown in fig. 2A and 2B is used as a non-exclusive example of the present disclosure. That is, in some embodiments, the semiconductor body 222 may include flat sidewalls 222-2 and curved sidewalls 222-1 in a vertical direction.

In some implementations, each vertical transistor 220 may further include a gate structure 225, the gate structure 225 surrounding multiple sides of the semiconductor body 222, i.e., surrounding the active region from multiple lateral directions. In other words, the active region of the vertical transistor 220, i.e., the semiconductor body 222, may be at least partially surrounded by the gate structure 225. For example, as shown in fig. 2A-2B and 3A-3B, the vertical transistor may be a three sided gate transistor, wherein the gate structure 225 surrounds the semiconductor body 222 (the active region in which the channel is formed) from three lateral directions. The tri-gate structure 225 may surround the curved sidewall 222-1 of the semiconductor body 222.

The gate structure 225 may comprise any suitable conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide. For example, the gate structure 225 may include doped polysilicon, i.e., gate polysilicon. In some embodiments, the gate structure 225 includes a plurality of conductive layers, such as a W layer over a TiN layer. In some embodiments, the gate dielectric 224 is located laterally between the tri-gate structure 225 and the curved sidewall 222-1 of the semiconductor body 222. Gate dielectric 224 may comprise any suitable dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric 224 may include silicon oxide, i.e., gate oxide.

As shown in fig. 2A and 2B, the tri-gate structure 225 of adjacent vertical transistors 220 in a first lateral direction (i.e., the word line direction or the x-direction) is continuous, e.g., is part of a continuous conductive layer having the tri-gate structure 225. That is, the plurality of three-sided gate structures 225 of a row (e.g., 211-216) of vertical transistors 220 may be connected to each other and extend in a first lateral direction to form a word line 250 of the row of vertical transistors 220. In contrast, the gate dielectrics 224 of adjacent vertical transistors in the word line direction are separated, e.g., not part of a continuous dielectric layer with gate dielectrics 224.

In a second lateral direction (i.e., bit line direction or y-direction), the three-sided gate structures 225 of adjacent vertical transistors 220 are separated by a plurality of first spacers 270 and second spacers 280, each of which extends between rows (e.g., 211-216) of vertical transistors 220 along the first lateral direction. In some embodiments, each of the plurality of first spacers 270 and second spacers 280 may include a dielectric wall extending in a first lateral direction parallel to the word line 250 to separate adjacent rows of vertical transistors 220. In some embodiments, the plurality of first spacers 270 and the second spacers 280 may include any suitable dielectric material, such as silicon oxide. In some embodiments, each of the plurality of first spacers 270 and second spacers 280 may further include one or more air gaps (not shown) embedded in the dielectric wall. As described below with respect to the manufacturing process, air gaps may be formed due to the relatively small spacing of the word lines 250 (and the rows of DRAM cells 210) in the second lateral direction. On the other hand, the relatively large dielectric constant of air in the air gap (e.g., about 4 times that of silicon oxide) may improve the insulating effect between word lines 250 (and rows of DRAM cells 210) as compared to some dielectrics (e.g., silicon oxide).

As shown in fig. 2A and 2B, a plurality of first spacers 270 and second spacers 280 are alternately arranged in the second lateral direction. Each first spacer 270 is located between curved sidewalls 222-1 of semiconductor bodies 222 of two adjacent rows of vertical transistors 220. Each second spacer 280 is located between the planar sidewalls 222-2 of the semiconductor bodies 222 of two adjacent rows of vertical transistors 220.

As shown in fig. 2A, in some embodiments, the semiconductor body 222 is aligned along a second lateral direction. In particular, the semiconductor bodies 222 of adjacent vertical transistors 220 separated by the second spacers 280 may be portions of an elliptical shape having a longitudinal axis along the second lateral direction. Each bit line 260 extending in the second lateral direction may be connected to the semiconductor body 222 of a column of vertical transistors 220. As shown in fig. 2B, in some other embodiments, the semiconductor body 222 is aligned along a third lateral direction (e.g., the h-direction as shown in fig. 2B) that has a non-zero angle relative to the first and second lateral directions. In particular, the semiconductor bodies 222 of adjacent vertical transistors 220 separated by the second spacers 280 may be portions of an elliptical shape having a longitudinal axis in the third lateral direction. The plurality of first bit lines 262 extending in the second lateral direction may be connected with semiconductor bodies 222 of a column of vertical transistors 220 belonging to an odd number of rows (e.g., 211, 213, 215 as shown in fig. 2B) of vertical transistors 220. A plurality of second bit lines 264, which are alternately arranged parallel to the first bit lines 262, may be connected with the semiconductor bodies 222 of a column of vertical transistors 220 belonging to an even number of rows (e.g., 212, 214, 216 as shown in fig. 2B) of vertical transistors 220.

Referring to fig. 3A and 3B, each vertical transistor 220 may further include a pair of source 227 and drain 228 (S/D, doped regions, also referred to as source and drain electrodes) formed at both ends of the semiconductor body 222 in a vertical direction (z-direction), respectively. Source 227 and drain 228 may be doped with any suitable P-type dopant, such As boron (B) or gallium (Ga), or any suitable N-type dopant, such As phosphorus (P) or arsenic (As). The source 225-7 and drain 225-8 may be located at opposite ends of the semiconductor body 222 in a vertical direction (z-direction). The gate structure 225 is vertically formed between the source 227 and the drain 228. Accordingly, when the gate voltage applied to the gate structure 225 is higher than the threshold voltage of the vertical transistor 220, a channel of the vertical transistor 220 may be formed in the semiconductor body 222 vertically between the source 225-7 and the drain 225-8.

One of the source/drains 227 may be connected to the bit line 260 through a bit line contact 327 and the other of the source/drains 228 may be connected to a memory cell (e.g., a capacitor 390 as shown in fig. 3A and 3B) through a memory cell contact 328. The memory cells may include any device capable of storing binary data (e.g., 0 and 1), including, but not limited to, capacitors for DRAM cells and FRAM cells, and PCM elements for PCM cells. In some embodiments, each vertical transistor 220 controls the selection and/or state switching of a corresponding memory cell coupled to the vertical transistor 220.

In some embodiments as shown in fig. 3A and 3B, the memory cell is a capacitor 390, the capacitor 390 including a first electrode (not shown) coupled to the source/drain 228 of the vertical transistor 220. Capacitor 390 may also include a capacitor dielectric (not shown) in contact with the first electrode and a second electrode (not shown) in contact with the capacitor dielectric. That is, the capacitor 390 may be a vertical capacitor in which two electrodes and a capacitor dielectric therebetween are vertically stacked (in the z-direction), and the capacitor dielectric may be sandwiched between the two electrodes. In some embodiments, each first electrode may be coupled to the source/drain 228 of a corresponding vertical transistor 220 in the same DRAM cell, while all second electrodes may be part of a common plate coupled to ground, e.g., a common ground. In some embodiments, the capacitor dielectric comprises a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al ₂ O ₃ 、HfO ₂ 、Ta ₂ O ₅ 、ZrO ₂ 、TiO ₂ Or any combination thereof. In some embodiments, both electrodes may include a leadElectrical materials including, but not limited to W, co, cu, al, tiN, taN, polysilicon, silicide, or any combination thereof.

It should be appreciated that the capacitor 390 may include any suitable structure and construction, such as a planar capacitor, stacked capacitor, multi-fin capacitor, cylindrical capacitor, trench capacitor, or substrate-to-board capacitor. That is, the capacitor 390 may be a vertical capacitor in which two electrodes and a capacitor dielectric therebetween are vertically stacked (in the z-direction), and the capacitor dielectric may be sandwiched between the two electrodes. In some embodiments, each first electrode may be coupled to the source/drain 228 of a corresponding vertical transistor 220 in the same DRAM cell, while all second electrodes may be part of a common plate coupled to ground, e.g., a common ground.

In some embodiments, as shown in fig. 2A-2B and fig. 3A-3B, each vertical transistor 220 is a three-sided gate transistor. That is, the tri-gate structure 225 may partially surround the semiconductor body 222 from three lateral directions. It should be noted that the three lateral directions include at least two opposite lateral directions (e.g., a positive x-direction and a negative x-direction) and a perpendicular lateral direction (e.g., a positive y-direction or a negative y-direction) between the two opposite lateral directions. Thus, in operation, a larger active channel region may be formed between the source and drain. That is, unlike planar transistors that include only a single planar gate (and result in a single planar channel), the vertical transistor 220 shown in fig. 2A-2B and 3A-3B may have a larger gate control area, thereby achieving better channel control with a smaller sub-threshold swing. During the off state, since the channel is fully depleted, the leakage current (I) of the vertical transistor 220 can be significantly reduced _off )。

In planar transistors and some lateral multi-gate transistors (e.g., finfets), the active region (e.g., semiconductor body (e.g., fin)) extends laterally (in the x-y plane) and the source and drain are disposed at different locations in the same lateral plane (x-y plane). In contrast, in the vertical transistor 220, the semiconductor body 222 extends vertically (in the z-direction) and the source and drain are disposed in different lateral planes, according to some embodiments. In some embodiments, the source and drain electrodes are formed at both ends of the semiconductor body 222, respectively, in a vertical direction (z-direction) so as to overlap in a plan view. Thus, the area occupied by the vertical transistor 220 (in the x-y plane) may be reduced compared to planar transistors and lateral multi-gate transistors. Moreover, the metal wiring coupled to the vertical transistor 220 may also be simplified, as the interconnect may be routed in a different plane. For example, bit line 260 and memory cell 212 may be formed on opposite sides of vertical transistor 220. In one example, the bit line 260 may be coupled to a source/drain 227 at an upper end of the semiconductor body 222, while the capacitor 390 may be coupled to another source/drain 228 at a lower end of the semiconductor body 222.

In some embodiments, one or more peripheral circuits (not shown) may be coupled to the memory cell array 200A/200B through the bit lines 260, the word lines 250, and any other suitable metal wiring. It is noted that the one or more peripheral circuits may include any suitable circuitry for facilitating operation of the memory cell array 200A/200B by applying voltage signals and/or current signals to each memory cell 210 via the word line 250 and the bit line 260 and sensing voltage signals and/or current signals from each memory cell 210. The one or more peripheral circuits may include various types of peripheral circuits formed using CMOS technology.

Fig. 11 illustrates a block diagram of a system 1100 with a memory device, according to some embodiments of the present disclosure. The system 1100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle-mounted computer, game controller, printer, pointing device, wearable electronic device, smart sensor, virtual Reality (VR) device, augmented Reality (AR) device, or any other suitable electronic device having storage therein. As shown in fig. 11, system 1100 may include a host 1108 and a memory system 1102, memory system 1102 having one or more memory devices 1104 and a memory controller 1106. Host 1108 can be a processor (e.g., a Central Processing Unit (CPU)) or a system on a chip (SoC) (e.g., an Application Processor (AP)) of an electronic device. Host 1108 may be configured to send data to memory device 1104 or to receive data from memory device 1104. The memory device 1104 may be any of the memory devices disclosed herein, such as the 3D memory device 100. In some implementations, the memory device 1104 includes an array of memory cells 200A/200B, each including a vertical transistor 220, as described in detail above.

According to some embodiments, memory controller 1106 is coupled to memory device 1104 and host 1108 and is configured to control memory device 1104. The memory controller 1106 may manage data stored in the memory device 1104 and communicate with the host 1108. The memory controller 1106 may be configured to control operations of the memory device 1104, such as read, write, and refresh operations. The memory controller 1106 may also be configured to manage various functions with respect to data stored or to be stored in the memory device 1104, including but not limited to refresh and timing control, command/request conversion, buffering and scheduling, and power management. In some implementations, the memory controller 1106 is also configured to determine the maximum storage capacity that the computer system can use, the number of memory banks, memory type and speed, memory granule data depth and data width, and other important parameters. Any other suitable function may also be performed by memory controller 1106. The memory controller 1106 may communicate with external devices (e.g., host 1108) according to a particular communication protocol. For example, the memory controller 1106 may communicate with external devices via at least one of various interface protocols (e.g., USB protocol, MMC protocol, peripheral Component Interconnect (PCI) protocol, PCI-E protocol, advanced Technology Attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small Computer Small Interface (SCSI) protocol, enhanced Small Disk Interface (ESDI) protocol, integrated Drive Electronics (IDE) protocol, firewire protocol, etc.).

Fig. 4 illustrates a flowchart of an exemplary manufacturing method 400 for forming a 3D memory device including vertical transistors, according to some embodiments of the present disclosure. Fig. 5A-5B, 6A-6B, 7A-7B, 8A-8B, 9A-9B, and 10A-10B illustrate schematic plan and schematic side cross-sectional views of an exemplary 3D memory device at certain stages of manufacture of the method 400 illustrated in fig. 4, in accordance with various embodiments of the present disclosure. It should be understood that the operations shown in method 400 are not exhaustive and that other operations may be performed before, after, or between any of the operations shown. Further, some of these operations may be performed simultaneously, or in a different order than shown in fig. 4.

As shown in fig. 4, the method 400 may begin at operation 401, where an array of semiconductor pillars may be formed at operation 401. In some embodiments, an array of semiconductor pillars may be formed in an upper portion of the semiconductor layer. Each semiconductor pillar may extend vertically (in the z-direction) and have any suitable 3D shape, such as a polyhedral shape or a cylindrical shape. That is, the cross-section of each semiconductor pillar in plan view (e.g., in the x-y plane) may have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape, an elliptical shape, or any other suitable shape.

In some embodiments, forming the array of semiconductor pillars may include forming a plurality of parallel first trenches in a first lateral direction and forming a plurality of parallel second trenches in a second lateral direction. As shown in the top view in fig. 5A, a plurality of parallel first trenches 530 are formed in a first lateral direction (e.g., x-direction, word line direction), and a plurality of parallel second trenches 540 are formed in a second lateral direction (e.g., y-direction, bit line direction). As shown in the side view along line CC' shown in fig. 5A in fig. 5B, a plurality of parallel first and second trenches 530, 540 extend vertically into an upper portion of the semiconductor layer 510 (e.g., a silicon substrate). The remaining portion of the upper portion of the semiconductor layer 510 forms an array of semiconductor pillars 520.

In some embodiments, a photolithography process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to pattern the first trench 530 and the second trench 540, and one or more dry etching and/or wet etching processes (e.g., RIE) are performed to etch the first trench 530 and the second trench 540 in the upper portion of the semiconductor layer 510. Thus, an array of semiconductor pillars 520 may be formed, each semiconductor pillar 520 extending vertically in an upper portion of the semiconductor layer 510. Since the semiconductor pillar 520 is formed by etching the semiconductor layer 510, the semiconductor pillar 520 may have the same material as the semiconductor layer 510, for example, single crystal silicon.

In fig. 5A, the second trenches 540 each extend in a second lateral direction (y-direction) perpendicular to the first lateral direction (x-direction). That is, each second trench 540 may be perpendicular to each first trench 530. In some other embodiments not shown in fig. 5A, the second trenches 540 may each extend in a third lateral direction (e.g., the h-direction as shown in fig. 2B) that has a non-zero angle relative to the first lateral direction (x-direction) and the second lateral direction (y-direction). That is, each second trench 540 may not be perpendicular to each first trench 530.

In some embodiments, forming the array of semiconductor pillars may further include rounding a lateral angle of each semiconductor pillar in the array of semiconductor pillars. As shown in fig. 5A, after forming the first trench 530 and the second trench 540, a further etching process (e.g., wet etching) may be performed to remove the lateral corners of each semiconductor pillar in the array of semiconductor pillars 520 such that each semiconductor pillar in the array of semiconductor pillars 520 has curved sidewalls. In some embodiments, the cross-section of each semiconductor pillar in plan view (e.g., in the x-y plane) may have a circular shape, an elliptical shape, or a square-like shape or a rectangular-like shape with rounded corners. In some embodiments, as shown in fig. 5A, the cross-section of each semiconductor pillar in plan view may have an elliptical shape with a longitudinal axis along the second lateral direction (y-direction). In some embodiments not shown in fig. 5A, the cross-section of each semiconductor pillar in plan view may have an elliptical shape with a longitudinal axis along a third lateral direction (e.g., the h-direction as shown in fig. 2B).

Referring back to fig. 4, the method 400 may proceed to operation 403, where a conductive structure may be formed in the first trench and the second trench to laterally surround each semiconductor pillar in the array of semiconductor pillars in operation 403. In some embodiments, the conductive structure may be isolated from the array of semiconductor pillars by a gate dielectric layer.

In some embodiments, forming the conductive structure may include forming a trench isolation structure in the first trench and the second trench. As shown in fig. 6A and 6B, a trench isolation structure 630 is formed in the first trench 530 and the second trench 540. In some embodiments, a dielectric (e.g., silicon oxide) is deposited to completely fill the first trench 530 and the second trench 540 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, spin-on processes, or any combination thereof. In some embodiments, a planarization process (e.g., CMP) is performed to remove excess dielectric deposited outside the top surface of semiconductor layer 510. Thus, an array of semiconductor pillars may be laterally separated from each layer by trench isolation structures 630. Then, as shown in fig. 7B, the trench isolation structure 630 may be etched back such that the remaining portions of the trench isolation structure 630 are located at bottom portions of the first trench 530 and the second trench 540.

In some embodiments, a gate dielectric layer 724 may be formed to cover exposed sidewalls of the semiconductor pillars 520. As shown in fig. 7A, a gate dielectric layer 724 may surround the sidewalls of each semiconductor pillar 520. In some embodiments, gate dielectric layer 724 is formed by depositing a layer of dielectric (e.g., silicon oxide) over the sidewalls of each semiconductor pillar 520 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD or any combination thereof. In some other embodiments, the gate dielectric layer 724 is formed by performing a wet oxidation and/or a dry oxidation process (e.g., in situ vapor generation (in situ steam generation, ISSG) oxidation) to form a native oxide (e.g., silicon oxide) as the gate dielectric layer 724 on the exposed sidewalls of the semiconductor pillars 520 (e.g., monocrystalline silicon).

After forming the gate dielectric layer, a conductive structure 740 is formed in the first trench 530 and the second trench 540. In some embodiments, to form the conductive structure 740, one or more conductive layers are deposited in the first trench 530 and the second trench 540 and over the gate dielectric layer 724. In some implementations, the conductive structure 740 may be formed by depositing one or more conductive materials (e.g., metals and/or metal compounds (e.g., W and TiN)) over the gate dielectric layer 724 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD or any combination thereof, to partially fill the first trench 530 and the second trench 540. For example, layers of TiN and W may be deposited sequentially to form conductive structure 740. A planarization process (e.g., CMP) may be performed to remove excess conductive material over the top surface of the semiconductor layer 510.

As shown in fig. 7B along line CC' shown in fig. 7A, in some embodiments, conductive structure 740 is etched back using, for example, dry etching and/or wet etching (e.g., RIE) to form a recess such that the upper end of conductive structure 740 is below the top surface of semiconductor pillar 520. In some embodiments, since gate dielectric layer 724 is not etched back, the upper end of conductive structure 740 is also located below the upper end of gate dielectric layer 724, gate dielectric layer 724 being flush with the top surface of semiconductor pillars 520. In some embodiments, as shown in fig. 7B, a dielectric layer 720 is formed in the remaining spaces of the first trench 530 and the second trench 540 and the recess (not shown) created by the etch back of the conductive structure 740, for example, by depositing a dielectric (e.g., silicon oxide) using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD or any combination thereof.

Referring back to fig. 4, then the method 400 may proceed to operation 405 and operation 407, in which in operation 405 a plurality of first spacers may be formed to separate adjacent rows of the array of semiconductor pillars, each of the first spacers extending in a first lateral direction; in operation 407, a plurality of second spacers may be formed to separate each semiconductor pillar in a corresponding row of the array of semiconductor pillars into two semiconductor bodies, each of the second spacers extending in the first lateral direction.

In some embodiments, a plurality of first spacers 870 may be formed to separate the conductive structure 740 into a plurality of conductive segments along the second lateral direction (y-direction), each first spacer 870 extending vertically between adjacent rows of semiconductor pillars 520 and extending laterally in parallel along the first lateral direction (x-direction). In some embodiments, to form the plurality of first spacers 870, the conductive structure 740 is patterned and etched to form a plurality of third trenches, each extending vertically between adjacent rows of semiconductor pillars 520 and extending laterally in parallel along the first lateral direction (x-direction), and a dielectric material is deposited to fill the plurality of third trenches.

In some embodiments, a plurality of second spacers 880 may be formed to separate the corresponding row of semiconductor pillars into a plurality of semiconductor bodies 820, each second spacer 880 extending vertically through the corresponding row of semiconductor pillars 520 and extending laterally parallel along a first lateral direction (x-direction). In some embodiments, to form the plurality of second spacers 880, the array of conductive structures 740 and semiconductor pillars 520 is patterned and etched to form a plurality of fourth trenches, each extending vertically through a corresponding row of semiconductor pillars 520 and extending laterally in a first lateral direction (x-direction), and a dielectric material is deposited to fill the plurality of fourth trenches.

In some embodiments, operations 405 and 407 may be performed simultaneously by a single photolithographic process for patterning the array of conductive structures 740 and semiconductor pillars 520 with third trenches and fourth trenches using an etch mask (e.g., photoresist mask and/or hard mask), and one or more dry etching and/or wet etching processes (e.g., RIE) are performed on the array of conductive structures 740 and semiconductor pillars 520 to etch the third trenches and fourth trenches. The etching may be controlled such that the bottoms of the third and fourth trenches may be flush with the bottom surface of the semiconductor pillars 520 or below the bottom surface of the semiconductor pillars 520. Then, for example, the first and second spacers 870 and 880 may be formed simultaneously by depositing a dielectric material (e.g., silicon oxide) to fill the third and fourth trenches using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof. A planarization process may be performed to remove excess dielectric over the top surface of the semiconductor layer 510.

In some embodiments, forming the plurality of first spacers 870 and second spacers 880 may include forming one or more air gaps (not shown) embedded in the dielectric material. One or more air gaps may be formed due to the relatively small spacing of the first and second spacers 870, 880 in the second lateral direction. The relatively large dielectric constant of air in the air gap (e.g., about 4 times that of silicon oxide) may improve the insulating effect between the separated conductive material(s) and semiconductive material(s) as compared to some dielectrics (e.g., silicon oxide).

Accordingly, in the second lateral direction (y-direction), the plurality of first spacers 870 and the second spacers 880 are alternately formed. Each row of semiconductor pillars 520 may be separated into two rows of semiconductor bodies 820 by corresponding second spacers 880. The conductive structure 740 may be separated into a plurality of word lines 850 by a plurality of first and second spacers 870 and 880. Each word line 850 may include a plurality of tri-gate structures (e.g., tri-gate structure 225) that each surround a curved sidewall of one of the semiconductor bodies 820 of a corresponding row aligned along the first lateral direction (x-direction). Thus, each first spacer 870 is formed between curved sidewalls of semiconductor bodies 222 in two adjacent rows of semiconductor bodies 820, and each second spacer 880 is formed between flat sidewalls of semiconductor bodies 820 in two adjacent rows of semiconductor bodies 820.

In some embodiments as shown in fig. 8A, the semiconductor body 820 is aligned along a second lateral direction (y-direction). In particular, the semiconductor bodies 820 separated by the second spacers 880 may be portions of an elliptical shape having a longitudinal axis along the second lateral direction (y-direction). In some other embodiments (not shown in fig. 8A), the semiconductor body 820 may be aligned along a third lateral direction (e.g., the h-direction as shown in fig. 2B) that has a non-zero angle relative to the first and second lateral directions. In particular, adjacent semiconductor bodies 820 separated by the second spacers 880 may be portions of an elliptical shape having a longitudinal axis along the third lateral direction.

Referring back to fig. 4, the method 400 may then proceed to operation 409, where a plurality of memory cells may be formed to electrically couple with the first end of each semiconductor body in operation 409.

In some embodiments as shown in fig. 9A and 9B, a first end (e.g., an upper end) of the semiconductor body 820 may be doped. As shown in fig. 9B, the exposed upper end of each semiconductor body 820, i.e., one of the two ends in the vertical direction (z-direction) of the semiconductor body 820, is doped to form a source/drain 827. In some embodiments, an implantation process and/or a thermal diffusion process is performed to dope the P-type dopant or the N-type dopant to the exposed upper end of the semiconductor body 820, thereby forming the source/drain 827. In some embodiments, a silicide layer is formed on the source/drain 827 by performing a silicidation process at the exposed upper end of the semiconductor body 820.

In some implementations, a plurality of memory cells are formed that are coupled to the semiconductor body (e.g., source/drain 827 thereof) through memory cell contacts. Each memory cell may include a capacitor 990 or a PCM element (not shown). In some embodiments as shown in fig. 9B, to form a memory cell as a capacitor 990, a first electrode is formed on the doped first end of the semiconductor body, a capacitor dielectric is formed on the first electrode, and a second electrode is formed on the capacitor dielectric. A common source/drain line 995 may be formed to couple capacitors 990 through memory cell contacts 992 in a column of vertical transistors. In some embodiments, common source/drain lines 995 may be formed on the capacitor dielectrics by patterning and etching electrode holes aligned with the respective capacitor dielectrics using photolithography and etching processes, and depositing conductive material to fill the electrode holes using a thin film deposition process.

Referring back to fig. 4, the method 400 may then proceed to operation 411, where a bit line may be formed to electrically couple with the second end of each semiconductor body in operation 411.

In some embodiments, the semiconductor layer 510 may be thinned to expose a second end (i.e., an undoped upper end) opposite the first end of the semiconductor body 820 (functioning as a lower end prior to flipping). In some implementations, a planarization process (e.g., CMP) and/or an etching process is performed on the semiconductor layer 510 until stopped by the trench isolation structures 630. As shown in fig. 10B, the exposed second end of the semiconductor body 820 is doped to form another source/drain 1002. In some embodiments, an implantation process and/or a thermal diffusion process is performed to dope the P-type dopant or the N-type dopant to the exposed upper end of the semiconductor body 820, thereby forming the source/drain 1002. In some embodiments, a silicide layer is formed on the source/drain 1002 by performing a silicidation process at the exposed upper ends of the semiconductor body 820. Thus, according to some embodiments, as shown in fig. 10B, each vertical transistor having a semiconductor body 820, source/drains 827 and 1002, a gate dielectric layer 724, and a tri-sided gate structure (part of word line 850) may be formed therefrom.

In some embodiments, a plurality of bit lines may be formed over the array of memory cells and electrically coupled to the second end of each semiconductor body. As shown in fig. 10B, a bit line 1026 may be formed to electrically couple with the source/drain 1002 at the upper end of the semiconductor body 820 through a bit line contact 1014. In some embodiments, bit line contacts 1014 and bit lines 1026 may be formed in a variety of processes including patterning and etching using photolithography and etching processes, and depositing conductive material using thin film deposition processes. For example, bit line contacts 1014 and bit lines 1026 may include conductive material deposited by one or more thin film deposition processes including, but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process for forming the interconnect may also include photolithography, CMP, wet/dry etching, or any other suitable process. Accordingly, the bit line 1026 and the capacitor 990 may be formed on opposite sides of the semiconductor body 820 and coupled to opposite ends of the semiconductor body 820.

It is noted that the exemplary method 400 first forms the capacitor 990 at the first end of the semiconductor body 820 and then forms the bit line 1026 at the second end of the semiconductor body 820. In some other embodiments, the fabrication method may first form bit line 1026 at a first end of semiconductor body 820 and then form capacitor 990 at a second end of semiconductor body 820.

The foregoing description of the specific embodiments may be readily modified and/or adapted for various applications. Accordingly, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor device, comprising:

an array of memory cells, each memory cell comprising:

a capacitor; and

a vertical transistor, the vertical transistor comprising:

a semiconductor body extending in a vertical direction and contacting the capacitor, and

a tri-gate structure surrounding the semiconductor body from three lateral directions.

2. The semiconductor device according to claim 1, wherein:

the tri-gate structure surrounds curved sidewalls of the semiconductor body.

3. The semiconductor device according to claim 1, wherein:

the three gate structures of a row of the vertical transistors along a first lateral direction are connected to each other to form a word line extending along the first lateral direction, and the three lateral directions include at least two opposing lateral directions along the first lateral direction.

4. The semiconductor device according to claim 3, further comprising:

a plurality of first and second spacers, each of the plurality of first and second spacers extending in the first lateral direction between rows of the vertical transistors.

5. The semiconductor device according to claim 3, wherein:

the plurality of first spacers and second spacers are alternately arranged along a second lateral direction perpendicular to the first lateral direction.

6. The semiconductor device according to claim 5, wherein:

the semiconductor body of one vertical transistor includes curved sidewalls and planar sidewalls.

7. The semiconductor device according to claim 6, wherein:

each first spacer is located between the curved sidewalls of the semiconductor bodies of the vertical transistors of two adjacent rows.

8. The semiconductor device according to claim 6, wherein:

each second spacer is located between the planar sidewalls of the semiconductor bodies of the vertical transistors of two adjacent rows.

9. The semiconductor device according to claim 6, wherein:

the semiconductor body is aligned along the second lateral direction.

10. The semiconductor device according to claim 6, wherein:

The semiconductor body is aligned along a third lateral direction having a non-zero angle relative to the first lateral direction.

11. The semiconductor device according to claim 2, further comprising:

a gate dielectric layer between the tri-gate structure and the curved sidewall of the semiconductor body.

12. The semiconductor device according to claim 5, further comprising:

a plurality of bit lines arranged in parallel along the second lateral direction,

wherein the capacitor is connected to a first end of the semiconductor body and the bit line is connected to a second end of the semiconductor body opposite the first end.

13. A method of forming a semiconductor device, comprising:

forming an array of semiconductor pillars;

forming a conductive structure laterally surrounding each semiconductor pillar in the array of semiconductor pillars;

forming a plurality of first spacers, each first spacer extending in a first lateral direction to separate adjacent rows of the array of semiconductor pillars; and

forming a plurality of second spacers, each second spacer extending along the first lateral direction to separate each semiconductor pillar in a corresponding row of the array of semiconductor pillars into two semiconductor bodies,

Wherein the conductive structure is divided into a plurality of word lines by the plurality of first and second spacers, each word line extending along the first lateral direction and comprising a plurality of tri-gate structures, each tri-gate structure surrounding three sides of the corresponding semiconductor body.

14. The method of claim 13, wherein forming the array of semiconductor pillars comprises:

forming a plurality of first trenches in the semiconductor layer, each first trench extending in the first lateral direction;

forming a plurality of second trenches in the semiconductor layer, each second trench extending in a second lateral direction different from the first lateral direction; and

and removing portions of an upper portion of the semiconductor layer to form an array of the semiconductor pillars, wherein each semiconductor pillar has a curved sidewall, rows of the array of semiconductor pillars are separated by the plurality of first trenches, and columns of the array of semiconductor pillars are separated by the plurality of second trenches.

15. The method of claim 14, wherein the first lateral direction is perpendicular to the second lateral direction.

16. The method of claim 14, wherein the first lateral direction is not perpendicular to the second lateral direction.

17. The method of claim 14, wherein forming the conductive structure comprises:

forming a base dielectric structure in the plurality of first trenches and second trenches to laterally surround each semiconductor pillar in the array of semiconductor pillars;

removing an upper portion of the base dielectric structure to expose an upper portion of each semiconductor pillar in the array of semiconductor pillars;

forming a gate dielectric layer on exposed sidewalls of each semiconductor pillar in the array of semiconductor pillars; and

the conductive structure is formed to laterally surround the gate dielectric layer of each semiconductor pillar in the array of semiconductor pillars.

18. The method of claim 17, wherein forming the plurality of first and second spacers comprises:

forming a plurality of third trenches in the conductive structure, each third trench extending along the first lateral direction and between adjacent rows of the array of semiconductor pillars;

forming a plurality of fourth trenches in the conductive structure and the array of semiconductor pillars, each fourth trench extending along the first lateral direction to divide each semiconductor pillar in the corresponding row of the array of semiconductor pillars into the two semiconductor bodies;

Forming the plurality of first spacers in the plurality of third trenches; and

the plurality of second spacers are formed in the plurality of fourth trenches.

19. The method of claim 18, further comprising:

forming a first doped region at a first end of each semiconductor body;

forming a capacitor electrically connected to the first doped region;

forming a second doped region at a second end of each semiconductor body opposite the first end; and

and forming a bit line electrically connected with the second doped region.

20. A memory system, comprising:

an array of memory cells, each memory cell comprising:

a capacitor; and

a vertical transistor, the vertical transistor comprising:

a tri-gate structure surrounding the semiconductor body from three lateral directions including at least two opposing lateral directions; and

a memory controller configured to control the array of memory cells.