CN117040498A - Clock generating circuit with variable duty ratio and electronic equipment - Google Patents
Clock generating circuit with variable duty ratio and electronic equipment Download PDFInfo
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- CN117040498A CN117040498A CN202311288192.6A CN202311288192A CN117040498A CN 117040498 A CN117040498 A CN 117040498A CN 202311288192 A CN202311288192 A CN 202311288192A CN 117040498 A CN117040498 A CN 117040498A
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- 239000003990 capacitor Substances 0.000 claims description 47
- 239000013078 crystal Substances 0.000 claims description 24
- 238000012795 verification Methods 0.000 claims description 22
- 230000003111 delayed effect Effects 0.000 claims description 12
- 230000003071 parasitic effect Effects 0.000 claims description 12
- 230000003068 static effect Effects 0.000 claims description 10
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
- H03B19/06—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes
- H03B19/14—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes by means of a semiconductor device
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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Abstract
The invention provides a clock generating circuit with variable duty ratio and electronic equipment, relating to the technical field of circuits, comprising: a signal generating circuit, a duty ratio correcting circuit and a frequency doubling circuit; the signal generating circuit, the duty ratio correction circuit and the frequency doubling circuit are sequentially connected in series; the signal generating circuit is used for generating an oscillating signal; the duty ratio correction circuit is used for receiving the oscillation signal, converting the oscillation signal into a clock signal with the duty ratio of a preset percentage, and sending the clock signal to the frequency doubling circuit; the frequency doubling circuit is used for receiving the clock signal, carrying out delay processing on the clock signal to obtain a delay signal, and determining a frequency doubling clock signal based on the delay signal and the clock signal. In the mode, the oscillating signal generated by the signal generating circuit is sent to the duty ratio correcting circuit for correction, so that the duty ratio of the clock signal sent to the frequency doubling circuit is ensured to meet the preset percentage, and the frequency of the obtained frequency doubling clock signal has stability.
Description
Technical Field
The present invention relates to the field of circuit technologies, and in particular, to a clock generating circuit with a variable duty cycle and an electronic device.
Background
The phase-locked loop is a main structural form of a frequency synthesizer in the current radio frequency receiver, and the clock generates an output clock signal with high precision and low phase noise, which is helpful for improving the performance of the phase-locked loop.
In a scenario where the frequency of the input clock signal of the pll cannot be increased, the clock signal is often multiplied to reduce the in-band noise and quantization noise of the pll.
When the clock signal is multiplied, if the duty ratio of the clock signal input to the frequency multiplication circuit deviates from 50%, the frequency stability of the output frequency multiplication clock signal is reduced, and the phase noise of the phase-locked loop is further deteriorated.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a clock generating circuit and an electronic device with variable duty ratio, so as to correct the duty ratio of the clock signal and make the frequency of the output multiplied clock signal have stability.
In a first aspect, an embodiment of the present invention provides a variable duty cycle clock generating circuit, including: a signal generating circuit, a duty ratio correcting circuit and a frequency doubling circuit; the signal generating circuit, the duty ratio correction circuit and the frequency doubling circuit are sequentially connected in series; the signal generating circuit is used for generating an oscillation signal and sending the oscillation signal to the duty ratio correcting circuit; the duty ratio correction circuit is used for receiving the oscillation signal, converting the oscillation signal into a clock signal with the duty ratio of a preset percentage, and sending the clock signal to the frequency doubling circuit; the frequency doubling circuit is used for receiving the clock signal, carrying out delay processing on the clock signal to obtain a delay signal, and determining a frequency doubling clock signal based on the delay signal and the clock signal.
In a preferred embodiment of the present invention, the signal generating circuit includes an oscillator, a crystal oscillator, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor; the crystal oscillator is connected with the input end and the output end of the oscillator, the upper polar plate of the first capacitor is connected with the input end of the oscillator, the lower polar plate of the first capacitor is grounded, the upper polar plate of the second capacitor is connected with the output end of the oscillator, the lower polar plate of the second capacitor is grounded, the upper polar plate of the third capacitor is connected with the input end of the oscillator and the crystal oscillator, the lower polar plate of the third capacitor is grounded, the upper polar plate of the fourth capacitor is connected with the output end of the oscillator and the crystal oscillator, and the lower polar plate of the fourth capacitor is grounded.
In a preferred embodiment of the present invention, the duty cycle correction circuit includes a duty cycle adjustment circuit and a duty cycle verification circuit, and the duty cycle adjustment circuit and the duty cycle verification circuit are connected in parallel; the duty ratio adjusting circuit is used for receiving the oscillating signal, converting the oscillating signal into a clock signal to be verified, and sending the clock signal to be verified to the duty ratio verifying circuit; the duty ratio verification circuit is used for receiving the clock signal to be verified, performing inversion processing on the clock signal to be verified to obtain an inversion logic signal, and verifying the clock signal to be verified based on the inversion logic signal.
In a preferred embodiment of the present invention, the duty cycle adjusting circuit includes a first buffer, an input end of the first buffer is connected to an output end of the oscillator, and an output end of the first buffer is connected to the frequency doubling circuit.
In a preferred embodiment of the present invention, the duty cycle verification circuit includes a duty cycle correction module, an input end of the duty cycle correction module is connected to an output end of the first buffer, and an output end of the duty cycle correction module is connected to an input end of the first buffer.
In a preferred embodiment of the present invention, the duty cycle correction module includes: the device comprises a duty ratio module, a filter, a comparator and a digital module, wherein the duty ratio module, the filter, the comparator and the digital module are sequentially connected in series, the input end of the duty ratio module is connected with the output end of the first buffer, and the output end of the digital module is connected with the input end of the first buffer.
In a preferred embodiment of the present invention, the frequency multiplier circuit includes: the frequency multiplier is connected with the second buffer in series, and the input end of the frequency multiplier is connected with the output end of the first buffer.
In a preferred embodiment of the present invention, the frequency multiplier includes a delay and an exclusive-or gate, wherein an input end of the delay is connected to an output end of the first buffer, an output end of the delay is connected to a first input end of the exclusive-or gate, a second input end of the exclusive-or gate is connected to an output end of the first buffer, and an output end of the exclusive-or gate is connected to the second buffer.
In a preferred embodiment of the present invention, the equivalent model of the crystal oscillator includes: the static capacitor is connected with the equivalent parasitic capacitor in parallel, the static capacitor is connected with the resistor in parallel, and the static capacitor is connected with the equivalent parasitic inductor in parallel.
In a second aspect, an embodiment of the present invention further provides an electronic device, including a clock generating circuit with a variable duty cycle according to the first aspect.
The embodiment of the invention has the following beneficial effects:
the embodiment of the invention provides a clock generating circuit with a variable duty ratio and electronic equipment, wherein an oscillating signal is generated through the signal generating circuit, the oscillating signal is sent to a duty ratio correcting circuit, the duty ratio correcting circuit receives the oscillating signal, the oscillating signal is converted into a clock signal with the duty ratio of a preset percentage, the clock signal is sent to a frequency doubling circuit, the frequency doubling circuit receives the clock signal, the clock signal is subjected to delay processing to obtain a delayed signal, the frequency doubling clock signal is determined based on the delayed signal and the clock signal, and the oscillating signal generated by the signal generating circuit is sent to the duty ratio correcting circuit for correction, so that the duty ratio of the clock signal sent to the frequency doubling circuit meets the preset percentage, the high precision and low phase noise of the clock signal are ensured, and the frequency of the obtained frequency doubling clock signal has stability.
Additional features and advantages of the disclosure will be set forth in the description which follows, or in part will be obvious from the description, or may be learned by practice of the techniques of the disclosure.
The foregoing objects, features and advantages of the disclosure will be more readily apparent from the following detailed description of the preferred embodiments taken in conjunction with the accompanying drawings.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of a variable duty cycle clock generation circuit according to an embodiment of the present invention;
FIG. 2 is a block diagram of another variable duty cycle clock generation circuit according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of an equivalent model of a crystal oscillator according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a duty cycle correction module according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a frequency multiplier according to an embodiment of the present invention;
fig. 6 is a schematic diagram of frequency multiplication according to an embodiment of the present invention.
The diagram is:
10-a signal generating circuit; a 20-duty cycle correction circuit; 30-a frequency doubling circuit; a 101-oscillator; 102, crystal oscillator; 103-a first capacitance; 104-a second capacitance; 105-a third capacitance; 106-fourth capacitance; 21-a duty cycle adjustment circuit; 22-duty cycle verification circuitry; 211-a first buffer; 221-a duty cycle correction module; 2211—a duty cycle module; 2212-a filter; 2213-comparator; 2214-a digital module; 301-frequency doubler; 302-a second buffer; 3011-a delayer; 3012-an exclusive-or gate; 1021-equivalent parasitic capacitance; 1022-resistance; 1023-equivalent parasitic inductance; 1024-static capacitance.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The phase-locked loop is a main structural form of a frequency synthesizer in the current radio frequency receiver, and the clock generates an output clock signal with high precision and low phase noise, which is helpful for improving the performance of the phase-locked loop.
In a scenario where the frequency of the input clock signal of the pll cannot be increased, the clock signal is often multiplied to reduce the in-band noise and quantization noise of the pll.
When the clock signal is multiplied, if the duty ratio of the clock signal input to the frequency multiplication circuit deviates from 50%, the frequency stability of the output frequency multiplication clock signal is reduced, and the phase noise of the phase-locked loop is further deteriorated. It is therefore necessary to perform duty cycle correction on the clock signal input to the frequency multiplier circuit.
The conventional duty cycle correction method is classified into analog correction and digital correction. The digital calibration accuracy is limited by the delay length, is sensitive to process angle, voltage and temperature variation, and has limited spurious suppression. Analog duty cycle calibration approaches typically have a smaller duty cycle calibration range, although higher calibration accuracy may be achieved.
Based on the above, the clock generating circuit and the electronic device with variable duty ratio provided by the embodiments of the present invention can correct the duty ratio of the clock signal sent to the frequency doubling circuit by sending the oscillation signal generated by the signal generating circuit to the duty ratio correcting circuit, thereby ensuring high precision and low phase noise of the clock signal, and enabling the frequency of the obtained frequency doubling clock signal to have stability.
For the convenience of understanding the present embodiment, a clock generating circuit with variable duty ratio disclosed in the embodiment of the present invention will be described in detail.
Example 1
The embodiment of the invention provides a clock generating circuit with a variable duty ratio, and fig. 1 is a structural diagram of the clock generating circuit with the variable duty ratio.
As shown in fig. 1, the one variable duty cycle clock generation circuit may include a signal generation circuit 10, a duty cycle correction circuit 20, and a frequency multiplication circuit 30; the signal generating circuit 10, the duty cycle correction circuit 20, and the frequency doubling circuit 30 are sequentially connected in series.
The signal generating circuit 10 is configured to generate an oscillation signal and send the oscillation signal to the duty cycle correction circuit 20.
The duty cycle correction circuit 20 is configured to receive the oscillation signal, convert the oscillation signal into a clock signal with a duty cycle of a preset percentage, and send the clock signal to the frequency doubling circuit 30.
Specifically, in order to ensure the frequency stability of the frequency multiplied signal, the preset percentage is 50%, i.e. the oscillating signal is converted into f 1 The clock signal with a duty cycle of 50% is sent to the frequency doubling circuit 30.
The frequency doubling circuit 30 is configured to receive a clock signal, delay the clock signal to obtain a delayed signal, and determine a doubled clock signal based on the delayed signal and the clock signal.
Specifically, the delay processing is to delay the clock signal by 90 ° to obtain a delayed signal, and the frequency-doubled clock signal is determined by the delayed signal and the clock signal. Wherein the frequency of the frequency multiplication clock signal can be 2 f 1 。
According to the clock generation circuit with the variable duty ratio, the oscillation signal is generated through the signal generation circuit 10 and is sent to the duty ratio correction circuit 20, the duty ratio correction circuit 20 receives the oscillation signal, the oscillation signal is converted into the clock signal with the duty ratio of the preset percentage, the clock signal is sent to the frequency doubling circuit 30, the frequency doubling circuit 30 receives the clock signal, the clock signal is subjected to delay processing to obtain the delayed signal, the frequency doubling clock signal is determined based on the delayed signal and the clock signal, the oscillation signal generated by the signal generation circuit 10 is sent to the duty ratio correction circuit 20 for correction, and therefore the duty ratio of the clock signal sent to the frequency doubling circuit 30 meets the preset percentage, high precision and low phase noise of the clock signal are guaranteed, and the frequency of the obtained frequency doubling clock signal has stability.
Example 2
The embodiment of the invention also provides another clock generating circuit with variable duty ratio; the clock generating circuit is realized on the basis of the clock generating circuit in the embodiment; the clock generation circuit focuses on the specific structures of the signal generation circuit 10, the duty ratio correction circuit 20, and the frequency multiplication circuit 30.
Fig. 2 is a block diagram of another variable duty cycle clock generating circuit according to an embodiment of the present invention. As shown in fig. 2, the signal generating circuit 10 includes an oscillator 101, a crystal oscillator 102, a first capacitor 103, a second capacitor 104, a third capacitor 105, and a fourth capacitor 106; the crystal oscillator 102 is connected with the input end and the output end of the oscillator 101, the upper polar plate of the first capacitor 103 is connected with the input end of the oscillator 101, the lower polar plate of the first capacitor 103 is grounded, the upper polar plate of the second capacitor 104 is connected with the output end of the oscillator 101, the lower polar plate of the second capacitor 104 is grounded, the upper polar plate of the third capacitor 105 is connected with the input end of the oscillator 101 and the crystal oscillator 102, the lower polar plate of the third capacitor 105 is grounded, the upper polar plate of the fourth capacitor 106 is connected with the output end of the oscillator 101 and the crystal oscillator 102, and the lower polar plate of the fourth capacitor 106 is grounded.
Wherein the first capacitor 103 and the second capacitor 104 are variable capacitors.
To ensure stability of the crystal 102, the oscillator 101 generates an oscillation signal to cancel the resonance of the crystal 102. Wherein the expression of the negative resistance generated by the oscillator 101 is:
wherein,representing a third capacitance 105, ">Representing the fourth capacitance 106, ">Indicating transconductance,/->Representing the capacitance of the oscillator 101, < >>Oscillating the angular frequency.
Wherein the crystal oscillator 102 may be a quartz crystal oscillator, and the frequency may be selected by the crystal oscillator 102, for example, the frequency is f 1 。
For convenience of understanding, fig. 3 is a schematic structural diagram of an equivalent model of a crystal oscillator according to an embodiment of the present invention.
As shown in fig. 3, the equivalent model of the crystal oscillator 102 includes: the equivalent parasitic capacitance 1021, the resistance 1022, the equivalent parasitic inductance 1023 and the static capacitance 1024 are sequentially connected in series, the static capacitance 1024 is connected in parallel with the equivalent parasitic capacitance 1021, the static capacitance 1024 is connected in parallel with the resistance 1022, and the static capacitance 1024 is connected in parallel with the equivalent parasitic inductance 1023.
The resonant frequency of the crystal oscillator 102 is expressed as follows:，/>representing the resonance frequency +.>Representing the circumference ratio>Representing the equivalent parasitic inductance 1023, < >>Representing equivalent parasitic capacitance 1021, < >>Representing multiplication.
The duty correction circuit 20 includes a duty adjustment circuit 21 and a duty verification circuit 22, and the duty adjustment circuit 21 and the duty verification circuit 22 are connected in parallel.
The duty cycle adjusting circuit 21 is configured to receive the oscillation signal, convert the oscillation signal into a clock signal to be verified, and send the clock signal to be verified to the duty cycle verifying circuit 22.
Illustratively, the duty cycle verification circuit 22 verifies the clock signal to be verified after receiving the clock signal to be verified, and if the verification is passed, the clock signal to be verified is sent to the duty cycle adjustment circuit 21 again, so the duty cycle adjustment circuit 21 is further configured to receive the clock signal to be verified and send the clock signal to be verified as a clock signal to the frequency doubling circuit 30.
Specifically, the duty ratio adjustment circuit 21 includes a first buffer 211, an input terminal of the first buffer 211 is connected to an output terminal of the oscillator 101, and an output terminal of the first buffer 211 is connected to the frequency multiplication circuit 30.
After the duty cycle verification circuit 22 receives the clock signal to be verified, if verification of the clock signal to be verified is not passed, the first buffer 211 may be replaced, so as to ensure that the replaced first buffer 211 may convert the oscillation signal into the clock signal.
Since the oscillation signal after passing through the first buffer 211 generally causes the duty ratio of the clock signal to be verified to deviate from the preset percentage due to the process mismatch, layout mismatch, temperature and other factors during the manufacture of the first buffer 211, the duty ratio verification circuit 22 is specifically configured to receive the clock signal to be verified, perform the negation processing on the clock signal to be verified to obtain a negated logic signal, and verify the clock signal to be verified based on the negated logic signal.
Specifically, the duty cycle verification circuit 22 may include a duty cycle correction module 221, an input terminal of the duty cycle correction module 221 being connected to an output terminal of the first buffer 211, and an output terminal of the duty cycle correction module 221 being connected to an input terminal of the first buffer 211.
Illustratively, the duty cycle verification circuit 22 performs inverse processing on the clock signal to be verified to obtain an inverse logic signal, samples the clock signal to be verified and the inverse logic signal to obtain a sampling clock signal and a sampling inverse logic signal, determines the common mode level of each of the sampling clock signal and the sampling inverse logic signal, determines whether the duty cycle of the sampling clock signal is a preset percentage according to the common mode level of each of the sampling clock signal and the sampling inverse logic signal, if the duty cycle is the preset percentage, the verification is passed, and if the duty cycle is not the preset percentage, the verification is failed.
For convenience of understanding, fig. 4 is a schematic structural diagram of a duty cycle correction module according to an embodiment of the present invention.
As shown in fig. 4, the duty ratio correction module 221 may include a duty ratio module 2211, a filter 2212, a comparator 2213, and a digital module 2214, where the duty ratio module 2211, the filter 2212, the comparator 2213, and the digital module 2214 are sequentially connected in series, an input terminal of the duty ratio module 2211 is connected to an output terminal of the first buffer 211, and an output terminal of the digital module 2214 is connected to an input terminal of the first buffer 211.
Illustratively, the duty cycle module 2211 may sample the clock signal to be verified and the inverting logic signal to obtain a sampling clock signal and an inverting logic signal, and input the sampling clock signal and the inverting logic signal to the filter 2212 to make the cut-off frequency of the filter 2212Extracting the common mode level of the sampling clock signal and the sampling inversion logic signal, sending the extracted common mode level of the sampling clock signal and the sampling inversion logic signal to the comparator 2213, further sending the level output by the comparator 2213 to the digital module 2214, judging whether the duty ratio of the sampling clock signal is a preset percentage by the digital module 2214, if not, replacing the first buffer 211, and converting the oscillation frequency again by using the replaced first buffer 211 until the oscillation frequency can be converted into the duty ratio of the preset percentageA clock signal.
Wherein, the filter 2212 is an RC filter,represents the cut-off frequency +.>Representing the circumference ratio>Resistor 1022 representing filter 2212, +.>Representing the capacitance of the filter 2212.
For easy understanding, fig. 5 is a schematic structural diagram of a frequency multiplier according to an embodiment of the present invention.
As shown in fig. 5, the frequency multiplier 301 may include a delay 3011 and an exclusive or gate 3012, where an input terminal of the delay 3011 is connected to an output terminal of the first buffer 211, an output terminal of the delay 3011 is connected to a first input terminal of the exclusive or gate 3012, a second input terminal of the exclusive or gate 3012 is connected to an output terminal of the first buffer 211, and an output terminal of the exclusive or gate 3012 is connected to the second buffer 302.
The delay signal is obtained by performing delay processing on the clock signal by using the frequency multiplier 301, the delay signal is input to the first input end of the exclusive-or gate 3012, the clock signal is input to the second input end of the exclusive-or gate 3012, and finally the frequency-multiplied clock signal is output by the exclusive-or gate 3012.
Wherein the frequency of the multiplied clock signal is 2 times the frequency of the clock signal.
Further, when the clock generating circuit is applied, considering that other circuits may affect the frequency-multiplied clock signal, the frequency-multiplied clock signal may be input to the other circuits through the second buffer 302, so that the interference of the other circuits on the frequency-multiplied clock signal is avoided, and the duty ratio of the frequency-multiplied clock signal is changed, thereby leading to an increase in phase noise.
The other circuits may be phase locked loops or other circuits requiring the use of a multiplied clock signal.
For ease of understanding, fig. 6 is a schematic diagram of frequency multiplication according to an embodiment of the present invention. As shown in fig. 6, the duty ratio of the clock signal is 50%, the delayed signal is a signal obtained by delaying the clock signal by 90 °, the multiplied clock signal is a signal output from the exclusive-or gate 3012 after the clock signal and the delayed signal are input to the exclusive-or gate 3012, and the frequency of the multiplied clock signal is 2 times the frequency of the clock signal.
According to the clock generating circuit with the variable duty ratio provided by the embodiment of the invention, the oscillating signal is sent to the first buffer 211, the first buffer 211 receives the oscillating signal, the oscillating signal is converted into the clock signal to be verified, the clock signal to be verified is sent to the duty ratio module 2211, the duty ratio module 2211 performs inversion processing on the clock signal to be verified to obtain the inversion logic signal, the sampled sampling clock signal and the sampling inversion logic signal are input to the filter 2212, the common mode level of each of the sampled sampling clock signal and the sampling inversion logic signal is sent to the comparator 2213, the level output by the comparator 2213 is sent to the digital module 2214, the digital module 2214 judges whether the duty ratio of the sampling clock signal is a preset percentage for verification, and the clock signal to be verified is sent to the frequency multiplier 301 as the clock signal for frequency multiplication after the verification is passed, so that the duty ratio of the clock signal sent to the frequency multiplier 301 meets the preset percentage, and the high precision and the low phase noise frequency multiplication stability of the clock signal is ensured.
Example 3
The embodiment of the invention also provides an electronic device, which is used for running the clock generating circuit with the variable duty ratio; the signal generating circuit 10 generates an oscillation signal, the oscillation signal is sent to the duty ratio correction circuit 20, the duty ratio correction circuit 20 receives the oscillation signal, the oscillation signal is converted into a clock signal with the duty ratio of a preset percentage, the clock signal is sent to the frequency doubling circuit 30, the frequency doubling circuit 30 receives the clock signal, the clock signal is subjected to delay processing to obtain a delay signal, the frequency doubling clock signal is determined based on the delay signal and the clock signal, the oscillation signal generated by the signal generating circuit 10 is sent to the duty ratio correction circuit 20 for correction, and therefore the duty ratio of the clock signal sent to the frequency doubling circuit 30 meets the preset percentage, high precision and low phase noise of the clock signal are guaranteed, and the frequency of the obtained frequency doubling clock signal has stability.
It will be clear to those skilled in the art that, for convenience and brevity of description, the structure of the electronic device described above may refer to the corresponding structure in the foregoing embodiment, and will not be described in detail herein.
Finally, it should be noted that: the above examples are only specific embodiments of the present invention, and are not intended to limit the scope of the present invention, but it should be understood by those skilled in the art that the present invention is not limited thereto, and that the present invention is described in detail with reference to the foregoing examples: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or perform equivalent substitution of some of the technical features, while remaining within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (10)
1. A variable duty cycle clock generation circuit, the clock generation circuit comprising: a signal generating circuit, a duty ratio correcting circuit and a frequency doubling circuit; the signal generating circuit, the duty ratio correcting circuit and the frequency doubling circuit are sequentially connected in series;
the signal generating circuit is used for generating an oscillation signal and sending the oscillation signal to the duty ratio correcting circuit;
the duty ratio correction circuit is used for receiving the oscillation signal, converting the oscillation signal into a clock signal with a duty ratio of a preset percentage, and sending the clock signal to the frequency doubling circuit;
the frequency doubling circuit is used for receiving the clock signal, delaying the clock signal to obtain a delayed signal, and determining a frequency doubling clock signal based on the delayed signal and the clock signal.
2. The clock generation circuit of claim 1, wherein the signal generation circuit comprises an oscillator, a crystal oscillator, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; the crystal oscillator is connected with the input end and the output end of the oscillator, the upper polar plate of the first capacitor is connected with the input end of the oscillator, the lower polar plate of the first capacitor is grounded, the upper polar plate of the second capacitor is connected with the output end of the oscillator, the lower polar plate of the second capacitor is grounded, the upper polar plate of the third capacitor is connected with the input end of the oscillator and the crystal oscillator, the lower polar plate of the third capacitor is grounded, the upper polar plate of the fourth capacitor is connected with the output end of the oscillator and the crystal oscillator, and the lower polar plate of the fourth capacitor is grounded.
3. The clock generation circuit of claim 2, wherein the duty cycle correction circuit comprises a duty cycle adjustment circuit and a duty cycle verification circuit, the duty cycle adjustment circuit and the duty cycle verification circuit being connected in parallel;
the duty ratio adjusting circuit is used for receiving the oscillating signal, converting the oscillating signal into a clock signal to be verified, and sending the clock signal to be verified to the duty ratio verifying circuit;
the duty ratio verification circuit is used for receiving the clock signal to be verified, performing inversion processing on the clock signal to be verified to obtain an inversion logic signal, and verifying the clock signal to be verified based on the inversion logic signal.
4. A clock generation circuit according to claim 3, wherein the duty cycle adjustment circuit comprises a first buffer, an input of the first buffer being connected to the output of the oscillator, an output of the first buffer being connected to the frequency doubling circuit.
5. The clock generation circuit of claim 4, wherein the duty cycle verification circuit comprises a duty cycle correction module, an input of the duty cycle correction module being coupled to the output of the first buffer, an output of the duty cycle correction module being coupled to the input of the first buffer.
6. The clock generation circuit of claim 5, wherein the duty cycle correction module comprises: the device comprises a duty ratio module, a filter, a comparator and a digital module, wherein the duty ratio module, the filter, the comparator and the digital module are sequentially connected in series, the input end of the duty ratio module is connected with the output end of the first buffer, and the output end of the digital module is connected with the input end of the first buffer.
7. The clock generation circuit of claim 6, wherein the frequency doubling circuit comprises: the frequency multiplier is connected with the second buffer in series, and the input end of the frequency multiplier is connected with the output end of the first buffer.
8. The clock generation circuit of claim 7, wherein the frequency multiplier comprises a delay and an exclusive-or gate, an input of the delay is connected to an output of the first buffer, an output of the delay is connected to a first input of the exclusive-or gate, a second input of the exclusive-or gate is connected to an output of the first buffer, and an output of the exclusive-or gate is connected to the second buffer.
9. The clock generation circuit of claim 2, wherein the equivalent model of the crystal oscillator comprises: the static capacitor is connected with the equivalent parasitic capacitor in parallel, the static capacitor is connected with the resistor in parallel, and the static capacitor is connected with the equivalent parasitic inductor in parallel.
10. An electronic device comprising the clock generation circuit of any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311288192.6A CN117040498B (en) | 2023-10-08 | 2023-10-08 | Clock generating circuit with variable duty ratio and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311288192.6A CN117040498B (en) | 2023-10-08 | 2023-10-08 | Clock generating circuit with variable duty ratio and electronic equipment |
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| Publication Number | Publication Date |
|---|---|
| CN117040498A true CN117040498A (en) | 2023-11-10 |
| CN117040498B CN117040498B (en) | 2024-01-26 |
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| CN117240220A (en) * | 2023-11-13 | 2023-12-15 | 成都明夷电子科技有限公司 | Radio frequency voltage controlled oscillator and electronic equipment |
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| CN117040498B (en) | 2024-01-26 |
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