CN117038743A - Infrared detector packaging structure and packaging method thereof - Google Patents
Infrared detector packaging structure and packaging method thereof Download PDFInfo
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- CN117038743A CN117038743A CN202311051964.4A CN202311051964A CN117038743A CN 117038743 A CN117038743 A CN 117038743A CN 202311051964 A CN202311051964 A CN 202311051964A CN 117038743 A CN117038743 A CN 117038743A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 28
- 229910000679 solder Inorganic materials 0.000 claims description 45
- 238000004519 manufacturing process Methods 0.000 claims description 34
- 238000010438 heat treatment Methods 0.000 claims description 23
- 238000009792 diffusion process Methods 0.000 claims description 19
- 238000003466 welding Methods 0.000 claims description 14
- 230000007423 decrease Effects 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 10
- 239000007788 liquid Substances 0.000 claims description 10
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000003384 imaging method Methods 0.000 abstract description 7
- 239000012535 impurity Substances 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 6
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 35
- 239000000463 material Substances 0.000 description 31
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 230000008018 melting Effects 0.000 description 8
- 238000002844 melting Methods 0.000 description 8
- 238000009713 electroplating Methods 0.000 description 6
- 238000001755 magnetron sputter deposition Methods 0.000 description 6
- 238000007740 vapor deposition Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000005496 eutectics Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 4
- 230000008020 evaporation Effects 0.000 description 4
- 238000001704 evaporation Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 229910000765 intermetallic Inorganic materials 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000007872 degassing Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/02016—Circuit arrangements of general character for the devices
- H01L31/02019—Circuit arrangements of general character for the devices for devices characterised by at least one potential jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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- Photometry And Measurement Of Optical Pulse Characteristics (AREA)
Abstract
The application relates to the field of semiconductors and discloses an infrared detector packaging structure and a packaging method thereof, wherein the infrared detector packaging structure comprises a window wafer and a circuit wafer which are oppositely arranged; the first seed layer is arranged on the opposite surfaces of the window wafer and the circuit wafer; the second seed layer is arranged on the opposite surface of the circuit wafer and the window wafer; the first wall body is arranged on the opposite surface of the first seed layer and the circuit wafer; the second wall body is arranged on the surface of the second seed layer opposite to the window wafer; and the bonding body is arranged between the first wall body and the second wall body. According to the infrared detector packaging structure, the first wall body and the second wall body are arranged between the window wafer and the circuit wafer, so that the distance between the window wafer and the circuit wafer is increased, the space of a cavity in the packaging structure can be increased, the vacuum degree inside a chip is improved, the chip performance is improved, the influence of impurities on the window wafer on the imaging effect of the chip can be reduced, and the yield of the packaging structure is improved.
Description
Technical Field
The application relates to the field of semiconductors, in particular to an infrared detector packaging structure and an infrared detector packaging method.
Background
The wafer level package directly takes a silicon wafer and the like as processing objects, packages a plurality of chips on the wafer simultaneously to form a detector and tests the detector in batches, has the characteristics of high production efficiency, low required cost, small package size and the like, and is widely applied to the electronic packaging industry.
At present, when the infrared detector adopts wafer level packaging, bonding film layers are respectively manufactured on the surfaces of a window wafer and a circuit wafer, and the window wafer and the circuit wafer are bonded in a eutectic welding mode. The film structure and components used in the eutectic bonding mode are relatively fixed, and are limited by the thickness of the film, so that the distance between the window wafer and the circuit wafer is usually smaller. The current packaging structure has the defects that firstly, for devices with performances such as an infrared detector and the like greatly influenced by the vacuum degree in the chip, the smaller distance between a window wafer and a circuit wafer can reduce the degassing efficiency, so that the vacuum degree in the chip is reduced, and the further improvement of the chip performance is restricted; second, the lower surface of the window wafer is close to the FPA (Focal Plane Array ) on the circuit wafer, so that the imaging effect of particles and other impurities on the window wafer on the chip can be seriously affected, and the yield of the infrared detector package is greatly limited.
Therefore, how to solve the above technical problems should be of great interest to those skilled in the art.
Disclosure of Invention
The application aims to provide an infrared detector packaging structure and a packaging method thereof, which are used for increasing the space of a cavity in the packaging structure, improving the vacuum degree in a chip and reducing the influence of impurities on a window wafer on the imaging effect of the chip.
In order to solve the above technical problems, the present application provides an infrared detector package structure, including:
a window wafer and a circuit wafer which are oppositely arranged;
the first seed layer is arranged on the opposite surfaces of the window wafer and the circuit wafer;
the second seed layer is arranged on the opposite surface of the circuit wafer and the window wafer;
the first wall body is arranged on the opposite surface of the first seed layer and the circuit wafer;
the second wall body is arranged on the surface of the second seed layer opposite to the window wafer;
and the bonding body is arranged between the first wall body and the second wall body.
Optionally, the bonding body is formed by solid-liquid diffusion bonding of a first bonding layer located on the opposite surface of the first wall body and the circuit wafer and a second bonding layer located on the opposite surface of the second wall body and the window wafer.
Optionally, the first bonding layer includes a first stacked reactive film layer and a first solder film layer, and the second bonding layer includes a second stacked reactive film layer and a second solder film layer; the first reaction film layer is positioned on the surface of the first wall opposite to the circuit wafer, and the second reaction film layer is positioned on the surface of the second wall opposite to the window wafer.
Optionally, the cross-sectional shape of the first reactive film layer and/or the second reactive film layer is a target shape, and the cross-sectional width of the target shape gradually decreases in a direction away from the first wall and/or the second wall.
Optionally, the target shape is trapezoidal.
Optionally, the taper angle of the first reaction film layer and/or the second reaction film layer is between 0 and 90 degrees.
Optionally, the shapes of the first wall body and the second wall body comprise a column shape and a table shape.
The application also provides a packaging method of the infrared detector packaging structure, which comprises the following steps:
manufacturing a first seed layer on the surface of the window wafer;
manufacturing a first wall on the surface, facing away from the window wafer, of the first seed layer;
manufacturing a first bonding layer on the surface of the first wall body, which is away from the first seed layer;
manufacturing a second seed layer on the surface of the circuit wafer;
manufacturing a second wall on the surface, facing away from the circuit wafer, of the second seed layer;
manufacturing a second bonding layer on the surface of the second wall body, which is away from the second seed layer;
and arranging the window wafer and the circuit wafer oppositely, and correspondingly contacting and bonding the first bonding layer and the second bonding layer to form a bonding body.
Optionally, the manufacturing a first bonding layer on a surface of the first wall facing away from the first seed layer includes:
manufacturing a first reaction film layer on the surface of the first wall body, which is away from the first seed layer;
manufacturing a first solder film layer on the surface of the first reaction film layer, which is away from the first wall body;
the manufacturing of the second bonding layer on the surface of the second wall body, which is away from the second seed layer, comprises the following steps:
manufacturing a second reaction film layer on the surface of the second wall body, which is away from the second seed layer;
and manufacturing a second solder film layer on the surface of the second reaction film layer, which is away from the second wall body.
Optionally, after the first reaction film layer is manufactured on the surface of the first wall facing away from the first seed layer, the method further includes:
correcting the first reaction film layer by utilizing photoetching and anisotropic etching so that the cross section shape of the first reaction film layer is a target shape, wherein the cross section width of the target shape gradually decreases in a direction away from the second wall body;
after the second reaction film layer is manufactured on the surface of the second wall body, which is away from the second seed layer, the method further comprises the following steps:
and correcting the shape of the second reaction film layer by utilizing photoetching and anisotropic etching so as to enable the cross-sectional shape of the second reaction film layer to be a target shape, wherein the cross-sectional width of the target shape gradually decreases in a direction away from the second wall body.
Optionally, the window wafer and the circuit wafer are disposed opposite to each other, so that the first bonding layer and the second bonding layer correspondingly contact and bond the first bonding layer and the second bonding layer includes:
arranging the window wafer and the circuit wafer oppositely so that the first bonding layer and the second bonding layer are correspondingly contacted;
and heating and pressurizing the window wafer and the circuit wafer respectively through a heating and pressurizing device to enable the first solder film layer and the second solder film layer to be melted, and forming diffusion pairs with the corresponding first reaction film layer and second reaction film layer to perform diffusion welding.
The application provides an infrared detector packaging structure, which comprises: a window wafer and a circuit wafer which are oppositely arranged; the first seed layer is arranged on the opposite surfaces of the window wafer and the circuit wafer; the second seed layer is arranged on the opposite surface of the circuit wafer and the window wafer; the first wall body is arranged on the opposite surface of the first seed layer and the circuit wafer; the second wall body is arranged on the surface of the second seed layer opposite to the window wafer; and the bonding body is arranged between the first wall body and the second wall body.
Therefore, the infrared detector packaging structure is provided with the first wall body and the second wall body between the window wafer and the circuit wafer, so that the distance between the window wafer and the circuit wafer is increased, the space of a cavity in the packaging structure can be increased, the vacuum degree inside a chip is improved, the chip performance is improved, the influence of impurities on the window wafer on the imaging effect of the chip can be reduced, and the yield of the packaging structure is improved. In addition, the first seed layer can ensure stable and reliable connection between the first wall body and the window wafer, and the second seed layer can ensure stable and reliable connection between the second wall body and the circuit wafer, so that the structural stability of the packaging structure is ensured.
In addition, the application also provides a packaging method with the advantages.
Drawings
For a clearer description of embodiments of the application or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description below are only some embodiments of the application, and that other drawings can be obtained from them without inventive effort for a person skilled in the art.
FIG. 1 is a schematic cross-sectional view of an infrared detector package structure according to an embodiment of the present application;
fig. 2 is a schematic diagram of an infrared detector package structure before bonding according to an embodiment of the present application;
FIG. 3 is a schematic cross-sectional view of a first reactive film layer and a second reactive film layer according to an embodiment of the present application;
fig. 4 is a flowchart of a packaging method of an infrared detector packaging structure according to an embodiment of the present application;
fig. 5 to 18 are flowcharts of a packaging process of an infrared detector package structure according to an embodiment of the present application;
in the figure, 1, a window wafer, 2, a circuit wafer, 3, a first seed layer, 4, a second seed layer, 5, a first wall, 6, a second wall, 7, a bonding body, 71, a first bonding layer, 72, a second bonding layer, 8, a first reaction film layer, 9, a second reaction film layer, 10, a first solder film layer, 11, a second solder film layer, 12, photoresist, 13, a first heating plate, 14 and a second heating plate.
Detailed Description
In order to better understand the aspects of the present application, the present application will be described in further detail with reference to the accompanying drawings and detailed description. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present application is not limited to the specific embodiments disclosed below.
As described in the background art, the distance between the window wafer and the circuit wafer in the current infrared detector packaging structure is smaller, so that on one hand, the internal vacuum degree of the chip in the packaging structure is affected, and on the other hand, the influence of impurities such as particles on the window wafer on the imaging effect of the chip is aggravated.
In view of this, the present application provides an infrared detector package structure, please refer to fig. 1, including:
a window wafer 1 and a circuit wafer 2 which are oppositely arranged;
a first seed layer 3 disposed on the opposite surface of the window wafer 1 and the circuit wafer 2;
a second seed layer 4 disposed on the opposite surface of the circuit wafer 2 to the window wafer 1;
the first wall body 5 is arranged on the surface of the first seed layer 3 opposite to the circuit wafer 2;
the second wall 6 is arranged on the surface of the second seed layer 4 opposite to the window wafer 1;
and a bonding body 7 arranged between the first wall body 5 and the second wall body 6.
The first seed layer 3, the second seed layer 4, the first wall 5, the second wall 6, the bonding body 7, the window wafer 1 and the circuit wafer 2 form a cavity in the packaging structure.
The material of the first wall body 5 is metal, the material of the window wafer 1 is semiconductor material such as silicon, and most of the metal and the semiconductor material such as silicon cannot be directly and reliably bonded, so that the first seed layer 3 is arranged to realize the adhesion between the first wall body 5 and the window wafer 1 and ensure the reliability of connection.
The material of the first seed layer 3 may be a metal, such as Ti, cr, etc., and is not particularly limited in the present application.
The thickness of the first seed layer 3 may be 0.1 to 10 μm, and the width may be set according to design requirements, and the present application is not particularly limited.
The material of the first wall 5 may be determined according to the material of the first seed layer 3 and the material of the first reaction film layer 8 disposed on the first wall 5, for example, the material of the first wall 5 may be Cu, ni, ag, au, pt or the like.
It should be noted that, in this embodiment, the structure of the first wall 5 is not limited and may be set by itself. For example, the first wall 5 has a single-layered structure, or the first wall 5 includes at least two layered first wall 5 unit layers. The thickness of the first wall 5 may be 1-1000 micrometers, and may be specifically set.
The shape of the first wall 5 includes, but is not limited to, a column shape, a table shape, and the like, where the column shape may be a column, a prism, and the like, and the table shape may be a round table, a prismatic table, and the like, and specifically may be set according to the actual situation.
The first wall body 5 is located on the surface of the first seed layer 3, which faces away from the window wafer 1, and it can be understood that the width of the first wall body 5 is smaller than or equal to the width of the first seed layer 3, so that the first seed layer 3 is distributed between the first wall body 5 and the window wafer 1.
The second wall 6 is made of metal, the circuit wafer 2 is made of semiconductor materials such as silicon, and most of the metal and the semiconductor materials such as silicon cannot be directly and reliably bonded, so that the second seed layer 4 is arranged to achieve adhesion between the second wall 6 and the circuit wafer 2, and connection reliability is guaranteed.
The material of the second seed layer 4 is a metal, such as Ti, cr, etc., and is not particularly limited in the present application.
The thickness of the second seed layer 4 may be 0.1 to 10 μm, and the width may be set according to design requirements, and the present application is not particularly limited.
The material of the second wall 6 may be determined according to the material of the second seed layer 4 and the material of the second reaction film layer 9 on the second wall 6, for example, the material of the second wall 6 may be Cu, ni, ag, au, pt or the like. The thickness of the second wall 6 may be 1-1000 micrometers, and may be specifically set.
The shape of the second wall 6 includes, but is not limited to, a column shape, a table shape, and the like, where the column shape may be a column, a prism, and the like, and the table shape may be a round table, a prismatic table, and the like, and specifically may be set according to the actual situation.
The second wall 6 is located on the surface of the second seed layer 4 facing away from the circuit wafer 2, and it can be understood that the width of the second wall 6 is smaller than or equal to the width of the second seed layer 4, so that the second seed layer 4 is distributed between the second wall 6 and the circuit wafer 2.
It should be noted that, in this embodiment, the structure of the second wall 6 is not limited and may be set by itself. For example, the second wall 6 has a single-layered structure, or the second wall 6 includes at least two layered second wall 6 unit layers.
The infrared detector packaging structure in this embodiment is provided with first wall body 5 and second wall body 6 between window wafer 1 and circuit wafer 2 for distance between window wafer 1 and the circuit wafer 2 increases, can increase the space of cavity in the packaging structure, improves the inside vacuum degree of chip, improves the chip performance, and can reduce the influence of impurity on window wafer 1 to the chip imaging effect, promotes packaging structure's yield. In addition, the first seed layer 3 can ensure stable and reliable connection between the first wall 5 and the window wafer 1, and the second seed layer 4 can ensure stable and reliable connection between the second wall 6 and the circuit wafer 2, so that the structural stability of the packaging structure is ensured.
Referring to fig. 2, in one embodiment of the present application, the bonding body 7 is formed by solid-liquid diffusion bonding of a first bonding layer 71 located on the opposite surface of the first wall 5 to the circuit wafer 2 and a second bonding layer 72 located on the opposite surface of the second wall 6 to the window wafer 1.
Compared with the bonding mode of eutectic welding, the bonding mode of solid-liquid diffusion bonding is adopted in the embodiment, bonding is realized through high-pressure diffusion, and the bonding temperature can be reduced to be lower than the melting point of the material. The chip after bonding can bear the temperature far exceeding the melting point of bonding materials, so the chip can be used at higher temperature, the process interval of subsequent processing is greatly widened, the chip can be applied in more scenes, and better bonding quality can be realized under the high-pressure condition of the bonding surface.
As an embodiment, the first bonding layer 71 includes a first reaction film layer 8 and a first solder film layer 10 stacked, and the second bonding layer 72 includes a second reaction film layer 9 and a second solder film layer 11 stacked; the first reactive film layer 8 is located on the surface of the first wall 5 opposite to the circuit wafer 2, and the second reactive film layer 9 is located on the surface of the second wall 6 opposite to the window wafer 1.
The two materials of the first solder film layer 10 and the first reaction film layer 8 need to form a solid-liquid diffusion bond 7 system, that is, an intermetallic compound can be formed therebetween.
The material of the first reactive film layer 8 may be a metal material, including but not limited to Cu, ni, ag, au, pt, co. The material of the first reaction film layer 8 may be the same as or different from the material of the first wall 5, which is within the scope of the present application.
The material of the first solder film layer 10 may be a metal material including, but not limited to, in, cu. The thickness of the first solder film layer 10 may be 1 to 5 micrometers, as the case may be; the width of the first solder film layer 10 may be 70% to 90% of the width of the first reaction film layer 8, as the case may be.
The shape of the first solder film layer 10 may be a column, a prism, or the like, and the mesa may be a truncated cone, a truncated pyramid, or the like.
The two materials of the second solder film 11 and the second reaction film 9 need to form a solid-liquid diffusion bond 7, i.e. an intermetallic compound can be formed between them.
The material of the second reactive film layer 9 may be a metal material, including but not limited to Cu, ni, ag, au, pt, co. The material of the second reaction film layer 9 may be the same as or different from the material of the second wall 6, which is within the scope of the present application.
The material of the second solder film layer 11 may be a metal material including, but not limited to, in, cu. The thickness of the first solder film layer 10 may be 1 to 5 micrometers, as the case may be; the width of the second solder film layer 11 may be 70% to 90% of the width of the second reaction film layer 9, as the case may be.
The second solder film layer 11 may have a columnar shape, a prismatic shape, or a truncated shape such as a truncated cone or a truncated pyramid.
In order to enhance the pressure bearing capability of the first reaction film layer 8 and the second reaction film layer 9 in bonding, the bonding temperature is reduced, the cross section shape of the first reaction film layer 8 and/or the second reaction film layer 9 is a target shape, and the cross section width of the target shape is gradually reduced in the direction away from the first wall 5 and/or the second wall 6.
The cross-sectional shapes of the first reactive film layer 8 and the second reactive film layer 9 are longitudinal cross-sectional shapes, as shown in fig. 2.
In this embodiment, the arrangement of the cross-sectional shapes of the first reactive film layer 8 and the second reactive film layer 9 includes three cases, the first case is that only the cross-sectional shape of the first reactive film layer 8 is a target shape, and the cross-sectional width of the target shape gradually decreases in the direction away from the first wall 5; second, only the cross-sectional shape of the second reaction film layer 9 is a target shape, and the cross-sectional width of the target shape gradually decreases in a direction away from the second wall 6; third, the cross-sectional shapes of the first reaction film layer 8 and the second reaction film layer 9 are target shapes, the cross-sectional width of the target shape of the first reaction film layer 8 gradually decreases in a direction away from the first wall 5, and the cross-sectional width of the target shape of the second reaction film layer 9 gradually decreases in a direction away from the second wall 6.
In the case of performing the solid-liquid diffusion bonding, the actual pressure-bearing area is the smaller of the two areas of the surface of the first reaction film layer 8 opposite to the second reaction film layer 9 and the surface of the second reaction film layer 9 opposite to the first reaction film layer 8. Therefore, when only the cross-sectional shape of the first reactive film layer 8 is the target shape, the area of the surface of the first reactive film layer 8 away from the first wall 5 is smaller than the area of the surface of the second reactive film layer 9 away from the second wall 6. When only the cross-sectional shape of the second reaction film layer 9 is the target shape, the area of the surface of the second reaction film layer 9 away from the second wall 6 is smaller than the area of the surface of the first reaction film layer 8 away from the first wall 5. When the cross-sectional shapes of the first reaction film layer 8 and the second reaction film layer 9 are both target shapes, the area of the surface of the first reaction film layer 8 away from the first wall 5 may be equal to the area of the surface of the second reaction film layer 9 away from the second wall 6.
As an embodiment, the taper angle of the first reaction film layer 8 and/or the second reaction film layer 9 is between 0 ° and 90 °. Furthermore, the taper angle of the first reaction film layer 8 and/or the second reaction film layer 9 is between 15 degrees and 60 degrees, so that the bearing pressure of the first reaction film layer 8 can be improved, and meanwhile, the alignment of the first welding film layer and the first reaction film layer 8 and the welding are facilitated.
In the related art, when eutectic welding is adopted, the heating temperature is higher, and the temperature is 30-50 ℃ higher than the melting point of the solder, so that low-temperature bonding cannot be realized. After bonding, the solder melts after heating the chip above the melting point of the solder layer, resulting in damage to the chip structure. Meanwhile, an alternative bonding material system is severely limited, and a bonding process interval is narrow; if the same pressure is applied to the circuit wafer 2, the circuit will be at risk of failure.
As an embodiment, the target shape is trapezoidal, and the pressure applied during bonding may be between 0.3MPa and 20MPa, and the heating temperature is higher than the melting point of the first solder film layer 10 and the second solder film layer 11 by 10 ℃ or less. Namely, in the embodiment, by increasing the pressure, the heating temperature during bonding can be reduced, the bonding time is shortened, the process interval is greatly expanded, the chip packaging efficiency is improved, and meanwhile, the circuit wafer 2 can be prevented from being invalid.
It is understood that when the target shape is a trapezoid, the shape of the first reaction film layer 8 and/or the second reaction film layer 9 may be a truncated cone or a truncated pyramid, or the like.
When the target shape is a trapezoid, the sides on both sides are straight lines, and in addition, the sides on both sides of the target shape may be curved as shown in fig. 3.
In summary, the infrared detector package structure of the application has the following advantages:
first, in terms of technology, a solid-liquid diffusion welding technology different from the traditional eutectic welding technology is selected, bonding is realized through high-pressure diffusion, and the bonding temperature can be reduced below the melting point of the material. The chip after bonding can bear the temperature far exceeding the melting point of bonding materials, so the chip can be used at higher temperature, the process interval of subsequent processing is greatly widened, and the chip can be applied in more scenes.
Second, two-way optimization is performed from the design structure. On the one hand, in order to improve the vacuum degree inside the chip and reduce the influence of particle impurities on the window on imaging, a wall layer with adjustable height is designed in the window wafer and the circuit wafer film layer so as to increase the distance between the window wafer and the circuit wafer. On the other hand, in order to prevent the failure of the circuit wafer while meeting the high-voltage condition of the bonding area, a film layer structure which is in a trapezoid shape as a whole is designed, and the pressure intensity acting on the bonding surface is improved by adjusting the area of the bonding surface.
Referring to fig. 4, the present application further provides a packaging method of an infrared detector packaging structure, including:
step S101: and manufacturing a first seed layer on the surface of the window wafer.
Step S102: and manufacturing a first wall body on the surface of the first seed layer, which is away from the window wafer.
Step S103: and manufacturing a first bonding layer on the surface of the first wall body, which is away from the first seed layer.
As an implementation manner, the manufacturing the first bonding layer on the surface of the first wall body facing away from the first seed layer includes:
manufacturing a first reaction film layer on the surface of the first wall body, which is away from the first seed layer;
and manufacturing a first solder film layer on the surface of the first reaction film layer, which is away from the first wall body.
In one embodiment of the present application, after the first reaction film layer is formed on the surface of the first wall facing away from the first seed layer, the method may further include:
and correcting the first reaction film layer by utilizing photoetching and anisotropic etching so that the cross section shape of the first reaction film layer is a target shape, wherein the cross section width of the target shape gradually decreases in a direction away from the second wall body.
Referring to fig. 5 to 10, steps S101 to S103 and the process of modifying the first reaction film layer will be described together.
The first seed layer 3 is formed on the entire surface (upper surface or lower surface) of the window wafer 1, and the first seed layer 3 may be formed by vapor deposition or the like.
The surface of the first seed layer 3 is coated with photoresist 12, the photoresist 12 is patterned, and the first wall 5 is manufactured in the grooves of the patterned photoresist 12. The thickness of the photoresist 12 is not lower than the sum of the thicknesses of the first wall 5 and the first reaction film layer 8, so that adhesion of metals at different positions in the deposition process is avoided, and no position can allow gas or liquid to contact the photoresist 12, so that the photoresist 12 cannot be removed; the first wall 5 is manufactured by evaporation, electroplating or magnetron sputtering, and the electroplating has the advantages of high efficiency and low cost compared with the evaporation and the magnetron sputtering.
A first reactive film layer 8 is formed on the surface of the first wall 5, and then the photoresist 12 is removed and a new photoresist 12 is recoated on the window wafer 1.
The pattern of the first reactive film layer 8 is corrected by photolithography and anisotropic etching so that the cross-sectional shape of the first reactive film layer 8 is a target shape, which is illustrated by a trapezoid in the drawing, and then the photoresist 12 is removed. The manner in which photoresist 12 is removed may be selected from dry photoresist removal or wet photoresist removal.
The main method of anisotropic etching is to add a resist, the taper angle of the modified first reaction film layer 8 can be between 0 and 90 degrees, and further, can be between 15 and 60 degrees, so that the pressure born by the first reaction film layer 8 can be improved, and meanwhile, the alignment of the first welding film layer and the first reaction film layer 8 and the welding are facilitated.
A new photoresist 12 is recoated on the window wafer 1 and the photoresist 12 is removed by photolithography, depositing a first solder film layer 10 on the first reactive film layer 8. The manner in which photoresist 12 is removed may be selected from dry photoresist removal or wet photoresist removal.
The first reaction film layer 8 and the first solder film layer 10 may be manufactured by vapor deposition, electroplating, magnetron sputtering, or the like, wherein when the vapor deposition is adopted, the manufactured first reaction film layer 8 and the manufactured first solder film layer 10 have good film forming quality and high precision, do not need to be laid with a circuit network below, and can be compatible with a plurality of metal types.
The first seed layer 3 not corresponding to the first wall 5 is removed.
It is understood that when the first reactive film layer 8 is not modified, the cross-sectional shape of the first reactive film layer 8 may be rectangular or square, or the like.
Step S104: and manufacturing a second seed layer on the surface of the circuit wafer.
Step S105: and manufacturing a second wall body on the surface of the second seed layer, which is away from the circuit wafer.
Step S106: and manufacturing a second bonding layer on the surface of the second wall body, which is away from the second seed layer.
As an implementation manner, the making the second bonding layer on the surface of the second wall body facing away from the second seed layer includes:
manufacturing a second reaction film layer on the surface of the second wall body, which is away from the second seed layer;
and manufacturing a second solder film layer on the surface of the second reaction film layer, which is away from the second wall body.
In one embodiment of the present application, after the second wall body has a surface facing away from the second seed layer, the method may further include:
and correcting the shape of the second reaction film layer by utilizing photoetching and anisotropic etching so as to enable the cross-sectional shape of the second reaction film layer to be a target shape, wherein the cross-sectional width of the target shape gradually decreases in a direction away from the second wall body.
Referring to fig. 11 to 16, steps S104 to S106 and the process of correcting the second reaction layer will be described together.
The second seed layer 4 is formed on the entire surface (upper surface or lower surface) of the circuit wafer 2, and the second seed layer 4 may be formed by vapor deposition or the like.
The surface of the second seed layer 4 is coated with photoresist 12, the photoresist 12 is patterned, and the second wall 6 is manufactured in the grooves of the patterned photoresist 12. The thickness of the photoresist 12 is not lower than the sum of the thicknesses of the second wall 6 and the second reaction film layer 9, so as to avoid adhesion of metals at different positions in the deposition process, and no position can allow gas or liquid to contact the photoresist 12, so that the photoresist 12 cannot be removed; the second wall 6 is manufactured by evaporation, electroplating or magnetron sputtering, and the electroplating has the advantages of high efficiency and low cost compared with the evaporation and the magnetron sputtering.
A second reactive film layer 9 is made on the surface of the second wall 6, then the photoresist 12 is removed and a new photoresist 12 is recoated on the circuit wafer 2.
The pattern of the second reactive film layer 9 is corrected by photolithography and anisotropic etching so that the cross-sectional shape of the second reactive film layer 9 is a target shape, which is illustrated by a trapezoid in the drawing, and then the photoresist 12 is removed. The manner in which photoresist 12 is removed may be selected from dry photoresist removal or wet photoresist removal.
The main method of anisotropic etching is to add a resist, the taper angle of the modified second reaction film layer 9 can be between 0 and 90 degrees, and further, can be between 15 and 60 degrees, so that the pressure born by the second reaction film layer 9 can be improved, and meanwhile, the alignment of the second welding film layer and the second reaction film layer 9 and the welding are facilitated.
A new photoresist 12 is recoated on the circuit wafer 2 and the photoresist 12 is removed by photolithography, depositing a second solder film layer 11 on the second reactive film layer 9. The manner in which photoresist 12 is removed may be selected from dry photoresist removal or wet photoresist removal.
The second reaction film layer 9 and the second solder film layer 11 may be manufactured by vapor deposition, electroplating, magnetron sputtering, or the like, and when vapor deposition is adopted, the manufactured second reaction film layer 9 and second solder film layer 11 have good film forming quality and high precision, do not need to lay a circuit network below, and are compatible with multiple metal types.
The second seed layer 4 not corresponding to the second wall 6 is removed.
It is understood that when the first reactive film layer 8 is not modified, the cross-sectional shape of the first reactive film layer 8 may be rectangular or square, or the like.
Step S107: and arranging the window wafer and the circuit wafer oppositely, and correspondingly contacting and bonding the first bonding layer and the second bonding layer to form a bonding body.
As an embodiment, the window wafer and the circuit wafer are disposed opposite to each other, and the bonding between the first bonding layer and the second bonding layer includes:
arranging the window wafer and the circuit wafer oppositely so that the first bonding layer and the second bonding layer are correspondingly contacted;
and heating and pressurizing the window wafer and the circuit wafer respectively through a heating and pressurizing device to enable the first solder film layer and the second solder film layer to be melted, and forming diffusion pairs with the corresponding first reaction film layer and second reaction film layer to perform diffusion welding.
As shown in fig. 17 to 18, the heating and pressurizing device may include a first heating plate 13 and a second heating plate 14, where the first heating plate 13 may be disposed on the outer surface of the window wafer 1, the second heating plate 14 may be disposed on the outer surface of the circuit wafer 2, and the window wafer 1 and the circuit wafer 2 may be uniformly heated, and heat may be transferred to the area to be soldered, so that the first solder film layer 10 and the second solder film layer 11 after bonding are melted simultaneously and form a diffusion couple with the first reaction film layer 8 and the lower second reaction film layer 9, and diffusion soldering is started. The highest temperature range of the to-be-welded area is 100-500 ℃. And simultaneously, uniformly loading pressure on the window wafer 1 and the circuit wafer 2, and transmitting the pressure to a region to be welded through the window wafer 1 and the circuit wafer 2, wherein the pressure range of the region to be welded is 0.3-20 MPa.
After bonding is completed, the first heating plate 13 and the second heating plate 14 are stopped at the same time, the bonded structure starts to be cooled, pressurization is stopped at the same time after the bonded structure is cooled to room temperature, the first heating plate 13 is separated from the window wafer 1, and the bonded structure is taken out, so that the infrared detector packaging structure is obtained.
During bonding, both increased pressure and increased heating temperature may promote diffusion to improve bonding quality. When the cross-sectional shape of the first reactive film layer and/or the second reactive film layer is modified to the target shape, the pressure bearing capacity of the first reactive film layer and/or the second reactive film layer in bonding can be increased, so that the heating temperature can be reduced, and the heating temperature is higher than the melting point of the first solder film layer and the second solder film layer by 10 ℃ or less.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other.
The infrared detector packaging structure and the infrared detector packaging method provided by the application are described in detail. The principles and embodiments of the present application have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present application and its core ideas. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the application can be made without departing from the principles of the application and these modifications and adaptations are intended to be within the scope of the application as defined in the following claims.
Claims (11)
1. An infrared detector package structure, comprising:
a window wafer (1) and a circuit wafer (2) which are arranged oppositely;
a first seed layer (3) arranged on the opposite surfaces of the window wafer (1) and the circuit wafer (2);
a second seed layer (4) arranged on the opposite surface of the circuit wafer (2) and the window wafer (1);
the first wall body (5) is arranged on the surface of the first seed layer (3) opposite to the circuit wafer (2);
the second wall body (6) is arranged on the surface of the second seed layer (4) opposite to the window wafer (1);
and the bonding body (7) is arranged between the first wall body (5) and the second wall body (6).
2. The infrared detector package structure as set forth in claim 1, wherein the bonding body (7) is formed by solid-liquid diffusion bonding of a first bonding layer (71) located on a surface of the first wall (5) opposite to the circuit wafer (2) and a second bonding layer (72) located on a surface of the second wall (6) opposite to the window wafer (1).
3. The infrared detector package structure as claimed in claim 2, wherein the first bonding layer (71) includes a laminated first reactive film layer (8) and first solder film layer (10), and the second bonding layer (72) includes a laminated second reactive film layer (9) and second solder film layer (11); the first reaction film layer (8) is located on the surface, opposite to the circuit wafer (2), of the first wall body (5), and the second reaction film layer (9) is located on the surface, opposite to the window wafer (1), of the second wall body (6).
4. An infrared detector package as claimed in claim 3, characterized in that the cross-sectional shape of the first reactive film layer (8) and/or the second reactive film layer (9) is a target shape, the cross-sectional width of which is gradually reduced in a direction away from the first wall (5) and/or the second wall (6).
5. The infrared detector package as set forth in claim 4, wherein the target shape is a trapezoid.
6. The infrared detector package structure as claimed in claim 4, wherein the taper angle of the first reaction film layer (8) and/or the second reaction film layer (9) is between 0 ° and 90 °.
7. The infrared detector package structure as claimed in any one of claims 1 to 6, wherein the shape of the first wall (5) and the second wall (6) includes a columnar shape, a mesa shape.
8. The packaging method of the infrared detector packaging structure is characterized by comprising the following steps of:
manufacturing a first seed layer (3) on the surface of the window wafer (1);
manufacturing a first wall body (5) on the surface of the first seed layer (3) deviating from the window wafer (1);
manufacturing a first bonding layer (71) on the surface of the first wall body (5) facing away from the first seed layer (3);
manufacturing a second seed layer (4) on the surface of the circuit wafer (2);
manufacturing a second wall (6) on the surface of the second seed layer (4) facing away from the circuit wafer (2);
manufacturing a second bonding layer (72) on the surface of the second wall body (6) facing away from the second seed layer (4);
the window wafer (1) and the circuit wafer (2) are arranged opposite to each other, and the first bonding layer (71) and the second bonding layer (72) are correspondingly contacted and bonded to form a bonding body (7).
9. The method for encapsulating an infrared detector package structure according to claim 8, wherein fabricating a first bonding layer (71) on a surface of the first wall (5) facing away from the first seed layer (3) includes:
manufacturing a first reaction film layer (8) on the surface of the first wall body (5) deviating from the first seed layer (3);
manufacturing a first solder film layer (10) on the surface of the first reaction film layer (8) facing away from the first wall body (5);
manufacturing a second bonding layer (72) on the surface of the second wall body (6) facing away from the second seed layer (4) comprises:
a second reaction film layer (9) is manufactured on the surface of the second wall body (6) deviating from the second seed layer (4);
and manufacturing a second solder film layer (11) on the surface of the second reaction film layer (9) facing away from the second wall body (6).
10. The method for encapsulating an infrared detector package as claimed in claim 9, further comprising, after the first reaction film layer (8) is formed on the surface of the first wall (5) facing away from the first seed layer (3):
correcting the first reaction film layer (8) by utilizing photoetching and anisotropic etching so that the cross-sectional shape of the first reaction film layer (8) is a target shape, wherein the cross-sectional width of the target shape gradually decreases in a direction away from the second wall body (6);
after the second reaction film layer (9) is manufactured on the surface of the second wall body (6) facing away from the second seed layer (4), the method further comprises the following steps:
and correcting the shape of the second reaction film layer (9) by utilizing photoetching and anisotropic etching so as to enable the cross-sectional shape of the second reaction film layer (9) to be a target shape, wherein the cross-sectional width of the target shape gradually decreases in a direction away from the second wall body (6).
11. The packaging method of the infrared detector package structure according to any one of claims 8 to 10, wherein disposing the window wafer (1) and the circuit wafer (2) opposite to each other so that the first bonding layer (71) and the second bonding layer (72) are in corresponding contact and bonding includes:
arranging the window wafer (1) and the circuit wafer (2) opposite to each other, and enabling the first bonding layer (71) and the second bonding layer (72) to be correspondingly contacted;
and heating and pressurizing the window wafer (1) and the circuit wafer (2) respectively by a heating and pressurizing device to enable the first solder film layer (10) and the second solder film layer (11) to be melted, and forming diffusion pairs with the corresponding first reaction film layer (8) and second reaction film layer (9) to perform diffusion welding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311051964.4A CN117038743A (en) | 2023-08-21 | 2023-08-21 | Infrared detector packaging structure and packaging method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311051964.4A CN117038743A (en) | 2023-08-21 | 2023-08-21 | Infrared detector packaging structure and packaging method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117038743A true CN117038743A (en) | 2023-11-10 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311051964.4A Pending CN117038743A (en) | 2023-08-21 | 2023-08-21 | Infrared detector packaging structure and packaging method thereof |
Country Status (1)
| Country | Link |
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| CN (1) | CN117038743A (en) |
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2023
- 2023-08-21 CN CN202311051964.4A patent/CN117038743A/en active Pending
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