CN117038581A - Method for removing pseudo grid - Google Patents

Method for removing pseudo grid Download PDF

Info

Publication number
CN117038581A
CN117038581A CN202311008859.2A CN202311008859A CN117038581A CN 117038581 A CN117038581 A CN 117038581A CN 202311008859 A CN202311008859 A CN 202311008859A CN 117038581 A CN117038581 A CN 117038581A
Authority
CN
China
Prior art keywords
layer
gate
pmos region
pseudo
dummy gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311008859.2A
Other languages
Chinese (zh)
Inventor
徐文胜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Original Assignee
Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huali Integrated Circuit Manufacturing Co Ltd filed Critical Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority to CN202311008859.2A priority Critical patent/CN117038581A/en
Publication of CN117038581A publication Critical patent/CN117038581A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The application provides a method for removing a pseudo gate, which comprises the following steps: step S1, providing a substrate with a PMOS region and an NMOS region, wherein a pseudo grid is formed on the substrate; step S2, forming a photoresist layer to expose the PMOS region; s3, ion implantation is carried out, and boron is doped in the pseudo grid electrode in the PMOS region; step S4, removing the photoresist layer; step S5, removing the pseudo grid electrode in the NMOS region; step S6, forming a first grid stack body in the NMOS region; step S7, removing the pseudo grid electrode positioned in the PMOS region; step S8, forming a second grid stack body in the PMOS region. The application obviously increases the process window for removing the pseudo grid, reduces the possibility of residue, reduces defects and improves the yield; the damage of an interface layer and a gate dielectric layer below the pseudo gate is reduced, the performance and stability of the device are improved, and the yield is further improved.

Description

Method for removing pseudo grid
Technical Field
The application relates to the technical field of semiconductors, in particular to a method for removing a pseudo gate.
Background
With the shrinking of semiconductor manufacturing processes, in order to further control leakage, it has been difficult to control channel current in gate stacks formed by stacking silicon oxynitride and polysilicon, so that a high-K metal gate (HKMG) process has been developed during the 28nm semiconductor manufacturing process, and control of the gate is enhanced by depositing a high-K dielectric layer and a work function metal layer, while overlying multiple ion implants to control leakage. Compared with the traditional process before 28nm, the HKMG process can realize better cost and consumption ratio and higher device performance. However, the HKMG process also introduces a number of technical difficulties, particularly the control of the N/PMOS interface, and the control of the N/PMOS threshold voltage (Vt).
To isolate the N/PMOS,28nm semiconductor fabrication process developed a solution to remove the dummy gate (Dummy Poly remove, DPR) in steps, first dummy gate removal for PMOS, then depositing the high K metal gate stack for PMOS, then dummy gate removal for NMOS, then depositing the high K metal gate stack for NMOS. The problem is that when the N/PMOS demarcation is carried out, the etching carried out in the pseudo gate removing process is in order to keep the interface layer and the gate dielectric layer at the bottom not damaged, the Over Etching (OE) of balanced etching and the shape control capability of etching are relatively poor, the pseudo gate residue at the bottom is easy to be caused, and the performance and the yield of the device are further affected.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present application is to provide a method for removing a dummy gate, which is used for solving the problems of damage to an underlying interface layer and a gate dielectric layer and the existence of dummy gate residues when removing the dummy gate in the prior art.
To achieve the above and other related objects, the present application provides a method for removing a dummy gate, comprising:
step S1, providing a substrate with a PMOS region and an NMOS region, wherein a pseudo grid is formed on the substrate;
step S2, forming a photoresist layer to expose the PMOS region;
s3, ion implantation is carried out, and boron is doped in the pseudo grid electrode in the PMOS region;
step S4, removing the photoresist layer;
step S5, removing the pseudo grid electrode in the NMOS region;
step S6, forming a first grid stack body in the NMOS region;
step S7, removing the pseudo grid electrode positioned in the PMOS region;
step S8, forming a second grid stack body in the PMOS region.
Preferably, the ion implantation is performed in multiple passes.
Preferably, the ion implantation is also doped with carbon in the dummy gate located in the PMOS region.
Preferably, in step S5, a wet etching is used to remove the dummy gate in the NMOS region.
Preferably, the etching solution of the wet etching is ammonia water.
Preferably, in step S7, the dummy gate in the PMOS region is removed by dry etching or wet etching.
Preferably, an interface layer and a gate dielectric layer which are stacked from bottom to top are formed between the dummy gate and the substrate.
Preferably, the material of the dummy gate is amorphous silicon or polysilicon, the gate dielectric layer is a high dielectric constant material layer or a stacked structure formed by stacking a silicon oxide layer and a high dielectric constant material layer from bottom to top, and the interface layer is a titanium nitride layer.
Preferably, the first gate stack includes a work function metal layer, a barrier metal layer, and a metal gate stacked from bottom to top.
Preferably, the second gate stack includes a first work function metal layer, a capping layer, a second work function metal layer, a barrier metal layer, and a metal gate, which are stacked from bottom to top.
As described above, the method for removing the pseudo gate provided by the application has the following beneficial effects: the process window for removing the pseudo grid is obviously increased, the possibility of residue is reduced, defects are reduced, and the yield is improved; the damage of an interface layer and a gate dielectric layer below the pseudo gate is reduced, the performance and stability of the device are improved, and the yield is further improved.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, it will be apparent that the drawings in the description below are some embodiments of the application, and that other drawings can be obtained from these drawings without inventive effort for a person skilled in the art.
FIGS. 1A-1G are schematic cross-sectional views of a device formed after completion of steps in a conventional method for removing a dummy gate;
FIG. 2 is a flowchart of a method for removing a dummy gate according to an embodiment of the present application;
fig. 3A to fig. 3H are schematic cross-sectional views of a device formed after each step in the method for removing a dummy gate according to the embodiment of the present application.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application.
The following description of the embodiments of the present application will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," and the like indicate orientations or positional relationships, which are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the devices or elements being referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present application described below may be combined with each other as long as they do not collide with each other.
The existing method for removing the pseudo grid comprises the following process flows:
as shown in fig. 1A, an isolation structure 101 is formed on a substrate 100, the isolation structure 101 divides the substrate 100 into a PMOS region and an NMOS region, and a dummy gate 102 and an interlayer dielectric layer 103 are further formed on the substrate 100;
as shown in fig. 1B, a first photoresist layer 105 is formed, exposing the NMOS region;
as shown in fig. 1C, the dummy gate 102 in the NMOS region is removed, and then the first photoresist layer 105 is removed;
as shown in fig. 1D, a first gate stack 106 is formed in the NMOS region;
as shown in fig. 1E, a second photoresist layer 107 is formed, exposing the PMOS region;
as shown in fig. 1F, the dummy gate 102 in the PMOS region is removed, and then the second photoresist layer 107 is removed;
as shown in fig. 1G, a second gate stack 108 is formed in the PMOS region.
After the dummy gate 102 in the PMOS region is removed, there is a residue of the dummy gate 102 at the location indicated by the dashed arrow in fig. 1F, thereby affecting the performance and yield of the device.
In order to solve the problem, the application provides a method for removing the pseudo gate.
Referring to fig. 2, a flowchart of a method for removing a dummy gate according to an embodiment of the application is shown.
As shown in fig. 2, the method for removing the dummy gate includes the following steps:
step S1, providing a substrate with a PMOS region and an NMOS region, wherein a pseudo grid is formed on the substrate;
step S2, forming a photoresist layer to expose the PMOS region;
s3, ion implantation is carried out, and boron is doped in the pseudo grid electrode in the PMOS region;
step S4, removing the photoresist layer;
step S5, removing the pseudo grid electrode in the NMOS region;
step S6, forming a first grid stack body in the NMOS region;
step S7, removing the pseudo grid electrode positioned in the PMOS region;
step S8, forming a second grid stack body in the PMOS region.
In step S1, as shown in fig. 3A, the substrate 300 is a silicon substrate, a germanium substrate, a silicon-on-insulator substrate, or the like; or the material of the substrate 300 may also include other materials such as III-V compounds such as gallium arsenide. Those skilled in the art may select the constituent materials of the substrate 300 according to the type of device structure formed on the substrate 300, and thus the type of the substrate 300 should not limit the scope of the present application.
The substrate 300 has an isolation feature 301 formed thereon, the isolation feature 301 dividing the substrate into a PMOS region and an NMOS region.
The isolation member 301 may be made of a material such as silicon dioxide (SiO 2 ) Any insulating material, or "high K" dielectric with a high dielectric constant, for example, above 3.9. In some cases, the spacer 301 may be composed of an oxide substance. Materials suitable for the isolation member 301 may include, for example, silicon dioxide (SiO 2 ) Hafnium oxide (HfO) 2 ) Alumina (Al) 2 O 3 ) Yttria (Y) 2 O 3 ) Tantalum oxide (Ta) 2 O 5 ) Titanium dioxide (TiO) 2 ) Praseodymium oxide (Pr) 2 O 3 ) Zirconium oxide (ZrO) 2 ) Erbium oxide (ErOx), and other materials now known or later developed that have similar characteristics.
The isolation features 301 are illustratively formed by shallow trench isolation processes (STI, shallow Trench Isolation) including, but not limited to, shallow trench etching, oxide filling, and oxide planarization.
The shallow trench etching includes, but is not limited to, isolation oxide layer, nitride deposition, shallow trench isolation by using a mask plate and shallow trench etching of STI. Wherein the STI oxide fill includes, but is not limited to, a trench liner silicon oxide, a trench CVD (chemical vapor deposition) oxide fill, or a PVD (physical vapor deposition) oxide fill. Wherein planarization of the wafer surface can be achieved by a variety of methods. Planarization of the wafer may be achieved by filling the gap with SOG (spin-on-glass), which may consist of 80% solvent and 20% silicon dioxide, baking the SOG after deposition, evaporating the solvent, leaving the silicon dioxide in the gap, or performing an etch back of the entire surface to reduce the thickness of the entire wafer. Planarization processes, including but not limited to polishing of trench oxide (chemical mechanical polishing may be employed) and nitride removal, may also be effectively performed by CMP processes (also referred to as chemical mechanical polishing processes).
The PMOS region of the substrate 300 is formed with an N-well, the NMOS region of the substrate 300 is formed with a P-well, and the P-well is formed in a deep N-well, which is not shown in the drawing for simplicity.
A dummy gate 302 is formed on the substrate 300, and the material of the dummy gate 302 is amorphous silicon or polysilicon, for example.
As an example, before forming the dummy gate 302, a gate dielectric layer 303 and an interface layer 305 are further formed on the substrate 300, which are stacked from bottom to top.
Illustratively, the material of gate dielectric layer 303 is a high dielectric constant (high-k) material, such as hafnium oxide (HfO) 2 ) Alumina (Al) 2 O 3 ) Hafnium silicate (HfSiOx), zirconium dioxide (ZrO 2 ) Hafnium zirconate (HfZrOx), and the like. The gate dielectric layer 303 may also be a stacked structure formed by stacking silicon oxide (or silicon oxynitride) and a high dielectric constant (high K) material from bottom to top. The material of the interface layer 305 is titanium nitride (TiN).
As an example, after the dummy gate 302 is formed, an etch stop layer 310 and an interlayer dielectric layer 306 are sequentially formed on the substrate 300.
Illustratively, the material of etch stop layer 310 is silicon nitride, a layerThe material of the inter-dielectric layer 306 is, for example and without limitation: silicon nitride (Si) 3 N 4 ) Silicon oxide (SiO) 2 ) Fluorinated SiO 2 (FSG), hydrogenated silicon oxycarbide (SiCOH), porous SiCOH, borophosphosilicate glass (BPSG), silsesquioxanes, carbon (C) doped oxides (i.e., organosilicates) comprising silicon (Si), carbon (C), oxygen (O) and/or hydrogen (H) atoms, thermosetting polyarylene ethers, or other low dielectric constant (< 3.9) materials.
In step S2, as shown in fig. 3B, a photoresist layer 307 is formed, exposing the PMOS region. As an example, the forming step of the photoresist layer 307 includes: forming a photoresist layer on the substrate 300 through a spin coating process; and removing the photoresist layer on the PMOS region through photoetching and etching processes.
In step S3, as shown in fig. 3C, ion implantation is performed to dope boron in the dummy gate 302 located in the PMOS region. As an example, the ion implantation may be performed in multiple times while doping the dummy gate 302 in the PMOS region with boron and also doping with carbon.
In step S4, as shown in fig. 3D, the photoresist layer 307 is removed. Illustratively, the photoresist layer 307 is removed using an SPM lift-off and clean process, where SPM is a mixture of sulfuric acid and hydrogen peroxide.
In step S5, as shown in fig. 3E, the dummy gate 302 in the NMOS region is removed. As an example, the removal is performed by wet etching, and the etching liquid of the wet etching is ammonia water.
Since boron is doped in the dummy gate 302 located in the PMOS region in step S3 by ion implantation, the etching rate of the dummy gate 302 located in the PMOS region is significantly reduced by the wet etching, and the etching rate is lower as the amount of boron doped is larger, i.e., the selectivity of the wet etching to silicon and boron doped silicon is high, and in the process of removing the dummy gate 302 located in the NMOS region, the sidewall of the dummy gate 302 located in the PMOS region can be controlled to have a very straight morphology, so as to form a very good N/PMOS boundary.
In addition, the selection ratio of the wet etching to the silicon and the boron doped silicon is larger than that of the dry etching to the silicon and the silicon oxide adopted in the prior art, so that the over-etching amount of the wet etching can be remarkably increased, the dummy gate 302 is ensured to be etched to be free from residue, and meanwhile, the interface layer 305 and the gate dielectric layer 303 below the dummy gate 302 are not damaged.
In step S6, as shown in fig. 3F, a first gate stack 308 is formed in the NMOS region. As an example, the first gate stack 308 includes a work function metal layer, a barrier metal layer, and a metal gate stacked from bottom to top, wherein a material of the work function metal layer may include carbon doped titanium aluminum (TiAlC), titanium aluminum (TiAl), or a combination thereof, a material of the barrier metal layer may be TiN, and a material of the metal gate may include tungsten (W), aluminum (Al), or a combination thereof.
In step S7, as shown in fig. 3G, the dummy gate 302 in the PMOS region is removed. As an example, the removal is performed using a dry etching or wet etching process.
In step S8, as shown in fig. 3H, a second gate stack 309 is formed in the PMOS region. As an example, the second gate stack 309 includes a first work function metal layer, a capping layer, a second work function metal layer, a barrier metal layer, and a metal gate stacked from bottom to top, wherein a material of the first work function metal layer may be titanium nitride (TiN), a material of the capping layer may be TiN, a material of the second work function metal layer may include carbon doped titanium aluminum (TiAlC), titanium aluminum (TiAl), or a combination thereof, a material of the barrier metal layer may be TiN, a material of the metal gate may include tungsten (W), aluminum (Al), or a combination thereof, and thicknesses sequentially increase when the materials of the first work function metal layer, the capping layer, and the barrier metal layer are TiN.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In summary, according to the method for removing the dummy gate provided by the application, on one hand, the process window for removing the dummy gate 302 can be obviously increased, the possibility of residue is reduced, the defects are reduced, and the yield is improved; on the other hand, the damage of the interface layer 305 and the gate dielectric layer 303 below the dummy gate 302 can be reduced, the performance and stability of the device can be improved, and the yield can be further improved. Therefore, the application effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. A method of removing a dummy gate, the method comprising:
step S1, providing a substrate with a PMOS region and an NMOS region, wherein a pseudo grid electrode is formed on the substrate;
step S2, forming a photoresist layer to expose the PMOS region;
s3, performing ion implantation, and doping boron in the pseudo gate positioned in the PMOS region;
step S4, removing the photoresist layer;
step S5, removing the pseudo grid electrode positioned in the NMOS region;
step S6, forming a first grid stack body in the NMOS region;
step S7, removing the pseudo grid electrode positioned in the PMOS region;
step S8, forming a second grid stack body in the PMOS region.
2. The method of claim 1, wherein the ion implantation is performed in multiple passes.
3. The method of claim 1 or 2, wherein the ion implantation further dopes carbon in a dummy gate located in the PMOS region.
4. The method of claim 1, wherein in step S5, a wet etching is used to remove the dummy gate in the NMOS region.
5. The method of claim 4, wherein the etching solution of the wet etching is ammonia.
6. The method according to claim 1, wherein in the step S7, the dummy gate in the PMOS region is removed by dry etching or wet etching.
7. The method of claim 1, wherein an interfacial layer and a gate dielectric layer are formed between the dummy gate and the substrate, the interfacial layer and the gate dielectric layer being stacked from bottom to top.
8. The method of claim 7, wherein the material of the dummy gate is amorphous silicon or polysilicon, the gate dielectric layer is a high dielectric constant material layer or a stacked structure formed by stacking a silicon oxide layer and a high dielectric constant material layer from bottom to top, and the interface layer is a titanium nitride layer.
9. The method of claim 1, wherein the first gate stack comprises a work function metal layer, a barrier metal layer, and a metal gate stacked from bottom to top.
10. The method of claim 1, wherein the second gate stack comprises a first work function metal layer, a capping layer, a second work function metal layer, a barrier metal layer, and a metal gate stacked from bottom to top.
CN202311008859.2A 2023-08-10 2023-08-10 Method for removing pseudo grid Pending CN117038581A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311008859.2A CN117038581A (en) 2023-08-10 2023-08-10 Method for removing pseudo grid

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311008859.2A CN117038581A (en) 2023-08-10 2023-08-10 Method for removing pseudo grid

Publications (1)

Publication Number Publication Date
CN117038581A true CN117038581A (en) 2023-11-10

Family

ID=88624027

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311008859.2A Pending CN117038581A (en) 2023-08-10 2023-08-10 Method for removing pseudo grid

Country Status (1)

Country Link
CN (1) CN117038581A (en)

Similar Documents

Publication Publication Date Title
CN108231664B (en) Semiconductor device and method of forming the same
US9431304B2 (en) Method and structure for metal gates
TWI419208B (en) Method of fabricating semiconductor device
US20190088650A1 (en) Cut Metal Gate with Slanted Sidewalls
CN107665858A (en) IC-components and forming method thereof
US11380772B2 (en) Gate structure and patterning method for multiple threshold voltages
US11699621B2 (en) Method for patterning a lanthanum containing layer
US11114347B2 (en) Self-protective layer formed on high-k dielectric layers with different materials
US8530317B1 (en) Corner rounding to improve metal fill in replacement gate process
US10283417B1 (en) Self-protective layer formed on high-k dielectric layers with different materials
US11908685B2 (en) Methods of reducing gate spacer loss during semiconductor manufacturing
KR20180069679A (en) Semiconductor epitaxy bordering isolation structure
TW201839823A (en) Method of manufacturing semiconductor device
US7119023B2 (en) Process integration of SOI FETs with active layer spacer
US9508590B2 (en) Methods and apparatus of metal gate transistors
CN117038581A (en) Method for removing pseudo grid
US11916128B2 (en) Metal oxide interlayer structure for nFET and pFET
CN116469769A (en) Method for improving PMOS threshold voltage mismatch
CN116799004B (en) Semiconductor integrated device and manufacturing method thereof
US11855186B2 (en) Semiconductor device and manufacturing method thereof
CN117238759A (en) Method for improving metal aluminum gate loss
US20230119827A1 (en) Semiconductor Device Structure And Method For Forming The Same
CN117198893A (en) Method for improving oversized middle section metal contact through hole
CN116960063A (en) Method for improving uniformity of high-voltage MOS offset isolation layer
CN106558548B (en) A kind of semiconductor devices and its manufacturing method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination