CN117038444A - Dry etching method and semiconductor process equipment - Google Patents
Dry etching method and semiconductor process equipment Download PDFInfo
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- CN117038444A CN117038444A CN202311024464.1A CN202311024464A CN117038444A CN 117038444 A CN117038444 A CN 117038444A CN 202311024464 A CN202311024464 A CN 202311024464A CN 117038444 A CN117038444 A CN 117038444A
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- 238000000034 method Methods 0.000 title claims abstract description 127
- 230000008569 process Effects 0.000 title claims abstract description 86
- 238000001312 dry etching Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 239000007789 gas Substances 0.000 claims abstract description 93
- 238000005530 etching Methods 0.000 claims abstract description 66
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 55
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 37
- 239000011737 fluorine Substances 0.000 claims abstract description 37
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims abstract description 33
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 28
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims abstract description 22
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 19
- 239000001301 oxygen Substances 0.000 claims abstract description 19
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 19
- 238000001020 plasma etching Methods 0.000 claims abstract description 17
- 229910052734 helium Inorganic materials 0.000 claims abstract description 14
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 14
- 229910052786 argon Inorganic materials 0.000 claims abstract description 11
- 239000001307 helium Substances 0.000 claims abstract description 11
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims abstract description 11
- 230000004888 barrier function Effects 0.000 claims description 8
- 238000004590 computer program Methods 0.000 claims description 6
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 77
- 239000000463 material Substances 0.000 description 6
- -1 fluorine ions Chemical class 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910008310 Si—Ge Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000002064 nanoplatelet Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 229910018557 Si O Inorganic materials 0.000 description 2
- 229910008045 Si-Si Inorganic materials 0.000 description 2
- 229910006411 Si—Si Inorganic materials 0.000 description 2
- 230000002238 attenuated effect Effects 0.000 description 2
- 238000001000 micrograph Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000010327 methods by industry Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
Abstract
The embodiment of the invention discloses a dry etching method and semiconductor process equipment, wherein the dry etching method is used for selectively etching a SiGe layer from a laminated structure comprising alternately stacked Si layers and SiGe layers, and the method comprises the following steps: and performing plasma etching on the laminated structure by using a process gas to selectively remove the SiGe layer from the laminated structure, wherein the process gas comprises a fluorine-containing gas and an auxiliary etching gas, the auxiliary etching gas comprises an oxygen element, and the auxiliary etching gas further comprises at least one of a nitrogen element, a helium element and an argon element.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a dry etching method and semiconductor process equipment.
Background
With the continued advancement of moore's law, gate All Around (GAA) transistors are considered as effective substitutes for fin field effect transistors (finfets) after the semiconductor process has evolved to the 3nm node. In GAA fabrication process engineering, high selectivity is critical to etching horizontally stacked nanoplatelets of the sacrificial layer. The industry typically produces vertically stacked Si or SiGe nanowires by selectively removing SiGe or Si in Si and SiGe multilayer stacks. Typically, nfets are formed by selectively removing SiGe in a Si and SiGe multilayer stack to produce vertically stacked Si nanoplatelets, and selectively removing Si material to produce vertically stacked SiGe nanoplatelets to form pfets. In order to reduce the subsequent negative impact on the device, it is desirable that the SiGe and Si materials have a very high selectivity during etching relative to the other to avoid or reduce damage to the channel.
At present, wet etching technology is generally adopted in the industry to realize high selectivity etching of SiGe and Si materials, however, wet etching is easy to distort etching patterns, and accurate etching effect is difficult to obtain. The dry etching process faces the dilemma of low etching selectivity.
Disclosure of Invention
The embodiment of the invention discloses a dry etching method and semiconductor process equipment, which are used for solving the problems of low etching selectivity and low productivity when a SiGe layer is selectively etched from a laminated structure of a Si layer and a SiGe layer in the related technology.
To solve the above technical problem, according to a first aspect, an embodiment of the present invention discloses a dry etching method for selectively etching a SiGe layer from a stacked structure including Si layers and SiGe layers alternately stacked, the method including: and performing plasma etching on the laminated structure by using a process gas to selectively remove the SiGe layer from the laminated structure, wherein the process gas comprises a fluorine-containing gas and an auxiliary etching gas, and the auxiliary etching gas comprises at least one of an oxygen element, a nitrogen element, a helium element and an argon element.
As some alternative embodiments, the auxiliary etching gas includes an oxygen element, and the auxiliary etching gas further includes at least one of a nitrogen element, a helium element, and an argon element.
As some alternative embodiments, the fluorine-containing gas comprises a fluorocarbon-based gas.
As some alternative embodiments, the fluorocarbon groupThe gas comprising CF 4 、C 4 F 8 、C 3 F 6 、CHF 3 、CH 2 F 2 、CH 3 At least one of F.
As some alternative embodiments, the auxiliary etching gas includes N 2 、O 2 、NO、NO 2 At least one of He, ar.
As some alternative embodiments, the ratio of fluorine element to oxygen element content in the process gas ranges from 1 to 100; or the content ratio of fluorine element to nitrogen element is in the range of 1 to 100; or the content ratio of fluorine element to helium element is in the range of 1 to 100; or the content ratio of fluorine element to argon element is in the range of 1 to 100.
As some alternative embodiments, the process chamber pressure is 100 to 5000mTorr during the step of plasma etching the laminate structure with the process gas.
As some alternative embodiments, in the step of plasma etching the stacked structure using a process gas, the flow rate of the process gas ranges from 10 to 4000sccm.
As some alternative embodiments, in the step of performing plasma etching on the laminated structure using a process gas, the plasma etching is isotropic etching.
As some alternative embodiments, before the step of plasma etching the stacked structure with a process gas, the method further comprises: and removing the natural oxide layer on the surface of the Si layer or the SiGe layer.
As some alternative embodiments, the natural oxide layer of the stacked structure is subjected to anisotropic plasma etching by using the fluorine-containing gas.
According to a second aspect, an embodiment of the present invention provides a semiconductor processing apparatus, including: the wafer carrying device is arranged in the second area, and is used for carrying out the process on the wafer carrying device; control means comprising at least one memory and at least one processor, said memory having stored therein a computer program, said processor executing said computer program to implement the dry etching method according to any of the above-mentioned first aspects.
As some optional embodiments, the semiconductor process apparatus further comprises: a gas inlet assembly for delivering a process gas to the first region of the process chamber; and the first radio frequency component is used for exciting the process gas in the first area into plasma.
As some alternative embodiments, the perforated barrier comprises multiple layers, and at least some of the through holes of the perforated barrier of adjacent layers are not aligned with each other.
As some alternative embodiments, the perforated separator is grounded or a predetermined voltage is applied.
In the dry etching method and the semiconductor process equipment provided by the embodiment of the invention, the SiGe layer is selectively etched from the stacked structure of the Si layer and the SiGe layer which are alternately stacked by utilizing the process gas, and the process gas comprises an auxiliary etching gas besides fluorine-containing gas serving as a main etching gas, wherein the auxiliary etching gas comprises at least one of oxygen element, nitrogen element, helium element and argon element, and the etching selectivity of SiGe relative to Si is obviously improved by the auxiliary etching gas, so that the loss of the Si layer is ensured to be smaller while the SiGe layer is removed, and the performance of the subsequently manufactured GAA-FET is improved.
Drawings
Fig. 1A is a schematic diagram showing a stacked structure to which a dry etching method according to an embodiment of the present invention is applied;
FIG. 1B shows a schematic diagram of selectively etching a SiGe layer from the stacked structure shown in FIG. 1A;
FIG. 2 shows an electron microscope image obtained after etching the laminated structure with a process gas added with oxygen and nitrogen elements;
FIG. 3 shows a schematic diagram of a semiconductor processing apparatus according to an embodiment of the invention;
fig. 4 shows a schematic top view of a perforated baffle according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It is to be understood by one skilled in the art that the present embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. Furthermore, each of the examples given in connection with the various embodiments is intended to be illustrative, and not limiting. Moreover, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details of the embodiments of the present invention are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present methods and structures. It should also be noted that like and corresponding elements are denoted by like reference numerals.
In the following description, numerous specific details are set forth, such as specific structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of various embodiments of the invention. However, it will be understood by those skilled in the art that the various embodiments of the invention may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present invention.
For purposes of the following description, the terms "upper," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof shall relate to the structure and method as disclosed in the drawing figures of the specification. It will be understood that when an element as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly on another element, there are no intervening elements between the two. It will also be understood that when an element is referred to as being "under" another element, it can be directly under the other element or intervening elements may be present. On the contrary. When an element is referred to as being directly under another element, there are no intervening elements present therebetween.
The technical scheme disclosed by the embodiment of the invention is described in detail below with reference to the accompanying drawings.
Fig. 1A shows a stacked structure applied by a dry etching method according to an embodiment of the present invention, where the stacked structure may include alternately stacked Si layers 101 and SiGe layers 102, a hard mask layer 103 may be disposed above the alternately stacked Si layers 101 and SiGe layers 102, the hard mask layer 103 may be a silicon oxide layer or a silicon nitride layer or a stack of a silicon oxide layer and a silicon nitride layer, and the Si layers 101 and SiGe layers 102 are etched with the hard mask layer 103 as an etching mask, so as to form a fin-shaped stacked structure as shown in fig. 1A, and in a subsequent semiconductor process, the Si layers 101 are selectively removed from the stacked structure to leave the Si layers 101 as channels of GAA-FETs to be formed, or the Si layers 101 are selectively removed from the stacked structure to leave the SiGe layers 102 as channels of GAA-FETs to be formed, so as to fabricate pfets. In the stacked structure illustrated in fig. 1A, the Si layer 101 and the SiGe layer 102 may be formed on the surface of a substrate by epitaxial growth, and in the example of fig. 1A, the substrate is Si, and it should be understood by those skilled in the art that the material of the substrate is not limited thereto, but may be other simple substance or compound semiconductor materials, such as Ge, siGe, gaAs, inSb, gaP, gaSb, inAlAs, inGaAs, gaSbP, gaAsSb or InP, etc.
To achieve nFET fabrication, siGe layer 102 needs to be selectively etched from the stack structure, as shown in fig. 1B. The manner in which the SiGe layer 102 is selectively removed by wet etching is generally limited to wet etching processes and cannot be used in the process of the advanced technology node. The industry is continually exploring the use of dry etch processes to selectively remove SiGe layers, but there is no report that high etch selectivity can be achieved.
Hereinafter, a dry etching method of an embodiment of the present invention will be described in detail to selectively etch a SiGe layer from a stacked structure including Si layers and SiGe layers alternately stacked.
In this embodiment, the stacked structure is plasma etched using a process gas comprising a fluorine-containing gas and an auxiliary etching gas. The fluorine-containing gas is used as a main etching gas, and after being excited, fluorine ions and fluorine-containing free radicals are generated to react with the film layer to be etched to realize etching, and the auxiliary etching gas can comprise at least one of oxygen element, nitrogen element, helium element and argon element and is used for improving the etching selectivity of SiGe relative to Si so as to realize selective etching of the SiGe layer. After the SiGe layer in the laminated structure is etched and removed, the residual Si layer is used as a channel of the GAA-FET, and the Si layer with larger damage can seriously influence the performance of the GAA-FET.
In the step of plasma etching the laminated structure by using the process gas, the bond energy between Si-Si atoms is 2.31eV and is slightly larger than the bond energy of doped Si-Ge (2.12 eV), and during the reaction, fluorine ions and fluorine-containing free radicals are easier to break Si-Ge bonds to form a volatilizable product SiF 4 And GeF 4 . Of course, siGe has a relatively low etch selectivity with respect to Si in the presence of fluorine-containing gas alone, since the difference between Si-Si bond energy and Si-Ge bond energy is not large. Under the condition that oxygen element is added into the process gas, the Si layer reacts with the oxygen element to generate Si-O bond with higher bond energy (the Si-O bond energy is 9.0 eV), and a protective layer is formed to inhibit fluorine ions and fluorine-containing free radicals from reacting with Si; the doped SiGe layer has more active sites to participate in the reaction of fluorine ions and fluorine-containing free radicals, so that the etching selectivity of SiGe relative to Si can be improved by adopting the process gas added with the oxygen element.
The inventors of the present invention found that when the content ratio of fluorine element to oxygen element in the process gas is changed, the morphology of the laminated structure after etching is affected. In some optional implementations of the embodiments of the present invention, when the content ratio of fluorine element to oxygen element is in a range of 1 to 100, the etched morphology of the stacked structure can be further improved.
In the case where the auxiliary etching gas includes only oxygen element, it can be seen from the electron microscope image obtained after etching the stacked structure that the thickness of the Si layer located outside the stacked structure is slightly smaller than that of the Si layer located inside the stacked structure, that is, the Si layer located outside is damaged while the SiGe layer is removed. In order to further enhance the etching selectivity of SiGe with respect to Si, the auxiliary etching gas may further include at least one of nitrogen element, helium element and argon element in addition to oxygen element. Taking the auxiliary etching gas including oxygen element and nitrogen element as an example, as shown in fig. 2, compared with the etching morphology obtained by the auxiliary etching gas including only oxygen element, the etching selectivity of SiGe relative to Si can be further improved by adding oxygen element and nitrogen element simultaneously in the process gas, and the etching selectivity of SiGe relative to Si can reach about 100. The inventors of the present invention have found that the addition of helium or argon to the auxiliary etching gas can also have a similar effect, and can further enhance the etching selectivity of SiGe relative to Si. Meanwhile, as can be seen from fig. 2, the sidewall of the etched concave SiGe layer is smoother, so that the dry etching method according to the embodiment of the present invention is also very suitable for removing the SiGe layer with a predetermined thickness. In a subsequent GAA-FET fabrication process, the space after the SiGe layer of predetermined thickness is removed may be filled with an insulating layer of silicon oxide or silicon nitride or the like, which may be used to avoid the gate structure of the subsequently formed GAA-FET from conducting with the source or drain region.
The inventors of the present invention have also found that when the content ratio of fluorine element to nitrogen element in the process gas is changed, an influence is exerted on the etching selectivity and etching rate. In some optional implementations of the embodiments of the present invention, when the content ratio of fluorine element to nitrogen element ranges from 1 to 100, the etching selectivity and etching rate can be improved. Correspondingly, when the content ratio of the fluorine element to the helium element is in the range of 1 to 100, or when the content ratio of the fluorine element to the argon element is in the range of 1 to 100, the etching selection ratio and the etching rate can be improved.
In some alternative implementations of the present embodiments, the fluorine-containing gas may include a fluorocarbon-based gas, and more particularly may include CF 4 、C 4 F 8 、C 3 F 6 、CHF 3 、CH 2 F 2 、CH 3 F, the auxiliary etching gas comprises N 2 、O 2 、NO、NO 2 At least one of He, ar. In one particular example, the process gas may include CF 4 、N 2 And O 2 In order to further improve the shape of the laminated structure after etching, the CF 4 With O 2 In a flow ratio in the range of 0.5 to 50, CF 4 And N 2 The flow ratio of (2) is in the range of 0.5 to 50. More preferably, CF 4 With O 2 In a flow ratio in the range of 2 to 20, CF 4 And N 2 The flow ratio of (2) to 20.
The inventor of the invention discovers that the pressure of the process chamber can influence the etching rate and the etched morphology of the laminated structure, the etching rate can be improved by increasing the pressure of the process chamber, but the etched morphology of the laminated structure is deteriorated by excessively high pressure of the process chamber. In some alternative implementations of the present embodiments, the process chamber pressure ranges from 100 to 5000mTorr and the process gas flow ranges from 10 to 4000sccm.
The inventors of the present invention have found that the temperature of the wafer carrier surface used to carry the wafer can have an impact on the etch rate and the topography of the stack after etching, and that too high a temperature can result in a reduced etch selectivity of SiGe relative to Si. The wafer carrying device may include, for example, an electrostatic chuck, a vacuum chuck, or a mechanical chuck. In some alternative implementations of the embodiments of the present invention, the temperature of the surface of the wafer carrier for carrying the wafer needs to be less than a predetermined value.
In some alternative implementations of embodiments of the invention, the plasma may be excited, for example, using an upper electrode rf coil, with a power range of 100 to 3000W and a lower electrode bias power of 0 to 100W, such that the plasma etch is an isotropic etch or a substantially isotropic etch.
Further, before the selective plasma etching is performed on the stacked structure, the dry etching method according to the embodiment of the present invention may further include: and removing the natural oxide layer on the surface of the Si layer or the SiGe layer.
In this embodiment, the natural oxide layer on the surface of the stacked structure may be removed by using a fluorine-containing gas, which may be the same as the fluorine-containing gas used for selectively etching the SiGe layer described above, so that the steps of removing the natural oxide layer and selectively etching the SiGe layer in the same process chamber may be achieved, without transferring the wafer back and forth between different process chambers, and the productivity may be improved.
In some alternative implementations of the present embodiments, the fluorine-containing gas may include a fluorocarbon-based gas, more particularly a CF 4 、C 4 F 8 、C 3 F 6 、CHF 3 、CH 2 F 2 、CH 3 At least one of F. Unlike the step of selectively etching the SiGe layer, in the step of removing the natural oxide layer, a lower electrode bias power is applied so that the plasma etching is anisotropic etching.
In some alternative implementations of embodiments of the invention, in the step of removing the native oxide layer, the process chamber pressure is 0 to 2000mTorr, the upper electrode rf power applied is 10 to 2000W, the lower electrode rf bias power is 20 to 2000W, the upper and lower electrode rf frequencies may be, for example, 2MHz, 400KHz, 13.56MHz, 27MHz, etc., the total flow of process gases is 10 to 1000sccm, and the temperature of the wafer carrier, such as an electrostatic chuck, is 0 to 100 ℃.
Correspondingly, the embodiment of the invention also provides a semiconductor process device, and the dry etching method of the embodiment of the invention can be realized by adopting the semiconductor process device shown in fig. 3. As shown in fig. 3, the semiconductor processing apparatus may include a process chamber 210, the process chamber 210 may include a wafer carrier 211 and a perforated partition 212, and the wafer carrier 211 may include, for example, an electrostatic chuck, a vacuum chuck, a mechanical chuck, or the like, for carrying a wafer to be processed. The semiconductor processing equipment may employ an upper electrode rf coil to energize the plasma or a remote plasma. In some alternative implementations of embodiments of the invention, the semiconductor processing apparatus may further include an gas inlet assembly 220 for delivering a process gas to the process chamber 210 and a first rf assembly 230 for igniting the process gas into a plasma. Optionally, the semiconductor processing apparatus may further include a second rf power source coupled to the wafer carrier 211 for providing an rf bias.
The perforated separator 212 is generally plate-shaped, and two layers of perforated separator are shown in the example of fig. 3, however, the present invention is not limited thereto, and one or more layers of perforated separator may be provided, and as shown in fig. 4, a plurality of through holes are provided in the perforated separator 212, where the number, shape and size of the through holes are not limited, and preferably the through holes are uniformly distributed in the perforated separator 212. The perforated baffle 212 is disposed parallel to the load-bearing surface of the wafer load-bearing device 211 to divide the chamber body of the process chamber into a first region 213 at the upper side of the process chamber and a second region 214 at the lower side of the process chamber, the wafer load-bearing device 211 being located within the second region 214. The gas inlet assembly 220 is configured to deliver a process gas to a first region 213 of the process chamber 210, the first rf assembly 230 is configured to energize the process gas of the first region 213 into a plasma, and the first rf assembly 230 may include, for example, an rf coil and a first rf power source located at the top of the process chamber 210.
The process gas delivered through the gas inlet assembly 220 is excited by the first rf assembly 230 to generate a plasma in the first region 213, where the plasma includes energetic electrons, ions, and radicals. The perforated separator 212 is grounded or a predetermined voltage is applied such that electrons and charged ions are filtered out while passing through the perforated separator 212, and free radicals can pass through the perforated separator 212 to the second region 214 due to no charge, so that the reactive species in the second region 214 are mostly free radicals. Thus, in the dry etching method of the embodiment of the present invention, selective etching of the SiGe layer from the stacked structure of the Si layer and the SiGe layer alternately stacked is mainly achieved using radicals.
In some implementations of the present embodiments, the perforated barrier 212 is multi-layered and at least some of the through holes of the perforated barrier 212 of adjacent layers are not aligned with each other, preferably all of the through holes of the perforated barrier 212 of adjacent layers are not aligned with each other, as shown in fig. 3, such that the process gas cannot pass through the multi-layered perforated barrier 212 in a straight line, lengthening the travel path of the process gas such that more electrons and charged ions are filtered or attenuated to further increase the proportion of radicals in the second region 214. Further, the through holes may be specifically designed, e.g., curved, to extend the travel path of the process gas so that more electrons and charged ions are filtered or attenuated to further increase the proportion of radicals in the second region 214, thereby enabling better selective etching.
The semiconductor process apparatus according to the embodiment of the present invention may further include a control device (not shown), which may be, for example, a lower computer or an upper computer of the semiconductor process apparatus, and the control device may include at least one memory and at least one processor, where the memory stores a computer program, and the processor executes the computer program to implement the dry etching method described above.
In the control device, the processor may be a central processing unit (Central Processing Unit, CPU), other general purpose processor, digital signal processor (Digital Signal Processor, DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), field programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or a combination thereof.
The memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some alternative embodiments, the memory may also include memory located remotely from the processor, the remote memory being connectable to the processor through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof. The memory, as a non-transitory computer readable storage medium, may be used to store a non-transitory software program, a non-transitory computer executable program, and a module, such as program instructions corresponding to a dry etching method in an embodiment of the present invention, for example, control to open a corresponding valve to enable a corresponding kind and flow of process gas to enter the process chamber 210, control the first rf assembly 230 to excite a plasma with a predetermined power, control the heater of the wafer carrier 211 to heat to a predetermined temperature, control the pumping device of the process chamber to enable the process chamber to reach a predetermined pressure, and so on. The processor executes the non-transitory program instructions stored in the memory to perform various functional applications of the processor and data processing, i.e., to implement the dry etching method in the method embodiment described above.
The details of the above semiconductor processing apparatus may be correspondingly understood by referring to the corresponding related descriptions and effects in the above-described dry etching method embodiment, which are not repeated herein.
The foregoing embodiments of the present invention mainly describe differences between the embodiments, and as long as there is no contradiction between different optimization features of the embodiments, the embodiments may be combined to form a better embodiment, and in view of brevity of line text, no further description is provided herein.
The foregoing is merely exemplary of the present invention and is not intended to limit the present invention. Various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the invention are to be included in the scope of the claims of the present invention.
Claims (14)
1. A dry etching method for selectively etching a SiGe layer from a stacked structure comprising alternately stacked Si layers and SiGe layers, the method comprising:
plasma etching the stacked structure with a process gas to selectively remove the SiGe layer from the stacked structure, wherein
The process gas includes a fluorine-containing gas and an auxiliary etching gas including an oxygen element, and further including at least one of a nitrogen element, a helium element, and an argon element.
2. The dry etching method according to claim 1, wherein the fluorine-containing gas comprises a fluorocarbon-based gas.
3. The dry etching method according to claim 2, wherein the fluorocarbon-based gas includes CF 4 、C 4 F 8 、C 3 F 6 、CHF 3 、CH 2 F 2 、CH 3 At least one of F.
4. The dry etching method according to claim 1, wherein the auxiliary etching gas includes N 2 、O 2 、NO、NO 2 At least one of He, ar.
5. The dry etching method according to claim 2, wherein a content ratio of fluorine element to oxygen element in the process gas is in a range of 1 to 100; or alternatively
The content ratio of fluorine element to nitrogen element is 1-100; or alternatively
The content ratio of fluorine element to helium element is in the range of 1 to 100; or alternatively
The content ratio of fluorine element to argon element is in the range of 1 to 100.
6. The dry etching method according to claim 1, wherein in the step of plasma etching the laminated structure with a process gas, a process chamber pressure is 100 to 5000mTorr.
7. The dry etching method according to claim 1, wherein in the step of plasma etching the laminated structure with a process gas, a flow rate of the process gas is in a range of 10 to 4000sccm.
8. The dry etching method according to claim 1, wherein in the step of plasma etching the laminated structure with a process gas, the plasma etching is isotropic etching.
9. The dry etching method according to any one of claims 1 to 8, characterized in that before the step of plasma etching the laminated structure with a process gas, the method further comprises:
and removing the natural oxide layer on the surface of the Si layer or the SiGe layer.
10. The dry etching method according to claim 9, wherein the natural oxide layer of the stacked structure is anisotropically plasma etched using the fluorine-containing gas.
11. A semiconductor processing apparatus, comprising:
the wafer carrying device is arranged in the second area, and is used for carrying out the process on the wafer carrying device;
control device comprising at least one memory and at least one processor, said memory having stored therein a computer program, said processor executing said computer program to implement the dry etching method according to any of claims 1 to 10.
12. The semiconductor processing apparatus of claim 11, further comprising:
a gas inlet assembly for delivering a process gas to the first region of the process chamber;
and the first radio frequency component is used for exciting the process gas in the first area into plasma.
13. The semiconductor processing apparatus of claim 11, wherein the perforated barrier comprises multiple layers and at least some of the perforations of the perforated barrier of adjacent layers are not aligned with each other.
14. The semiconductor processing apparatus of claim 11, wherein the perforated separator is grounded or a predetermined voltage is applied.
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