CN117033069A - Data transmission circuit and method - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/22—Parsing or analysis of headers
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Abstract
The application provides a data transmission circuit and a method, wherein the data transmission circuit comprises: a selection module, an internal state machine, an excitation generation module, and a state check module. The data transmission circuit can check the current data transmission state of the internal state machine through the state checking module, generates a state switching control signal consistent with an external state signal through the excitation generating module under the condition that the internal state machine is in an abnormal state, and sends the generated state switching control signal to the internal state machine through the selecting module, so that the internal state machine can adjust the data transmission mode of the circuit according to the state switching control signal, and convert the internal state machine into a normal data transmission mode, thereby greatly reducing the interference degree of the ESD on data communication and ensuring the effectiveness and timeliness of the data communication after being interfered by the ESD.
Description
Technical Field
The present application relates to the field of data transmission technologies, and in particular, to a data transmission circuit and method.
Background
Electrostatic discharge (ESD) is an objective phenomenon, and Static electricity is generated by contact, friction, accumulation of components, and the like, and is characterized by long accumulation time, high voltage and short action time, so that the instant voltage of electrostatic discharge is very high.
Under the condition of ESD interference, data transmission between the slave and the host can be in an abnormal state, and the effectiveness and timeliness of data communication can be greatly influenced.
Disclosure of Invention
Accordingly, an objective of the embodiments of the present application is to provide a data transmission circuit and a method for solving the technical problem that the effectiveness and timeliness of ESD interference on data communication are greatly affected.
In a first aspect, an embodiment of the present application provides a data transmission circuit, including: a selection module, an internal state machine, an excitation generation module, and a state check module;
the state checking module is respectively connected with the internal state machine and the external input interface in a communication way; the state checking module is configured to determine a state checking result of the internal state machine according to an external state signal input by the external input interface and the current data transmission state of the internal state machine; wherein the status check result includes a normal status and an abnormal status;
the excitation generation module is in communication connection with the state checking module; the excitation generation module is configured to generate a state switching control signal consistent with the external state signal in the case that the state check result is the abnormal state;
the selection module is respectively in communication connection with the excitation generation module, the external input interface, the state check module and the internal state machine; the selection module is configured to send a corresponding state signal to the internal state machine according to the state check result; wherein the status signal comprises the external status signal and the status switch control signal;
the internal state machine is configured to switch a data transmission mode of the circuit according to the state signal.
In the implementation process, the data transmission circuit can generate the state switching control signal consistent with the external state signal through the excitation generation module under the condition that the internal state machine is in an abnormal state, and send the generated state switching control signal to the internal state machine through the selection module, so that the internal state machine can adjust the data transmission mode of the circuit according to the state switching control signal, and switch the internal state machine to a normal data transmission mode, thereby greatly reducing the interference degree of the ESD on data communication, ensuring the effectiveness and timeliness of the data communication after the ESD interference, and solving the technical problem that the effectiveness and timeliness of the ESD interference on the data communication can be greatly influenced.
Optionally, in an embodiment of the present application, the data transmission circuit further includes: a decoding and checking module; the decoding and checking module is in communication connection with the internal state machine and the state checking module; the decoding and checking module is configured to decode the initial data packet transmitted by the internal state machine to obtain decoded data, and check the decoded data to obtain a checking result; wherein, the check result comprises normal decoding data and abnormal decoding data; and sending an abnormality check start signal to the state check module when the check result is that the decoded data is abnormal.
In the implementation process, decoding is carried out on the initial data packet transmitted by the internal state machine through the decoding and checking module to obtain decoded data, and when the checking result of the decoded data is that the decoded data is normal, the transmitted data is normal, and at the moment, the current data transmission state of the internal state machine is not required to be checked; and when the verification result of the decoded data is that the decoded data is abnormal, sending an abnormal detection starting signal to a state detection module to detect whether the data transmission error is caused by the abnormal state of the internal state machine. Therefore, the working time of the state checking module can be shortened, and the working loss and the heating value of the circuit are further reduced.
Optionally, in an embodiment of the present application, the state checking module is specifically configured to determine the state checking result according to the external state signal and a current data transmission state of the internal state machine when the abnormality checking start signal is received.
In the implementation process, the state checking module only needs to check whether the data transmission error caused by the abnormal state of the internal state machine exists or not under the condition that the abnormal checking starting signal is received. Therefore, the working time of the state checking module can be shortened, and the working loss and the heating value of the circuit are further reduced.
Optionally, in an embodiment of the present application, the external input interface is an MIPI interface; the decoding data comprises at least one of a packet head format of the initial data packet, a packet tail format of the initial data packet, an ECC check code and a CRC check code; the decoded data anomalies include at least one of packet header format anomalies, packet trailer format anomalies, ECC check code anomalies, and CRC check code anomalies.
In the above implementation, in the MIPI protocol, the transmitted data would transmit a fixed header, trailer, ECC check code, and CRC check code in compliance with the MIPI protocol. By verifying the packet header format, the packet tail format, the ECC check code and the CRC check code after the initial data packet is decoded, the decoded data is described as being abnormal under the condition that the packet header format is abnormal, the packet tail format is abnormal, the ECC check code is abnormal or the CRC check code is abnormal.
Optionally, in an embodiment of the present application, the selecting module is specifically configured to send the external status signal to the internal state machine when the status check result is the normal status; and sending the state switching control signal to the internal state machine when the state check result is the abnormal state.
In the implementation process, the state switching control signal is sent to the internal state machine under the condition that the state checking result is in an abnormal state, so that the internal state machine can switch the internal state machine to a normal data transmission mode according to the data transmission mode of the state switching control signal adjusting circuit, the interference degree of the ESD on data communication is greatly reduced, the effectiveness and timeliness of the data communication after the ESD interference are ensured, and the technical problem that the effectiveness and timeliness of the ESD interference on the data communication are greatly influenced is solved.
In a second aspect, an embodiment of the present application further provides a data transmission method, applied to a data transmission circuit including a selection module, an internal state machine, an excitation generation module, and a state check module, where the data transmission method includes:
determining a state check result of the internal state machine based on the state check module according to an external state signal input by an external input interface and the current data transmission state of the internal state machine; wherein the status check result includes a normal status and an abnormal status;
generating a state switching control signal consistent with the external state signal based on the excitation generation module in the case that the state check result is the abnormal state;
transmitting a corresponding state signal to the internal state machine based on the selection module according to the state check result; wherein the status signal comprises the external status signal and the status switch control signal;
and switching a data transmission mode of the circuit according to the state signal based on the internal state machine.
In the implementation process, the data transmission method can generate the state switching control signal consistent with the external state signal through the excitation generation module under the condition that the internal state machine is in an abnormal state, and send the generated state switching control signal to the internal state machine through the selection module, so that the internal state machine can adjust the data transmission mode of the circuit according to the state switching control signal, and switch the internal state machine to a normal data transmission mode, thereby greatly reducing the interference degree of the ESD on data communication, ensuring the effectiveness and timeliness of the data communication after the ESD interference, and solving the technical problem that the effectiveness and timeliness of the data communication are greatly influenced by the ESD interference.
By adopting the data transmission circuit and the method provided by the application, under the condition that the internal state machine is in an abnormal state, the state switching control signal consistent with the external state signal is generated by the excitation generation module, and the generated state switching control signal is sent to the internal state machine by the selection module, so that the internal state machine can adjust the data transmission mode of the circuit according to the state switching control signal, and the internal state machine is converted into a normal data transmission mode, thereby greatly reducing the interference degree of ESD on data communication, ensuring the effectiveness and timeliness of the data communication after the ESD interference, and solving the technical problem that the effectiveness and timeliness of the data communication are greatly influenced by the ESD interference.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a data transmission circuit according to an embodiment of the present application;
fig. 2 is a schematic diagram of a data transmission state according to an embodiment of the present application;
fig. 3 is a schematic diagram of another data transmission circuit according to an embodiment of the present application;
fig. 4 is a flow chart of a data transmission method according to an embodiment of the present application.
Detailed Description
Embodiments of the technical scheme of the present application will be described in detail below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical aspects of the present application, and thus are merely examples, and are not intended to limit the scope of the present application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
In the description of embodiments of the present application, the technical terms "first," "second," and the like are used merely to distinguish between different objects and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated, a particular order or a primary or secondary relationship. In the description of the embodiments of the present application, the meaning of "plurality" is two or more unless otherwise specifically defined.
Please refer to fig. 1, which illustrates a schematic structure of a data transmission circuit 01 according to an embodiment of the present application. The data transmission circuit 01 includes: a selection module 10, an internal state machine 20, an excitation generation module 30, and a state check module 40;
the state checking module 40 is respectively connected with the internal state machine 20 and the external input interface in a communication way; the state checking module 40 is configured to determine a state checking result of the internal state machine 20 according to the external state signal input by the external input interface and the current data transmission state of the internal state machine 20; wherein the status check result includes a normal status and an abnormal status;
the excitation generating module 30 is in communication with the status checking module 40; the excitation generation module 30 is configured to generate a state switching control signal in accordance with the external state signal in the case where the state check result is the abnormal state;
the selection module 10 is respectively in communication with the stimulus generation module 30, the external input interface, the status checking module 40 and the internal state machine 20; the selection module 10 is configured to send a corresponding status signal to the internal state machine 20 according to the status check result; wherein the status signal comprises the external status signal and the status switch control signal;
the internal state machine 20 is configured to switch the data transmission mode of the circuit in dependence of the state signal.
Wherein the selection module 10 may be implemented by a selector, for example, an alternative selector; based on the received status check result of the internal state machine 20, a corresponding status signal is selected and the selected status signal is transmitted to the internal state machine 20. Specifically, the selection module 10 may send an external state signal to the internal state machine 20 in case the state check result is a normal state; and transmitting a state switching control signal to the internal state machine 20 when the state check result is an abnormal state. Alternatively, the selection module 10 may send an external state signal to the internal state machine 20 in the case where an abnormal state does not occur in the internal state machine 20; and, in the case that an abnormal state occurs in the internal state machine 20, transmitting a state switching control signal to the internal state machine 20. The internal state machine 20 refers to a state machine that is internal to the data transfer circuit 01 and can switch the data transfer mode of the data transfer circuit 01.
Specifically, if the data transmission circuit 01 is a MIPI protocol-based data transmission circuit, the internal state machine 20 is a MIPI state machine; if data transfer circuit 01 is a JTAG protocol data transfer circuit, internal state machine 20 is a JTAG state machine. Taking the data transmission circuit 01 as an example of a data transmission circuit of the MIPI protocol, the excitation generation module 30 may generate a state switching control signal consistent with an external state signal based on the MIPI protocol (specifically, may be the received MIPI state instruction); accordingly, the data transmission modes may include: a high-speed transmission mode and a low-power transmission mode; the state check module 40 may confirm the correct data transmission state that should be currently in based on the control instruction input by the MIPI protocol, and determine the state check result of the internal state machine 20 based on the consistency of the "current data transmission state of the internal state machine 20" with the correct data transmission state.
Taking the data transmission circuit 01 as a data transmission circuit based on the MIPI protocol as an example, the external input interface may be a MIPI interface, and the MIPI interface may correspond to a plurality of data transmission lines, and each data transmission line is provided with an independently existing internal state machine and corresponds to one data transmission circuit. In normal data transmission, the data transmission modes of the data transmission channel and the clock channel should be consistent.
Referring to fig. 2, fig. 2 is a schematic diagram of a data transmission state according to an embodiment of the application. Wherein mipi_clk represents the state of the clock LANE, mipi_lane0 represents the data transfer state of data LANE0, mipi_lane1 represents the data transfer state of data LANE1, mipi_lane2 represents the data transfer state of data LANE2, mipi_lane3 represents the data transfer state of data LANE 3. In the normal state, the data transmission states of mipi_clk, mipi_lane0, mipi_lane1, mipi_lane2, and mipi_lane3 are all in a High Speed (HS) mode or are all in a Low Loss (LP) mode. In the abnormal state, the situation that the data transmission state of the clock channel is inconsistent with the data transmission state of the data channel can only occur. It will be appreciated that FIG. 2 is merely illustrative of two abnormal state conditions, and that more abnormal state conditions may be included in practice; and the case where the number of data channels is 4 is exemplarily shown, the number of data channels may be 6 or other values.
Therefore, in the case that the internal state machine 20 is in an abnormal state, the data transmission circuit 01 provided by the embodiment of the application generates the state switching control signal consistent with the external state signal through the excitation generation module 30, and sends the generated state switching control signal to the internal state machine 20 through the selection module 10, so that the internal state machine 20 can adjust the data transmission mode of the circuit according to the state switching control signal, and switch the internal state machine 20 to a normal data transmission mode, thereby greatly reducing the interference degree of the ESD on data communication, ensuring the effectiveness and timeliness of the data communication after the ESD interference, and solving the technical problem that the effectiveness and timeliness of the data communication are greatly affected by the ESD interference.
Referring to fig. 3, fig. 3 is a schematic diagram of another data transmission circuit 02 according to an embodiment of the application.
In some alternative embodiments, the data transmission circuit 02 further comprises: a decode verification module 50; the decode verification module 50 is communicatively coupled to the internal state machine 20 and the state check module 40; the decoding and checking module 50 is configured to decode the initial data packet transmitted by the internal state machine 20 to obtain decoded data, and check the decoded data to obtain a check result; wherein, the check result comprises normal decoding data and abnormal decoding data; and, in case the verification result is that the decoded data is abnormal, transmitting an abnormality check start signal to the state check module 40.
Taking the data transmission circuit as an example of the data transmission circuit based on the MIPI protocol, the data decoding check 50 may check the decoded data based on an algorithm or a data transmission format specified by the MIPI protocol.
In some alternative embodiments, the status checking module 40 is specifically configured to determine the status checking result according to the external status signal and the current data transmission status of the internal state machine 20 when the anomaly checking start signal is received.
The state checking module 40 only needs to check whether there is a data transmission error caused by the abnormal state of the internal state machine 20 when the abnormal check start signal is received. This shortens the operation time of the status checking module 40, thereby reducing the operation loss and the heat generation amount of the circuit.
In some alternative embodiments, the external input interface is an MIPI interface; the decoding data comprises at least one of a packet head format of the initial data packet, a packet tail format of the initial data packet, an ECC check code and a CRC check code; the decoded data anomalies include at least one of packet header format anomalies, packet trailer format anomalies, ECC check code anomalies, and CRC check code anomalies.
Wherein, the ECC check code (Error Correction Code) is used for encoding the transmitted data based on an ECC algorithm, and the added redundant information can make the data more reliable; in the case where an error occurs when data is transmitted, the error can be detected and corrected by checking redundancy information (ECC check code). The CRC check code (Cyclic Redundancy check) is a short fixed bit check code generated from a network packet or a signature of a computer file or the like. The external input interface is an MIPI interface, that is, the data transmission circuit is a data transmission circuit based on MIPI protocol, at this time, the data decoding check 50 can calculate ECC check code and CRC check code based on the data input by the external input interface and the algorithm specified by MIPI protocol; and judging whether the ECC check code is abnormal or not according to the received ECC standard check code, CRC standard check code, the ECC check code obtained by decoding and the CRC check code. The data decoding verification 50 may also verify the header format of the initial data packet and the trailer format of the initial data packet obtained after decoding based on the standard header format and the standard trailer format specified by the MIPI protocol, to determine whether the header format abnormality or the trailer format abnormality occurs.
In some alternative embodiments, the selection module 10 is specifically configured to send the external status signal to the internal state machine 20 if the status check result is the normal status; and transmitting the state switching control signal to the internal state machine 20 in the case where the state check result is the abnormal state.
Under the condition that the state check result is an abnormal state, a state switching control signal is sent to the internal state machine 20, so that the internal state machine 20 can adjust a data transmission mode of a circuit according to the state switching control signal, and the internal state machine 20 is converted into a normal data transmission mode, thereby greatly reducing the interference degree of ESD on data communication, ensuring the effectiveness and timeliness of the data communication after being interfered by the ESD, and solving the technical problem that the effectiveness and timeliness of the data communication are greatly affected by the ESD interference.
In some optional embodiments, the status checking module is further configured to determine an anomaly type of the anomaly status if the status checking result is an anomaly status; wherein the exception types include interface exceptions and internal state machine exceptions.
By classifying the types of the abnormal states, the cause of the abnormal states can be conveniently ascertained, and the subsequent optimization process can be more specifically performed. Specifically, if the abnormal state is mostly interface abnormality, the external connection condition of the data transmission circuit can be optimized; if the abnormal state is abnormal in the internal state machine, the design parameters of the internal state machine can be optimized.
Referring to fig. 4, fig. 4 is a flow chart of a data transmission method according to an embodiment of the application. The data transmission method is applied to a data transmission circuit (which may be the above-mentioned data transmission circuit 01 or 02) including a selection module, an internal state machine, an excitation generation module, and a state check module, and includes:
step 201, determining a state check result of the internal state machine based on the state check module according to an external state signal input by an external input interface and a current data transmission state of the internal state machine; wherein the status check result includes a normal status and an abnormal status;
step 202, generating a state switching control signal consistent with the external state signal based on the excitation generation module when the state check result is the abnormal state;
step 203, based on the selection module, sending a corresponding status signal to the internal state machine according to the status check result; wherein the status signal comprises the external status signal and the status switch control signal;
step 204, switching the data transmission mode of the circuit according to the state signal based on the internal state machine.
In some optional embodiments, the data transmission circuit further includes a decode and check module; the data transmission method further comprises the following steps: decoding the initial data packet transmitted by the internal state machine based on the decoding and checking module to obtain decoded data, and checking the decoded data to obtain a checking result; wherein, the check result comprises normal decoding data and abnormal decoding data; and sending an abnormality check start signal to the state check module when the check result is that the decoded data is abnormal.
In some alternative embodiments, the determining, based on the state check module, a state check result of the internal state machine according to an external state signal input by an external input interface and a current data transmission state of the internal state machine includes: and determining a state check result of the internal state machine according to the external state signal and the current data transmission state of the internal state machine under the condition that the state check module receives the abnormality check starting signal.
In some alternative embodiments, the external input interface is an MIPI interface; the decoding data comprises at least one of a packet head format of the initial data packet, a packet tail format of the initial data packet, an ECC check code and a CRC check code; the decoded data anomalies include at least one of packet header format anomalies, packet trailer format anomalies, ECC check code anomalies, and CRC check code anomalies.
In some optional embodiments, step 203, based on the selection module, sends a corresponding status signal to the internal state machine according to the status check result, including: transmitting the external state signal to the internal state machine based on the selection module in the case that the state check result is the normal state; and sending the state switching control signal to the internal state machine when the state check result is the abnormal state.
It should be understood that the data transmission method corresponds to the above-mentioned data transmission circuit embodiment, and specific implementation manners of the steps of the data transmission method may be referred to the above description, and detailed descriptions are omitted herein as appropriate to avoid repetition.
In the embodiments of the present application, it should be understood that the disclosed circuits and methods may be implemented in other manners. The above-described circuit embodiments are merely illustrative, for example, of the flowcharts and block diagrams in the figures that illustrate the architecture, functionality, and operation of possible implementations of circuits, methods or computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, the functional modules in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
The foregoing description is merely an optional implementation of the embodiment of the present application, but the scope of the embodiment of the present application is not limited thereto, and any person skilled in the art may easily think about changes or substitutions within the technical scope of the embodiment of the present application, and the changes or substitutions are covered by the scope of the embodiment of the present application.
Claims (10)
1. A data transmission circuit, the circuit comprising: a selection module, an internal state machine, an excitation generation module, and a state check module;
the state checking module is respectively connected with the internal state machine and the external input interface in a communication way; the state checking module is configured to determine a state checking result of the internal state machine according to an external state signal input by the external input interface and the current data transmission state of the internal state machine; wherein the status check result includes a normal status and an abnormal status;
the excitation generation module is in communication connection with the state checking module; the excitation generation module is configured to generate a state switching control signal consistent with the external state signal in the case that the state check result is the abnormal state;
the selection module is respectively in communication connection with the excitation generation module, the external input interface, the state check module and the internal state machine; the selection module is configured to send a corresponding state signal to the internal state machine according to the state check result; wherein the status signal comprises the external status signal and the status switch control signal;
the internal state machine is configured to switch a data transmission mode of the circuit according to the state signal.
2. The circuit of claim 1, wherein the circuit further comprises: a decoding and checking module;
the decoding and checking module is in communication connection with the internal state machine and the state checking module; the decoding and checking module is configured to decode the initial data packet transmitted by the internal state machine to obtain decoded data, and check the decoded data to obtain a checking result; wherein, the check result comprises normal decoding data and abnormal decoding data; and sending an abnormality check start signal to the state check module when the check result is that the decoded data is abnormal.
3. The circuit of claim 2, wherein the status checking module is specifically configured to determine the status checking result based on the external status signal and a current data transmission status of the internal state machine upon receipt of the anomaly checking on signal.
4. The circuit of claim 2, wherein the external input interface is a MIPI interface; the decoding data comprises at least one of a packet head format of the initial data packet, a packet tail format of the initial data packet, an ECC check code and a CRC check code;
the decoded data anomalies include at least one of packet header format anomalies, packet trailer format anomalies, ECC check code anomalies, and CRC check code anomalies.
5. The circuit of claim 1, wherein the selection module is specifically configured to send the external state signal to the internal state machine if the state check result is the normal state; and sending the state switching control signal to the internal state machine when the state check result is the abnormal state.
6. A data transmission method, the method being applied to a data transmission circuit comprising a selection module, an internal state machine, an excitation generation module, and a state check module, the method comprising:
determining a state check result of the internal state machine based on the state check module according to an external state signal input by an external input interface and the current data transmission state of the internal state machine; wherein the status check result includes a normal status and an abnormal status;
generating a state switching control signal consistent with the external state signal based on the excitation generation module in the case that the state check result is the abnormal state;
transmitting a corresponding state signal to the internal state machine based on the selection module according to the state check result; wherein the status signal comprises the external status signal and the status switch control signal;
and switching a data transmission mode of the circuit according to the state signal based on the internal state machine.
7. The method of claim 6, wherein the data transmission circuit further comprises a decode-and-check module; the method further comprises the steps of:
decoding the initial data packet transmitted by the internal state machine based on the decoding and checking module to obtain decoded data, and checking the decoded data to obtain a checking result; wherein, the check result comprises normal decoding data and abnormal decoding data; and sending an abnormality check start signal to the state check module when the check result is that the decoded data is abnormal.
8. The method of claim 7, wherein the determining the state check result of the internal state machine based on the state check module according to the external state signal input by the external input interface and the current data transmission state of the internal state machine comprises: and determining a state check result of the internal state machine according to the external state signal and the current data transmission state of the internal state machine under the condition that the state check module receives the abnormality check starting signal.
9. The method of claim 7, wherein the external input interface is a MIPI interface; the decoding data comprises at least one of a packet head format of the initial data packet, a packet tail format of the initial data packet, an ECC check code and a CRC check code;
the decoded data anomalies include at least one of packet header format anomalies, packet trailer format anomalies, ECC check code anomalies, and CRC check code anomalies.
10. The method of claim 6, wherein said sending, based on said selection module, a corresponding status signal to said internal state machine according to said status check result comprises:
transmitting the external state signal to the internal state machine based on the selection module in the case that the state check result is the normal state; and sending the state switching control signal to the internal state machine when the state check result is the abnormal state.
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